1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Clock_Ip_Divider.c
8 * @version 2.0.0
9 *
10 * @brief CLOCK driver implementations.
11 * @details CLOCK driver implementations.
12 *
13 * @addtogroup CLOCK_DRIVER Clock Ip Driver
14 * @{
15 */
16
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20
21
22 /*==================================================================================================
23 * INCLUDE FILES
24 * 1) system and project includes
25 * 2) needed interfaces from external units
26 * 3) internal and external interfaces from this unit
27 ==================================================================================================*/
28
29 #include "Clock_Ip_Private.h"
30
31
32 /*==================================================================================================
33 SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define CLOCK_IP_DIVIDER_VENDOR_ID_C 43
36 #define CLOCK_IP_DIVIDER_AR_RELEASE_MAJOR_VERSION_C 4
37 #define CLOCK_IP_DIVIDER_AR_RELEASE_MINOR_VERSION_C 7
38 #define CLOCK_IP_DIVIDER_AR_RELEASE_REVISION_VERSION_C 0
39 #define CLOCK_IP_DIVIDER_SW_MAJOR_VERSION_C 2
40 #define CLOCK_IP_DIVIDER_SW_MINOR_VERSION_C 0
41 #define CLOCK_IP_DIVIDER_SW_PATCH_VERSION_C 0
42
43 /*==================================================================================================
44 * FILE VERSION CHECKS
45 ==================================================================================================*/
46 /* Check if Clock_Ip_Divider.c file and Clock_Ip_Private.h file are of the same vendor */
47 #if (CLOCK_IP_DIVIDER_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
48 #error "Clock_Ip_Divider.c and Clock_Ip_Private.h have different vendor ids"
49 #endif
50
51 /* Check if Clock_Ip_Divider.c file and Clock_Ip_Private.h file are of the same Autosar version */
52 #if ((CLOCK_IP_DIVIDER_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
53 (CLOCK_IP_DIVIDER_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
54 (CLOCK_IP_DIVIDER_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
55 )
56 #error "AutoSar Version Numbers of Clock_Ip_Divider.c and Clock_Ip_Private.h are different"
57 #endif
58
59 /* Check if Clock_Ip_Divider.c file and Clock_Ip_Private.h file are of the same Software version */
60 #if ((CLOCK_IP_DIVIDER_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
61 (CLOCK_IP_DIVIDER_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
62 (CLOCK_IP_DIVIDER_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
63 )
64 #error "Software Version Numbers of Clock_Ip_Divider.c and Clock_Ip_Private.h are different"
65 #endif
66
67 /*==================================================================================================
68 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
69 ==================================================================================================*/
70
71 /*==================================================================================================
72 * LOCAL MACROS
73 ==================================================================================================*/
74
75 /*==================================================================================================
76 * LOCAL CONSTANTS
77 ==================================================================================================*/
78
79 /*==================================================================================================
80 * LOCAL VARIABLES
81 ==================================================================================================*/
82
83 /*==================================================================================================
84 * GLOBAL CONSTANTS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * GLOBAL VARIABLES
89 ==================================================================================================*/
90
91 /*==================================================================================================
92 * GLOBAL FUNCTION PROTOTYPES
93 ==================================================================================================*/
94 /* Clock start section code */
95 #define MCU_START_SEC_CODE
96
97 #include "Mcu_MemMap.h"
98 #ifdef CLOCK_IP_SCG_ASYNC_DIV1
99 void Clock_Ip_SetScgAsyncDiv1_TrustedCall(Clock_Ip_DividerConfigType const* Config);
100 #endif
101
102 #ifdef CLOCK_IP_SCG_ASYNC_DIV2
103 void Clock_Ip_SetScgAsyncDiv2_TrustedCall(Clock_Ip_DividerConfigType const* Config);
104 #endif
105
106 #ifdef CLOCK_IP_SCG_DIVCORE_RUN
107 /* Set divider value of CORE_RUN_CLK to register */
108 void Clock_Ip_SetScgRunDivcore_TrustedCall(Clock_Ip_DividerConfigType const* Config);
109 #endif
110
111 #ifdef CLOCK_IP_SCG_DIVBUS_RUN
112 /* Set divider value of BUS_RUN_CLK to register */
113 void Clock_Ip_SetScgRunDivbus_TrustedCall(Clock_Ip_DividerConfigType const* Config);
114 #endif
115
116 #ifdef CLOCK_IP_SCG_DIVSLOW_RUN
117 /* Set divider value of SLOW_RUN_CLK to register */
118 void Clock_Ip_SetScgRunDivslow_TrustedCall(Clock_Ip_DividerConfigType const* Config);
119 #endif
120
121 #ifdef CLOCK_IP_SCG_DIVCORE_VLPR
122 /* Set divider value of CORE_VLPR_CLK to register */
123 void Clock_Ip_SetScgVlprDivcore_TrustedCall(Clock_Ip_DividerConfigType const* Config);
124 #endif
125
126 #ifdef CLOCK_IP_SCG_DIVBUS_VLPR
127 /* Set divider value of BUS_VLPR_CLK to register */
128 void Clock_Ip_SetScgVlprDivbus_TrustedCall(Clock_Ip_DividerConfigType const* Config);
129 #endif
130
131 #ifdef CLOCK_IP_SCG_DIVSLOW_VLPR
132 /* Set divider value of SLOW_VLPR_CLK to register */
133 void Clock_Ip_SetScgVlprDivslow_TrustedCall(Clock_Ip_DividerConfigType const* Config);
134 #endif
135
136 #ifdef CLOCK_IP_SCG_DIVCORE_HSRUN
137 /* Set divider value of CORE_HSRUN_CLK to register */
138 void Clock_Ip_SetScgHsrunDivcore_TrustedCall(Clock_Ip_DividerConfigType const* Config);
139 #endif
140
141 #ifdef CLOCK_IP_SCG_DIVBUS_HSRUN
142 /* Set divider value of BUS_HSRUN_CLK to register */
143 void Clock_Ip_SetScgHsrunDivbus_TrustedCall(Clock_Ip_DividerConfigType const* Config);
144 #endif
145
146 #ifdef CLOCK_IP_SCG_DIVSLOW_HSRUN
147 /* Set divider value of SLOW_HSRUN_CLK to register */
148 void Clock_Ip_SetScgHsrunDivslow_TrustedCall(Clock_Ip_DividerConfigType const* Config);
149 #endif
150
151 #ifdef CLOCK_IP_SIM_CLKOUT_DIV
152 /* Set divider value of CLKOUT0_CLK to register */
153 void Clock_Ip_SetSimClkoutDiv_TrustedCall(Clock_Ip_DividerConfigType const *Config);
154 #endif
155
156 #ifdef CLOCK_IP_PCC_PCD_FRAC
157 void Clock_Ip_SetPccPcdDivFrac_TrustedCall(Clock_Ip_DividerConfigType const* Config);
158 #endif
159
160 #ifdef CLOCK_IP_SIM_TRACE_DIV_MUL
161 void Clock_Ip_SetSimTraceDivMul_TrustedCall(Clock_Ip_DividerConfigType const* Config);
162 #endif
163
164 /*==================================================================================================
165 * LOCAL FUNCTION PROTOTYPES
166 ==================================================================================================*/
167
168 static void Clock_Ip_Callback_DividerEmpty(Clock_Ip_DividerConfigType const* Config);
169 #ifdef CLOCK_IP_SCG_ASYNC_DIV1
170 static void Clock_Ip_SetScgAsyncDiv1(Clock_Ip_DividerConfigType const* Config);
171 #endif
172 #ifdef CLOCK_IP_SCG_ASYNC_DIV2
173 static void Clock_Ip_SetScgAsyncDiv2(Clock_Ip_DividerConfigType const* Config);
174 #endif
175 #ifdef CLOCK_IP_SCG_DIVCORE_RUN
176 static void Clock_Ip_SetScgRunDivcore(Clock_Ip_DividerConfigType const* Config);
177 #endif
178 #ifdef CLOCK_IP_SCG_DIVBUS_RUN
179 static void Clock_Ip_SetScgRunDivbus(Clock_Ip_DividerConfigType const* Config);
180 #endif
181 #ifdef CLOCK_IP_SCG_DIVSLOW_RUN
182 static void Clock_Ip_SetScgRunDivslow(Clock_Ip_DividerConfigType const* Config);
183 #endif
184 #ifdef CLOCK_IP_SCG_DIVCORE_VLPR
185 static void Clock_Ip_SetScgVlprDivcore(Clock_Ip_DividerConfigType const* Config);
186 #endif
187 #ifdef CLOCK_IP_SCG_DIVBUS_VLPR
188 static void Clock_Ip_SetScgVlprDivbus(Clock_Ip_DividerConfigType const* Config);
189 #endif
190 #ifdef CLOCK_IP_SCG_DIVSLOW_VLPR
191 static void Clock_Ip_SetScgVlprDivslow(Clock_Ip_DividerConfigType const* Config);
192 #endif
193 #ifdef CLOCK_IP_SCG_DIVCORE_HSRUN
194 static void Clock_Ip_SetScgHsrunDivcore(Clock_Ip_DividerConfigType const* Config);
195 #endif
196 #ifdef CLOCK_IP_SCG_DIVBUS_HSRUN
197 static void Clock_Ip_SetScgHsrunDivbus(Clock_Ip_DividerConfigType const* Config);
198 #endif
199 #ifdef CLOCK_IP_SCG_DIVSLOW_HSRUN
200 static void Clock_Ip_SetScgHsrunDivslow(Clock_Ip_DividerConfigType const* Config);
201 #endif
202
203 #ifdef CLOCK_IP_SIM_CLKOUT_DIV
204 static void Clock_Ip_SetSimClkoutDiv(Clock_Ip_DividerConfigType const *Config);
205 #endif
206
207 #ifdef CLOCK_IP_PCC_PCD_FRAC
208 static void Clock_Ip_SetPccPcdDivFrac(Clock_Ip_DividerConfigType const* Config);
209 #endif
210 #ifdef CLOCK_IP_SIM_TRACE_DIV_MUL
211 static void Clock_Ip_SetSimTraceDivMul(Clock_Ip_DividerConfigType const* Config);
212 #endif
213
214
215 /* Clock stop section code */
216 #define MCU_STOP_SEC_CODE
217
218 #include "Mcu_MemMap.h"
219 /*==================================================================================================
220 * LOCAL FUNCTIONS
221 ==================================================================================================*/
222 #define MCU_START_SEC_CODE
223 /* Clock start section code */
224
225 #include "Mcu_MemMap.h"
226
Clock_Ip_Callback_DividerEmpty(Clock_Ip_DividerConfigType const * Config)227 static void Clock_Ip_Callback_DividerEmpty(Clock_Ip_DividerConfigType const* Config)
228 {
229 (void)Config;
230 /* No implementation */
231 }
232
233 #ifdef CLOCK_IP_SCG_ASYNC_DIV1
Clock_Ip_SetScgAsyncDiv1(Clock_Ip_DividerConfigType const * Config)234 static void Clock_Ip_SetScgAsyncDiv1(Clock_Ip_DividerConfigType const* Config)
235 {
236 if (NULL_PTR != Config)
237 {
238 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
239 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
240 OsIf_Trusted_Call1param(Clock_Ip_SetScgAsyncDiv1_TrustedCall,(Config));
241 #else
242 Clock_Ip_SetScgAsyncDiv1_TrustedCall(Config);
243 #endif
244 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
245 }
246 }
247 #endif
248
249 #ifdef CLOCK_IP_SCG_ASYNC_DIV2
Clock_Ip_SetScgAsyncDiv2(Clock_Ip_DividerConfigType const * Config)250 static void Clock_Ip_SetScgAsyncDiv2(Clock_Ip_DividerConfigType const* Config)
251 {
252 if (NULL_PTR != Config)
253 {
254 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
255 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
256 OsIf_Trusted_Call1param(Clock_Ip_SetScgAsyncDiv2_TrustedCall,(Config));
257 #else
258 Clock_Ip_SetScgAsyncDiv2_TrustedCall(Config);
259 #endif
260 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
261 }
262 }
263 #endif
264
265 #ifdef CLOCK_IP_SCG_DIVCORE_RUN
Clock_Ip_SetScgRunDivcore(Clock_Ip_DividerConfigType const * Config)266 static void Clock_Ip_SetScgRunDivcore(Clock_Ip_DividerConfigType const* Config)
267 {
268 if (NULL_PTR != Config)
269 {
270 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
271 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
272 OsIf_Trusted_Call1param(Clock_Ip_SetScgRunDivcore_TrustedCall,(Config));
273 #else
274 Clock_Ip_SetScgRunDivcore_TrustedCall(Config);
275 #endif
276 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
277 }
278 }
279 #endif
280
281 #ifdef CLOCK_IP_SCG_DIVBUS_RUN
Clock_Ip_SetScgRunDivbus(Clock_Ip_DividerConfigType const * Config)282 static void Clock_Ip_SetScgRunDivbus(Clock_Ip_DividerConfigType const* Config)
283 {
284 if (NULL_PTR != Config)
285 {
286 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
287 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
288 OsIf_Trusted_Call1param(Clock_Ip_SetScgRunDivbus_TrustedCall,(Config));
289 #else
290 Clock_Ip_SetScgRunDivbus_TrustedCall(Config);
291 #endif
292 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
293 }
294 }
295 #endif
296
297 #ifdef CLOCK_IP_SCG_DIVSLOW_RUN
Clock_Ip_SetScgRunDivslow(Clock_Ip_DividerConfigType const * Config)298 static void Clock_Ip_SetScgRunDivslow(Clock_Ip_DividerConfigType const* Config)
299 {
300 if (NULL_PTR != Config)
301 {
302 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
303 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
304 OsIf_Trusted_Call1param(Clock_Ip_SetScgRunDivslow_TrustedCall,(Config));
305 #else
306 Clock_Ip_SetScgRunDivslow_TrustedCall(Config);
307 #endif
308 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
309 }
310 }
311 #endif
312
313 #ifdef CLOCK_IP_SCG_DIVCORE_VLPR
Clock_Ip_SetScgVlprDivcore(Clock_Ip_DividerConfigType const * Config)314 static void Clock_Ip_SetScgVlprDivcore(Clock_Ip_DividerConfigType const* Config)
315 {
316 if (NULL_PTR != Config)
317 {
318 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
319 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
320 OsIf_Trusted_Call1param(Clock_Ip_SetScgVlprDivcore_TrustedCall,(Config));
321 #else
322 Clock_Ip_SetScgVlprDivcore_TrustedCall(Config);
323 #endif
324 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
325 }
326 }
327 #endif
328
329 #ifdef CLOCK_IP_SCG_DIVBUS_VLPR
Clock_Ip_SetScgVlprDivbus(Clock_Ip_DividerConfigType const * Config)330 static void Clock_Ip_SetScgVlprDivbus(Clock_Ip_DividerConfigType const* Config)
331 {
332 if (NULL_PTR != Config)
333 {
334 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
335 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
336 OsIf_Trusted_Call1param(Clock_Ip_SetScgVlprDivbus_TrustedCall,(Config));
337 #else
338 Clock_Ip_SetScgVlprDivbus_TrustedCall(Config);
339 #endif
340 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
341 }
342 }
343 #endif
344
345 #ifdef CLOCK_IP_SCG_DIVSLOW_VLPR
Clock_Ip_SetScgVlprDivslow(Clock_Ip_DividerConfigType const * Config)346 static void Clock_Ip_SetScgVlprDivslow(Clock_Ip_DividerConfigType const* Config)
347 {
348 if (NULL_PTR != Config)
349 {
350 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
351 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
352 OsIf_Trusted_Call1param(Clock_Ip_SetScgVlprDivslow_TrustedCall,(Config));
353 #else
354 Clock_Ip_SetScgVlprDivslow_TrustedCall(Config);
355 #endif
356 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
357 }
358 }
359 #endif
360
361 #ifdef CLOCK_IP_SCG_DIVCORE_HSRUN
Clock_Ip_SetScgHsrunDivcore(Clock_Ip_DividerConfigType const * Config)362 static void Clock_Ip_SetScgHsrunDivcore(Clock_Ip_DividerConfigType const* Config)
363 {
364 if (NULL_PTR != Config)
365 {
366 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
367 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
368 OsIf_Trusted_Call1param(Clock_Ip_SetScgHsrunDivcore_TrustedCall,(Config));
369 #else
370 Clock_Ip_SetScgHsrunDivcore_TrustedCall(Config);
371 #endif
372 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
373 }
374 }
375 #endif
376
377 #ifdef CLOCK_IP_SCG_DIVBUS_HSRUN
Clock_Ip_SetScgHsrunDivbus(Clock_Ip_DividerConfigType const * Config)378 static void Clock_Ip_SetScgHsrunDivbus(Clock_Ip_DividerConfigType const* Config)
379 {
380 if (NULL_PTR != Config)
381 {
382 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
383 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
384 OsIf_Trusted_Call1param(Clock_Ip_SetScgHsrunDivbus_TrustedCall,(Config));
385 #else
386 Clock_Ip_SetScgHsrunDivbus_TrustedCall(Config);
387 #endif
388 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
389 }
390 }
391 #endif
392
393 #ifdef CLOCK_IP_SCG_DIVSLOW_HSRUN
Clock_Ip_SetScgHsrunDivslow(Clock_Ip_DividerConfigType const * Config)394 static void Clock_Ip_SetScgHsrunDivslow(Clock_Ip_DividerConfigType const* Config)
395 {
396 if (NULL_PTR != Config)
397 {
398 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
399 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
400 OsIf_Trusted_Call1param(Clock_Ip_SetScgHsrunDivslow_TrustedCall,(Config));
401 #else
402 Clock_Ip_SetScgHsrunDivslow_TrustedCall(Config);
403 #endif
404 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
405 }
406 }
407 #endif
408
409 #ifdef CLOCK_IP_SIM_CLKOUT_DIV
Clock_Ip_SetSimClkoutDiv(Clock_Ip_DividerConfigType const * Config)410 static void Clock_Ip_SetSimClkoutDiv(Clock_Ip_DividerConfigType const *Config)
411 {
412 if (NULL_PTR != Config)
413 {
414 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
415 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
416 OsIf_Trusted_Call1param(Clock_Ip_SetSimClkoutDiv_TrustedCall,(Config));
417 #else
418 Clock_Ip_SetSimClkoutDiv_TrustedCall(Config);
419 #endif
420 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
421 }
422 }
423 #endif
424
425 #ifdef CLOCK_IP_PCC_PCD_FRAC
Clock_Ip_SetPccPcdDivFrac(Clock_Ip_DividerConfigType const * Config)426 static void Clock_Ip_SetPccPcdDivFrac(Clock_Ip_DividerConfigType const* Config)
427 {
428 if (NULL_PTR != Config)
429 {
430 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
431 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
432 OsIf_Trusted_Call1param(Clock_Ip_SetPccPcdDivFrac_TrustedCall,(Config));
433 #else
434 Clock_Ip_SetPccPcdDivFrac_TrustedCall(Config);
435 #endif
436 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
437 }
438 }
439 #endif
440
441 #ifdef CLOCK_IP_SIM_TRACE_DIV_MUL
Clock_Ip_SetSimTraceDivMul(Clock_Ip_DividerConfigType const * Config)442 static void Clock_Ip_SetSimTraceDivMul(Clock_Ip_DividerConfigType const* Config)
443 {
444 if (NULL_PTR != Config)
445 {
446 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
447 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
448 OsIf_Trusted_Call1param(Clock_Ip_SetSimTraceDivMul_TrustedCall,(Config));
449 #else
450 Clock_Ip_SetSimTraceDivMul_TrustedCall(Config);
451 #endif
452 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
453 }
454 }
455 #endif
456
457
458
459 /*==================================================================================================
460 * GLOBAL FUNCTIONS
461 ==================================================================================================*/
462 #ifdef CLOCK_IP_SCG_ASYNC_DIV1
Clock_Ip_SetScgAsyncDiv1_TrustedCall(Clock_Ip_DividerConfigType const * Config)463 void Clock_Ip_SetScgAsyncDiv1_TrustedCall(Clock_Ip_DividerConfigType const* Config)
464 {
465 uint32 RegValue;
466 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
467 uint32 DividerValue = Clock_Ip_au8DividerValueHardwareValue[Config->Value]; /* Hw value corresponding to divider value. Translate the value by which is divided to hardware value. */
468
469
470 RegValue = Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV;
471 RegValue &= ~SCG_SIRCDIV_SIRCDIV1_MASK;
472 RegValue |= (DividerValue << SCG_SIRCDIV_SIRCDIV1_SHIFT);
473 Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV = RegValue;
474 }
475 #endif
476
477 #ifdef CLOCK_IP_SCG_ASYNC_DIV2
Clock_Ip_SetScgAsyncDiv2_TrustedCall(Clock_Ip_DividerConfigType const * Config)478 void Clock_Ip_SetScgAsyncDiv2_TrustedCall(Clock_Ip_DividerConfigType const* Config)
479 {
480 uint32 RegValue;
481 uint32 Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
482 uint32 DividerValue = Clock_Ip_au8DividerValueHardwareValue[Config->Value]; /* Hw value corresponding to divider value. Translate the value by which is divided to hardware value. */
483
484 RegValue = Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV;
485 RegValue &= ~SCG_SIRCDIV_SIRCDIV2_MASK;
486 RegValue |= (DividerValue << SCG_SIRCDIV_SIRCDIV2_SHIFT);
487 Clock_Ip_apxScgPeriphAsyncDivs[Instance]->ASYNC_DIV = RegValue;
488 }
489 #endif
490
491 #ifdef CLOCK_IP_SCG_DIVCORE_RUN
492 /* Set divider value of CORE_RUN_CLK to register */
Clock_Ip_SetScgRunDivcore_TrustedCall(Clock_Ip_DividerConfigType const * Config)493 void Clock_Ip_SetScgRunDivcore_TrustedCall(Clock_Ip_DividerConfigType const* Config)
494 {
495 uint32 RegValue;
496
497 RegValue = IP_SCG->RCCR;
498 RegValue &= ~SCG_RCCR_DIVCORE_MASK;
499 RegValue |= ((Config->Value - 1U) << SCG_RCCR_DIVCORE_SHIFT);
500 IP_SCG->RCCR = RegValue;
501 }
502 #endif
503
504 #ifdef CLOCK_IP_SCG_DIVBUS_RUN
505 /* Set divider value of BUS_RUN_CLK to register */
Clock_Ip_SetScgRunDivbus_TrustedCall(Clock_Ip_DividerConfigType const * Config)506 void Clock_Ip_SetScgRunDivbus_TrustedCall(Clock_Ip_DividerConfigType const* Config)
507 {
508 uint32 RegValue;
509
510 RegValue = IP_SCG->RCCR;
511 RegValue &= ~SCG_RCCR_DIVBUS_MASK;
512 RegValue |= ((Config->Value - 1U) << SCG_RCCR_DIVBUS_SHIFT);
513 IP_SCG->RCCR = RegValue;
514 }
515 #endif
516
517 #ifdef CLOCK_IP_SCG_DIVSLOW_RUN
518 /* Set divider value of SLOW_RUN_CLK to register */
Clock_Ip_SetScgRunDivslow_TrustedCall(Clock_Ip_DividerConfigType const * Config)519 void Clock_Ip_SetScgRunDivslow_TrustedCall(Clock_Ip_DividerConfigType const* Config)
520 {
521 uint32 RegValue;
522
523 RegValue = IP_SCG->RCCR;
524 RegValue &= ~SCG_RCCR_DIVSLOW_MASK;
525 RegValue |= ((Config->Value - 1U) << SCG_RCCR_DIVSLOW_SHIFT);
526 IP_SCG->RCCR = RegValue;
527 }
528 #endif
529
530 #ifdef CLOCK_IP_SCG_DIVCORE_VLPR
531 /* Set divider value of CORE_VLPR_CLK to register */
Clock_Ip_SetScgVlprDivcore_TrustedCall(Clock_Ip_DividerConfigType const * Config)532 void Clock_Ip_SetScgVlprDivcore_TrustedCall(Clock_Ip_DividerConfigType const* Config)
533 {
534 uint32 RegValue;
535
536 RegValue = IP_SCG->VCCR;
537 RegValue &= ~SCG_VCCR_DIVCORE_MASK;
538 RegValue |= ((Config->Value - 1U) << SCG_VCCR_DIVCORE_SHIFT);
539 IP_SCG->VCCR = RegValue;
540 }
541 #endif
542
543 #ifdef CLOCK_IP_SCG_DIVBUS_VLPR
544 /* Set divider value of BUS_VLPR_CLK to register */
Clock_Ip_SetScgVlprDivbus_TrustedCall(Clock_Ip_DividerConfigType const * Config)545 void Clock_Ip_SetScgVlprDivbus_TrustedCall(Clock_Ip_DividerConfigType const* Config)
546 {
547 uint32 RegValue;
548
549 RegValue = IP_SCG->VCCR;
550 RegValue &= ~SCG_VCCR_DIVBUS_MASK;
551 RegValue |= ((Config->Value - 1U) << SCG_VCCR_DIVBUS_SHIFT);
552 IP_SCG->VCCR = RegValue;
553 }
554 #endif
555
556 #ifdef CLOCK_IP_SCG_DIVSLOW_VLPR
557 /* Set divider value of SLOW_VLPR_CLK to register */
Clock_Ip_SetScgVlprDivslow_TrustedCall(Clock_Ip_DividerConfigType const * Config)558 void Clock_Ip_SetScgVlprDivslow_TrustedCall(Clock_Ip_DividerConfigType const* Config)
559 {
560 uint32 RegValue;
561
562 RegValue = IP_SCG->VCCR;
563 RegValue &= ~SCG_VCCR_DIVSLOW_MASK;
564 RegValue |= ((Config->Value - 1U) << SCG_VCCR_DIVSLOW_SHIFT);
565 IP_SCG->VCCR = RegValue;
566 }
567 #endif
568
569 #ifdef CLOCK_IP_SCG_DIVCORE_HSRUN
570 /* Set divider value of CORE_HSRUN_CLK to register */
Clock_Ip_SetScgHsrunDivcore_TrustedCall(Clock_Ip_DividerConfigType const * Config)571 void Clock_Ip_SetScgHsrunDivcore_TrustedCall(Clock_Ip_DividerConfigType const* Config)
572 {
573 uint32 RegValue;
574
575 RegValue = IP_SCG->HCCR;
576 RegValue &= ~SCG_HCCR_DIVCORE_MASK;
577 RegValue |= ((Config->Value - 1U) << SCG_HCCR_DIVCORE_SHIFT);
578 IP_SCG->HCCR = RegValue;
579 }
580 #endif
581
582 #ifdef CLOCK_IP_SCG_DIVBUS_HSRUN
583 /* Set divider value of BUS_HSRUN_CLK to register */
Clock_Ip_SetScgHsrunDivbus_TrustedCall(Clock_Ip_DividerConfigType const * Config)584 void Clock_Ip_SetScgHsrunDivbus_TrustedCall(Clock_Ip_DividerConfigType const* Config)
585 {
586 uint32 RegValue;
587
588 RegValue = IP_SCG->HCCR;
589 RegValue &= ~SCG_HCCR_DIVBUS_MASK;
590 RegValue |= ((Config->Value - 1U) << SCG_HCCR_DIVBUS_SHIFT);
591 IP_SCG->HCCR = RegValue;
592 }
593 #endif
594
595 #ifdef CLOCK_IP_SCG_DIVSLOW_HSRUN
596 /* Set divider value of SLOW_HSRUN_CLK to register */
Clock_Ip_SetScgHsrunDivslow_TrustedCall(Clock_Ip_DividerConfigType const * Config)597 void Clock_Ip_SetScgHsrunDivslow_TrustedCall(Clock_Ip_DividerConfigType const* Config)
598 {
599 uint32 RegValue;
600
601 RegValue = IP_SCG->HCCR;
602 RegValue &= ~SCG_HCCR_DIVSLOW_MASK;
603 RegValue |= ((Config->Value - 1U) << SCG_HCCR_DIVSLOW_SHIFT);
604 IP_SCG->HCCR = RegValue;
605 }
606 #endif
607
608 #ifdef CLOCK_IP_SIM_CLKOUT_DIV
609 /* Set divider value of CLKOUT0_CLK to register */
Clock_Ip_SetSimClkoutDiv_TrustedCall(Clock_Ip_DividerConfigType const * Config)610 void Clock_Ip_SetSimClkoutDiv_TrustedCall(Clock_Ip_DividerConfigType const *Config)
611 {
612 uint32 RegValue;
613
614 RegValue = IP_SIM->CHIPCTL;
615 RegValue &= ~SIM_CHIPCTL_CLKOUTDIV_MASK;
616 RegValue |= SIM_CHIPCTL_CLKOUTDIV(Config->Value - 1U);
617 IP_SIM->CHIPCTL = RegValue;
618 }
619 #endif
620
621 #ifdef CLOCK_IP_PCC_PCD_FRAC
Clock_Ip_SetPccPcdDivFrac_TrustedCall(Clock_Ip_DividerConfigType const * Config)622 void Clock_Ip_SetPccPcdDivFrac_TrustedCall(Clock_Ip_DividerConfigType const* Config)
623 {
624 uint32 RegValue;
625
626 RegValue = IP_PCC->PCCn[Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]];
627 RegValue &= ~(PCC_PCCn_PCD_MASK | PCC_PCCn_FRAC_MASK);
628 RegValue |= PCC_PCCn_PCD(Config->Value - 1U); /* Divider */
629 RegValue |= PCC_PCCn_FRAC((uint32)(Config->Options[0U]) - 1U); /* Multiplier */
630 IP_PCC->PCCn[Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_DIVIDER_INDEX]] = RegValue;
631 }
632 #endif
633
634 #ifdef CLOCK_IP_SIM_TRACE_DIV_MUL
Clock_Ip_SetSimTraceDivMul_TrustedCall(Clock_Ip_DividerConfigType const * Config)635 void Clock_Ip_SetSimTraceDivMul_TrustedCall(Clock_Ip_DividerConfigType const* Config)
636 {
637 uint32 RegValue;
638
639 /* Disable TRACEDIVEN to configure TRACEDIV */
640 IP_SIM->CLKDIV4 &= ~(SIM_CLKDIV4_TRACEDIVEN_MASK);
641 RegValue = IP_SIM->CLKDIV4;
642 RegValue &= ~(SIM_CLKDIV4_TRACEDIV_MASK | SIM_CLKDIV4_TRACEFRAC_MASK);
643 RegValue |= SIM_CLKDIV4_TRACEDIV((uint32)(Config->Value) - 1U) | /* Divider */
644 SIM_CLKDIV4_TRACEFRAC((uint32)(Config->Options[0U]) - 1U); /* Multiplier */
645 IP_SIM->CLKDIV4 = RegValue;
646 }
647 #endif
648
649
650
651 /* Clock stop section code */
652 #define MCU_STOP_SEC_CODE
653
654 #include "Mcu_MemMap.h"
655
656 /*==================================================================================================
657 * GLOBAL CONSTANTS
658 ==================================================================================================*/
659
660 /* Clock start constant section data */
661 #define MCU_START_SEC_CONST_UNSPECIFIED
662
663 #include "Mcu_MemMap.h"
664
665 const Clock_Ip_DividerCallbackType Clock_Ip_axDividerCallbacks[CLOCK_IP_DIVIDER_CALLBACKS_COUNT] =
666 {
667 {
668 Clock_Ip_Callback_DividerEmpty, /* Set */
669 },
670 #ifdef CLOCK_IP_SCG_ASYNC_DIV1
671 {
672 Clock_Ip_SetScgAsyncDiv1, /* Set */
673 },
674 #endif
675 #ifdef CLOCK_IP_SCG_ASYNC_DIV2
676 {
677 Clock_Ip_SetScgAsyncDiv2, /* Set */
678 },
679 #endif
680 #ifdef CLOCK_IP_SCG_DIVCORE_RUN
681 {
682 Clock_Ip_SetScgRunDivcore, /* Set */
683 },
684 #endif
685 #ifdef CLOCK_IP_SCG_DIVBUS_RUN
686 {
687 Clock_Ip_SetScgRunDivbus, /* Set */
688 },
689 #endif
690 #ifdef CLOCK_IP_SCG_DIVSLOW_RUN
691 {
692 Clock_Ip_SetScgRunDivslow, /* Set */
693 },
694 #endif
695 #ifdef CLOCK_IP_SCG_DIVCORE_VLPR
696 {
697 Clock_Ip_SetScgVlprDivcore, /* Set */
698 },
699 #endif
700 #ifdef CLOCK_IP_SCG_DIVBUS_VLPR
701 {
702 Clock_Ip_SetScgVlprDivbus, /* Set */
703 },
704 #endif
705 #ifdef CLOCK_IP_SCG_DIVSLOW_VLPR
706 {
707 Clock_Ip_SetScgVlprDivslow, /* Set */
708 },
709 #endif
710 #ifdef CLOCK_IP_SCG_DIVCORE_HSRUN
711 {
712 Clock_Ip_SetScgHsrunDivcore, /* Set */
713 },
714 #endif
715 #ifdef CLOCK_IP_SCG_DIVBUS_HSRUN
716 {
717 Clock_Ip_SetScgHsrunDivbus, /* Set */
718 },
719 #endif
720 #ifdef CLOCK_IP_SCG_DIVSLOW_HSRUN
721 {
722 Clock_Ip_SetScgHsrunDivslow, /* Set */
723 },
724 #endif
725 #ifdef CLOCK_IP_SIM_CLKOUT_DIV
726 {
727 Clock_Ip_SetSimClkoutDiv, /* Set */
728 },
729 #endif
730 #ifdef CLOCK_IP_PCC_PCD_FRAC
731 {
732 Clock_Ip_SetPccPcdDivFrac, /* Set */
733 },
734 #endif
735 #ifdef CLOCK_IP_SIM_TRACE_DIV_MUL
736 {
737 Clock_Ip_SetSimTraceDivMul, /* Set */
738 },
739 #endif
740
741 };
742
743 /* Clock stop constant section data */
744 #define MCU_STOP_SEC_CONST_UNSPECIFIED
745
746 #include "Mcu_MemMap.h"
747
748
749 #ifdef __cplusplus
750 }
751 #endif
752
753 /** @} */
754
