1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_ospi.h 4 * @author MCD Application Team 5 * @brief Header file of OSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32U5xx_HAL_OSPI_H 22 #define STM32U5xx_HAL_OSPI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32u5xx_hal_def.h" 30 #include "stm32u5xx_ll_dlyb.h" 31 32 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 33 34 /** @addtogroup STM32U5xx_HAL_Driver 35 * @{ 36 */ 37 38 /** @addtogroup OSPI 39 * @{ 40 */ 41 42 /* Exported types ------------------------------------------------------------*/ 43 /** @defgroup OSPI_Exported_Types OSPI Exported Types 44 * @{ 45 */ 46 #define HAL_OSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef 47 48 /** 49 * @brief OSPI Init structure definition 50 */ 51 typedef struct 52 { 53 uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt 54 indicating that data are available in reception or free place 55 is available in transmission. 56 This parameter can be a value between 1 and 32 */ 57 uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to 58 quad mode on two different devices to increase the throughput. 59 This parameter can be a value of @ref OSPI_DualQuad */ 60 uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. 61 This parameter can be a value of @ref OSPI_MemoryType */ 62 uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, 63 it corresponds to the number of address bits required to access 64 the external device. 65 This parameter can be a value between 1 and 32 */ 66 uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select 67 must remain high between commands. 68 This parameter can be a value between 1 and 8 */ 69 uint32_t FreeRunningClock; /*!< It enables or not the free running clock. 70 This parameter can be a value of @ref OSPI_FreeRunningClock */ 71 uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. 72 This parameter can be a value of @ref OSPI_ClockMode */ 73 uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. 74 This parameter can be a value of @ref OSPI_WrapSize */ 75 uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating 76 the external clock based on the AHB clock. 77 This parameter can be a value between 1 and 256 */ 78 uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order 79 to take in account external signal delays. 80 This parameter can be a value of @ref OSPI_SampleShifting */ 81 uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. 82 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 83 uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and 84 defines the boundary of bytes to release the chip select. 85 This parameter can be a value between 0 and 31 */ 86 uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected 87 by the delay block. 88 This parameter can be a value of @ref OSPI_DelayBlockBypass */ 89 uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is 90 released every MaxTran+1 bytes when the other OctoSPI request the access 91 to the bus. 92 This parameter can be a value between 0 and 255 */ 93 uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every 94 Refresh+1 clock cycles. 95 This parameter can be a value between 0 and 0xFFFFFFFF */ 96 } OSPI_InitTypeDef; 97 98 /** 99 * @brief HAL OSPI Handle Structure definition 100 */ 101 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 102 typedef struct __OSPI_HandleTypeDef 103 #else 104 typedef struct 105 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 106 { 107 OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ 108 OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ 109 uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ 110 __IO uint32_t XferSize; /*!< Number of data to transfer */ 111 __IO uint32_t XferCount; /*!< Counter of data transferred */ 112 DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ 113 __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ 114 __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ 115 uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ 116 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 117 void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi); 118 void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 119 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 120 void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 121 void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 122 void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 123 void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 124 void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); 125 void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi); 126 void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi); 127 128 void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi); 129 void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi); 130 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 131 } OSPI_HandleTypeDef; 132 133 /** 134 * @brief HAL OSPI Regular Command Structure definition 135 */ 136 typedef struct 137 { 138 uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or 139 to the registers for the write operation (these registers are only 140 used for memory-mapped mode). 141 This parameter can be a value of @ref OSPI_OperationType */ 142 uint32_t FlashId; /*!< It indicates which external device is selected for this command (it 143 applies only if Dualquad is disabled in the initialization structure). 144 This parameter can be a value of @ref OSPI_FlashID */ 145 uint32_t Instruction; /*!< It contains the instruction to be sent to the device. 146 This parameter can be a value between 0 and 0xFFFFFFFF */ 147 uint32_t InstructionMode; /*!< It indicates the mode of the instruction. 148 This parameter can be a value of @ref OSPI_InstructionMode */ 149 uint32_t InstructionSize; /*!< It indicates the size of the instruction. 150 This parameter can be a value of @ref OSPI_InstructionSize */ 151 uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. 152 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 153 uint32_t Address; /*!< It contains the address to be sent to the device. 154 This parameter can be a value between 0 and 0xFFFFFFFF */ 155 uint32_t AddressMode; /*!< It indicates the mode of the address. 156 This parameter can be a value of @ref OSPI_AddressMode */ 157 uint32_t AddressSize; /*!< It indicates the size of the address. 158 This parameter can be a value of @ref OSPI_AddressSize */ 159 uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. 160 This parameter can be a value of @ref OSPI_AddressDtrMode */ 161 uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. 162 This parameter can be a value between 0 and 0xFFFFFFFF */ 163 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. 164 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 165 uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. 166 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 167 uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. 168 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 169 uint32_t DataMode; /*!< It indicates the mode of the data. 170 This parameter can be a value of @ref OSPI_DataMode */ 171 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 172 This field is only used for indirect mode. 173 This parameter can be a value between 1 and 0xFFFFFFFF */ 174 uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. 175 This parameter can be a value of @ref OSPI_DataDtrMode */ 176 uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. 177 This parameter can be a value between 0 and 31 */ 178 uint32_t DQSMode; /*!< It enables or not the data strobe management. 179 This parameter can be a value of @ref OSPI_DQSMode */ 180 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. 181 This parameter can be a value of @ref OSPI_SIOOMode */ 182 } OSPI_RegularCmdTypeDef; 183 184 /** 185 * @brief HAL OSPI Hyperbus Configuration Structure definition 186 */ 187 typedef struct 188 { 189 uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. 190 This parameter can be a value between 0 and 255 */ 191 uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. 192 This parameter can be a value between 0 and 255 */ 193 uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. 194 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 195 uint32_t LatencyMode; /*!< It configures the latency mode. 196 This parameter can be a value of @ref OSPI_LatencyMode */ 197 } OSPI_HyperbusCfgTypeDef; 198 199 /** 200 * @brief HAL OSPI Hyperbus Command Structure definition 201 */ 202 typedef struct 203 { 204 uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. 205 This parameter can be a value of @ref OSPI_AddressSpace */ 206 uint32_t Address; /*!< It contains the address to be sent tot he device. 207 This parameter can be a value between 0 and 0xFFFFFFFF */ 208 uint32_t AddressSize; /*!< It indicates the size of the address. 209 This parameter can be a value of @ref OSPI_AddressSize */ 210 uint32_t NbData; /*!< It indicates the number of data transferred with this command. 211 This field is only used for indirect mode. 212 This parameter can be a value between 1 and 0xFFFFFFFF 213 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 214 uint32_t DQSMode; /*!< It enables or not the data strobe management. 215 This parameter can be a value of @ref OSPI_DQSMode */ 216 } OSPI_HyperbusCmdTypeDef; 217 218 /** 219 * @brief HAL OSPI Auto Polling mode configuration structure definition 220 */ 221 typedef struct 222 { 223 uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. 224 This parameter can be any value between 0 and 0xFFFFFFFF */ 225 uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. 226 This parameter can be any value between 0 and 0xFFFFFFFF */ 227 uint32_t MatchMode; /*!< Specifies the method used for determining a match. 228 This parameter can be a value of @ref OSPI_MatchMode */ 229 uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. 230 This parameter can be a value of @ref OSPI_AutomaticStop */ 231 uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. 232 This parameter can be any value between 0 and 0xFFFF */ 233 } OSPI_AutoPollingTypeDef; 234 235 /** 236 * @brief HAL OSPI Memory Mapped mode configuration structure definition 237 */ 238 typedef struct 239 { 240 uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. 241 This parameter can be a value of @ref OSPI_TimeOutActivation */ 242 uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. 243 This parameter can be any value between 0 and 0xFFFF */ 244 } OSPI_MemoryMappedTypeDef; 245 246 /** 247 * @brief HAL OSPI IO Manager Configuration structure definition 248 */ 249 typedef struct 250 { 251 uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. 252 This parameter can be a value between 1 and 8 */ 253 uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. 254 This parameter can be a value between 0 and 8, 0 means that signal not used */ 255 uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. 256 This parameter can be a value between 1 and 8 */ 257 uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 258 This parameter can be a value of @ref OSPIM_IOPort */ 259 uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 260 This parameter can be a value of @ref OSPIM_IOPort */ 261 uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected 262 if some signals are multiplexed in the OSPI IO Manager with the other OSPI. 263 This parameter can be a value between 1 and 256 */ 264 } OSPIM_CfgTypeDef; 265 266 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 267 /** 268 * @brief HAL OSPI Callback ID enumeration definition 269 */ 270 typedef enum 271 { 272 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 273 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 274 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 275 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 276 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 277 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 278 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 279 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 280 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 281 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 282 283 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 284 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 285 } HAL_OSPI_CallbackIDTypeDef; 286 287 /** 288 * @brief HAL OSPI Callback pointer definition 289 */ 290 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 291 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 292 /** 293 * @} 294 */ 295 296 /* Exported constants --------------------------------------------------------*/ 297 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 298 * @{ 299 */ 300 301 /** @defgroup OSPI_State OSPI State 302 * @{ 303 */ 304 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 305 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 306 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 307 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 308 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 309 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 310 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 311 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 312 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 313 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 314 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 315 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 316 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup OSPI_ErrorCode OSPI Error Code 322 * @{ 323 */ 324 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 325 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 326 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 327 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 328 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 329 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 330 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 331 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 332 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 333 /** 334 * @} 335 */ 336 337 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 338 * @{ 339 */ 340 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 341 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 342 /** 343 * @} 344 */ 345 346 /** @defgroup OSPI_MemoryType OSPI Memory Type 347 * @{ 348 */ 349 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 350 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 351 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ 352 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 353 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 359 * @{ 360 */ 361 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 362 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 363 /** 364 * @} 365 */ 366 367 /** @defgroup OSPI_ClockMode OSPI Clock Mode 368 * @{ 369 */ 370 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 371 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 372 /** 373 * @} 374 */ 375 376 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 377 * @{ 378 */ 379 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 380 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 381 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 382 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 383 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 384 /** 385 * @} 386 */ 387 388 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 389 * @{ 390 */ 391 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 392 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 398 * @{ 399 */ 400 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 401 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas 407 * @{ 408 */ 409 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ 410 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ 411 /** 412 * @} 413 */ 414 415 /** @defgroup OSPI_OperationType OSPI Operation Type 416 * @{ 417 */ 418 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 419 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 420 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 421 #define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ 422 /** 423 * @} 424 */ 425 426 /** @defgroup OSPI_FlashID OSPI Flash Id 427 * @{ 428 */ 429 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 430 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 431 /** 432 * @} 433 */ 434 435 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 436 * @{ 437 */ 438 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 439 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 440 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 441 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 442 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 443 /** 444 * @} 445 */ 446 447 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 448 * @{ 449 */ 450 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 451 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 452 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 453 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 454 /** 455 * @} 456 */ 457 458 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 459 * @{ 460 */ 461 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 462 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup OSPI_AddressMode OSPI Address Mode 468 * @{ 469 */ 470 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 471 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 472 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 473 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 474 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 475 /** 476 * @} 477 */ 478 479 /** @defgroup OSPI_AddressSize OSPI Address Size 480 * @{ 481 */ 482 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 483 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 484 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 485 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 486 /** 487 * @} 488 */ 489 490 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 491 * @{ 492 */ 493 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 494 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 495 /** 496 * @} 497 */ 498 499 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 500 * @{ 501 */ 502 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 503 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 504 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 505 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 506 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 507 /** 508 * @} 509 */ 510 511 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 512 * @{ 513 */ 514 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 515 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 516 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 517 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 518 /** 519 * @} 520 */ 521 522 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 523 * @{ 524 */ 525 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 526 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 527 /** 528 * @} 529 */ 530 531 /** @defgroup OSPI_DataMode OSPI Data Mode 532 * @{ 533 */ 534 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 535 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 536 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 537 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 538 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 539 /** 540 * @} 541 */ 542 543 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 544 * @{ 545 */ 546 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 547 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 548 /** 549 * @} 550 */ 551 552 /** @defgroup OSPI_DQSMode OSPI DQS Mode 553 * @{ 554 */ 555 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 556 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 557 /** 558 * @} 559 */ 560 561 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 562 * @{ 563 */ 564 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 565 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 566 /** 567 * @} 568 */ 569 570 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 571 * @{ 572 */ 573 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 574 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 575 /** 576 * @} 577 */ 578 579 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 580 * @{ 581 */ 582 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 583 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 584 /** 585 * @} 586 */ 587 588 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 589 * @{ 590 */ 591 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 592 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 593 /** 594 * @} 595 */ 596 597 /** @defgroup OSPI_MatchMode OSPI Match Mode 598 * @{ 599 */ 600 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 601 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 602 /** 603 * @} 604 */ 605 606 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 607 * @{ 608 */ 609 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 610 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 611 /** 612 * @} 613 */ 614 615 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 616 * @{ 617 */ 618 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 619 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 620 /** 621 * @} 622 */ 623 624 /** @defgroup OSPI_Flags OSPI Flags 625 * @{ 626 */ 627 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 628 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 629 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 630 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 631 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 632 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 633 /** 634 * @} 635 */ 636 637 /** @defgroup OSPI_Interrupts OSPI Interrupts 638 * @{ 639 */ 640 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 641 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 642 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 643 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 644 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 645 /** 646 * @} 647 */ 648 649 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 650 * @{ 651 */ 652 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 653 /** 654 * @} 655 */ 656 657 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port 658 * @{ 659 */ 660 #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ 661 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ 662 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ 663 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ 664 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ 665 #define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */ 666 #define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */ 667 #define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */ 668 #define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */ 669 #define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */ 670 #define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */ 671 #define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */ 672 #define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */ 673 #define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */ 674 #define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */ 675 #define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */ 676 #define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */ 677 /** 678 * @} 679 */ 680 /** 681 * @} 682 */ 683 684 /* Exported macros -----------------------------------------------------------*/ 685 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 686 * @{ 687 */ 688 /** @brief Reset OSPI handle state. 689 * @param __HANDLE__ specifies the OSPI Handle. 690 * @retval None 691 */ 692 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 693 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 694 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 695 (__HANDLE__)->MspInitCallback = NULL; \ 696 (__HANDLE__)->MspDeInitCallback = NULL; \ 697 } while(0) 698 #else 699 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 700 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 701 702 /** @brief Enable the OSPI peripheral. 703 * @param __HANDLE__ specifies the OSPI Handle. 704 * @retval None 705 */ 706 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 707 708 /** @brief Disable the OSPI peripheral. 709 * @param __HANDLE__ specifies the OSPI Handle. 710 * @retval None 711 */ 712 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 713 714 /** @brief Enable the specified OSPI interrupt. 715 * @param __HANDLE__ specifies the OSPI Handle. 716 * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. 717 * This parameter can be one of the following values: 718 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 719 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 720 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 721 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 722 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 723 * @retval None 724 */ 725 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 726 727 728 /** @brief Disable the specified OSPI interrupt. 729 * @param __HANDLE__ specifies the OSPI Handle. 730 * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. 731 * This parameter can be one of the following values: 732 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 733 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 734 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 735 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 736 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 737 * @retval None 738 */ 739 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 740 741 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 742 * @param __HANDLE__ specifies the OSPI Handle. 743 * @param __INTERRUPT__ specifies the OSPI interrupt source to check. 744 * This parameter can be one of the following values: 745 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 746 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 747 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 748 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 749 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 750 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 751 */ 752 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR,(__INTERRUPT__)) \ 753 == (__INTERRUPT__)) 754 755 /** 756 * @brief Check whether the selected OSPI flag is set or not. 757 * @param __HANDLE__ specifies the OSPI Handle. 758 * @param __FLAG__ specifies the OSPI flag to check. 759 * This parameter can be one of the following values: 760 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 761 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 762 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 763 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 764 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 765 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 766 * @retval None 767 */ 768 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ 769 != 0U) ? SET : RESET) 770 771 /** @brief Clears the specified OSPI's flag status. 772 * @param __HANDLE__ specifies the OSPI Handle. 773 * @param __FLAG__ specifies the OSPI clear register flag that needs to be set 774 * This parameter can be one of the following values: 775 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 776 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 777 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 778 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 779 * @retval None 780 */ 781 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 782 783 /** 784 * @} 785 */ 786 787 /* Exported functions --------------------------------------------------------*/ 788 /** @addtogroup OSPI_Exported_Functions 789 * @{ 790 */ 791 792 /* Initialization/de-initialization functions ********************************/ 793 /** @addtogroup OSPI_Exported_Functions_Group1 794 * @{ 795 */ 796 HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); 797 void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi); 798 HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi); 799 void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi); 800 801 /** 802 * @} 803 */ 804 805 /* IO operation functions *****************************************************/ 806 /** @addtogroup OSPI_Exported_Functions_Group2 807 * @{ 808 */ 809 /* OSPI IRQ handler function */ 810 void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi); 811 812 /* OSPI command configuration functions */ 813 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 814 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 815 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 816 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 817 818 /* OSPI indirect mode functions */ 819 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 820 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 821 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 822 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); 823 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 824 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); 825 826 /* OSPI status flag polling mode functions */ 827 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 828 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 829 830 /* OSPI memory-mapped mode functions */ 831 HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 832 833 /* Callback functions in non-blocking modes ***********************************/ 834 void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi); 835 void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi); 836 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 837 838 /* OSPI indirect mode functions */ 839 void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi); 840 void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi); 841 void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi); 842 void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi); 843 void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi); 844 845 /* OSPI status flag polling mode functions */ 846 void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi); 847 848 /* OSPI memory-mapped mode functions */ 849 void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi); 850 851 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) 852 /* OSPI callback registering/unregistering */ 853 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, 854 pOSPI_CallbackTypeDef pCallback); 855 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 856 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 857 /** 858 * @} 859 */ 860 861 /* Peripheral Control and State functions ************************************/ 862 /** @addtogroup OSPI_Exported_Functions_Group3 863 * @{ 864 */ 865 HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); 866 HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi); 867 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold); 868 uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi); 869 HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout); 870 uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi); 871 uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi); 872 873 /** 874 * @} 875 */ 876 877 /* OSPI IO Manager configuration function ************************************/ 878 /** @addtogroup OSPI_Exported_Functions_Group4 879 * @{ 880 */ 881 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 882 883 /** 884 * @} 885 */ 886 887 888 /* OSPI Delay Block function ************************************/ 889 /** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function 890 * @{ 891 */ 892 HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); 893 HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); 894 HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); 895 896 /** 897 * @} 898 */ 899 /** 900 * @} 901 */ 902 903 /** 904 * @} 905 */ 906 907 /* End of exported functions -------------------------------------------------*/ 908 909 /* Private macros ------------------------------------------------------------*/ 910 /** 911 @cond 0 912 */ 913 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 914 915 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 916 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 917 918 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 919 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 920 ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ 921 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ 922 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 923 924 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 925 926 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 927 928 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 929 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 930 931 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 932 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 933 934 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 935 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 936 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 937 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 938 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 939 940 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 941 942 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 943 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 944 945 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 946 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 947 948 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 949 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 950 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \ 951 ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG)) 952 953 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ 954 ((FLASHID) == HAL_OSPI_FLASH_ID_2)) 955 956 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 957 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 958 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 959 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 960 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 961 962 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 963 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 964 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 965 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 966 967 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 968 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 969 970 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 971 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 972 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 973 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 974 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 975 976 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 977 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 978 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 979 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 980 981 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 982 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 983 984 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 985 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 986 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 987 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 988 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 989 990 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 991 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 992 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 993 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 994 995 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 996 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 997 998 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 999 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 1000 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 1001 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 1002 ((MODE) == HAL_OSPI_DATA_8_LINES)) 1003 1004 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 1005 1006 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 1007 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 1008 1009 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 1010 1011 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 1012 ((MODE) == HAL_OSPI_DQS_ENABLE)) 1013 1014 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 1015 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 1016 1017 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 1018 1019 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 1020 1021 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 1022 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 1023 1024 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 1025 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 1026 1027 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 1028 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 1029 1030 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 1031 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 1032 1033 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 1034 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 1035 1036 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 1037 1038 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 1039 1040 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 1041 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 1042 1043 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 1044 1045 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 1046 1047 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ 1048 ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) 1049 1050 #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) 1051 1052 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) 1053 1054 #define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) 1055 1056 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ 1057 ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 1058 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 1059 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 1060 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ 1061 ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \ 1062 ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \ 1063 ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \ 1064 ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \ 1065 ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \ 1066 ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \ 1067 ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \ 1068 ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \ 1069 ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \ 1070 ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \ 1071 ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \ 1072 ((PORT) == HAL_OSPIM_IOPORT_8_HIGH)) 1073 1074 #if defined (OCTOSPIM_CR_MUXEN) 1075 #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) 1076 #endif /*(OCTOSPIM_CR_MUXEN)*/ 1077 /** 1078 @endcond 1079 */ 1080 1081 /* End of private macros -----------------------------------------------------*/ 1082 1083 /** 1084 * @} 1085 */ 1086 1087 /** 1088 * @} 1089 */ 1090 1091 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 1092 1093 #ifdef __cplusplus 1094 } 1095 #endif 1096 1097 #endif /* STM32U5xx_HAL_OSPI_H */ 1098 1099
