1 /***************************************************************************//** 2 * \file cy_sysclk.h 3 * \version 3.70 4 * 5 * Provides an API declaration of the sysclk driver. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 /** 27 * \addtogroup group_sysclk 28 * \{ 29 * The System Clock (SysClk) driver contains the API for configuring system and 30 * peripheral clocks. 31 * 32 * The functions and other declarations used in this driver are in cy_sysclk.h. 33 * You can include cy_pdl.h to get access to all functions 34 * and declarations in the PDL. 35 * 36 * Firmware uses the API to configure, enable, or disable a clock. 37 * 38 * The clock system includes a variety of resources that can vary per device, including: 39 * - Internal clock sources such as internal oscillators 40 * - External clock sources such as crystal oscillators or a signal on an I/O pin 41 * - Generated clocks such as an FLL, a PLL, and peripheral clocks 42 * 43 * Consult the Technical Reference Manual for your device for details of the 44 * clock system. 45 * 46 * The PDL defines clock system capabilities in:\n 47 * devices/COMPONENT_CAT1\<subcategory\>/include/\<series\>_config.h. (E.g. 48 * devices/COMPONENT_CAT1A/include/psoc6_01_config.h). 49 * 50 * As an illustration of the clocking system, the following diagram shows the 51 * PSoC 63 series clock tree. The actual tree may vary depending on the device series. 52 * Consult the Technical Reference Manual for your device for details. 53 *  54 * 55 * The sysclk driver supports multiple peripheral clocks, as well as the fast 56 * clock, slow clock, backup domain clock, timer clock, and pump clock. The API 57 * for any given clock contains the functions to manage that clock. Functions 58 * for clock measurement and trimming are also provided. 59 * 60 * \section group_sysclk_configuration Configuration Considerations 61 * The availability of clock functions depend on the availability of the chip 62 * resources that support those functions. Consult the device TRM before 63 * attempting to use these functions. 64 * For PSoC 64 devices the clocks configurations are restricted and limited. 65 * Refer to the PRA driver, and the TRM and datasheet for details. 66 * 67 * \warning 68 * On the diagram above, the yellow muxes are glitch-safe. All glitch-safe 69 * mux transitions take four cycles of the source clock. 70 * It is not allowed to turn off the source clock during that time. 71 * 72 * PSoC 6 power modes limit the maximum clock frequency. 73 * Refer to the SysPm driver and the TRM for details. 74 * 75 * \section group_sysclk_more_information More Information 76 * Refer to the technical reference manual (TRM) and the device datasheet. 77 * 78 * \section group_sysclk_changelog Changelog 79 * <table class="doxtable"> 80 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 81 * <tr> 82 * <td>3.70</td> 83 * <td>Added new APIs \ref Cy_SysClk_ClkPwrSetDivider, \ref Cy_SysClk_ClkPwrGetDivider, \ref Cy_SysClk_ClkPwrGetFrequency, \ref Cy_SysClk_ClkPwrSetSource, \ref Cy_SysClk_ClkPwrGetSource. \n and enum \ref cy_en_clkpwr_in_sources_t </td> 84 * <td>Support Added for future devices of the CAT1B.</td> 85 * </tr> 86 * <tr> 87 * <td rowspan="2">3.60</td> 88 * <td>Support for CAT1D devices is added</td> 89 * <td>New devices support added</td> 90 * </tr> 91 * <tr> 92 * <td>Remove local structure initialization to avoid optimization</td> 93 * <td>Code cleanup</td> 94 * </tr> 95 * <tr> 96 * <td>3.50</td> 97 * <td> 98 * Bug fixes and few new APIs addition.<br>Newly added APIs: 99 * \n Cy_SysClk_PllGetFrequency() for CAT1A,CAT1C and CAT1D devices, 100 * \n Cy_SysClk_Pll200MGetFrequency() for CAT1C devices, 101 * \n Cy_SysClk_Pll400MGetFrequency() for CAT1C devices, 102 * \n Cy_SysClk_ImoEnable() for CAT1D devices, 103 * \n Cy_SysClk_ImoDisable() for CAT1D devices, 104 * \n Cy_SysClk_ImoIsEnabled() for CAT1D devices, 105 * \n Cy_SysClk_ImoDeepsleepEnable() for CAT1D devices, 106 * \n Cy_SysClk_ImoIsDeepsleepEnabled() for CAT1D devices, 107 * \n Cy_SysClk_ImoDeepsleepDisable() for CAT1D devices, 108 * \n Cy_SysClk_ClkFastSrcGetDivider() for CAT1C devices, 109 * \n Cy_SysClk_ClkFastSrcSetDivider() for CAT1C devices, 110 * \n Cy_SysClk_ClkFastSrcGetFrequency() for CAT1C devices, 111 * </td> 112 * <td>Bug fixes and new devices support.</td> 113 * </tr> 114 * <tr> 115 * <td rowspan="3">3.40</td> 116 * <td> 117 * Added CAT1C and CAT1D devices support. 118 * </td> 119 * <td>Support for new devices.</td> 120 * </tr> 121 * <tr> 122 * <td>New API's for PLL400M and PLL200M.</td> 123 * <td>To handle the new PLL's for CAT1C devices.</td> 124 * </tr> 125 * <tr> 126 * <td>New API's Added 127 * * Cy_SysClk_Pll200MConfigure() 128 * * Cy_SysClk_Pll200MManualConfigure() 129 * * Cy_SysClk_Pll200MGetConfiguration() 130 * * Cy_SysClk_Pll200MEnable() 131 * * Cy_SysClk_Pll200MIsEnabled() 132 * * Cy_SysClk_Pll200MLocked() 133 * * Cy_SysClk_Pll200MLostLock() 134 * * Cy_SysClk_Pll200MDisable() 135 * * Cy_SysClk_Pll400MConfigure() 136 * * Cy_SysClk_Pll400MManualConfigure() 137 * * Cy_SysClk_Pll400MGetConfiguration() 138 * * Cy_SysClk_Pll400MEnable() 139 * * Cy_SysClk_Pll400MIsEnabled() 140 * * Cy_SysClk_Pll400MLocked() 141 * * Cy_SysClk_Pll400MLostLock() 142 * * Cy_SysClk_Pll200MDisable() 143 * * Cy_SysClk_IhoDeepsleepEnable() 144 * * Cy_SysClk_IhoIsDeepsleepEnabled() 145 * * Cy_SysClk_IhoDeepsleepDisable() 146 * * Cy_SysClk_IloSrcEnable() 147 * * Cy_SysClk_IloSrcIsEnabled() 148 * * Cy_SysClk_IloSrcDisable() 149 * * Cy_SysClk_IloSrcHibernateOn() 150 * * Cy_SysClk_PiloBackupEnable() 151 * * Cy_SysClk_PiloBackupDisable() 152 * * Cy_SysClk_PiloTcscEnable() 153 * * Cy_SysClk_PiloTcscDisable() 154 * * Cy_SysClk_AltHfEnable() 155 * * Cy_SysClk_IsAltHfEnabled() 156 * * Cy_SysClk_IloSetTrim() 157 * * Cy_SysClk_IloGetTrim() 158 * * Cy_SysClk_ClkMfSetSource() 159 * * Cy_SysClk_ClkMfGetSource() 160 * * Cy_SysClk_ClkHfDirectSel() 161 * * Cy_SysClk_IsClkHfDirectSelEnabled() 162 * * Cy_SysClk_PeriGroupGetSlaveCtl() 163 * * Cy_SysClk_IsPeriGroupSlaveCtlSet() 164 * * Cy_SysClk_PeriPclkGetFrequency() 165 * * Cy_SysClk_PeriPclkGetDividerEnabled() 166 * * Cy_Sysclk_PeriPclkGetClkHfNum() 167 * * Cy_SysClk_ClkMemSetDivider() 168 * * Cy_SysClk_ClkMemGetDivider() 169 * * Cy_SysClk_ClkMemGetFrequency() 170 * 171 * </td> 172 * <td>New API's to handle CAT1B, CAT1C and CAT1D devices.</td> 173 * </tr> 174 * <tr> 175 * <td rowspan="3">3.30</td> 176 * <td> 177 * For PSoC64 device, allow CM0+ to call CY_PRA_FUNCTION_CALL_X_X API in functions 178 * accessing FUNCTION_POLICY registers. So that System Configuration structure is 179 * updated with new parameters. 180 * </td> 181 * <td>For PSoC64 device, System configuration can be done from CM0+ application.</td> 182 * </tr> 183 * <tr> 184 * <td>Fixed MISRA 2012 violations.</td> 185 * <td>MISRA 2012 compliance.</td> 186 * </tr> 187 * <tr> 188 * <td>Return type doxygen updated for PSoC64 devices.</td> 189 * <td>Doxygen update for PSoC64 devices.</td> 190 * </tr> 191 * <tr> 192 * <td>3.20</td> 193 * <td>Added new API's \ref Cy_SysClk_FllGetFrequency and \ref Cy_SysClk_PllGetFrequency.</td> 194 * <td>Fetch the FLL and PLL frequency.</td> 195 * </tr> 196 * <tr> 197 * <td>3.10</td> 198 * <td>Support for CM33.</td> 199 * <td>New devices support.</td> 200 * </tr> 201 * <tr> 202 * <td rowspan="2">3.0</td> 203 * <td>The behavior of \ref Cy_SysClk_EcoEnable and \ref Cy_SysClk_PllEnable is changed - 204 * these functions disable the resource in case of enabling failure (timeout).</td> 205 * <td>Usability enhancement.</td> 206 * </tr> 207 * <tr> 208 * <td>The implementation of \ref Cy_SysClk_ClkPathGetSource, 209 * \ref Cy_SysClk_FllConfigure, 210 * \ref Cy_SysClk_FllGetConfiguration, 211 * \ref Cy_SysClk_PllConfigure 212 * and \ref Cy_SysClk_ClkMeasurementCountersGetFreq 213 * is updated in accordance to the MISRA 2012 requirements. No behavioral changes.</td> 214 * <td>MISRA 2012 compliance.</td> 215 * </tr> 216 * <tr> 217 * <td>2.20.1</td> 218 * <td>Updated source code comments.</td> 219 * <td>Documentation update.</td> 220 * </tr> 221 * <tr> 222 * <td rowspan="3">2.20</td> 223 * <td>Added the assertion mechanism to the following functions: 224 * * Cy_SysClk_EcoDisable() 225 * * Cy_SysClk_IloEnable() 226 * * Cy_SysClk_IloHibernateOn() 227 * * Cy_SysClk_PiloEnable() 228 * * Cy_SysClk_PiloDisable() 229 * * Cy_SysClk_WcoDisable() 230 * * Cy_SysClk_WcoBypass() 231 * * Cy_SysClk_ClkFastSetDivider() 232 * * Cy_SysClk_ClkPeriSetDivider() 233 * * Cy_SysClk_ClkLfSetSource() 234 * * Cy_SysClk_ClkTimerSetSource() 235 * * Cy_SysClk_ClkTimerSetDivider() 236 * * Cy_SysClk_ClkTimerEnable() 237 * * Cy_SysClk_ClkTimerDisable() 238 * * Cy_SysClk_ClkPumpSetSource() 239 * * Cy_SysClk_ClkPumpSetDivider() 240 * * Cy_SysClk_ClkPumpEnable() 241 * * Cy_SysClk_ClkPumpDisable() 242 * * Cy_SysClk_ClkBakSetSource() 243 * 244 * Now, the functions described above halt in assertion when a PRA 245 * request returns not successful operation. This change is 246 * applicable only for the PSoC 64 family devices. 247 * </td> 248 * <td>Enhancements for the debugging process.</td> 249 * </tr> 250 * <tr> 251 * <td>Added \ref Cy_SysClk_PiloInitialTrim and \ref Cy_SysClk_PiloUpdateTrimStep functions. 252 * Extended the \ref Cy_SysClk_PiloTrim function to use the step-size value calculated for PILO 253 * based on the \ref Cy_SysClk_PiloInitialTrim and \ref Cy_SysClk_PiloUpdateTrimStep 254 * functions call. </td> 255 * </td> 256 * <td>User experience enhancement.</td> 257 * </tr> 258 * <tr> 259 * <td> 260 * * Added the warning that during a glitch-safe mux, the transition is not allowed 261 * to disable the previous clock source. See more info 262 * in the \ref group_sysclk_configuration. 263 * * Removed Known Issues table. 264 * </td> 265 * <td>Documentation updates.</td> 266 * </tr> 267 * <tr> 268 * <td rowspan="3">2.10</td> 269 * <td>Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return 270 * PRA driver status value.</td> 271 * <td>The SysClk driver uses the PRA driver to change the protected registers. 272 * A SysClk driver function that calls a PRA driver function will return the PRA 273 * error status code if the called PRA function returns an error. In these cases, 274 * refer to PRA return statuses. Refer to functions description for details.</td> 275 * </tr> 276 * <tr> 277 * <td>Updated the code of \ref Cy_SysClk_ClkPathGetFrequency function.</td> 278 * <td>Make the code more error-resistant to user errors for some corner cases.</td> 279 * </tr> 280 * <tr> 281 * <td>Minor documentation updates.</td> 282 * <td>Documentation enhancement.</td> 283 * </tr> 284 * <tr> 285 * <td>2.0</td> 286 * <td>Updated the ECO trimming values calculation algorithm in the \ref Cy_SysClk_EcoConfigure implementation. \n 287 * This change may invalidate the already used crystals, in cases: \n 288 * * The crystal frequency is less than 16 MHz. \n 289 * * The maximum amplitude (internal calculation value) is less than 0.65 V. \n 290 * 291 * For detail, refer the \ref Cy_SysClk_EcoConfigure documentation and the ECO Trimming section of the device TRM.</td> 292 * <td>Enhanced the ECO performance for high-noise conditions that result from simultaneous switching of GPIOs and/or high switching activity on the chip.</td> 293 * </tr> 294 * <tr> 295 * <td>1.60</td> 296 * <td>Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n 297 * \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n 298 * \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n 299 * \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n 300 * \ref Cy_SysClk_ClkPumpGetFrequency.</td> 301 * <td>API enhancement.</td> 302 * </tr> 303 * <tr> 304 * <td>1.50</td> 305 * <td>\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.</td> 306 * <td>API enhancement.</td> 307 * </tr> 308 * <tr> 309 * <td>1.40.2</td> 310 * <td>Update documentation based on collateral review feedback.</td> 311 * <td>User experience enhancement.</td> 312 * </tr> 313 * <tr> 314 * <td>1.40.1</td> 315 * <td>Fix compiler warning.</td> 316 * <td></td> 317 * </tr> 318 * <tr> 319 * <td rowspan="4">1.40</td> 320 * <td>Updated the following functions implementation: \ref Cy_SysClk_PllConfigure and \ref Cy_SysClk_PllEnable.</td> 321 * <td> 322 * Fixed the \ref Cy_SysClk_PllConfigure API function behaviour when it is called with a bypass mode, \n 323 * Fixed the \ref Cy_SysClk_PllEnable API function behaviour when it is called with a zero timeout. 324 * </td> 325 * </tr> 326 * <tr> 327 * <td>Added the following functions: \ref Cy_SysClk_MfoEnable, \ref Cy_SysClk_MfoIsEnabled,\n 328 * \ref Cy_SysClk_MfoDisable, \ref Cy_SysClk_ClkMfEnable, \ref Cy_SysClk_ClkMfIsEnabled,\n 329 * \ref Cy_SysClk_ClkMfDisable, \ref Cy_SysClk_ClkMfGetDivider, \ref Cy_SysClk_ClkMfSetDivider,\n. 330 * \ref Cy_SysClk_ClkMfGetFrequency</td> 331 * <td>New device support.</td> 332 * </tr> 333 * <tr> 334 * <td>Added the following new API functions \ref Cy_SysClk_FllIsEnabled, \ref Cy_SysClk_PllIsEnabled,\n 335 * \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_ClkHfGetFrequency, \ref Cy_SysClk_ClkFastGetFrequency,\n 336 * \ref Cy_SysClk_ClkPeriGetFrequency and \ref Cy_SysClk_ClkSlowGetFrequency</td> 337 * <td>Enhancement based on usability feedback</td> 338 * </tr> 339 * <tr> 340 * <td>Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUP</td> 341 * <td>Macros were moved into \ref group_syslib</td> 342 * </tr> 343 * <tr> 344 * <td rowspan="2">1.30</td> 345 * <td>Updated the following functions implementation: \ref Cy_SysClk_EcoConfigure and \ref Cy_SysClk_FllConfigure.</td> 346 * <td>Math library dependency is removed, the floating-point math is replaced with integer math.</td> 347 * </tr> 348 * <tr> 349 * <td>Updated the following functions implementation: \ref Cy_SysClk_EcoEnable, \ref Cy_SysClk_EcoGetStatus, \ref Cy_SysClk_FllGetConfiguration \n 350 * and \ref Cy_SysClk_DeepSleepCallback. \n 351 * The \ref Cy_SysClk_DeepSleepCallback now implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. \n 352 * The actions that were done in \ref CY_SYSPM_CHECK_READY case are moved to \ref CY_SYSPM_BEFORE_TRANSITION. \n 353 * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL.</td> 354 * <td>Defect fixing.</td> 355 * </tr> 356 * <tr> 357 * <td rowspan="4">1.20</td> 358 * <td>Flattened the organization of the driver source code into the single 359 * source directory and the single include directory. 360 * </td> 361 * <td>Driver library directory-structure simplification.</td> 362 * </tr> 363 * <tr> 364 * <td>Updated \ref Cy_SysClk_FllLocked function description</td> 365 * <td>The SRSS_ver1 HW details clarification</td> 366 * </tr> 367 * <tr> 368 * <td>Removed the following functions: 369 * - Cy_SysClk_FllLostLock 370 * - Cy_SysClk_WcoConfigureCsv 371 * - Cy_SysClk_ClkHfConfigureCsv 372 * </td> 373 * <td>No hardware support for the removed functions.</td> 374 * </tr> 375 * <tr> 376 * <td>Added register access layer. Use register access macros instead 377 * of direct register access using dereferenced pointers.</td> 378 * <td>Makes register access device-independent, so that the PDL does 379 * not need to be recompiled for each supported part number.</td> 380 * </tr> 381 * <tr> 382 * <td>1.11</td> 383 * <td>Updated the following functions. Now they use a semaphore when 384 * try to read the status or configure the SysClk measurement counters: 385 * * Cy_SysClk_StartClkMeasurementCounters() 386 * * Cy_SysClk_ClkMeasurementCountersGetFreq() 387 * 388 * Now Cy_SysClk_ClkMeasurementCountersGetFreq() returns zero value, 389 * if during measurement device was in the Deep Sleep or partially 390 * blocking flash operation occurred </td> 391 * <td>Added arbiter mechanism for correct usage of the SysClk measurement 392 * counters</td> 393 * </tr> 394 * <tr> 395 * <td>1.10.1</td> 396 * <td>Renamed Power Management section to Low Power Callback section</td> 397 * <td>Documentation update and clarification</td> 398 * </tr> 399 * <tr> 400 * <td rowspan="5">1.10</td> 401 * <td>Updated FLL parameter calculation</td> 402 * <td>Support low frequency sources</td> 403 * </tr> 404 * <tr> 405 * <td>Added Cy_SysClk_PiloSetTrim() and Cy_SysclkPiloGetTrim() functions</td> 406 * <td>Support PILO manual trims</td> 407 * </tr> 408 * <tr> 409 * <td>Made Cy_SysClk_FllLostLock() function dependent on SRSS v1</td> 410 * <td>Feature is not supported in SRSS v1</td> 411 * </tr> 412 * <tr> 413 * <td>Updated Cy_SysClk_DeepSleepCallback() to save/restore both FLL and PLL settings</td> 414 * <td>The function should return when the lock is established or a timeout has occurred</td> 415 * </tr> 416 * <tr> 417 * <td>General documentation updates</td> 418 * <td></td> 419 * </tr> 420 * <tr> 421 * <td>1.0</td> 422 * <td>Initial version</td> 423 * <td></td> 424 * </tr> 425 * </table> 426 * 427 * \defgroup group_sysclk_macros Macros 428 * \{ 429 * \} 430 * \defgroup group_sysclk_enums General Enumerated Types 431 * \{ 432 * \defgroup group_sysclk_returns Function return values 433 * \} 434 * \defgroup group_sysclk_ext External Clock Source (EXTCLK) 435 * \{ 436 * The External Clock Source (EXTCLK) is a clock source routed into SOC 437 * through a GPIO pin. The EXTCLK is a source clock that can be used to 438 * source one or more clock paths (Refer to \ref group_sysclk_path_src). 439 * These clock paths can then source the processors and peripherals in 440 * the device. 441 * 442 * The EXTCLK relies on the presence of an external clock signal applied 443 * to the GPIO pin. The pin must be configured to operate in Digital 444 * High-Z drive mode with input buffer on and HSIOM connection 445 * set to HSIOM_SEL_ACT_4. 446 * 447 * \defgroup group_sysclk_ext_funcs Functions 448 * \} 449 * \defgroup group_sysclk_eco External Crystal Oscillator (ECO) 450 * \{ 451 * The External Crystal Oscillator (ECO) is a clock source that consists 452 * of an oscillator circuit that drives an external crystal through its 453 * dedicated ECO pins. The ECO is a source clock that can be used to 454 * source one or more clock paths (Refer to \ref group_sysclk_path_src). 455 * These clock paths can then source the processors and peripherals in 456 * the device. 457 * 458 * The ECO relies on the presence of an external crystal. The pins 459 * connected to this crystal must be configured to operate in analog 460 * drive mode with HSIOM connection set to GPIO control (HSIOM_SEL_GPIO). 461 * 462 * \defgroup group_sysclk_eco_funcs Functions 463 * \defgroup group_sysclk_eco_enums Enumerated Types 464 * \} 465 * \defgroup group_sysclk_path_src Clock Path Source 466 * \{ 467 * Clock paths are a series of multiplexers that allow a source clock 468 * to drive multiple clocking resources down the chain. These paths are 469 * used for active domain clocks that are not operational during chip 470 * Deep Sleep, hibernate and off modes. Illustrated below is a diagram 471 * of the clock paths for the PSoC 63 series, showing the first three 472 * clock paths. The source clocks for these paths are highlighted in 473 * the red box. 474 * 475 * - IMO: 8 MHz Internal Main Oscillator (Default) 476 * - EXTCLK: External clock (signal brought in through dedicated pins) 477 * - ECO: External Crystal Oscillator (requires external crystal on dedicated pins) 478 * - ALTHF: Select on-chip signals (e.g. \ref group_ble_clk) 479 * - Digital Signal (DSI): Digital signal from a UDB source 480 * 481 * Some clock paths such as path 0 and path 1 have additional resources 482 * that can be utilized to provide a higher frequency clock. For example, 483 * path 0 source clock can be used as the reference clock for the FLL and 484 * path 1 source clock can be used as the reference clock for the PLL. 485 * 486 *  487 * 488 * \note The PDL driver cannot configure a clock path to use Digital Signal 489 * Interconnect (DSI) outputs as sources. This must be done through DSI 490 * configuration tool such as PSoC Creator. 491 * 492 * \defgroup group_sysclk_path_src_funcs Functions 493 * \defgroup group_sysclk_path_src_enums Enumerated Types 494 * \} 495 * \defgroup group_sysclk_fll Frequency Locked Loop (FLL) 496 * \{ 497 * The FLL is a clock generation circuit that can be used to produce a 498 * higher frequency clock from a reference clock. The output clock exhibits 499 * some characteristics of the reference clock such as the accuracy of the 500 * source. However other attributes such as the clock phase are not preserved. 501 * The FLL is similar in purpose to a (Phase locked loop) PLL but they are 502 * not equivalent. 503 * 504 * - They may have different frequency ranges. 505 * - The FLL starts up (locks) faster and consumes less current than the PLL. 506 * - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz). 507 * - The FLL does not lock phase. The hardware consist of a counter with a 508 * current-controlled oscillator (CCO). The counter counts the number of output 509 * clock edges in a reference clock period and adjusts the CCO until the 510 * expected ratio is achieved (locked). After initial lock, the CCO is 511 * adjusted dynamically to keep the ratio within tolerance. The lock tolerance 512 * is user-adjustable. 513 *  514 * 515 * The SysClk driver supports two models for configuring the FLL. The first 516 * model is to call the Cy_SysClk_FllConfigure() function, which calculates the 517 * necessary parameters for the FLL at run-time. This may be necessary for dynamic 518 * run-time changes to the FLL. However this method is slow as it needs to perform 519 * the calculation before configuring the FLL. The other model is to call 520 * Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values. 521 * This method is faster but requires prior knowledge of the necessary parameters. 522 * Consult the device TRM for the FLL calculation equations. 523 * 524 * \defgroup group_sysclk_fll_funcs Functions 525 * \defgroup group_sysclk_fll_structs Data Structures 526 * \defgroup group_sysclk_fll_enums Enumerated Types 527 * \} 528 * \defgroup group_sysclk_pll Phase Locked Loop (PLL) 529 * \{ 530 * The PLL is a clock generation circuit that can be used to produce a 531 * higher frequency clock from a reference clock. The output clock exhibits 532 * characteristics of the reference clock such as the accuracy of the source 533 * and its phase. The PLL is similar in purpose to a (Frequency locked loop) FLL 534 * but they are not equivalent. 535 * 536 * - They may have different frequency ranges. 537 * - The PLL starts up more slowly and consumes more current than the FLL. 538 * - The PLL requires a higher frequency source clock than FLL. 539 *  540 * 541 * The SysClk driver supports two models for configuring the PLL. The first 542 * model is to call the Cy_SysClk_PllConfigure() function, which calculates the 543 * necessary parameters for the PLL at run-time. This may be necessary for dynamic 544 * run-time changes to the PLL. However this method is slow as it needs to perform 545 * the calculation before configuring the PLL. The other model is to call 546 * Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values. 547 * This method is faster but requires prior knowledge of the necessary parameters. 548 * Consult the device TRM for the PLL calculation equations. 549 * 550 * \defgroup group_sysclk_pll_funcs Functions 551 * \defgroup group_sysclk_pll_structs Data Structures 552 * \} 553 * \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO) 554 * \{ 555 * The ILO operates with no external components and outputs a stable clock at 556 * 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is 557 * available in all power modes and can be used as a source for the Backup domain clock. 558 *  559 * 560 * To ensure the ILO remains active in Hibernate mode, and across power-on-reset 561 * (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn(). 562 * 563 * Additionally, the ILO clock can be trimmed to +/- 1.5% of nominal frequency using 564 * a higher precision clock source. Use the \ref group_sysclk_calclk API to measure 565 * the current ILO frequency before trimming. 566 * 567 * \note The ILO is always the source clock for the \ref group_wdt. Therefore: 568 * - The WDT must be unlocked when making an ILO function call in the PDL 569 * - It is recommended to always have the ILO enabled 570 * 571 * \defgroup group_sysclk_ilo_funcs Functions 572 * \} 573 * \defgroup group_sysclk_pilo Precision Internal Low-Speed Oscillator (PILO) 574 * \{ 575 * PILO provides a higher accuracy 32.768 kHz clock than the \ref group_sysclk_ilo "ILO". 576 * When periodically calibrated using a high-accuracy clock such as the 577 * \ref group_sysclk_eco "ECO", the PILO can achieve 250 ppm accuracy of nominal frequency. 578 * The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes. 579 * It is not available in Hibernate mode. 580 * 581 * The PILO can be used as a source for the \ref group_sysclk_clk_lf. However, 582 * because PILO is disabled in Hibernate mode, RTC timers cannot operate in this mode 583 * when clocked using the PILO. Instead, either the \ref group_sysclk_ilo "ILO" or 584 * \ref group_sysclk_wco "WCO" should be used when hibernate operation is required. 585 * 586 *  587 * 588 * Periodic calibration to a high-accuracy clock (such as ECO) is required to 589 * maintain accuracy. The application should use the functions described in the 590 * \ref group_sysclk_calclk API to measure the current PILO frequency before trimming. 591 * 592 * \defgroup group_sysclk_pilo_funcs Functions 593 * \} 594 * \defgroup group_sysclk_calclk Clock Measurement 595 * \{ 596 * These functions measure the frequency of a specified clock relative to a 597 * reference clock. They are typically called in the following order: 598 * 599 * 1. Specify the measured clock, the count, and the reference clock 600 * 2. Start the counters 601 * 3. Wait for the measurement counter to finish counting 602 * 4. Retrieve the measured frequency 603 * 604 * \note These functions may also be used as part of a clock trimming 605 * process. Refer to the \ref group_sysclk_trim "Clock Trim" API. 606 * 607 * \defgroup group_sysclk_calclk_funcs Functions 608 * \defgroup group_sysclk_calclk_enums Enumerated Types 609 * \defgroup group_sysclk_calclk_structs Data Structures 610 * \} 611 * \defgroup group_sysclk_trim Clock Trim (ILO, PILO) 612 * \{ 613 * These functions perform a single trim operation on the ILO or PILO. Each 614 * function's parameter is the actual frequency of the clock. To measure the 615 * frequency, use the functions described in the \ref group_sysclk_calclk API. 616 * 617 * To trim the clock as close as possible to the target frequency, multiple 618 * calls to the trim function may be needed. A typical usage example is to: 619 * 1. Call the clock measurement functions to get the actual frequency of the clock 620 * 2. Call the trim function, passing in the measured frequency 621 * 3. Repeat the above until the trim function reports that the clock is trimmed to within limits. 622 * 623 * \defgroup group_sysclk_trim_funcs Functions 624 * \} 625 * \defgroup group_sysclk_pm Low Power Callback 626 * \{ 627 * Entering and exiting low power modes require compatible clock configurations 628 * to be set before entering low power and restored upon wake-up and exit. The 629 * SysClk driver provides a Cy_SysClk_DeepSleepCallback() function to support 630 * Deep Sleep mode entry. 631 * 632 * This function can be called either by itself before initiating low-power mode 633 * entry or it can be used in conjunction with the SysPm driver as a registered 634 * callback. To do so, register this function as a callback before calling 635 * Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type, 636 * and call Cy_SysPm_RegisterCallback(). 637 * 638 * \note If the FLL or PLL source is the ECO, this function must be called. 639 * 640 * \defgroup group_sysclk_pm_funcs Functions 641 * \} 642 * \defgroup group_sysclk_wco Watch Crystal Oscillator (WCO) 643 * \{ 644 * The WCO is a highly accurate 32.768 kHz clock source capable of operating 645 * in all power modes (excluding the Off mode). It is the primary clock source for 646 * the backup domain clock, which is used by the real-time clock (RTC). The 647 * WCO can also be used as a source for the low-frequency clock to support other 648 * low power mode peripherals. 649 * 650 *  651 * 652 * The WCO requires the configuration of the dedicated WCO pins (SRSS_WCO_IN_PIN, 653 * SRSS_WCO_OUT_PIN). These must be configured as Analog Hi-Z drive modes and the 654 * HSIOM selection set to GPIO. The WCO can also be used in bypass mode, where 655 * an external 32.768 kHz square wave is brought in directly through the 656 * SRSS_WCO_OUT_PIN pin. 657 * 658 * \defgroup group_sysclk_wco_funcs Functions 659 * \defgroup group_sysclk_wco_enums Enumerated Types 660 * \} 661 * \defgroup group_sysclk_clk_hf High-Frequency Clocks 662 * \{ 663 * Multiple high frequency clocks (CLK_HF) are available in the device. For example, 664 * PSoC 63 series has five high-frequency root clocks. Each CLK_HF has a particular 665 * connection and chip-specific destination on the device. 666 * 667 * |Name |Description | 668 * |:--------|:-------------------------------------------------------| 669 * |CLK_HF[0]| Root clock for CPUs, PERI, and AHB infrastructure | 670 * |CLK_HF[1]| Root clock for the PDM/PCM and I2S audio subsystem | 671 * |CLK_HF[2]| Root clock for the Serial Memory Interface subsystem | 672 * |CLK_HF[3]| Root clock for USB communications | 673 * |CLK_HF[4]| Clock output on clk_ext pin (when used as an output) | 674 * 675 *  676 * 677 * Note this is a particular example. The actual tree may vary depending on the device series. 678 * Consult the Technical Reference Manual for your device for details. 679 * 680 * High frequency clocks are sourced by path clocks, which should be configured 681 * first. An exception to this rule is CLK_HF[0], which cannot be disabled. 682 * This divided clock drives the core processors and the peripherals in the system. 683 * In order to update its clock source, CLK_HF[0] source must be selected without 684 * disabling the clock. 685 * 686 *  687 * 688 * \defgroup group_sysclk_clk_hf_funcs Functions 689 * \defgroup group_sysclk_clk_hf_enums Enumerated Types 690 * \} 691 * \defgroup group_sysclk_clk_fast Fast Clock 692 * \{ 693 * The fast clock drives the "fast" processor (e.g. Cortex-M4 processor in PSoC 6). 694 * This clock is sourced by CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). 695 * A divider value of 1~256 can be used to further divide the CLK_HF[0] to a 696 * desired clock speed for the processor. 697 * 698 *  699 * 700 * \defgroup group_sysclk_clk_fast_funcs Functions 701 * \} 702 * \defgroup group_sysclk_clk_peri Peripheral Clock 703 * \{ 704 * The peripheral clock is a divided clock of CLK_HF0 (\ref group_sysclk_clk_hf "HF Clocks"). 705 * It is the source clock for the \ref group_sysclk_clk_slow, and most active domain 706 * peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256 707 * can be used to further divide the CLK_HF[0] to a desired clock speed for the peripherals. 708 * 709 *  710 * 711 * \defgroup group_sysclk_clk_peri_funcs Functions 712 * \} 713 * \defgroup group_sysclk_clk_peripheral Peripherals Clock Dividers 714 * \{ 715 * There are multiple peripheral clock dividers that, in effect, create 716 * multiple separate peripheral clocks. The available dividers vary per device 717 * series. As an example, for the PSoC 63 series there are 29 dividers: 718 * 719 * - eight 8-bit dividers 720 * - sixteen 16-bit dividers 721 * - four fractional 16.5-bit dividers (16 integer bits, 5 fractional bits) 722 * - one fractional 24.5-bit divider (24 integer bits, 5 fractional bits) 723 * 724 * 725 * The 8-bit and 16-bit dividers are integer dividers. A divider value of 1 726 * means the output frequency matches the input frequency (that is, there is 727 * no change). Otherwise the frequency is divided by the value of the divider. 728 * For example, if the input frequency is 50 MHz, and the divider is value 10, 729 * the output frequency is 5 MHz. 730 * 731 * The five fractional bits supports further precision in 1/32nd increments. For 732 * example, a divider with an integer value of 3 and a fractional value of 733 * 4 (4/32) results in a divider of 3.125. Fractional dividers are useful when 734 * a high-precision clock is required, for example, for a UART/SPI serial 735 * interface. 736 * 737 *  738 * 739 * Each peripheral can connect to any one of the programmable dividers. A 740 * particular peripheral clock divider can drive multiple peripherals. 741 * 742 * The SysClk driver also supports phase aligning two peripheral clock dividers using 743 * Cy_SysClk_PeriphEnablePhaseAlignDivider(). Alignment works for both integer 744 * and fractional dividers. The divider to which a second divider is aligned 745 * must already be enabled. 746 * 747 * \defgroup group_sysclk_clk_peripheral_funcs Functions 748 * \defgroup group_sysclk_clk_peripheral_enums Enumerated Types 749 * \} 750 * \defgroup group_sysclk_clk_slow Slow Clock 751 * \{ 752 * The slow clock is the source clock for the "slow" processor (e.g. Cortex-M0+ in PSoC 6). 753 * This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is 754 * a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider 755 * value of 1~256 can be used to further divide the Peri clock to a desired clock speed 756 * for the processor. 757 * 758 *  759 * 760 * \defgroup group_sysclk_clk_slow_funcs Functions 761 * \} 762 * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock 763 * \{ 764 * In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is 765 * connected to the system Alternative High-Frequency Clock input. In CAT1B devices, 766 * the BTSS IP will provide clock input to ALTHF. 767 * 768 * \defgroup group_sysclk_alt_hf_funcs Functions 769 * \} 770 * \defgroup group_sysclk_clk_lf Low-Frequency Clock 771 * \{ 772 * The low-frequency clock is the source clock for the \ref group_mcwdt 773 * and can be the source clock for \ref group_sysclk_clk_bak, which drives the 774 * \ref group_rtc. 775 * 776 * The low-frequency clock has three possible source clocks: 777 * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", and 778 * \ref group_sysclk_wco "WCO". 779 * 780 *  781 * 782 * \defgroup group_sysclk_clk_lf_funcs Functions 783 * \defgroup group_sysclk_clk_lf_enums Enumerated Types 784 * \} 785 * \defgroup group_sysclk_clk_timer Timer Clock 786 * \{ 787 * The timer clock can be a source for the alternative clock driving 788 * the \ref group_arm_system_timer. It can also be used as a reference clock 789 * for a counter in the \ref group_energy_profiler "Energy Profiler". 790 * 791 * The timer clock is a divided clock of either the IMO or CLK_HF[0] 792 * (\ref group_sysclk_clk_hf "HF Clocks"). 793 * 794 * \defgroup group_sysclk_clk_timer_funcs Functions 795 * \defgroup group_sysclk_clk_timer_enums Enumerated Types 796 * \} 797 * \defgroup group_sysclk_clk_pump Pump Clock 798 * \{ 799 * The pump clock is a clock source used to provide analog precision in low voltage 800 * applications. Depending on the usage scenario, it may be required to drive the 801 * internal voltage pump for the Continuous Time Block mini (CTBm) in the analog 802 * subsystem. The pump clock is a divided clock of one of the clock paths 803 * (\ref group_sysclk_path_src). 804 * 805 * \defgroup group_sysclk_clk_pump_funcs Functions 806 * \defgroup group_sysclk_clk_pump_enums Enumerated Types 807 * \} 808 * \defgroup group_sysclk_clk_bak Backup Domain Clock 809 * \{ 810 * The backup domain clock drives the \ref group_rtc. 811 * This clock has two possible source clocks: \ref group_sysclk_wco "WCO" 812 * or the \ref group_sysclk_clk_lf. In turn the low frequency clock is sourced by 813 * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", or 814 * \ref group_sysclk_wco "WCO". Typically the ILO is not suitable as an RTC source, 815 * because of its low accuracy. However the ILO does operate in hibernate mode and 816 * may be used as an alternative to the WCO with a tradeoff in precision. 817 * 818 * \defgroup group_sysclk_clk_bak_funcs Functions 819 * \defgroup group_sysclk_clk_bak_enums Enumerated Types 820 * \} 821 * \defgroup group_sysclk_mf Medium Frequency Domain Clock 822 * \{ 823 * The Medium Frequency Domain Clock is present only in SRSS_ver1_3. 824 * Consists of MFO - the Medium Frequency Oscillator, 825 * and CLK_MF - the Medium Frequency Clock divider. 826 * This clock chain is designed to source the LCD block 827 * in Deep Sleep mode, see \ref cy_en_seglcd_lsclk_t. 828 * 829 * \defgroup group_sysclk_mf_funcs Functions 830 * \defgroup group_sysclk_clk_mf_enums Enumerated Types 831 * \} 832 * \defgroup group_sysclk_iho Internal High Frequency(IHO) Clock 833 * \{ 834 * The IHO Clock is Internal High-speed Oscillator, which is present in CAT1B(48MHz) 835 * and CAT1D(50MHz) devices. 836 * 837 * \defgroup group_sysclk_iho_funcs Functions 838 * \defgroup group_sysclk_clk_iho_enums Enumerated Types 839 * \} 840 * \defgroup group_sysclk_imo Internal Main Oscillator(IMO) Clock 841 * \{ 842 * The IMO Clock is Internal Main Oscillator, which is present in CAT1A/CAT1B/CAT1C and 843 * CAT1D devices, where as it is it is 8MHz in CAT1A/CAT1B/CAT1C, and CAT1D supports 844 * two instances of IMO i.e. 2MHz frequency (deep sleep capable) and separate 845 * instance with 4Mhz for LPPASS. 846 * 847 * \defgroup group_sysclk_imo_funcs Functions 848 * \defgroup group_sysclk_clk_imo_enums Enumerated Types 849 * \} 850 * \defgroup group_sysclk_clk_mem Mem Clock 851 * \{ 852 * Clock for the Memories 853 854 * \defgroup group_sysclk_clk_mem_funcs Functions 855 * \} 856 * \defgroup group_sysclk_clk_pwr Power Clock 857 * \{ 858 * Clock for the power architecture components. 859 860 * \defgroup group_sysclk_clk_pwr_funcs Functions 861 * \defgroup group_sysclk_clk_pwr_enums Enumerated Types 862 * \} 863 864 */ 865 866 #if !defined (CY_SYSCLK_H) 867 #define CY_SYSCLK_H 868 869 #include "cy_device.h" 870 871 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 872 #include <stdbool.h> 873 #include "cy_syslib.h" 874 #include "cy_syspm.h" 875 876 #if defined(CY_DEVICE_SECURE) 877 #include "cy_pra.h" 878 #endif /* defined(CY_DEVICE_SECURE) */ 879 880 881 #if defined(__cplusplus) 882 extern "C" { 883 #endif /* __cplusplus */ 884 885 /** 886 * \addtogroup group_sysclk_macros 887 * \{ 888 */ 889 /** Driver major version */ 890 #define CY_SYSCLK_DRV_VERSION_MAJOR 3 891 /** Driver minor version */ 892 #define CY_SYSCLK_DRV_VERSION_MINOR 70 893 /** Sysclk driver identifier */ 894 #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) 895 896 /** ILO clock frequency */ 897 #define CY_SYSCLK_ILO_FREQ (32768UL) /* Hz */ 898 /** WCO clock frequency */ 899 #define CY_SYSCLK_WCO_FREQ (32768UL) /* Hz */ 900 /** PILO clock frequency */ 901 #define CY_SYSCLK_PILO_FREQ (32768UL) /* Hz */ 902 903 /** IMO clock frequency */ 904 #define CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */ 905 906 /** MFO clock frequency */ 907 #define CY_SYSCLK_MFO_FREQ (2000000UL) /* Hz */ 908 909 /** CY_SYSCLK_PILO_TRIM_STEP is the default PILO TRIM Step value */ 910 #define CY_SYSCLK_PILO_TRIM_STEP (5UL) /* Default PILO TRIM Step size */ 911 912 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) 913 /** 914 * \note 915 * This macro is available for CAT1B devices. 916 **/ 917 /** IHO clock frequency */ 918 #define CY_SYSCLK_IHO_FREQ (48000000UL) /* Hz */ 919 #endif /* CY_IP_MXS40SSRSS*/ 920 921 922 #if defined (CY_IP_MXS40SRSS) 923 /** 924 * \note 925 * This macro is available for CAT1A devices. 926 **/ 927 /** ECO clock frequency */ 928 #define CY_SYSCLK_ECO_FREQ (4000000UL) /* Hz */ 929 #endif /* CY_IP_MXS40SRSS */ 930 931 932 #if defined (CY_IP_MXS40SSRSS)|| defined (CY_IP_MXS22SRSS) 933 /** FLL BYPASS configure Delay , As per SAS 934 * "When changing BYPASS_SEL, do not turn off the reference clock 935 * or CCO clock for ten cycles (whichever is slower)" 936 * Slower if IMO, so delay = (10 * 1/(IMO freq in Mhz)) = 1.25 micro seconds, 937 * approximated to 2 micro second 938 **/ 939 #define CY_SYSCLK_BYPASS_CONFIGURE_DELAY (2UL) /* micro seconds */ 940 941 /** FLL Disable Timeout value 942 **/ 943 #define CY_SYSCLK_FLL_DISABLE_TIMEOUT (100UL) /* micro seconds */ 944 945 #else 946 947 /** FLL BYPASS configure Delay , As per SAS 948 * "When changing BYPASS_SEL, do not turn off the reference clock 949 * or CCO clock for seven cycles (whichever is slower)" 950 * Slower if IMO, so delay = (7 * 1/(IMO freq in Mhz)) = 0.875 micro seconds, 951 * approximated to 1 micro second 952 **/ 953 #define CY_SYSCLK_BYPASS_CONFIGURE_DELAY (1UL) /* micro seconds */ 954 955 /** FLL Disable Timeout value 956 **/ 957 #define CY_SYSCLK_FLL_DISABLE_TIMEOUT (100UL) /* micro seconds */ 958 959 #endif /* defined (CY_IP_MXS40SSRSS)|| defined (CY_IP_MXS22SRSS) */ 960 961 962 /******************************************************************************* 963 * Internal Defines 964 *******************************************************************************/ 965 #if defined (CY_IP_MXS22SRSS) 966 /** 967 * \note 968 * This macro is valid for CAT1D devices. 969 **/ 970 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 971 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IHO) || \ 972 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 973 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ECO) || \ 974 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 975 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 976 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_PILO)) 977 #elif defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3) 978 /** 979 * \note 980 * This macro is valid for CAT1C devices. 981 **/ 982 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 983 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 984 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 985 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ECO) || \ 986 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO0) || \ 987 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 988 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO1)) 989 #elif defined (CY_IP_MXS40SSRSS) 990 /** 991 * \note 992 * This macro is valid for CAT1B devices. 993 **/ 994 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 995 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 996 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 997 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ALTHF) || \ 998 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_IHO) || \ 999 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO) || \ 1000 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 1001 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_PILO)) 1002 #else 1003 /** 1004 * \note 1005 * This macro is valid for CAT1A devices. 1006 **/ 1007 /* Macro to validate parameters in Cy_SysClk_ClkPathSetSource() function */ 1008 #define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID(clkSrc) (((clkSrc) == CY_SYSCLK_CLKPATH_IN_IMO) || \ 1009 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_EXT) || \ 1010 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ALTHF) || \ 1011 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ECO) || \ 1012 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_ILO) || \ 1013 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_WCO) || \ 1014 ((clkSrc) == CY_SYSCLK_CLKPATH_IN_PILO) 1015 #endif 1016 1017 /** \} group_sysclk_macros */ 1018 1019 1020 /** 1021 * \addtogroup group_sysclk_returns 1022 * \{ 1023 */ 1024 /** Defines general-purpose function return values */ 1025 typedef enum 1026 { 1027 CY_SYSCLK_SUCCESS = 0x00UL, /**< Command completed with no errors */ 1028 CY_SYSCLK_BAD_PARAM = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x01UL), /**< Invalid function input parameter */ 1029 CY_SYSCLK_TIMEOUT = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x02UL), /**< Timeout occurred */ 1030 CY_SYSCLK_INVALID_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x03UL), /**< Clock is in an invalid state */ 1031 CY_SYSCLK_UNSUPPORTED_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x04UL) /**< Feature Unsupported */ 1032 } cy_en_sysclk_status_t; 1033 /** \} group_sysclk_returns */ 1034 1035 1036 /* ========================================================================== */ 1037 /* =========================== EXT SECTION ============================ */ 1038 /* ========================================================================== */ 1039 1040 /** \cond INTERNAL */ 1041 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) 1042 /* Internal storage for external clock frequency user setting */ 1043 extern uint32_t cySysClkExtFreq; 1044 #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */ 1045 /** \endcond */ 1046 1047 /** 1048 * \addtogroup group_sysclk_ext_funcs 1049 * \{ 1050 */ 1051 /******************************************************************************* 1052 * Function Name: Cy_SysClk_ExtClkSetFrequency 1053 ****************************************************************************//** 1054 * 1055 * Sets the signal frequency of the External Clock Source (EXTCLK) into the 1056 * internal storage to be used in \ref Cy_SysClk_ClkHfGetFrequency. 1057 * 1058 * \param freq The frequency of the External Clock Source. 1059 * 1060 * \funcusage 1061 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency 1062 * 1063 *******************************************************************************/ 1064 void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); 1065 1066 1067 /******************************************************************************* 1068 * Function Name: Cy_SysClk_ExtClkGetFrequency 1069 ****************************************************************************//** 1070 * 1071 * Returns the frequency of the External Clock Source (EXTCLK) from the 1072 * internal storage. 1073 * 1074 * \return The frequency of the External Clock Source. 1075 * 1076 * \funcusage 1077 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency 1078 * 1079 *******************************************************************************/ 1080 uint32_t Cy_SysClk_ExtClkGetFrequency(void); 1081 /** \} group_sysclk_ext_funcs */ 1082 1083 /* ========================================================================== */ 1084 /* =========================== ECO SECTION ============================ */ 1085 /* ========================================================================== */ 1086 1087 /** 1088 * \addtogroup group_sysclk_macros 1089 * \{ 1090 */ 1091 1092 /** 1093 * \defgroup group_sysclk_ecostatus ECO status 1094 * \{ 1095 * Constants used for expressing ECO status. 1096 */ 1097 #define CY_SYSCLK_ECOSTAT_AMPLITUDE 0UL /**< \brief ECO does not have sufficient amplitude */ 1098 #define CY_SYSCLK_ECOSTAT_INACCURATE 1UL /**< \brief ECO may not be meeting accuracy and duty cycle specs */ 1099 #define CY_SYSCLK_ECOSTAT_STABLE 2UL /**< \brief ECO has fully stabilized */ 1100 1101 #if defined (CY_IP_MXS28SRSS) 1102 /** 1103 * \note 1104 * This macro is available for CAT1B devices. 1105 **/ 1106 #define CY_SYSCLK_ECOSTAT_BLE_DISABLED 0UL /**< \brief ECO for BLE is disabled */ 1107 /** 1108 * \note 1109 * This macro is available for CAT1B devices. 1110 **/ 1111 #define CY_SYSCLK_ECOSTAT_BLE_ENABLED 1UL /**< \brief ECO for BLE is enabled */ 1112 #endif /* CY_IP_MXS28SRSS */ 1113 1114 /** \} group_sysclk_ecostatus */ 1115 1116 # if (defined (CY_DEVICE_SECURE)) 1117 /** 1118 * \note 1119 * This structure is available for CAT1A devices. 1120 **/ 1121 /** PRA structure for Cy_SysClk_EcoConfigure function parameters */ 1122 typedef struct 1123 { 1124 uint32_t praClkEcofreq; /**< freq */ 1125 uint32_t praCsum; /**< cSum */ 1126 uint32_t praEsr; /**< esr */ 1127 uint32_t praDriveLevel; /**< drivelevel */ 1128 } cy_stc_pra_clk_eco_configure_t; 1129 #endif /* (defined (CY_DEVICE_SECURE)) */ 1130 1131 /** \} group_sysclk_macros */ 1132 1133 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) 1134 /** \cond */ 1135 /** 1136 * \note 1137 * This macro is available for CAT1A, CAT1D, CAT1B devices. 1138 **/ 1139 #define SRSS_CLK_ECO_STATUS_Msk (SRSS_CLK_ECO_STATUS_ECO_OK_Msk | SRSS_CLK_ECO_STATUS_ECO_READY_Msk) 1140 /** \endcond */ 1141 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) */ 1142 1143 #if defined (CY_IP_MXS28SRSS) 1144 /** \cond */ 1145 /** 1146 * \note 1147 * It is available for CAT1B devices. 1148 **/ 1149 #define SRSS_CLK_ECO_STATUS_Msk (SRSS_CLK_ECO_STATUS_ECO_CORE_READY_Msk | SRSS_CLK_ECO_STATUS_ECO_CORE_AMP_OK_Msk) 1150 1151 /** \endcond */ 1152 #endif /* CY_IP_MXS28SRSS */ 1153 1154 1155 1156 #if defined (CY_IP_MXS28SRSS) 1157 /** 1158 * \addtogroup group_sysclk_eco_enums 1159 * \{ 1160 */ 1161 /** 1162 * ECO enable options for BLE 1163 */ 1164 /** 1165 * \note 1166 * This enum is available for CAT1B devices. 1167 **/ 1168 typedef enum 1169 { 1170 CY_SYSCLK_ECO_BLESS_CONTROL0 = 0U, /**< 0, 1: hardware controlled by BLESS. */ 1171 CY_SYSCLK_ECO_BLESS_CONTROL1 = 1U, /**< 0, 1: hardware controlled by BLESS. */ 1172 CY_SYSCLK_ECO_FORCE_ENABLE = 2U, /**< Force ECO enabled for use by BLE */ 1173 CY_SYSCLK_ECO_FORCE_DISABLE = 3U, /**< Force ECO disabled for use by BLE */ 1174 } cy_en_eco_for_ble_t; 1175 /** \} group_sysclk_eco_enums */ 1176 #endif /* CY_IP_MXS28SRSS */ 1177 1178 /** 1179 * \addtogroup group_sysclk_eco_funcs 1180 * \{ 1181 */ 1182 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 1183 /******************************************************************************* 1184 * Function Name: Cy_SysClk_EcoSetFrequency 1185 ****************************************************************************//** 1186 * 1187 * Stores the external crystal oscillator (ECO) frequency in a global variable 1188 * within Sysclk driver. 1189 * 1190 * \param freq Operating frequency of the crystal in Hz. 1191 * Valid range: 16000000...35000000 (16..35 MHz). 1192 * 1193 * \note 1194 * This API is available for CAT1A devices. 1195 * 1196 *******************************************************************************/ 1197 void Cy_SysClk_EcoSetFrequency(uint32_t freq); 1198 #endif /* (defined (CY_IP_MXS40SRSS)&& (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 1199 1200 #if defined (CY_IP_MXS40SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) || \ 1201 (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) 1202 1203 1204 /******************************************************************************* 1205 * Function Name: Cy_SysClk_EcoConfigure 1206 ****************************************************************************//** 1207 * 1208 * Configures the external crystal oscillator (ECO) trim bits based on crystal 1209 * characteristics. This function should be called only when the ECO is disabled. 1210 * 1211 * \param freq Operating frequency of the crystal in Hz. 1212 * Valid range: 16000000...35000000 (16..35 MHz). 1213 * 1214 * \param cSum The summary capacitance of 1215 * C0 (the crystal itself shunt capacitance) and 1216 * Cload (the parallel load capacitance), in pF. 1217 * So cSum = C0 + Cload. 1218 * Valid range: 1...100. 1219 * \note 1220 * For CAT1B Devices: 1221 * cSum stands for crystal load capacitance in pF. 1222 * 1223 * \param esr Effective series resistance of the crystal in Ohms. 1224 * Valid range: 1...1000. 1225 * 1226 * \param driveLevel Crystal drive level in uW. 1227 * Valid range: 1...2000. 1228 * 1229 * \return Error / status code: \n 1230 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 1231 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1232 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1233 * \note Behavior of this API is IP dependent. \n 1234 * On CAT1A device: \n 1235 * 1236 * For the PSoC 64 devices there are possible situations when function returns 1237 * the PRA error status code. This is because for PSoC 64 devices the function 1238 * uses the PRA driver to change the protected registers. Refer to 1239 * \ref cy_en_pra_status_t for more details. 1240 * The following calculations are implemented in the 32-bit integer math: 1241 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1242 * after \ref Cy_SysClk_EcoEnable call. 1243 * 1244 * \verbatim 1245 * freqKhz = freq / 1000 1246 * maxAmpl = sqrt(drivelevel / 2 / esr) / 3.14 / freqKhz / cSum 1247 * ampSect = INT(5 * 4 * 3.14^2 * freqKhz^2 * cSum^2 * 4 * esr / 1000000000 / 1000000 / 9) 1248 * As a result of the above calculations, max amplitude must be >= 0.65V, and the 1249 * number of amplifier sections must be <= 3, otherwise this function returns with 1250 * a parameter error. 1251 * 1252 * atrim = 15 1253 * agc_en = 1 1254 * wdtrim = 7 1255 * gtrim = ampSect > 1 ? ampSect : ampSect == 1 ? 0 : 1 1256 * rtrim = 0 1257 * ftrim = 3 1258 * \endverbatim 1259 * 1260 * \note 1261 * On CAT1C Device: \n 1262 * 1263 * \verbatim 1264 1265 * No TRIM registers configuration required for CAT1B devices, For legacy API is emptied 1266 * The following calculations are implemented, generally in floating point: 1267 * freqMHz = freq / 1000000 1268 * max amplitude Vpp = 1000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad 1269 * gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1000000000 1270 * Number of amplifier sections = INT(gm_min / 4.5) 1271 * 1272 * As a result of the above calculations, max amplitude must be >= 0.5, and the 1273 * number of amplifier sections must be <= 3, otherwise this function returns with 1274 * a parameter error. 1275 * 1276 * atrim = if (max amplitude < 0.5) then error 1277 * else 2 * the following: 1278 * max amplitude < 0.6: 0 1279 * max amplitude < 0.7: 1 1280 * max amplitude < 0.8: 2 1281 * max amplitude < 0.9: 3 1282 * max amplitude < 1.15: 5 1283 * max amplitude < 1.275: 6 1284 * max amplitude >= 1.275: 7 1285 * wdtrim = if (max amplitude < 0.5) then error 1286 * else 2 * the following: 1287 * max amplitude < 1.2: INT(5 * max amplitude) - 2 1288 * max amplitude >= 1.2: 3 1289 * gtrim = if (number of amplifier sections > 3) then error 1290 * else the following: 1291 * number of amplifier sections > 1: number of amplifier sections 1292 * number of amplifier sections = 1: 0 1293 * number of amplifier sections < 1: 1 1294 * rtrim = if (gtrim = error) then error 1295 * else the following: 1296 * freqMHz > 26.8: 0 1297 * freqMHz > 23.33: 1 1298 * freqMHz > 16.5: 2 1299 * freqMHz <= 16.5: 3 1300 * ftrim = if (atrim = error) then error 1301 * else INT(atrim / 2) 1302 * \endverbatim 1303 * 1304 * \note 1305 * This API is available for CAT1A, CAT1C and CAT1D devices. 1306 * 1307 * \funcusage 1308 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoConfigure 1309 * 1310 *******************************************************************************/ 1311 cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint32_t esr, uint32_t driveLevel); 1312 1313 /******************************************************************************* 1314 * Function Name: Cy_SysClk_EcoEnable 1315 ****************************************************************************//** 1316 * 1317 * Enables the external crystal oscillator (ECO). This function should be called 1318 * after \ref Cy_SysClk_EcoConfigure. 1319 * 1320 * \param timeoutus Amount of time in microseconds to wait for the ECO to stabilize. 1321 * To avoid waiting for stabilization, set this parameter to 0. 1322 * 1323 * \return Error / status code: \n 1324 * CY_SYSCLK_SUCCESS - ECO locked \n 1325 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1326 * CY_SYSCLK_INVALID_STATE - ECO already enabled \n 1327 * CY_SYSCLK_UNSUPPORTED_STATE - ECO is not present 1328 * For the PSoC 64 devices there are possible situations when function returns 1329 * the PRA error status code. This is because for PSoC 64 devices the function 1330 * uses the PRA driver to change the protected registers. Refer to 1331 * \ref cy_en_pra_status_t for more details. 1332 * 1333 * \note 1334 * Call \ref SystemCoreClockUpdate after this function calling 1335 * if it affects the CLK_HF0 frequency. 1336 * 1337 * \note 1338 * This API is available for CAT1A & CAT1C devices. 1339 * 1340 * \note 1341 * Take into account the possible platform specific clkHf (and further 1342 * clocking chain links) frequency limitations while using this API. 1343 * 1344 * \funcusage 1345 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable 1346 * 1347 *******************************************************************************/ 1348 cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus); 1349 1350 /******************************************************************************* 1351 * Function Name: Cy_SysClk_EcoGetFrequency 1352 ****************************************************************************//** 1353 * 1354 * Returns the frequency of the external crystal oscillator (ECO). 1355 * 1356 * \return The frequency of the ECO. 1357 * 1358 * \note If the ECO is not enabled or stable - a zero is returned. 1359 * 1360 * \funcusage 1361 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable 1362 * 1363 * \note 1364 * This API is available for CAT1A, CAT1C devices. 1365 * 1366 *******************************************************************************/ 1367 uint32_t Cy_SysClk_EcoGetFrequency(void); 1368 1369 1370 /******************************************************************************* 1371 * Function Name: Cy_SysClk_EcoDisable 1372 ****************************************************************************//** 1373 * 1374 * Disables the external crystal oscillator (ECO). This function should not be 1375 * called if the ECO is sourcing clkHf[0]. 1376 * 1377 * \funcusage 1378 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoDisable 1379 * 1380 * \note 1381 * This API is available for CAT1A, CAT1C devices. 1382 * 1383 *******************************************************************************/ 1384 void Cy_SysClk_EcoDisable(void); 1385 1386 1387 /******************************************************************************* 1388 * Function Name: Cy_SysClk_EcoGetStatus 1389 ****************************************************************************//** 1390 * 1391 * Reports the current status of the external crystal oscillator (ECO). 1392 * 1393 * \return 1394 * CY_SYSCLK_ECOSTAT_AMPLITUDE = ECO does not have sufficient amplitude \n 1395 * CY_SYSCLK_ECOSTAT_INACCURATE = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications \n 1396 * CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized 1397 * 1398 * \note 1399 * This API is available for CAT1A, CAT1C devices. 1400 * 1401 * \funcusage 1402 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoGetStatus 1403 * 1404 *******************************************************************************/ 1405 uint32_t Cy_SysClk_EcoGetStatus(void); 1406 #endif /* defined (CY_IP_MXS40SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL))*/ 1407 1408 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL)) 1409 1410 /******************************************************************************* 1411 * Function Name: Cy_SysClk_EcoPrescaleConfigure 1412 ****************************************************************************//** 1413 * 1414 * Configures the external crystal oscillator (ECO) using ECO Prescaler 1415 * Configuration Register and derives clk_eco_prescaler 1416 * 1417 * \param enable ECO Prescaler enable/disable. 1418 * 1419 * \param int_div 10-bit integer value. 1420 * 1421 * \param frac_div 8-bit fraction value. 1422 * 1423 * \return Error / status code: \n 1424 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 1425 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1426 * CY_SYSCLK_INVALID_STATE - ECO already enabled \n 1427 * CY_SYSCLK_UNSUPPORTED_STATE - ECO is not present 1428 * 1429 * \note 1430 * This API is available for CAT1C devices. 1431 * 1432 *******************************************************************************/ 1433 cy_en_sysclk_status_t Cy_SysClk_EcoPrescaleConfigure(uint32_t enable, uint32_t int_div, uint32_t frac_div); 1434 1435 /******************************************************************************* 1436 * Function Name: Cy_SysClk_EcoPrescaleIsEnabled 1437 ****************************************************************************//** 1438 * 1439 * Reports whether or not ECO Prescale is enabled. 1440 * 1441 * \return 1442 * false = disabled \n 1443 * true = enabled 1444 * 1445 * \note 1446 * This API is available for CAT1C devices. 1447 * 1448 *******************************************************************************/ 1449 bool Cy_SysClk_EcoPrescaleIsEnabled(void); 1450 1451 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_ECO_PRESENT == 1UL))*/ 1452 1453 #if defined (CY_IP_MXS28SRSS) 1454 /******************************************************************************* 1455 * Function Name: Cy_SysClk_EcoBleEnable 1456 ****************************************************************************//** 1457 * 1458 * Enables the external crystal oscillator (ECO) for BlueTooth Usage. This function should be called 1459 * after \ref Cy_SysClk_EcoConfigure. 1460 * 1461 * \param control To be selected from \ref cy_en_eco_for_ble_t 1462 * 1463 * \param timeoutus timeoutus 1464 * 1465 * \return Error / status code: \n 1466 * CY_SYSCLK_SUCCESS - ECO locked \n 1467 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1468 * CY_SYSCLK_INVALID_STATE - ECO already enabled \n 1469 * CY_SYSCLK_UNSUPPORTED_STATE - ECO is not present 1470 * 1471 * \note 1472 * This API is available for CAT1B devices. 1473 * 1474 *******************************************************************************/ 1475 cy_en_sysclk_status_t Cy_SysClk_EcoBleControl(cy_en_eco_for_ble_t control, uint32_t timeoutus); 1476 1477 /******************************************************************************* 1478 * Function Name: Cy_SysClk_EcoBleGetStatus 1479 ****************************************************************************//** 1480 * 1481 * Reports the current status w.r.to BLE of the external crystal oscillator (ECO). 1482 * 1483 * \return 1484 * CY_SYSCLK_ECOSTAT_BLE_ENABLED = ECO for BLE is enabled \n 1485 * CY_SYSCLK_ECOSTAT_BLE_DISABLED = ECO for BLE is not enabled 1486 * 1487 * \note 1488 * This API is available for CAT1B devices. 1489 * 1490 *******************************************************************************/ 1491 uint32_t Cy_SysClk_EcoBleGetStatus(void); 1492 #endif /* defined (CY_IP_MXS28SRSS) */ 1493 1494 /** \} group_sysclk_eco_funcs */ 1495 1496 1497 /* ========================================================================== */ 1498 /* ==================== INPUT MULTIPLEXER SECTION ===================== */ 1499 /* ========================================================================== */ 1500 /** 1501 * \addtogroup group_sysclk_path_src_enums 1502 * \{ 1503 */ 1504 /** 1505 * Input multiplexer clock sources 1506 */ 1507 1508 1509 typedef enum 1510 { 1511 #if defined (CY_IP_MXS22SRSS) 1512 CY_SYSCLK_CLKPATH_IN_IHO = 0U, /**< Select the IHO as the output of the path mux */ 1513 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1514 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1515 CY_SYSCLK_CLKPATH_IN_IMO = 3U, /**< Select the IMO as the output of the path mux */ 1516 CY_SYSCLK_CLKPATH_IN_ALTHF0 = 4U, /**< Select the ALTHF0 as the output of the path mux */ 1517 CY_SYSCLK_CLKPATH_IN_ALTHF1 = 5U, /**< Select the ALTHF1 as the output of the path mux */ 1518 CY_SYSCLK_CLKPATH_IN_DSIMUX = 7U, /**< Select the DSI MUX output as the output of the path mux */ 1519 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1520 * Make sure the DSI clock sources are available on used device. 1521 */ 1522 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 1523 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1524 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1525 * Make sure the ALTLF clock sources in available on used device. 1526 */ 1527 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1528 * Make sure the PILO clock sources in available on used device. 1529 */ 1530 #elif defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3) 1531 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 1532 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1533 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1534 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 1535 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 1536 CY_SYSCLK_CLKPATH_IN_LPECO = 5U, /**< Select the LPECO as the output of the path mux */ 1537 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1538 * Make sure the DSI clock sources are available on used device. 1539 */ 1540 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, 1541 CY_SYSCLK_CLKPATH_IN_ILO0 = CY_SYSCLK_CLKPATH_IN_ILO,/**< Select the ILO0 (16) as the output of the DSI mux and path mux */ 1542 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1543 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1544 * Make sure the ALTLF clock sources in available on used device. 1545 */ 1546 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1547 * Make sure the PILO clock sources in available on used device. 1548 */ 1549 CY_SYSCLK_CLKPATH_IN_ILO1 = 0x114U, /**< Select the ILO1 (20) as the output of the DSI mux and path mux */ 1550 #elif defined (CY_IP_MXS40SSRSS) 1551 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 1552 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1553 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1554 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 1555 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 1556 CY_SYSCLK_CLKPATH_IN_LPECO = 5U, /**< Select the LPECO as the output of the path mux */ 1557 CY_SYSCLK_CLKPATH_IN_IHO = 6U, /**< Select the IHO as the output of the path mux */ 1558 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1559 * Make sure the DSI clock sources are available on used device. 1560 */ 1561 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 1562 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1563 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1564 * Make sure the ALTLF clock sources in available on used device. 1565 */ 1566 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1567 * Make sure the PILO clock sources in available on used device. 1568 */ 1569 CY_SYSCLK_CLKPATH_IN_ILO1 = 0x114U, /**< Select the ILO1 (20) as the output of the DSI mux and path mux */ 1570 #else 1571 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 1572 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1573 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1574 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 1575 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 1576 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1577 * Make sure the DSI clock sources are available on used device. 1578 */ 1579 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 1580 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1581 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1582 * Make sure the ALTLF clock sources in available on used device. 1583 */ 1584 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1585 * Make sure the PILO clock sources in available on used device. 1586 */ 1587 #endif 1588 } cy_en_clkpath_in_sources_t; 1589 1590 1591 #if (defined(CY_DEVICE_SECURE)) 1592 /** 1593 * \note 1594 * This structure is available for CAT1A devices. 1595 **/ 1596 /** PRA structure for Cy_SysClk_ClkPathSetSource function parameters */ 1597 typedef struct 1598 { 1599 uint32_t clk_path; /**< clkpath */ 1600 cy_en_clkpath_in_sources_t source; /**< Source */ 1601 } cy_stc_pra_clkpathsetsource_t; 1602 #endif /* (defined(CY_DEVICE_SECURE)) */ 1603 1604 /** \} group_sysclk_path_src_enums */ 1605 1606 /** 1607 * \addtogroup group_sysclk_path_src_funcs 1608 * \{ 1609 */ 1610 /******************************************************************************* 1611 * Function Name: Cy_SysClk_ClkPathSetSource 1612 ****************************************************************************//** 1613 * 1614 * Configures the source for the specified clock path. 1615 * 1616 * \param clkPath Selects which clock path to configure; 0 is the first clock 1617 * path, which is the FLL. 1618 * 1619 * \param source \ref cy_en_clkpath_in_sources_t 1620 * 1621 * \return \ref cy_en_sysclk_status_t 1622 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1623 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1624 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1625 * uses the PRA driver to change the protected registers. Refer to 1626 * \ref cy_en_pra_status_t for more details. 1627 * 1628 * \note 1629 * If calling this function changes an FLL or PLL input frequency, disable the FLL 1630 * or PLL before calling this function. After calling this function, call the FLL 1631 * or PLL configure function, for example \ref Cy_SysClk_FllConfigure(). 1632 * 1633 * \note 1634 * Call \ref SystemCoreClockUpdate after this function calling 1635 * if it affects the CLK_HF0 frequency. 1636 * 1637 * \note 1638 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1639 * it affects the CLK_HF0 frequency and the frequency is increasing. 1640 * 1641 * \note 1642 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1643 * it affects the CLK_HF0 frequency and the frequency is decreasing. 1644 * 1645 * \funcusage 1646 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 1647 * 1648 * \note 1649 * Take into account the possible platform specific clkHf (and further 1650 * clocking chain links) frequency limitations while using this API. 1651 * 1652 * \note It takes four cycles of the originally selected clock to switch away 1653 * from it. Do not disable the original clock during this time. 1654 * 1655 *******************************************************************************/ 1656 cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); 1657 1658 1659 /******************************************************************************* 1660 * Function Name: Cy_SysClk_ClkPathGetSource 1661 ****************************************************************************//** 1662 * 1663 * Reports which source is selected for the path mux. 1664 * 1665 * \param clkPath Selects which clock path to report; 0 is the first clock path, 1666 * which is the FLL. 1667 * 1668 * \return \ref cy_en_clkpath_in_sources_t 1669 * 1670 * \funcusage 1671 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathGetSource 1672 * 1673 *******************************************************************************/ 1674 cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); 1675 1676 1677 /******************************************************************************* 1678 * Function Name: Cy_SysClk_ClkPathMuxGetFrequency 1679 ****************************************************************************//** 1680 * 1681 * Returns the output frequency of the clock path mux. 1682 * 1683 * \return The output frequency of the path mux. 1684 * 1685 * \note If the return value equals zero, that means either: 1686 * - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or 1687 * - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). 1688 * 1689 * \funcusage 1690 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 1691 * 1692 *******************************************************************************/ 1693 uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath); 1694 1695 1696 /******************************************************************************* 1697 * Function Name: Cy_SysClk_ClkPathGetFrequency 1698 ****************************************************************************//** 1699 * 1700 * Returns the output frequency of the clock path mux. 1701 * 1702 * \return The output frequency of the path mux. 1703 * 1704 * \note If the return value equals zero, that means either: 1705 * - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or 1706 * - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). 1707 * 1708 * \funcusage 1709 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable 1710 * 1711 *******************************************************************************/ 1712 uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath); 1713 /** \} group_sysclk_path_src_funcs */ 1714 1715 1716 /* ========================================================================== */ 1717 /* =========================== FLL SECTION ============================ */ 1718 /* ========================================================================== */ 1719 /** 1720 * \addtogroup group_sysclk_fll_enums 1721 * \{ 1722 */ 1723 /** FLL and PLL output mode. 1724 * See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL. 1725 */ 1726 typedef enum 1727 { 1728 CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0U, /**< Output FLL/PLL input source when not locked, and FLL/PLL output when locked */ 1729 CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1U, /**< Same as AUTO */ 1730 CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2U, /**< Output FLL/PLL input source regardless of lock status */ 1731 CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3U /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable */ 1732 } cy_en_fll_pll_output_mode_t; 1733 1734 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 1735 /** FLL current-controlled oscillator (CCO) frequency ranges. 1736 * See register CLK_FLL_CONFIG4, bits CCO_RANGE. 1737 */ 1738 typedef enum 1739 { 1740 CY_SYSCLK_FLL_CCO_RANGE0, /**< Target frequency is in range 48 - 64 MHz */ 1741 CY_SYSCLK_FLL_CCO_RANGE1, /**< Target frequency is in range 64 - 85 MHz */ 1742 CY_SYSCLK_FLL_CCO_RANGE2, /**< Target frequency is in range 85 - 113 MHz */ 1743 CY_SYSCLK_FLL_CCO_RANGE3, /**< Target frequency is in range 113 - 150 MHz */ 1744 CY_SYSCLK_FLL_CCO_RANGE4 /**< Target frequency is in range 150 - 200 MHz */ 1745 } cy_en_fll_cco_ranges_t; 1746 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 1747 /** \} group_sysclk_fll_enums */ 1748 1749 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 1750 1751 /** 1752 * \addtogroup group_sysclk_fll_structs 1753 * \{ 1754 */ 1755 /** Structure containing information for manual configuration of FLL. 1756 */ 1757 typedef struct 1758 { 1759 uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ 1760 uint16_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ 1761 cy_en_fll_cco_ranges_t ccoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */ 1762 bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */ 1763 uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */ 1764 uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */ 1765 uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */ 1766 uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */ 1767 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ 1768 uint16_t cco_Freq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */ 1769 } cy_stc_fll_manual_config_t; 1770 1771 /** \} group_sysclk_fll_structs */ 1772 1773 /** 1774 * \addtogroup group_sysclk_fll_funcs 1775 * \{ 1776 *//******************************************************************************* 1777 * Function Name: Cy_SysClk_FllConfigure 1778 ****************************************************************************//** 1779 * 1780 * Configures the FLL, for best accuracy optimization. 1781 * 1782 * \param inputFreq frequency of input source, in Hz 1783 * 1784 * \param outputFreq Desired FLL output frequency, in Hz. Allowable range is 1785 * 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide 1786 * by 2 option is required. 1787 * 1788 * \param outputMode \ref cy_en_fll_pll_output_mode_t 1789 * If output mode is bypass, then the output frequency equals the input source 1790 * frequency regardless of the frequency parameter values. 1791 * 1792 * \return Error / status code: \n 1793 * CY_SYSCLK_SUCCESS - FLL successfully configured \n 1794 * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled \n 1795 * CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range \n 1796 * CY_SYSCLK_UNSUPPORTED_STATE - FLL is not present 1797 * 1798 * \note 1799 * Call this function after changing the FLL input frequency, for example if 1800 * \ref Cy_SysClk_ClkPathSetSource() is called. 1801 * 1802 * \note 1803 * Do not call this function when the FLL is enabled. If it is called, then this function 1804 * returns with an CY_SYSCLK_INVALID_STATE return value and no register updates. 1805 * 1806 * \note 1807 * Call \ref SystemCoreClockUpdate after this function calling 1808 * if it affects the CLK_HF0 frequency. 1809 * 1810 * \note 1811 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1812 * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. 1813 * 1814 * \note 1815 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1816 * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. 1817 * 1818 * \note 1819 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1820 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 1821 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 1822 * 1823 * \funcusage 1824 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllConfigure 1825 * 1826 *******************************************************************************/ 1827 cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode); 1828 1829 1830 /******************************************************************************* 1831 * Function Name: Cy_SysClk_FllManualConfigure 1832 ****************************************************************************//** 1833 * 1834 * Manually configures the FLL based on user inputs. 1835 * 1836 * \param config \ref cy_stc_fll_manual_config_t 1837 * 1838 * \return Error / status code: \n 1839 * CY_SYSCLK_SUCCESS - FLL successfully configured \n 1840 * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled 1841 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1842 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1843 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1844 * uses the PRA driver to change the protected registers. Refer to 1845 * \ref cy_en_pra_status_t for more details. 1846 * 1847 * \note 1848 * Call this function after changing the FLL input frequency, for example if 1849 * \ref Cy_SysClk_ClkPathSetSource() is called. 1850 * 1851 * \note 1852 * Do not call this function when the FLL is enabled. If it is called, then this function 1853 * returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates. 1854 * 1855 * \note 1856 * Call \ref SystemCoreClockUpdate after this function calling 1857 * if it affects the CLK_HF0 frequency. 1858 * 1859 * \note 1860 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1861 * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. 1862 * 1863 * \note 1864 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1865 * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. 1866 * 1867 * \note 1868 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1869 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 1870 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 1871 * 1872 * \funcusage 1873 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllManualConfigure 1874 * 1875 *******************************************************************************/ 1876 cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config); 1877 1878 1879 /******************************************************************************* 1880 * Function Name: Cy_SysClk_FllGetConfiguration 1881 ****************************************************************************//** 1882 * 1883 * Reports the FLL configuration settings. 1884 * 1885 * \param config \ref cy_stc_fll_manual_config_t 1886 * 1887 * \note 1888 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1889 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 1890 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 1891 * 1892 * \funcusage 1893 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration 1894 * 1895 *******************************************************************************/ 1896 void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config); 1897 1898 1899 /******************************************************************************* 1900 * Function Name: Cy_SysClk_FllEnable 1901 ****************************************************************************//** 1902 * 1903 * Enables the FLL. The FLL should be configured before calling this function. 1904 * 1905 * \param timeoutus Amount of time in micro seconds to wait for FLL to lock. 1906 * If lock doesn't occur, the FLL is stopped. To avoid waiting for lock, set this to 0 1907 * and manually check for lock using \ref Cy_SysClk_FllLocked. 1908 * 1909 * \return Error / status code: \n 1910 * CY_SYSCLK_SUCCESS - FLL successfully enabled \n 1911 * CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock 1912 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1913 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1914 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1915 * uses the PRA driver to change the protected registers. Refer to 1916 * \ref cy_en_pra_status_t for more details. 1917 * 1918 * \note 1919 * While waiting for the FLL to lock, the FLL bypass mode is set to \ref CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 1920 * After the FLL is locked, the FLL bypass mdoe is then set to \ref CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT. 1921 * 1922 * \note 1923 * Call \ref SystemCoreClockUpdate after calling this function 1924 * if it affects the CLK_HF0 frequency. 1925 * 1926 * \note 1927 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1928 * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 1929 * 1930 * \note 1931 * Take into account the possible platform specific clkHf (and further 1932 * clocking chain links) frequency limitations while using this API. 1933 * 1934 * \funcusage 1935 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable 1936 * 1937 *******************************************************************************/ 1938 cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus); 1939 1940 1941 /******************************************************************************* 1942 * Function Name: Cy_SysClk_FllIsEnabled 1943 ****************************************************************************//** 1944 * 1945 * Reports whether or not the FLL is enabled. 1946 * 1947 * \return 1948 * false = disabled \n 1949 * true = enabled 1950 * 1951 * \funcusage 1952 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable 1953 * 1954 *******************************************************************************/ 1955 bool Cy_SysClk_FllIsEnabled(void); 1956 1957 1958 /******************************************************************************* 1959 * Function Name: Cy_SysClk_FllLocked 1960 ****************************************************************************//** 1961 * 1962 * Reports whether the FLL is locked first time during FLL starting. 1963 * Intended to be used with \ref Cy_SysClk_FllEnable with zero timeout. 1964 * 1965 * \return 1966 * false = not locked \n 1967 * true = locked 1968 * 1969 * \note 1970 * The unlock occurrence may appear during FLL normal operation, so this function 1971 * is not recommended to check the FLL normal operation stability. 1972 * 1973 * \funcusage 1974 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllLocked 1975 * 1976 *******************************************************************************/ 1977 bool Cy_SysClk_FllLocked(void); 1978 1979 1980 /******************************************************************************* 1981 * Function Name: Cy_SysClk_FllDisable 1982 ****************************************************************************//** 1983 * 1984 * Disables the FLL and the CCO. 1985 * 1986 * \return \ref cy_en_sysclk_status_t 1987 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1988 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1989 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1990 * uses the PRA driver to change the protected registers. Refer to 1991 * \ref cy_en_pra_status_t for more details. 1992 * 1993 * \note 1994 * Call \ref SystemCoreClockUpdate after this function calling 1995 * if it affects the CLK_HF0 frequency. 1996 * 1997 * \note 1998 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1999 * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2000 * 2001 * \funcusage 2002 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable 2003 * 2004 *******************************************************************************/ 2005 cy_en_sysclk_status_t Cy_SysClk_FllDisable(void); 2006 2007 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) 2008 2009 /******************************************************************************* 2010 * Function Name: Cy_SysClk_FllOutputDividerEnable 2011 ****************************************************************************//** 2012 * 2013 * Enables/Disables the FLL output divider 2014 * 2015 * \param enable 2016 * 2017 *******************************************************************************/ 2018 void Cy_SysClk_FllOutputDividerEnable(bool enable); 2019 2020 #endif 2021 2022 /******************************************************************************* 2023 * Function Name: Cy_SysClk_FllGetFrequency 2024 ****************************************************************************//** 2025 * 2026 * Returns the output frequency of the FLL. 2027 * 2028 * \return The output frequency of FLL. 2029 * 2030 * \note If the return value equals zero, that means FLL is disabled. 2031 * 2032 * \funcusage 2033 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetFrequency 2034 * 2035 *******************************************************************************/ 2036 uint32_t Cy_SysClk_FllGetFrequency(void); 2037 2038 /** \} group_sysclk_fll_funcs */ 2039 #endif /* defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 2040 2041 /* ========================================================================== */ 2042 /* =========================== PLL SECTION ============================ */ 2043 /* ========================================================================== */ 2044 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) 2045 /** 2046 * \addtogroup group_sysclk_pll_structs 2047 * \{ 2048 */ 2049 /** Structure containing information for configuration of a PLL. 2050 */ 2051 typedef struct 2052 { 2053 uint32_t inputFreq; /**< frequency of PLL source, in Hz */ 2054 uint32_t outputFreq; /**< frequency of PLL output, in Hz */ 2055 bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 2056 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ 2057 } cy_stc_pll_config_t; 2058 2059 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) || defined(CY_DOXYGEN) 2060 /** Structure containing information for configuration of a DPLL-LP. 2061 */ 2062 /** 2063 * \note 2064 * This structure is available only for CAT1D devices. 2065 **/ 2066 typedef struct 2067 { 2068 uint8_t feedbackDiv; /**< CONFIG register, FEEDBACK_DIV (P) bits */ 2069 uint8_t referenceDiv; /**< CONFIG register, REFERENCE_DIV (Q) bits */ 2070 uint8_t outputDiv; /**< CONFIG register, OUTPUT_DIV bits */ 2071 bool pllDcoMode; /**< CONFIG register, PLL_DCO_MODE bit */ 2072 cy_en_fll_pll_output_mode_t outputMode; /**< CONFIG register, BYPASS_SEL bits */ 2073 uint32_t fracDiv; /**< CONFIG2 register, FRAC_DIV bits, only for CAT1B(B2),CAT1D devices */ 2074 bool fracDitherEn; /**< CONFIG2 register, FRAC_DITHER_EN bit, only for CAT1B(B2),CAT1D devices */ 2075 bool fracEn; /**< CONFIG2 register, FRAC_EN bit, only for CAT1B(B2),CAT1D devices */ 2076 uint32_t sscgDepth; /**< CONFIG3 register, SSCG_DEPTH bits, only for CAT1B(B2),CAT1D devices */ 2077 uint8_t sscgRate; /**< CONFIG3 register, SSCG_RATE bits, only for CAT1B(B2),CAT1D devices */ 2078 bool sscgDitherEn; /**< CONFIG3 register, SSCG_DITHER_EN bit, only for CAT1B(B2),CAT1D devices */ 2079 bool sscgMode; /**< CONFIG3 register, SSCG_MODE bit, only for CAT1B(B2),CAT1D devices */ 2080 bool sscgEn; /**< CONFIG3 register, SSCG_EN bit, only for CAT1B(B2),CAT1D devices */ 2081 #if defined (CY_IP_MXS22SRSS) 2082 uint32_t dcoCode; /**< CONFIG4 register, DCO_CODE bits, only for CAT1D devices */ 2083 bool disableBias; /**< CONFIG4 register, PLL_CS_PB2_DIS bit, only for CAT1D devices */ 2084 bool enableDcoSd; /**< CONFIG4 register, DCO_SD_EN bit, only for CAT1D devices */ 2085 uint32_t kiInt; /**< CONFIG5 register, Gain of P/I loop filter integrator path for INT operation only for CAT1D devices */ 2086 uint32_t kiFrac; /**< CONFIG5 register, Gain of P/I loop filter proportional path for FRACT operation only for CAT1D devices */ 2087 uint32_t kiSscg; /**< CONFIG5 register, Gain of P/I loop filter proportional path for SSCG operation only for CAT1D devices */ 2088 uint32_t kpInt; /**< CONFIG5 register, Gain of P/I loop filter integrator path for INT operation. only for CAT1D devices */ 2089 uint32_t kpFrac; /**< CONFIG5 register, Gain of P/I loop filter integrator path for FRACT operation. only for CAT1D devices */ 2090 uint32_t kpSscg; /**< CONFIG5 register, Gain of P/I loop filter integrator path for SSCG operation. only for CAT1D devices */ 2091 #else 2092 uint32_t dcoCode; /**< CONFIG4 register, DCO_CODE bits, only for CAT1B(B2), devices */ 2093 uint32_t accMode; /**< CONFIG4 register, ACC_MODE bits, only for CAT1B(B2), devices */ 2094 uint32_t tdcMode; /**< CONFIG4 register, TDC_MODE bits, only for CAT1B(B2), devices */ 2095 uint32_t pllTg; /**< CONFIG4 register, PLL_TG bits, only for CAT1B(B2), devices */ 2096 bool accCntLock; /**< CONFIG4 register, ACC_CNT_LOCK bits, only for CAT1B(B2), devices */ 2097 uint32_t kiInt; /**< CONFIG5 register, KI_INT bits, only for CAT1B(B2), devices */ 2098 uint32_t kpInt; /**< CONFIG5 register, KP_INT bits, only for CAT1B(B2), devices */ 2099 uint32_t kiAccInt; /**< CONFIG5 register, KI_ACC_INT bits, only for CAT1B(B2), devices */ 2100 uint32_t kpAccInt; /**< CONFIG5 register, KP_ACC_INT bits, only for CAT1B(B2), devices */ 2101 uint32_t kiFrac; /**< CONFIG6 register, KI_FRACT bits, only for CAT1B(B2), devices */ 2102 uint32_t kpFrac; /**< CONFIG6 register, KP_FRACT bits, only for CAT1B(B2), devices */ 2103 uint32_t kiAccFrac; /**< CONFIG6 register, KI_ACC_FRACT bits, only for CAT1B(B2), devices */ 2104 uint32_t kpAccFrac; /**< CONFIG7 register, KP_ACC_FRACT bits, only for CAT1B(B2), devices */ 2105 uint32_t kiSscg; /**< CONFIG7 register, KI_SSCG bits, only for CAT1B(B2), devices */ 2106 uint32_t kpSscg; /**< CONFIG7 register, KP_SSCG bits, only for CAT1B(B2), devices */ 2107 uint32_t kiAccSscg; /**< CONFIG7 register, KI_ACC_SSCG bits, only for CAT1B(B2), devices */ 2108 uint32_t kpAccSscg; /**< CONFIG7 register, KP_ACC_SSCG bits, only for CAT1B(B2), devices */ 2109 #endif 2110 } cy_stc_dpll_lp_config_t; 2111 2112 #if defined (CY_IP_MXS22SRSS) 2113 /** DPLL-HP wait mode selection enum. 2114 * See CONFIG2 register, bits MODE_SEL. 2115 */ 2116 typedef enum 2117 { 2118 CY_SYSCLK_DPLL_HP_CLK4MHZ_1US_CNT_VAL = 0U, /**< clk_dig frequency = 4MHz*/ 2119 CY_SYSCLK_DPLL_HP_CLK10MHZ_1US_CNT_VAL = 1U, /**< clk_dig frequency = 10MHz*/ 2120 CY_SYSCLK_DPLL_HP_CLK15MHZ_1US_CNT_VAL = 2U, /**< clk_dig frequency = 15MHz*/ 2121 CY_SYSCLK_DPLL_HP_CLK20MHZ_1US_CNT_VAL = 3U, /**< clk_dig frequency = 20MHz*/ 2122 CY_SYSCLK_DPLL_HP_CLK30MHZ_1US_CNT_VAL = 4U, /**< clk_dig frequency = 30MHz*/ 2123 CY_SYSCLK_DPLL_HP_CLK40MHZ_1US_CNT_VAL = 5U, /**< clk_dig frequency = 40MHz*/ 2124 CY_SYSCLK_DPLL_HP_CLK45MHZ_1US_CNT_VAL = 6U, /**< clk_dig frequency = 45MHz*/ 2125 CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL = 7U /**< clk_dig frequency = 50MHz*/ 2126 } cy_en_wait_mode_select_t; 2127 2128 2129 /** Structure containing information for configuration of a DPLL-HP. 2130 */ 2131 /** 2132 * \note 2133 * This structure is available only for CAT1D devices. 2134 **/ 2135 typedef struct 2136 { 2137 uint8_t nDiv; /**< CONFIG register, NDIV bits, Ratio between DCO frequency and reference frequency */ 2138 uint8_t pDiv; /**< CONFIG register, PDIV bits, Pre-Divider for scaling the reference frequency */ 2139 uint8_t kDiv; /**< CONFIG register, KDIV bits, Post-Divider */ 2140 cy_en_fll_pll_output_mode_t outputMode; /**< CONFIG register, BYPASS_SEL bits */ 2141 bool pllEn; /**< CONFIG register, ENABLE bits, Master Enable for PLL */ 2142 2143 uint32_t nDivFract; /**< CONFIG2 register, NDIV_FRACT bits, N-divider division factor */ 2144 cy_en_wait_mode_select_t freqModeSel; /**< CONFIG2 register, MODE_SEL bits, Selects the waiting time for Power Initialization sequence */ 2145 uint8_t ivrTrim ; /**< CONFIG2 register, IVR_TRIM bits, Trim value for the Regulated Voltage */ 2146 2147 bool clkrSel; /**< CONFIG3 register, CLKR_SEL bit, Select re-timed reference clock */ 2148 bool fdsmSel; /**< CONFIG3 register, FDSM_SEL bit, DSM clock division select, true - div_by_2, false - div_by_4 */ 2149 2150 uint8_t alphaCoarse; /**< CONFIG4 register, LF_LC_ALPHA bits, Alpha value of the coarse filter */ 2151 uint8_t betaCoarse; /**< CONFIG4 register, LF_LC_BETA bits, Beta value of the coarse filter */ 2152 uint8_t flockThresh; /**< CONFIG4 register, FLOCK_EN_THRESH bits, PQDIFF threshold under which FINE Filtering gets enabled */ 2153 uint8_t flockWait; /**< CONFIG4 register, FLOCK_WAITPER bits, Period over which flock_en_thresh must be met in order for FINE Filtering enabling */ 2154 uint8_t flockLkThres; /**< CONFIG4 register, FLOCK_LK_THRESH bits, PQDIFF threshold under which DLL asserts Freq LOCK */ 2155 uint8_t flockLkWait; /**< CONFIG4 register, FLOCK_LK_WAITPER bits, Period over which flock_en_thresh must be met in order for Freq Locking */ 2156 uint8_t flockObs; /**< CONFIG4 register, FLOCK_OBSWIN bits, Period over which PQDIFF is computed/observed */ 2157 2158 uint8_t alphaExt; /**< CONFIG5 register, LF_ALPHA bits, External Alpha value */ 2159 uint8_t betaExt; /**< CONFIG5 register, LF_BETA bits, External Beta value */ 2160 bool lfEn; /**< CONFIG5 register, LF_SET_PARAMS bit, enable for external loop filter control (alpha and beta values) */ 2161 uint16_t dtCal; /**< CONFIG5 register, DUTY CAL circuit status */ 2162 2163 uint16_t tmodFreq; /**< TRIGMOD register, TRIMOD_FREQ bits, Triangular-Frequency Modulation: modulation frequency */ 2164 uint16_t tmodGrad; /**< TRIGMOD register, TRIMOD_GRD bits, Triangular-Frequency Modulation: modulation gradient */ 2165 2166 uint32_t tmodRate; /**< TRIGMOD2 register, TRIMOD_RATE bits, Triangular-Frequency Modulation Rate */ 2167 bool tmodEn; /**< TRIGMOD2 register, TRIMOD_EN bit, Triangular-Frequency Modulation enable */ 2168 bool tmodStop; /**< TRIGMOD2 register, TRIMOD_STP bit, Triangular-Frequency Modulation stop */ 2169 2170 bool pllLocked; /**< STATUS register, LOCKED bits, PLL Lock Indicator */ 2171 bool pllUnlock; /**< STATUS register, UNLOCK_OCCURRED bit, Sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware*/ 2172 bool lockDetReset; /**< STATUS register, LOCKDET_RES bit, Restart lock detector */ 2173 bool lockDetRstAck; /**< STATUS register, LOCKDET_RES_ACK bit, Acknowledgement for lock detection restart */ 2174 2175 uint8_t dcCalDelta; /**< DUTYCAL_CTRL register, DELTA bits, Margins for the duty cycle calibration error */ 2176 bool dcRatioStatus; /**< DUTYCAL_CTRL register, RATIO_OK bit, Status of the duty calibration ratio*/ 2177 bool dcStatus; /**< DUTYCAL_CTRL register, OK bit, Status of the duty calibration*/ 2178 uint16_t dcTarget; /**< DUTYCAL_CTRL register, TARGET bits, Duty cycle target */ 2179 bool dcEnRingOsc; /**< DUTYCAL_CTRL register, CTRL_RG_EN bit, Enables ring oscillator for duty cycle digitization */ 2180 bool dcEn; /**< DUTYCAL_CTRL register, EN bit, Enables duty cycle calibration */ 2181 }cy_stc_dpll_hp_config_t; 2182 #endif 2183 #endif 2184 2185 /** Structure containing information for manual configuration of a PLL. 2186 */ 2187 typedef struct 2188 { 2189 #if defined (CY_IP_MXS40SRSS) ||defined(CY_DOXYGEN) 2190 uint8_t feedbackDiv; /**< CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ 2191 uint8_t referenceDiv; /**< CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ 2192 uint8_t outputDiv; /**< CLK_PLL_CONFIG register, OUTPUT_DIV bits */ 2193 bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 2194 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ 2195 #endif 2196 2197 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined(CY_DOXYGEN) 2198 uint32_t fracDiv; /**< CLK_PLL_CONFIG2 register, FRAC_DIV bits, only for CAT1C devices */ 2199 bool fracDitherEn; /**< CLK_PLL_CONFIG2 register, FRAC_DITHER_EN bit, only for CAT1C devices */ 2200 bool fracEn; /**< CLK_PLL_CONFIG2 register, FRAC_EN bit, only for CAT1C devices */ 2201 uint32_t sscgDepth; /**< CLK_PLL_CONFIG3 register, SSCG_DEPTH bits, only for CAT1C devices */ 2202 uint8_t sscgRate; /**< CLK_PLL_CONFIG3 register, SSCG_RATE bits, only for CAT1C devices */ 2203 bool sscgEn; /**< CLK_PLL_CONFIG3 register, SSCG_EN bit, only for CAT1C devices */ 2204 #endif 2205 #if defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) || defined(CY_DOXYGEN) 2206 cy_stc_dpll_lp_config_t *lpPllCfg; /**< DPLL-LP configuration */ 2207 #if defined (CY_IP_MXS22SRSS) 2208 cy_stc_dpll_hp_config_t *hpPllCfg; /**< DPLL-HP configuration */ 2209 #endif 2210 #endif 2211 } cy_stc_pll_manual_config_t; 2212 /** \} group_sysclk_pll_structs */ 2213 2214 #if (defined(CY_DEVICE_SECURE)) 2215 2216 /** PRA structure for Cy_SysClk_PllManualConfigure function parameters */ 2217 typedef struct 2218 { 2219 uint32_t clkPath; /**< clkPath */ 2220 cy_stc_pll_manual_config_t *praConfig; /**< config */ 2221 } cy_stc_pra_clk_pll_manconfigure_t; 2222 #endif /* (defined(CY_DEVICE_SECURE)) */ 2223 2224 /** 2225 * \addtogroup group_sysclk_pll_funcs 2226 * \{ 2227 *//******************************************************************************* 2228 * Function Name: Cy_SysClk_PllConfigure 2229 ****************************************************************************//** 2230 * 2231 * Configures a given PLL. 2232 * The configuration formula used is: 2233 * Fout = pll_clk * (P / Q / div_out), where: 2234 * Fout is the desired output frequency 2235 * pll_clk is the frequency of the input source 2236 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 2237 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 2238 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 2239 * 2240 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. 2241 * 2242 * \param config \ref cy_stc_pll_config_t 2243 * 2244 * \return Error / status code: \n 2245 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2246 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2247 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 2248 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2249 * 2250 * \note 2251 * Call this function after changing the PLL input frequency, for example if 2252 * \ref Cy_SysClk_ClkPathSetSource() is called. 2253 * 2254 * \note 2255 * Do not call this function when the PLL is enabled. If it is called, then this function 2256 * returns immediately with an error return value and no register updates. 2257 * 2258 * \note 2259 * Call \ref SystemCoreClockUpdate after this function calling 2260 * if it affects the CLK_HF0 frequency. 2261 * 2262 * \note 2263 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2264 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 2265 * 2266 * \note 2267 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2268 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 2269 * 2270 * \note 2271 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2272 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 2273 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 2274 * 2275 * \note 2276 * This API is available for CAT1A, CAT1C and CAT1D devices. 2277 * 2278 * \funcusage 2279 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllConfigure 2280 * 2281 *******************************************************************************/ 2282 cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config); 2283 2284 2285 /******************************************************************************* 2286 * Function Name: Cy_SysClk_PllManualConfigure 2287 ****************************************************************************//** 2288 * 2289 * Manually configures a PLL based on user inputs. 2290 * 2291 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. 2292 * 2293 * \param config \ref cy_stc_pll_manual_config_t 2294 * 2295 * \return Error / status code: \n 2296 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2297 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2298 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2299 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2300 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2301 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2302 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2303 * uses the PRA driver to change the protected registers. Refer to 2304 * \ref cy_en_pra_status_t for more details. 2305 * 2306 * \note 2307 * Call this function after changing the PLL input frequency; for example if 2308 * \ref Cy_SysClk_ClkPathSetSource() is called. 2309 * 2310 * \note 2311 * Do not call this function when the PLL is enabled. If it is called, then this function 2312 * returns immediately with an error return value and no register updates. 2313 * 2314 * \note 2315 * Call \ref SystemCoreClockUpdate after this function calling 2316 * if it affects the CLK_HF0 frequency. 2317 * 2318 * \note 2319 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2320 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 2321 * 2322 * \note 2323 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2324 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 2325 * 2326 * \note 2327 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2328 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 2329 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 2330 * 2331 * \note 2332 * This API is available for CAT1A, CAT1C and CAT1D devices. 2333 * 2334 * \funcusage 2335 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllManualConfigure 2336 * 2337 *******************************************************************************/ 2338 cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config); 2339 2340 2341 /******************************************************************************* 2342 * Function Name: Cy_SysClk_PllGetConfiguration 2343 ****************************************************************************//** 2344 * 2345 * Reports configuration settings for a PLL. 2346 * 2347 * \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid. 2348 * 2349 * \param config \ref cy_stc_pll_manual_config_t 2350 * 2351 * \return Error / status code: \n 2352 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 2353 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2354 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2355 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2356 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2357 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2358 * uses the PRA driver to change the protected registers. Refer to 2359 * \ref cy_en_pra_status_t for more details. 2360 * 2361 * \note 2362 * On PSoC 64 devices the configuration on the PRA driver will be reflected 2363 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 2364 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 2365 * 2366 * \note 2367 * This API is available for CAT1A, CAT1C and CAT1D devices. 2368 * 2369 * \funcusage 2370 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration 2371 * 2372 *******************************************************************************/ 2373 cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config); 2374 2375 2376 /******************************************************************************* 2377 * Function Name: Cy_SysClk_PllEnable 2378 ****************************************************************************//** 2379 * 2380 * Enables the PLL. The PLL should be configured before calling this function. 2381 * 2382 * \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid. 2383 * 2384 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 2385 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 2386 * and manually check for lock using \ref Cy_SysClk_PllLocked. 2387 * 2388 * \return Error / status code: \n 2389 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 2390 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 2391 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2392 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2393 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2394 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2395 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2396 * uses the PRA driver to change the protected registers. Refer to 2397 * \ref cy_en_pra_status_t for more details. 2398 * 2399 * \note 2400 * Call \ref SystemCoreClockUpdate after this function calling 2401 * if it affects the CLK_HF0 frequency. 2402 * 2403 * \note 2404 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2405 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 2406 * 2407 * \note 2408 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2409 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2410 * 2411 * \note 2412 * This API is available for CAT1A, CAT1C and CAT1D devices. 2413 * 2414 * \note 2415 * Take into account the possible platform specific clkHf (and further 2416 * clocking chain links) frequency limitations while using this API. 2417 * 2418 * \funcusage 2419 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllEnable 2420 * 2421 *******************************************************************************/ 2422 cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus); 2423 2424 2425 /******************************************************************************* 2426 * Function Name: Cy_SysClk_PllIsEnabled 2427 ****************************************************************************//** 2428 * 2429 * Reports whether or not the selected PLL is enabled. 2430 * 2431 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 2432 * 2433 * \return 2434 * false = disabled \n 2435 * true = enabled 2436 * 2437 * \note 2438 * This API is available for CAT1A, CAT1C and CAT1D devices. 2439 * 2440 * \funcusage 2441 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable 2442 * 2443 *******************************************************************************/ 2444 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath); 2445 2446 2447 /******************************************************************************* 2448 * Function Name: Cy_SysClk_PllLocked 2449 ****************************************************************************//** 2450 * 2451 * Reports whether or not the selected PLL is locked. 2452 * 2453 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 2454 * 2455 * \return 2456 * false = not locked \n 2457 * true = locked 2458 * 2459 * \note 2460 * This API is available for CAT1A, CAT1C and CAT1D devices. 2461 * 2462 * \funcusage 2463 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLocked 2464 * 2465 *******************************************************************************/ 2466 bool Cy_SysClk_PllLocked(uint32_t clkPath); 2467 2468 2469 /******************************************************************************* 2470 * Function Name: Cy_SysClk_PllLostLock 2471 ****************************************************************************//** 2472 * 2473 * Reports whether or not the selected PLL lost its lock since the last time this 2474 * function was called. Clears the lost lock indicator. 2475 * 2476 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 2477 * 2478 * \return 2479 * false = did not lose lock \n 2480 * true = lost lock 2481 * 2482 * \note 2483 * This API is available for CAT1A, CAT1C and CAT1D devices. 2484 * 2485 * \funcusage 2486 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLostLock 2487 * 2488 *******************************************************************************/ 2489 bool Cy_SysClk_PllLostLock(uint32_t clkPath); 2490 2491 2492 /******************************************************************************* 2493 * Function Name: Cy_SysClk_PllDisable 2494 ****************************************************************************//** 2495 * 2496 * Disables the selected PLL. 2497 * 2498 * \param clkPath Selects which PLL to disable. 1 is the first PLL; 0 is invalid. 2499 * 2500 * \return Error / status code: \n 2501 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 2502 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2503 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2504 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2505 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2506 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2507 * uses the PRA driver to change the protected registers. Refer to 2508 * \ref cy_en_pra_status_t for more details. 2509 * 2510 * \note 2511 * Call \ref SystemCoreClockUpdate after this function calling 2512 * if it affects the CLK_HF0 frequency. 2513 * 2514 * \note 2515 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 2516 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 2517 * 2518 * \note 2519 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 2520 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2521 * 2522 * \sideeffect 2523 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 2524 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 2525 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 2526 * 2527 * \note 2528 * This API is available for CAT1A, CAT1C and CAT1D devices. 2529 * 2530 * \funcusage 2531 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable 2532 * 2533 *******************************************************************************/ 2534 cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath); 2535 2536 /******************************************************************************* 2537 * Function Name: Cy_SysClk_PllGetFrequency 2538 ****************************************************************************//** 2539 * 2540 * Returns the output frequency of the PLL. 2541 * 2542 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid 2543 * 2544 * \return The output frequency of the path PLL. 2545 * 2546 * \note If the return value equals zero, that means PLL is disabled. 2547 * 2548 * \note 2549 * This API is available for CAT1A, CAT1C and CAT1D devices. 2550 * 2551 * \funcusage 2552 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetFrequency 2553 * 2554 *******************************************************************************/ 2555 uint32_t Cy_SysClk_PllGetFrequency(uint32_t clkPath); 2556 2557 2558 #if defined(CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SSRSS) && (SRSS_NUM_TOTAL_PLL > 0UL)) || defined(CY_DOXYGEN) 2559 2560 /******************************************************************************* 2561 * Function Name: Cy_SysClk_DpllLpConfigure 2562 ****************************************************************************//** 2563 * 2564 * Configures DPLL-LP. 2565 * 2566 * The configuration formula used is: 2567 * Fout = pll_clk * (P / Q / div_out), where: 2568 * Fout is the desired output frequency 2569 * pll_clk is the frequency of the input source 2570 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 2571 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 2572 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 2573 * 2574 * \param pllNum Selects which DPLL-LP to configure 2575 * 2576 * \param config \ref cy_stc_pll_config_t 2577 * 2578 * \return Error / status code: \n 2579 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2580 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2581 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 2582 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2583 * 2584 * \note 2585 * Call this function after changing the PLL input frequency, for example if 2586 * \ref Cy_SysClk_ClkPathSetSource() is called. 2587 * 2588 * \note 2589 * Do not call this function when the PLL is enabled. If it is called, then this function 2590 * returns immediately with an error return value and no register updates. 2591 * 2592 * \note 2593 * Call \ref SystemCoreClockUpdate after this function calling 2594 * if it affects the CLK_HF0 frequency. 2595 * 2596 * \note 2597 * This API is available only for CAT1D devices. 2598 * 2599 *******************************************************************************/ 2600 cy_en_sysclk_status_t Cy_SysClk_DpllLpConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 2601 2602 2603 /******************************************************************************* 2604 * Function Name: Cy_SysClk_DpllLpManualConfigure 2605 ****************************************************************************//** 2606 * 2607 * Manually configures a DPLL-LP based on user inputs. 2608 * 2609 * \param pllNum Selects which DPLL-LP to configure. 2610 * 2611 * \param config \ref cy_stc_pll_manual_config_t 2612 * 2613 * \return Error / status code: \n 2614 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2615 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2616 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2617 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2618 * 2619 * \note 2620 * Call this function after changing the PLL input frequency; for example if 2621 * \ref Cy_SysClk_ClkPathSetSource() is called. 2622 * 2623 * \note 2624 * Do not call this function when the PLL is enabled. If it is called, then this function 2625 * returns immediately with an error return value and no register updates. 2626 * 2627 * \note 2628 * Call \ref SystemCoreClockUpdate after this function calling 2629 * if it affects the CLK_HF0 frequency. 2630 * 2631 * \note 2632 * This API is available only for CAT1D devices. 2633 * 2634 *******************************************************************************/ 2635 cy_en_sysclk_status_t Cy_SysClk_DpllLpManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 2636 2637 2638 /******************************************************************************* 2639 * Function Name: Cy_SysClk_DpllLpGetConfiguration 2640 ****************************************************************************//** 2641 * 2642 * Reports configuration settings for DPLL-LP. 2643 * 2644 * \param pllNum Selects which DPLL-LP to report. 2645 * 2646 * \param config \ref cy_stc_pll_manual_config_t 2647 * 2648 * \return Error / status code: \n 2649 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 2650 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2651 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2652 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2653 * 2654 * \note 2655 * This API is available only for CAT1D devices. 2656 * 2657 *******************************************************************************/ 2658 cy_en_sysclk_status_t Cy_SysClk_DpllLpGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 2659 2660 2661 /******************************************************************************* 2662 * Function Name: Cy_SysClk_DpllLpEnable 2663 ****************************************************************************//** 2664 * 2665 * Enables the DPLL-LP. The PLL should be configured before calling this function. 2666 * 2667 * \param pllNum Selects which DPLL-LP to enable. 2668 * 2669 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 2670 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 2671 * and manually check for lock using \ref Cy_SysClk_PllLocked. 2672 * 2673 * \return Error / status code: \n 2674 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 2675 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 2676 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2677 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2678 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2679 * 2680 * \note 2681 * Call \ref SystemCoreClockUpdate after this function calling 2682 * if it affects the CLK_HF0 frequency. 2683 * 2684 * \note 2685 * This API is available only for CAT1D devices. 2686 * 2687 *******************************************************************************/ 2688 cy_en_sysclk_status_t Cy_SysClk_DpllLpEnable(uint32_t pllNum, uint32_t timeoutus); 2689 2690 2691 /******************************************************************************* 2692 * Function Name: Cy_SysClk_DpllLpIsEnabled 2693 ****************************************************************************//** 2694 * 2695 * Reports whether or not the selected DPLL-LP is enabled. 2696 * 2697 * \param pllNum Selects which DPLL-LP to check. 2698 * 2699 * \return 2700 * false = disabled \n 2701 * true = enabled 2702 * 2703 * \note 2704 * This API is available only for CAT1D devices. 2705 * 2706 *******************************************************************************/ 2707 bool Cy_SysClk_DpllLpIsEnabled(uint32_t pllNum); 2708 2709 2710 /******************************************************************************* 2711 * Function Name: Cy_SysClk_DpllLpLocked 2712 ****************************************************************************//** 2713 * 2714 * Reports whether or not the selected DPLL-LP is locked. 2715 * 2716 * \param pllNum Selects which DPLL-LP to check. 2717 * 2718 * \return 2719 * false = not locked \n 2720 * true = locked 2721 * 2722 * \note 2723 * This API is available only for CAT1D devices. 2724 * 2725 *******************************************************************************/ 2726 bool Cy_SysClk_DpllLpLocked(uint32_t pllNum); 2727 2728 2729 /******************************************************************************* 2730 * Function Name: Cy_SysClk_DpllLpLostLock 2731 ****************************************************************************//** 2732 * 2733 * Reports whether or not the selected DPLL-LP lost its lock since the last time this 2734 * function was called. Clears the lost lock indicator. 2735 * 2736 * \param pllNum Selects which DPLL-LP to check. 2737 * 2738 * \return 2739 * false = did not lose lock \n 2740 * true = lost lock 2741 * 2742 * \note 2743 * This API is available only for CAT1D devices. 2744 * 2745 *******************************************************************************/ 2746 bool Cy_SysClk_DpllLpLostLock(uint32_t pllNum); 2747 2748 2749 /******************************************************************************* 2750 * Function Name: Cy_SysClk_DpllLpDisable 2751 ****************************************************************************//** 2752 * 2753 * Disables the selected DPLL-LP. 2754 * 2755 * \param pllNum Selects which DPLL-LP to disable. 2756 * 2757 * \return Error / status code: \n 2758 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 2759 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2760 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2761 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2762 * 2763 * \note 2764 * Call \ref SystemCoreClockUpdate after this function calling 2765 * if it affects the CLK_HF0 frequency. 2766 * 2767 * \sideeffect 2768 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 2769 * If AUTO mode should be used, call \ref Cy_SysClk_DpllLpConfigure or 2770 * \ref Cy_SysClk_DpllLpManualConfigure before calling \ref Cy_SysClk_DpllLpEnable. 2771 * 2772 * \note 2773 * This API is available only for CAT1D devices. 2774 * 2775 *******************************************************************************/ 2776 cy_en_sysclk_status_t Cy_SysClk_DpllLpDisable(uint32_t pllNum); 2777 2778 /******************************************************************************* 2779 * Function Name: Cy_SysClk_DpllLpGetFrequency 2780 ****************************************************************************//** 2781 * 2782 * Gets the frequency of DPLL-LP 2783 * 2784 * \param pllNum Selects which DPLL-LP to check. 2785 * 2786 * \return 2787 * DPLL-LP Frequency 2788 * 2789 * \note 2790 * This API is available only for CAT1D devices. 2791 * 2792 *******************************************************************************/ 2793 uint32_t Cy_SysClk_DpllLpGetFrequency(uint32_t pllNum); 2794 2795 #if defined(CY_IP_MXS22SRSS) || defined(CY_DOXYGEN) 2796 2797 /******************************************************************************* 2798 * Function Name: Cy_SysClk_DpllHpConfigure 2799 ****************************************************************************//** 2800 * 2801 * Configures DPLL-HP. 2802 * 2803 * The configuration formula used is: 2804 * Fout = (pll_clk * NDIV) / (PDIV * KDIV), where: 2805 * Fout is the desired output frequency 2806 * pll_clk is the frequency of the input source 2807 * NDIV is the Ratio between DCO frequency and reference frequency. 2808 * PDIV is the reference divider. 2809 * KDIV is the post divider. 2810 * 2811 * \param pllNum Selects which DPLL-HP to configure 2812 * 2813 * \param config \ref cy_stc_pll_config_t 2814 * 2815 * \return Error / status code: \n 2816 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2817 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2818 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 2819 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2820 * 2821 * \note 2822 * Call this function after changing the PLL input frequency, for example if 2823 * \ref Cy_SysClk_ClkPathSetSource() is called. 2824 * 2825 * \note 2826 * Do not call this function when the PLL is enabled. If it is called, then this function 2827 * returns immediately with an error return value and no register updates. 2828 * 2829 * \note 2830 * Call \ref SystemCoreClockUpdate after this function calling 2831 * if it affects the CLK_HF0 frequency. 2832 * 2833 * \note 2834 * This API is available only for CAT1D devices. 2835 * 2836 *******************************************************************************/ 2837 cy_en_sysclk_status_t Cy_SysClk_DpllHpConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 2838 2839 2840 /******************************************************************************* 2841 * Function Name: Cy_SysClk_DpllHpManualConfigure 2842 ****************************************************************************//** 2843 * 2844 * Manually configures a DPLL-HP based on user inputs. 2845 * 2846 * \param pllNum Selects which DPLL-HP to configure. 2847 * 2848 * \param config \ref cy_stc_pll_manual_config_t 2849 * 2850 * \return Error / status code: \n 2851 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 2852 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2853 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2854 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2855 * 2856 * \note 2857 * Call this function after changing the PLL input frequency; for example if 2858 * \ref Cy_SysClk_ClkPathSetSource() is called. 2859 * 2860 * \note 2861 * Do not call this function when the PLL is enabled. If it is called, then this function 2862 * returns immediately with an error return value and no register updates. 2863 * 2864 * \note 2865 * Call \ref SystemCoreClockUpdate after this function calling 2866 * if it affects the CLK_HF0 frequency. 2867 * 2868 * \note 2869 * This API is available only for CAT1D devices. 2870 * 2871 *******************************************************************************/ 2872 cy_en_sysclk_status_t Cy_SysClk_DpllHpManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 2873 2874 2875 /******************************************************************************* 2876 * Function Name: Cy_SysClk_DpllHpGetConfiguration 2877 ****************************************************************************//** 2878 * 2879 * Reports configuration settings for DPLL-HP. 2880 * 2881 * \param pllNum Selects which DPLL-HP to report. 2882 * 2883 * \param config \ref cy_stc_pll_manual_config_t 2884 * 2885 * \return Error / status code: \n 2886 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 2887 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2888 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2889 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2890 * 2891 * \note 2892 * This API is available only for CAT1D devices. 2893 * 2894 *******************************************************************************/ 2895 cy_en_sysclk_status_t Cy_SysClk_DpllHpGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 2896 2897 2898 /******************************************************************************* 2899 * Function Name: Cy_SysClk_DpllHpEnable 2900 ****************************************************************************//** 2901 * 2902 * Enables the DPLL-HP. The PLL should be configured before calling this function. 2903 * 2904 * \param pllNum Selects which DPLL-HP to enable. 2905 * 2906 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 2907 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 2908 * and manually check for lock using \ref Cy_SysClk_PllLocked. 2909 * 2910 * \return Error / status code: \n 2911 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 2912 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 2913 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2914 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2915 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2916 * 2917 * \note 2918 * Call \ref SystemCoreClockUpdate after this function calling 2919 * if it affects the CLK_HF0 frequency. 2920 * 2921 * \note 2922 * This API is available only for CAT1D devices. 2923 * 2924 *******************************************************************************/ 2925 cy_en_sysclk_status_t Cy_SysClk_DpllHpEnable(uint32_t pllNum, uint32_t timeoutus); 2926 2927 2928 /******************************************************************************* 2929 * Function Name: Cy_SysClk_DpllHpIsEnabled 2930 ****************************************************************************//** 2931 * 2932 * Reports whether or not the selected DPLL-HP is enabled. 2933 * 2934 * \param pllNum Selects which DPLL-HP to check. 2935 * 2936 * \return 2937 * false = disabled \n 2938 * true = enabled 2939 * 2940 * \note 2941 * This API is available only for CAT1D devices. 2942 * 2943 *******************************************************************************/ 2944 bool Cy_SysClk_DpllHpIsEnabled(uint32_t pllNum); 2945 2946 2947 /******************************************************************************* 2948 * Function Name: Cy_SysClk_DpllHpLocked 2949 ****************************************************************************//** 2950 * 2951 * Reports whether or not the selected DPLL-HP is locked. 2952 * 2953 * \param pllNum Selects which DPLL-HP to check. 2954 * 2955 * \return 2956 * false = not locked \n 2957 * true = locked 2958 * 2959 * \note 2960 * This API is available only for CAT1D devices. 2961 * 2962 *******************************************************************************/ 2963 bool Cy_SysClk_DpllHpLocked(uint32_t pllNum); 2964 2965 2966 /******************************************************************************* 2967 * Function Name: Cy_SysClk_DpllHpLostLock 2968 ****************************************************************************//** 2969 * 2970 * Reports whether or not the selected DPLL-HP lost its lock since the last time this 2971 * function was called. Clears the lost lock indicator. 2972 * 2973 * \param pllNum Selects which DPLL-HP to check. 2974 * 2975 * \return 2976 * false = did not lose lock \n 2977 * true = lost lock 2978 * 2979 * \note 2980 * This API is available only for CAT1D devices. 2981 * 2982 *******************************************************************************/ 2983 bool Cy_SysClk_DpllHpLostLock(uint32_t pllNum); 2984 2985 2986 /******************************************************************************* 2987 * Function Name: Cy_SysClk_DpllHpDisable 2988 ****************************************************************************//** 2989 * 2990 * Disables the selected DPLL-HP. 2991 * 2992 * \param pllNum Selects which DPLL-HP to disable. 2993 * 2994 * \return Error / status code: \n 2995 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 2996 * CY_SYSCLK_BAD_PARAM - invalid clock path number 2997 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 2998 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 2999 * 3000 * \note 3001 * Call \ref SystemCoreClockUpdate after this function calling 3002 * if it affects the CLK_HF0 frequency. 3003 * 3004 * \sideeffect 3005 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3006 * If AUTO mode should be used, call \ref Cy_SysClk_DpllHpConfigure or 3007 * \ref Cy_SysClk_DpllHpManualConfigure before calling \ref Cy_SysClk_DpllHpEnable. 3008 * 3009 * \note 3010 * This API is available only for CAT1D devices. 3011 * 3012 *******************************************************************************/ 3013 cy_en_sysclk_status_t Cy_SysClk_DpllHpDisable(uint32_t pllNum); 3014 3015 /******************************************************************************* 3016 * Function Name: Cy_SysClk_DpllHpGetFrequency 3017 ****************************************************************************//** 3018 * 3019 * Gets the frequency of DPLL-HP 3020 * 3021 * \param pllNum Selects which DPLL-HP to check. 3022 * 3023 * \return 3024 * DPLL-LP Frequency 3025 * 3026 * \note 3027 * This API is available only for CAT1D devices. 3028 * 3029 *******************************************************************************/ 3030 uint32_t Cy_SysClk_DpllHpGetFrequency(uint32_t pllNum); 3031 3032 #endif 3033 #endif 3034 3035 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3) 3036 3037 /******************************************************************************** 3038 * Function Name: Cy_SysClk_Pll200MConfigure 3039 ****************************************************************************//** 3040 * 3041 * Configures 200M PLL. 3042 * The configuration formula used is: 3043 * Fout = pll_clk * (P / Q / div_out), where: 3044 * Fout is the desired output frequency 3045 * pll_clk is the frequency of the input source 3046 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 3047 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 3048 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 3049 * 3050 * \param pllNum Selects which PLL to configure 3051 * 3052 * \param config \ref cy_stc_pll_config_t 3053 * 3054 * \return Error / status code: \n 3055 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3056 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3057 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 3058 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3059 * 3060 * \note 3061 * Call this function after changing the PLL input frequency, for example if 3062 * \ref Cy_SysClk_ClkPathSetSource() is called. 3063 * 3064 * \note 3065 * Do not call this function when the PLL is enabled. If it is called, then this function 3066 * returns immediately with an error return value and no register updates. 3067 * 3068 * \note 3069 * Call \ref SystemCoreClockUpdate after this function calling 3070 * if it affects the CLK_HF0 frequency. 3071 * 3072 * \note 3073 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3074 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3075 * 3076 * \note 3077 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3078 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3079 * 3080 * \note 3081 * This API is available only for CAT1C devices. 3082 * 3083 *******************************************************************************/ 3084 cy_en_sysclk_status_t Cy_SysClk_Pll200MConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 3085 3086 3087 /******************************************************************************* 3088 * Function Name: Cy_SysClk_Pll200MManualConfigure 3089 ****************************************************************************//** 3090 * 3091 * Manually configures a 200M PLL based on user inputs. 3092 * 3093 * \param pllNum Selects which PLL to configure. 3094 * 3095 * \param config \ref cy_stc_pll_manual_config_t 3096 * 3097 * \return Error / status code: \n 3098 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3099 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3100 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3101 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3102 * For the PSoC 64 devices there are possible situations when function returns 3103 * the PRA error status code. This is because for PSoC 64 devices the function 3104 * uses the PRA driver to change the protected registers. Refer to 3105 * \ref cy_en_pra_status_t for more details. 3106 * 3107 * \note 3108 * Call this function after changing the PLL input frequency; for example if 3109 * \ref Cy_SysClk_ClkPathSetSource() is called. 3110 * 3111 * \note 3112 * Do not call this function when the PLL is enabled. If it is called, then this function 3113 * returns immediately with an error return value and no register updates. 3114 * 3115 * \note 3116 * Call \ref SystemCoreClockUpdate after this function calling 3117 * if it affects the CLK_HF0 frequency. 3118 * 3119 * \note 3120 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3121 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3122 * 3123 * \note 3124 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3125 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3126 * 3127 * \note 3128 * This API is available only for CAT1C devices. 3129 * 3130 *******************************************************************************/ 3131 cy_en_sysclk_status_t Cy_SysClk_Pll200MManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 3132 3133 3134 /******************************************************************************* 3135 * Function Name: Cy_SysClk_Pll200MGetConfiguration 3136 ****************************************************************************//** 3137 * 3138 * Reports configuration settings for 200M PLL. 3139 * 3140 * \param pllNum Selects which PLL to report. 3141 * 3142 * \param config \ref cy_stc_pll_manual_config_t 3143 * 3144 * \return Error / status code: \n 3145 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 3146 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3147 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3148 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3149 * 3150 * \note 3151 * This API is available only for CAT1C devices. 3152 * 3153 *******************************************************************************/ 3154 cy_en_sysclk_status_t Cy_SysClk_Pll200MGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 3155 3156 3157 /******************************************************************************* 3158 * Function Name: Cy_SysClk_Pll200MEnable 3159 ****************************************************************************//** 3160 * 3161 * Enables the 200M PLL. The PLL should be configured before calling this function. 3162 * 3163 * \param pllNum Selects which PLL to enable. 3164 * 3165 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 3166 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 3167 * and manually check for lock using \ref Cy_SysClk_PllLocked. 3168 * 3169 * \return Error / status code: \n 3170 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 3171 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 3172 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3173 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3174 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3175 * 3176 * \note 3177 * Call \ref SystemCoreClockUpdate after this function calling 3178 * if it affects the CLK_HF0 frequency. 3179 * 3180 * \note 3181 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3182 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3183 * 3184 * \note 3185 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3186 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3187 * 3188 * \note 3189 * This API is available only for CAT1C devices. 3190 * 3191 *******************************************************************************/ 3192 cy_en_sysclk_status_t Cy_SysClk_Pll200MEnable(uint32_t pllNum, uint32_t timeoutus); 3193 3194 3195 /******************************************************************************* 3196 * Function Name: Cy_SysClk_Pll200MIsEnabled 3197 ****************************************************************************//** 3198 * 3199 * Reports whether or not the selected 200M PLL is enabled. 3200 * 3201 * \param pllNum Selects which PLL to check. 3202 * 3203 * \return 3204 * false = disabled \n 3205 * true = enabled 3206 * 3207 * \note 3208 * This API is available only for CAT1C devices. 3209 * 3210 *******************************************************************************/ 3211 bool Cy_SysClk_Pll200MIsEnabled(uint32_t pllNum); 3212 3213 3214 /******************************************************************************* 3215 * Function Name: Cy_SysClk_Pll200MLocked 3216 ****************************************************************************//** 3217 * 3218 * Reports whether or not the selected 200M PLL is locked. 3219 * 3220 * \param pllNum Selects which PLL to check. 3221 * 3222 * \return 3223 * false = not locked \n 3224 * true = locked 3225 * 3226 * \note 3227 * This API is available only for CAT1C devices. 3228 * 3229 *******************************************************************************/ 3230 bool Cy_SysClk_Pll200MLocked(uint32_t pllNum); 3231 3232 3233 /******************************************************************************* 3234 * Function Name: Cy_SysClk_Pll200MLostLock 3235 ****************************************************************************//** 3236 * 3237 * Reports whether or not the selected 200M PLL lost its lock since the last time this 3238 * function was called. Clears the lost lock indicator. 3239 * 3240 * \param pllNum Selects which PLL to check. 3241 * 3242 * \return 3243 * false = did not lose lock \n 3244 * true = lost lock 3245 * 3246 * \note 3247 * This API is available only for CAT1C devices. 3248 * 3249 *******************************************************************************/ 3250 bool Cy_SysClk_Pll200MLostLock(uint32_t pllNum); 3251 3252 3253 /******************************************************************************* 3254 * Function Name: Cy_SysClk_Pll200MDisable 3255 ****************************************************************************//** 3256 * 3257 * Disables the selected 200M PLL. 3258 * 3259 * \param pllNum Selects which PLL to disable. 3260 * 3261 * \return Error / status code: \n 3262 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 3263 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3264 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3265 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3266 * 3267 * \note 3268 * Call \ref SystemCoreClockUpdate after this function calling 3269 * if it affects the CLK_HF0 frequency. 3270 * 3271 * \note 3272 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3273 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3274 * 3275 * \note 3276 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3277 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3278 * 3279 * \sideeffect 3280 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3281 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 3282 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 3283 * 3284 * \note 3285 * This API is available only for CAT1C devices. 3286 * 3287 *******************************************************************************/ 3288 cy_en_sysclk_status_t Cy_SysClk_Pll200MDisable(uint32_t pllNum); 3289 3290 /******************************************************************************* 3291 * Function Name: Cy_SysClk_Pll200MGetFrequency 3292 ****************************************************************************//** 3293 * 3294 * Gets the frequency of PLL200M 3295 * 3296 * \param pllNum Selects which PLL to check. 3297 * 3298 * \return 3299 * PLL200M Frequency 3300 * 3301 * \note 3302 * This API is available only for CAT1C devices. 3303 * 3304 *******************************************************************************/ 3305 uint32_t Cy_SysClk_Pll200MGetFrequency(uint32_t pllNum); 3306 3307 3308 /******************************************************************************* 3309 * Function Name: Cy_SysClk_Pll400MConfigure 3310 ****************************************************************************//** 3311 * 3312 * Configures 400M PLL. 3313 * The configuration formula used is: 3314 * Fout = pll_clk * (P / Q / div_out), where: 3315 * Fout is the desired output frequency 3316 * pll_clk is the frequency of the input source 3317 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 3318 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 3319 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 3320 * 3321 * \param pllNum Selects which PLL to configure 3322 * 3323 * \param config \ref cy_stc_pll_config_t 3324 * 3325 * \return Error / status code: \n 3326 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3327 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3328 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range \n 3329 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3330 * 3331 * \note 3332 * Call this function after changing the PLL input frequency, for example if 3333 * \ref Cy_SysClk_ClkPathSetSource() is called. 3334 * 3335 * \note 3336 * Do not call this function when the PLL is enabled. If it is called, then this function 3337 * returns immediately with an error return value and no register updates. 3338 * 3339 * \note 3340 * Call \ref SystemCoreClockUpdate after this function calling 3341 * if it affects the CLK_HF0 frequency. 3342 * 3343 * \note 3344 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3345 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3346 * 3347 * \note 3348 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3349 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3350 * 3351 * \note 3352 * This API is available only for CAT1C devices. 3353 * 3354 *******************************************************************************/ 3355 cy_en_sysclk_status_t Cy_SysClk_Pll400MConfigure(uint32_t pllNum, const cy_stc_pll_config_t *config); 3356 3357 3358 /******************************************************************************* 3359 * Function Name: Cy_SysClk_Pll400MManualConfigure 3360 ****************************************************************************//** 3361 * 3362 * Manually configures a 400M PLL based on user inputs. 3363 * 3364 * \param pllNum Selects which PLL to configure. 3365 * 3366 * \param config \ref cy_stc_pll_manual_config_t 3367 * 3368 * \return Error / status code: \n 3369 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 3370 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3371 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3372 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3373 * 3374 * \note 3375 * Call this function after changing the PLL input frequency; for example if 3376 * \ref Cy_SysClk_ClkPathSetSource() is called. 3377 * 3378 * \note 3379 * Do not call this function when the PLL is enabled. If it is called, then this function 3380 * returns immediately with an error return value and no register updates. 3381 * 3382 * \note 3383 * Call \ref SystemCoreClockUpdate after this function calling 3384 * if it affects the CLK_HF0 frequency. 3385 * 3386 * \note 3387 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3388 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 3389 * 3390 * \note 3391 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3392 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 3393 * 3394 * \note 3395 * This API is available only for CAT1C devices. 3396 * 3397 *******************************************************************************/ 3398 cy_en_sysclk_status_t Cy_SysClk_Pll400MManualConfigure(uint32_t pllNum, const cy_stc_pll_manual_config_t *config); 3399 3400 3401 /******************************************************************************* 3402 * Function Name: Cy_SysClk_Pll400MGetConfiguration 3403 ****************************************************************************//** 3404 * 3405 * Reports configuration settings for 400M PLL. 3406 * 3407 * \param pllNum Selects which PLL to report. 3408 * 3409 * \param config \ref cy_stc_pll_manual_config_t 3410 * 3411 * \return Error / status code: \n 3412 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 3413 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3414 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3415 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3416 * 3417 * \note 3418 * This API is available only for CAT1C devices. 3419 * 3420 *******************************************************************************/ 3421 cy_en_sysclk_status_t Cy_SysClk_Pll400MGetConfiguration(uint32_t pllNum, cy_stc_pll_manual_config_t *config); 3422 3423 3424 /******************************************************************************* 3425 * Function Name: Cy_SysClk_Pll400MEnable 3426 ****************************************************************************//** 3427 * 3428 * Enables the 400M PLL. The PLL should be configured before calling this function. 3429 * 3430 * \param pllNum Selects which PLL to enable. 3431 * 3432 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 3433 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 3434 * and manually check for lock using \ref Cy_SysClk_PllLocked. 3435 * 3436 * \return Error / status code: \n 3437 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 3438 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 3439 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3440 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3441 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3442 * 3443 * \note 3444 * Call \ref SystemCoreClockUpdate after this function calling 3445 * if it affects the CLK_HF0 frequency. 3446 * 3447 * \note 3448 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3449 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3450 * 3451 * \note 3452 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3453 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3454 * 3455 * \note 3456 * This API is available only for CAT1C devices. 3457 * 3458 *******************************************************************************/ 3459 cy_en_sysclk_status_t Cy_SysClk_Pll400MEnable(uint32_t pllNum, uint32_t timeoutus); 3460 3461 3462 /******************************************************************************* 3463 * Function Name: Cy_SysClk_Pll400MIsEnabled 3464 ****************************************************************************//** 3465 * 3466 * Reports whether or not the selected 400M PLL is enabled. 3467 * 3468 * \param pllNum Selects which PLL to check. 3469 * 3470 * \return 3471 * false = disabled \n 3472 * true = enabled 3473 * 3474 * \note 3475 * This API is available only for CAT1C devices. 3476 * 3477 *******************************************************************************/ 3478 bool Cy_SysClk_Pll400MIsEnabled(uint32_t pllNum); 3479 3480 3481 /******************************************************************************* 3482 * Function Name: Cy_SysClk_Pll400MLocked 3483 ****************************************************************************//** 3484 * 3485 * Reports whether or not the selected 400M PLL is locked. 3486 * 3487 * \param pllNum Selects which PLL to check. 3488 * 3489 * \return 3490 * false = not locked \n 3491 * true = locked 3492 * 3493 * \note 3494 * This API is available only for CAT1C devices. 3495 * 3496 *******************************************************************************/ 3497 bool Cy_SysClk_Pll400MLocked(uint32_t pllNum); 3498 3499 3500 /******************************************************************************* 3501 * Function Name: Cy_SysClk_Pll400MLostLock 3502 ****************************************************************************//** 3503 * 3504 * Reports whether or not the selected 400M PLL lost its lock since the last time this 3505 * function was called. Clears the lost lock indicator. 3506 * 3507 * \param pllNum Selects which PLL to check. 3508 * 3509 * \return 3510 * false = did not lose lock \n 3511 * true = lost lock 3512 * 3513 * \note 3514 * This API is available only for CAT1C devices. 3515 * 3516 *******************************************************************************/ 3517 bool Cy_SysClk_Pll400MLostLock(uint32_t pllNum); 3518 3519 3520 /******************************************************************************* 3521 * Function Name: Cy_SysClk_Pll400MDisable 3522 ****************************************************************************//** 3523 * 3524 * Disables the selected 400M PLL. 3525 * 3526 * \param pllNum Selects which PLL to disable. 3527 * 3528 * \return Error / status code: \n 3529 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 3530 * CY_SYSCLK_BAD_PARAM - invalid clock path number 3531 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is already enabled \n 3532 * CY_SYSCLK_UNSUPPORTED_STATE - PLL is not present 3533 * 3534 * \note 3535 * Call \ref SystemCoreClockUpdate after this function calling 3536 * if it affects the CLK_HF0 frequency. 3537 * 3538 * \note 3539 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3540 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 3541 * 3542 * \note 3543 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3544 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 3545 * 3546 * \sideeffect 3547 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 3548 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 3549 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 3550 * 3551 * \note 3552 * This API is available only for CAT1C devices. 3553 * 3554 *******************************************************************************/ 3555 cy_en_sysclk_status_t Cy_SysClk_Pll400MDisable(uint32_t pllNum); 3556 3557 /******************************************************************************* 3558 * Function Name: Cy_SysClk_Pll400MGetFrequency 3559 ****************************************************************************//** 3560 * 3561 * Gets the frequency of PLL400M 3562 * 3563 * \param pllNum Selects which PLL to check. 3564 * 3565 * \return 3566 * PLL400M Frequency 3567 * 3568 * \note 3569 * This API is available only for CAT1C devices. 3570 * 3571 *******************************************************************************/ 3572 uint32_t Cy_SysClk_Pll400MGetFrequency(uint32_t pllNum); 3573 3574 #endif 3575 3576 /** \} group_sysclk_pll_funcs */ 3577 3578 #endif 3579 3580 3581 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 3582 /* ========================================================================== */ 3583 /* =========================== IHO SECTION ============================ */ 3584 /* ========================================================================== */ 3585 3586 /** 3587 * \addtogroup group_sysclk_iho_funcs 3588 * \{ 3589 */ 3590 3591 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 3592 3593 /******************************************************************************* 3594 * Function Name: Cy_SysClk_IhoEnable 3595 ****************************************************************************//** 3596 * 3597 * Enables the IHO. 3598 * 3599 * \note 3600 * Call \ref SystemCoreClockUpdate after this function calling 3601 * if it affects the CLK_HF0 frequency. 3602 * 3603 * \note 3604 * This API is available for CAT1B and CAT1D. 3605 * 3606 * \note 3607 * Take into account the possible platform specific clkHf (and further 3608 * clocking chain links) frequency limitations while using this API. 3609 * 3610 *******************************************************************************/ 3611 void Cy_SysClk_IhoEnable(void); 3612 3613 3614 /******************************************************************************* 3615 * Function Name: Cy_SysClk_IhoIsEnabled 3616 ****************************************************************************//** 3617 * 3618 * Reports whether or not the selected IHO is enabled. 3619 * 3620 * \return 3621 * false = disabled \n 3622 * true = enabled 3623 * 3624 * \note 3625 * This API is available for CAT1B and CAT1D. 3626 * 3627 *******************************************************************************/ 3628 bool Cy_SysClk_IhoIsEnabled(void); 3629 3630 /******************************************************************************* 3631 * Function Name: Cy_SysClk_IhoDisable 3632 ****************************************************************************//** 3633 * 3634 * Disables IHO. 3635 * 3636 * \note 3637 * Call \ref SystemCoreClockUpdate after this function calling 3638 * if it affects the CLK_HF0 frequency. 3639 * 3640 * \note 3641 * This API is available for CAT1B and CAT1D. 3642 * 3643 *******************************************************************************/ 3644 void Cy_SysClk_IhoDisable(void); 3645 3646 #endif 3647 3648 #if defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 3649 3650 /******************************************************************************* 3651 * Function Name: Cy_SysClk_IhoDeepsleepEnable 3652 ****************************************************************************//** 3653 * 3654 * Enables the IHO during deepsleep mode 3655 * 3656 * \note 3657 * Call \ref SystemCoreClockUpdate after this function calling 3658 * if it affects the CLK_HF0 frequency. 3659 * 3660 * \note 3661 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 3662 * 3663 *******************************************************************************/ 3664 void Cy_SysClk_IhoDeepsleepEnable(void); 3665 3666 3667 /******************************************************************************* 3668 * Function Name: Cy_SysClk_IhoIsDeepsleepEnabled 3669 ****************************************************************************//** 3670 * 3671 * Reports whether or not the selected IHO is enabled during deepsleep mode. 3672 * 3673 * \return 3674 * false = disabled \n 3675 * true = enabled 3676 * 3677 * \note 3678 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 3679 * 3680 *******************************************************************************/ 3681 bool Cy_SysClk_IhoIsDeepsleepEnabled(void); 3682 3683 /******************************************************************************* 3684 * Function Name: Cy_SysClk_IhoDeepsleepDisable 3685 ****************************************************************************//** 3686 * 3687 * Disables IHO during deepsleep mode. 3688 * 3689 * \note 3690 * Call \ref SystemCoreClockUpdate after this function calling 3691 * if it affects the CLK_HF0 frequency. 3692 * 3693 * \note 3694 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 3695 * 3696 *******************************************************************************/ 3697 void Cy_SysClk_IhoDeepsleepDisable(void); 3698 3699 /******************************************************************************* 3700 * Function Name: Cy_SysClk_IhoDeepsleepDisable 3701 ****************************************************************************//** 3702 * 3703 * Set the trim value for IHO. 3704 * 3705 * \param trimVal Trim value to be set for IHO. 3706 * 3707 * \note 3708 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 3709 * 3710 *******************************************************************************/ 3711 void Cy_SysClk_IhoSetTrim(uint32_t trimVal); 3712 3713 /******************************************************************************* 3714 * Function Name: Cy_SysClk_IhoDeepsleepDisable 3715 ****************************************************************************//** 3716 * 3717 * Get the trim value configured for IHO. 3718 * 3719 * \return 3720 * Configured IHO Trim value. 3721 * 3722 * \note 3723 * This API is available for devices having CY_IP_MXS22SRSS(CAT1D) IP. 3724 * 3725 *******************************************************************************/ 3726 uint32_t Cy_SysClk_IhoGetTrim(void); 3727 3728 3729 #endif/* CY_IP_MXS22SRSS*/ 3730 3731 /** \} group_sysclk_iho_funcs */ 3732 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)*/ 3733 3734 /* ========================================================================== */ 3735 /* =========================== IMO SECTION ============================ */ 3736 /* ========================================================================== */ 3737 3738 /** 3739 * \addtogroup group_sysclk_imo_funcs 3740 * \{ 3741 */ 3742 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) 3743 3744 /******************************************************************************* 3745 * Function Name: Cy_SysClk_ImoEnable 3746 ****************************************************************************//** 3747 * 3748 * Enables the IMO. 3749 * 3750 * \note 3751 * This API is available for CAT1B and CAT1C devices. 3752 * 3753 *******************************************************************************/ 3754 void Cy_SysClk_ImoEnable(void); 3755 3756 /******************************************************************************* 3757 * Function Name: Cy_SysClk_ImoIsEnabled 3758 ****************************************************************************//** 3759 * 3760 * Reports whether or not the selected IMO is enabled. 3761 * 3762 * \return 3763 * false = disabled \n 3764 * true = enabled 3765 * 3766 * \note 3767 * This API is available for CAT1B and CAT1C devices. 3768 * 3769 *******************************************************************************/ 3770 bool Cy_SysClk_ImoIsEnabled(void); 3771 3772 /******************************************************************************* 3773 * Function Name: Cy_SysClk_ImoDisable 3774 ****************************************************************************//** 3775 * 3776 * Disables IMO. 3777 * 3778 * 3779 * \note 3780 * This API is available for CAT1B and CAT1C devices. 3781 * 3782 *******************************************************************************/ 3783 void Cy_SysClk_ImoDisable(void); 3784 #endif /* defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) */ 3785 3786 #if defined (CY_IP_MXS40SSRSS) 3787 3788 /******************************************************************************* 3789 * Function Name: Cy_SysClk_ImoDeepsleepEnable 3790 ****************************************************************************//** 3791 * 3792 * Enables the IMO during deepsleep mode 3793 * 3794 * \note 3795 * This API is available for CAT1B devices. 3796 * 3797 *******************************************************************************/ 3798 void Cy_SysClk_ImoDeepsleepEnable(void); 3799 3800 3801 /******************************************************************************* 3802 * Function Name: Cy_SysClk_ImoIsDeepsleepEnabled 3803 ****************************************************************************//** 3804 * 3805 * Reports whether or not the selected IMO is enabled during deepsleep mode. 3806 * 3807 * \return 3808 * false = disabled \n 3809 * true = enabled 3810 * 3811 * \note 3812 * This API is available for CAT1B devices. 3813 * 3814 *******************************************************************************/ 3815 bool Cy_SysClk_ImoIsDeepsleepEnabled(void); 3816 3817 /******************************************************************************* 3818 * Function Name: Cy_SysClk_ImoDeepsleepDisable 3819 ****************************************************************************//** 3820 * 3821 * Disables IMO during deepsleep mode. 3822 * 3823 * \note 3824 * This API is available for CAT1B devices. 3825 * 3826 *******************************************************************************/ 3827 void Cy_SysClk_ImoDeepsleepDisable(void); 3828 #endif /* defined (CY_IP_MXS40SSRSS) */ 3829 /** \} group_sysclk_imo_funcs */ 3830 3831 /* ========================================================================== */ 3832 /* =========================== ILO SECTION ============================ */ 3833 /* ========================================================================== */ 3834 /** 3835 * \addtogroup group_sysclk_ilo_funcs 3836 * \{ 3837 */ 3838 3839 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 3840 /******************************************************************************* 3841 * Function Name: Cy_SysClk_IloEnable 3842 ****************************************************************************//** 3843 * 3844 * Enables the ILO. 3845 * 3846 * \note The watchdog timer (WDT) must be unlocked before calling this function. 3847 * 3848 * \funcusage 3849 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloEnable 3850 * 3851 * \note 3852 * This API is available for CAT1A and CAT1B devices. 3853 * 3854 *******************************************************************************/ 3855 void Cy_SysClk_IloEnable(void); 3856 3857 3858 /******************************************************************************* 3859 * Function Name: Cy_SysClk_IloIsEnabled 3860 ****************************************************************************//** 3861 * 3862 * Reports the Enabled/Disabled status of the ILO. 3863 * 3864 * \return Boolean status of ILO: true - Enabled, false - Disabled. 3865 * 3866 * \funcusage 3867 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable 3868 * 3869 * \note 3870 * This API is available for CAT1A and CAT1B devices. 3871 * 3872 *******************************************************************************/ 3873 bool Cy_SysClk_IloIsEnabled(void); 3874 3875 3876 /******************************************************************************* 3877 * Function Name: Cy_SysClk_IloDisable 3878 ****************************************************************************//** 3879 * 3880 * Disables the ILO. ILO can't be disabled if WDT is enabled. 3881 * 3882 * \return Error / status code: \n 3883 * CY_SYSCLK_SUCCESS - ILO successfully disabled \n 3884 * CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. 3885 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 3886 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 3887 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 3888 * uses the PRA driver to change the protected registers. Refer to 3889 * \ref cy_en_pra_status_t for more details. 3890 * 3891 * \note The watchdog timer (WDT) must be unlocked before calling this function. 3892 * Do not call this function if the WDT is enabled, because the WDT is clocked by 3893 * the ILO. 3894 * 3895 * \funcusage 3896 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable 3897 * 3898 * \note 3899 * This API is available for CAT1A and CAT1B devices. 3900 * 3901 *******************************************************************************/ 3902 cy_en_sysclk_status_t Cy_SysClk_IloDisable(void); 3903 3904 3905 /******************************************************************************* 3906 * Function Name: Cy_SysClk_IloHibernateOn 3907 ****************************************************************************//** 3908 * 3909 * Controls whether the ILO stays on during a hibernate, or through an XRES or 3910 * brown-out detect (BOD) event. 3911 * 3912 * \param on 3913 * true = ILO stays on during hibernate or across XRES/BOD. \n 3914 * false = ILO turns off for hibernate or XRES/BOD. 3915 * 3916 * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. 3917 * 3918 * \funcusage 3919 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloHibernateOn 3920 * 3921 * \note 3922 * This API is available for CAT1A and CAT1B devices. 3923 * 3924 *******************************************************************************/ 3925 void Cy_SysClk_IloHibernateOn(bool on); 3926 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 3927 3928 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) 3929 /******************************************************************************* 3930 * Function Name: Cy_SysClk_IloSrcEnable 3931 ****************************************************************************//** 3932 * 3933 * Enables the ILO. 3934 * 3935 * \param iloNum - ILO index , 0 : ILO0, 1: ILO1 3936 * 3937 * \funcusage 3938 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcEnable 3939 * 3940 * \note The watchdog timer (WDT) must be unlocked before calling this function. 3941 * 3942 * \note 3943 * This API is available for CAT1C devices. 3944 * 3945 *******************************************************************************/ 3946 void Cy_SysClk_IloSrcEnable(uint32_t iloNum); 3947 3948 3949 /******************************************************************************* 3950 * Function Name: Cy_SysClk_IloSrcIsEnabled 3951 ****************************************************************************//** 3952 * 3953 * Reports the Enabled/Disabled status of the ILO. 3954 * 3955 * \param iloNum - ILO index , ILO0 or ILO1 3956 * 3957 * \funcusage 3958 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcIsEnabled 3959 * 3960 * \return Boolean status of ILO: true - Enabled, false - Disabled. 3961 * 3962 * \note 3963 * This API is available for CAT1C devices. 3964 * 3965 *******************************************************************************/ 3966 bool Cy_SysClk_IloSrcIsEnabled(uint32_t iloNum); 3967 3968 3969 /******************************************************************************* 3970 * Function Name: Cy_SysClk_IloSrcDisable 3971 ****************************************************************************//** 3972 * 3973 * Disables the ILO. ILO can't be disabled if WDT is enabled. 3974 * 3975 * \param iloNum - ILO index , 0 : ILO0, 1: ILO1 3976 * 3977 * \funcusage 3978 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcDisable 3979 * 3980 * \return Error / status code: \n 3981 * CY_SYSCLK_SUCCESS - ILO successfully disabled \n 3982 * CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. 3983 * 3984 * \note The watchdog timer (WDT) must be unlocked before calling this function. 3985 * Do not call this function if the WDT is enabled, because the WDT is clocked by 3986 * the ILO. 3987 * 3988 * \note 3989 * This API is available for CAT1C devices. 3990 * 3991 *******************************************************************************/ 3992 cy_en_sysclk_status_t Cy_SysClk_IloSrcDisable(uint32_t iloNum); 3993 3994 3995 /******************************************************************************* 3996 * Function Name: Cy_SysClk_IloSrcHibernateOn 3997 ****************************************************************************//** 3998 * 3999 * Controls whether the ILO0 stays on during a hibernate, or through an XRES or 4000 * brown-out detect (BOD) event, this feature is not available for ILO1. 4001 * 4002 * \param iloNum - ILO index , 0 : ILO0, 1: ILO1(Feature not available, ignored) 4003 * 4004 * \param on 4005 * true = ILO stays on during hibernate or across XRES/BOD. \n 4006 * false = ILO turns off for hibernate or XRES/BOD. 4007 * 4008 * \funcusage 4009 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloSrcHibernateOn 4010 * 4011 * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. 4012 * 4013 * \note 4014 * This API is available for CAT1C devices. 4015 * 4016 *******************************************************************************/ 4017 void Cy_SysClk_IloSrcHibernateOn(uint32_t iloNum, bool on); 4018 4019 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) */ 4020 4021 /** \} group_sysclk_ilo_funcs */ 4022 4023 4024 /* ========================================================================== */ 4025 /* =========================== PILO SECTION =========================== */ 4026 /* ========================================================================== */ 4027 /** 4028 * \addtogroup group_sysclk_pilo_funcs 4029 * \{ 4030 */ 4031 4032 /******************************************************************************* 4033 * Function Name: Cy_SysClk_PiloEnable 4034 ****************************************************************************//** 4035 * 4036 * Enables the PILO. 4037 * 4038 * \note This function blocks for 1 millisecond between enabling the PILO and 4039 * releasing the PILO reset. 4040 * 4041 * \funcusage 4042 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloEnable 4043 * 4044 *******************************************************************************/ 4045 void Cy_SysClk_PiloEnable(void); 4046 4047 4048 /******************************************************************************* 4049 * Function Name: Cy_SysClk_PiloIsEnabled 4050 ****************************************************************************//** 4051 * 4052 * Reports the Enabled/Disabled status of the PILO. 4053 * 4054 * \return Boolean status of PILO: true - Enabled, false - Disabled. 4055 * 4056 * \funcusage 4057 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable 4058 * 4059 *******************************************************************************/ 4060 bool Cy_SysClk_PiloIsEnabled(void); 4061 4062 4063 /******************************************************************************* 4064 * Function Name: Cy_SysClk_PiloDisable 4065 ****************************************************************************//** 4066 * 4067 * Disables the PILO. 4068 * 4069 * \funcusage 4070 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable 4071 * 4072 *******************************************************************************/ 4073 void Cy_SysClk_PiloDisable(void); 4074 4075 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 4076 4077 /******************************************************************************* 4078 * Function Name: Cy_SysClk_PiloSetTrim 4079 ****************************************************************************//** 4080 * 4081 * Sets the PILO trim bits, which adjusts the PILO frequency. This is typically 4082 * done after measuring the PILO frequency; see \ref Cy_SysClk_StartClkMeasurementCounters(). 4083 * 4084 * \funcusage 4085 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim 4086 * 4087 *******************************************************************************/ 4088 void Cy_SysClk_PiloSetTrim(uint32_t trimVal); 4089 4090 4091 /******************************************************************************* 4092 * Function Name: Cy_SysClk_PiloGetTrim 4093 ****************************************************************************//** 4094 * 4095 * Reports the current PILO trim bits value. 4096 * 4097 * \funcusage 4098 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim 4099 * 4100 *******************************************************************************/ 4101 uint32_t Cy_SysClk_PiloGetTrim(void); 4102 #endif /* defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3) */ 4103 4104 4105 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4106 /******************************************************************************* 4107 * Function Name: Cy_SysClk_PiloBackupEnable 4108 ****************************************************************************//** 4109 * 4110 * Enables the PILO as always on if Backup Domain is present. 4111 * 4112 * \note 4113 * This API is available for CAT1B & CAT1D devices. 4114 * 4115 *******************************************************************************/ 4116 void Cy_SysClk_PiloBackupEnable(void); 4117 4118 /******************************************************************************* 4119 * Function Name: Cy_SysClk_PiloBackupDisable 4120 ****************************************************************************//** 4121 * 4122 * Disables the PILO as always on if Backup Domain is present. 4123 * 4124 * \note 4125 * This API is available for CAT1B & CAT1D devices. 4126 * 4127 *******************************************************************************/ 4128 void Cy_SysClk_PiloBackupDisable(void); 4129 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 4130 4131 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4132 4133 /******************************************************************************* 4134 * Function Name: Cy_SysClk_PiloTcscEnable 4135 ****************************************************************************//** 4136 * 4137 * Enables the PILO TCSC(Second order temperature curvature correction) Feature. 4138 * 4139 * \note 4140 * This API is available for CAT1B devices. 4141 * 4142 *******************************************************************************/ 4143 void Cy_SysClk_PiloTcscEnable(void); 4144 4145 4146 /******************************************************************************* 4147 * Function Name: Cy_SysClk_PiloTcscDisable 4148 ****************************************************************************//** 4149 * 4150 * Disables the PILO TCSC(Second order temperature curvature correction) Feature. 4151 * 4152 * \note 4153 * This API is available for CAT1B devices. 4154 * 4155 *******************************************************************************/ 4156 void Cy_SysClk_PiloTcscDisable(void); 4157 4158 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 4159 4160 /** \} group_sysclk_pilo_funcs */ 4161 4162 4163 /* ========================================================================== */ 4164 /* ========================== ALTHF SECTION =========================== */ 4165 /* ========================================================================== */ 4166 /** 4167 * \addtogroup group_sysclk_alt_hf_funcs 4168 * \{ 4169 */ 4170 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4171 /******************************************************************************* 4172 * Function Name: Cy_SysClk_AltHfGetFrequency 4173 ****************************************************************************//** 4174 * 4175 * Reports the frequency of the Alternative High-Frequency Clock 4176 * 4177 * \note 4178 * This API is available for CAT1A and CAT1B devices. 4179 * 4180 * \funcusage 4181 * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() 4182 * 4183 *******************************************************************************/ 4184 uint32_t Cy_SysClk_AltHfGetFrequency(void); 4185 #endif 4186 4187 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4188 /******************************************************************************* 4189 * Function Name: Cy_SysClk_AltHfEnable 4190 ****************************************************************************//** 4191 * 4192 * Enables the ATLHF. 4193 * 4194 * \note 4195 * This API is available for CAT1B devices. 4196 * 4197 * \return Error / status code: \n 4198 * CY_SYSCLK_SUCCESS - ALTHF successfully disabled \n 4199 * CY_SYSCLK_TIMEOUT - ALTHF enabling failed due to timeout 4200 * 4201 *******************************************************************************/ 4202 cy_en_sysclk_status_t Cy_SysClk_AltHfEnable(uint32_t timeoutus); 4203 4204 /******************************************************************************* 4205 * Function Name: Cy_SysClk_IsAltHfEnabled 4206 ****************************************************************************//** 4207 * 4208 * Reports if ALTHF is enabled or not 4209 * 4210 * \note 4211 * This API is available for CAT1B devices. 4212 * 4213 * \return Status of ALTHF \n 4214 * true = Enabled \n 4215 * false = Not Enabled 4216 * 4217 *******************************************************************************/ 4218 bool Cy_SysClk_IsAltHfEnabled(void); 4219 4220 #endif /* defined (CY_IP_MXS40SSRSS) */ 4221 4222 /** \} group_sysclk_alt_hf_funcs */ 4223 4224 4225 /* ========================================================================== */ 4226 /* ========================== ALTLF SECTION =========================== */ 4227 /* ========================================================================== */ 4228 /** \cond For future usage */ 4229 uint32_t Cy_SysClk_AltLfGetFrequency(void); 4230 bool Cy_SysClk_AltLfIsEnabled(void); 4231 /** \endcond */ 4232 4233 4234 /* ========================================================================== */ 4235 /* ==================== CLOCK MEASUREMENT SECTION ===================== */ 4236 /* ========================================================================== */ 4237 /** 4238 * \addtogroup group_sysclk_calclk_enums 4239 * \{ 4240 */ 4241 /** Defines all possible clock sources */ 4242 #if defined(CY_IP_MXS22SRSS) 4243 typedef enum 4244 { 4245 CY_SYSCLK_MEAS_CLK_NC = 0U, 4246 CY_SYSCLK_MEAS_CLK_ILO = 1U, 4247 CY_SYSCLK_MEAS_CLK_WCO = 2U, 4248 CY_SYSCLK_MEAS_CLK_BAK = 3U, 4249 CY_SYSCLK_MEAS_CLK_ALTLF = 4U, 4250 CY_SYSCLK_MEAS_CLK_LFCLK = 5U, 4251 CY_SYSCLK_MEAS_CLK_IMO = 6U, 4252 CY_SYSCLK_MEAS_CLK_SLPCTRL = 7U, 4253 CY_SYSCLK_MEAS_CLK_PILO = 8U, 4254 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER = 9U, 4255 CY_SYSCLK_MEAS_CLK_MF = 10U, 4256 CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100U, 4257 CY_SYSCLK_MEAS_CLK_IHO = 0x101U, 4258 CY_SYSCLK_MEAS_CLK_EXT = 0x102U, 4259 CY_SYSCLK_MEAS_CLK_ECO = 0x103U, 4260 CY_SYSCLK_MEAS_CLK_ALTHF0 = 0x105U, 4261 CY_SYSCLK_MEAS_CLK_ALTHF1 = 0x106U, 4262 CY_SYSCLK_MEAS_CLK_TIMERCLK = 0x108U, 4263 CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x900U, 4264 CY_SYSCLK_MEAS_CLK_PATH0 = 0x900U, 4265 CY_SYSCLK_MEAS_CLK_PATH1 = 0x901U, 4266 CY_SYSCLK_MEAS_CLK_PATH2 = 0x902U, 4267 CY_SYSCLK_MEAS_CLK_PATH3 = 0x903U, 4268 CY_SYSCLK_MEAS_CLK_PATH4 = 0x904U, 4269 CY_SYSCLK_MEAS_CLK_PATH5 = 0x905U, 4270 CY_SYSCLK_MEAS_CLK_PATH6 = 0x906U, 4271 CY_SYSCLK_MEAS_CLK_PATH7 = 0x907U, 4272 CY_SYSCLK_MEAS_CLK_PATH8 = 0x908U, 4273 CY_SYSCLK_MEAS_CLK_PATH9 = 0x909U, 4274 CY_SYSCLK_MEAS_CLK_PATH10 = 0x90AU, 4275 CY_SYSCLK_MEAS_CLK_PATH11 = 0x90BU, 4276 CY_SYSCLK_MEAS_CLK_PATH12 = 0x90CU, 4277 CY_SYSCLK_MEAS_CLK_PATH13 = 0x90DU, 4278 CY_SYSCLK_MEAS_CLK_PATH14 = 0x90EU, 4279 CY_SYSCLK_MEAS_CLK_PATH15 = 0x90FU, 4280 CY_SYSCLK_MEAS_CLK_CLKHFS = 0xA00U, 4281 CY_SYSCLK_MEAS_CLK_CLKHF0 = 0xA00U, 4282 CY_SYSCLK_MEAS_CLK_CLKHF1 = 0xA01U, 4283 CY_SYSCLK_MEAS_CLK_CLKHF2 = 0xA02U, 4284 CY_SYSCLK_MEAS_CLK_CLKHF3 = 0xA03U, 4285 CY_SYSCLK_MEAS_CLK_CLKHF4 = 0xA04U, 4286 CY_SYSCLK_MEAS_CLK_CLKHF5 = 0xA05U, 4287 CY_SYSCLK_MEAS_CLK_CLKHF6 = 0xA06U, 4288 CY_SYSCLK_MEAS_CLK_CLKHF7 = 0xA07U, 4289 CY_SYSCLK_MEAS_CLK_CLKHF8 = 0xA08U, 4290 CY_SYSCLK_MEAS_CLK_CLKHF9 = 0xA09U, 4291 CY_SYSCLK_MEAS_CLK_CLKHF10 = 0xA0AU, 4292 CY_SYSCLK_MEAS_CLK_CLKHF11 = 0xA0BU, 4293 CY_SYSCLK_MEAS_CLK_CLKHF12 = 0xA0CU, 4294 CY_SYSCLK_MEAS_CLK_CLKHF13 = 0xA0DU, 4295 CY_SYSCLK_MEAS_CLK_CLKHF14 = 0xA0EU, 4296 CY_SYSCLK_MEAS_CLK_CLKHF15 = 0xA0FU, 4297 CY_SYSCLK_MEAS_CLK_LAST_CLK = 0xA10U 4298 } cy_en_meas_clks_t; 4299 #else 4300 typedef enum 4301 { 4302 CY_SYSCLK_MEAS_CLK_NC = 0U, 4303 CY_SYSCLK_MEAS_CLK_ILO = 1U, 4304 CY_SYSCLK_MEAS_CLK_WCO = 2U, 4305 CY_SYSCLK_MEAS_CLK_BAK = 3U, 4306 CY_SYSCLK_MEAS_CLK_ALTLF = 4U, 4307 CY_SYSCLK_MEAS_CLK_LFCLK = 5U, 4308 CY_SYSCLK_MEAS_CLK_IMO = 6U, 4309 CY_SYSCLK_MEAS_CLK_SLPCTRL = 7U, 4310 CY_SYSCLK_MEAS_CLK_PILO = 8U, 4311 CY_SYSCLK_MEAS_CLK_ILO1 = 9U, 4312 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER = 10U, 4313 CY_SYSCLK_MEAS_CLK_LPECO = 11U, 4314 CY_SYSCLK_MEAS_CLK_LPECO_PRESCALER = 12U, 4315 CY_SYSCLK_MEAS_CLK_MFO = 13U, 4316 CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100U, 4317 CY_SYSCLK_MEAS_CLK_ECO = 0x101U, 4318 CY_SYSCLK_MEAS_CLK_EXT = 0x102U, 4319 CY_SYSCLK_MEAS_CLK_ALTHF = 0x103U, 4320 CY_SYSCLK_MEAS_CLK_TIMERCLK = 0x104U, 4321 CY_SYSCLK_MEAS_CLK_IHO = 0x108U, 4322 CY_SYSCLK_MEAS_CLK_PWR = 0x109U, 4323 CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x500U, 4324 CY_SYSCLK_MEAS_CLK_PATH0 = 0x500U, 4325 CY_SYSCLK_MEAS_CLK_PATH1 = 0x501U, 4326 CY_SYSCLK_MEAS_CLK_PATH2 = 0x502U, 4327 CY_SYSCLK_MEAS_CLK_PATH3 = 0x503U, 4328 CY_SYSCLK_MEAS_CLK_PATH4 = 0x504U, 4329 CY_SYSCLK_MEAS_CLK_PATH5 = 0x505U, 4330 CY_SYSCLK_MEAS_CLK_PATH6 = 0x506U, 4331 CY_SYSCLK_MEAS_CLK_PATH7 = 0x507U, 4332 CY_SYSCLK_MEAS_CLK_PATH8 = 0x508U, 4333 CY_SYSCLK_MEAS_CLK_PATH9 = 0x509U, 4334 CY_SYSCLK_MEAS_CLK_PATH10 = 0x50AU, 4335 CY_SYSCLK_MEAS_CLK_PATH11 = 0x50BU, 4336 CY_SYSCLK_MEAS_CLK_PATH12 = 0x50CU, 4337 CY_SYSCLK_MEAS_CLK_PATH13 = 0x50DU, 4338 CY_SYSCLK_MEAS_CLK_PATH14 = 0x50EU, 4339 CY_SYSCLK_MEAS_CLK_PATH15 = 0x50FU, 4340 CY_SYSCLK_MEAS_CLK_CLKHFS = 0x600U, 4341 CY_SYSCLK_MEAS_CLK_CLKHF0 = 0x600U, 4342 CY_SYSCLK_MEAS_CLK_CLKHF1 = 0x601U, 4343 CY_SYSCLK_MEAS_CLK_CLKHF2 = 0x602U, 4344 CY_SYSCLK_MEAS_CLK_CLKHF3 = 0x603U, 4345 CY_SYSCLK_MEAS_CLK_CLKHF4 = 0x604U, 4346 CY_SYSCLK_MEAS_CLK_CLKHF5 = 0x605U, 4347 CY_SYSCLK_MEAS_CLK_CLKHF6 = 0x606U, 4348 CY_SYSCLK_MEAS_CLK_CLKHF7 = 0x607U, 4349 CY_SYSCLK_MEAS_CLK_CLKHF8 = 0x608U, 4350 CY_SYSCLK_MEAS_CLK_CLKHF9 = 0x609U, 4351 CY_SYSCLK_MEAS_CLK_CLKHF10 = 0x60AU, 4352 CY_SYSCLK_MEAS_CLK_CLKHF11 = 0x60BU, 4353 CY_SYSCLK_MEAS_CLK_CLKHF12 = 0x60CU, 4354 CY_SYSCLK_MEAS_CLK_CLKHF13 = 0x60DU, 4355 CY_SYSCLK_MEAS_CLK_CLKHF14 = 0x60EU, 4356 CY_SYSCLK_MEAS_CLK_CLKHF15 = 0x60FU, 4357 CY_SYSCLK_MEAS_CLK_LAST_CLK = 0x610U 4358 } cy_en_meas_clks_t; 4359 #endif 4360 /** \} group_sysclk_calclk_enums */ 4361 4362 /** 4363 * \addtogroup group_sysclk_calclk_structs 4364 * \{ 4365 */ 4366 #if (defined(CY_DEVICE_SECURE)) 4367 /** PRA structure for Cy_SysClk_StartClkMeasurementCounters function parameters */ 4368 typedef struct 4369 { 4370 cy_en_meas_clks_t clock1; /**< clock1 */ 4371 uint32_t count1; /**< count */ 4372 cy_en_meas_clks_t clock2; /**< clock2 */ 4373 } cy_stc_pra_start_clk_measurement_t; 4374 4375 #endif /* (defined(CY_DEVICE_SECURE)) */ 4376 /** \} group_sysclk_calclk_structs */ 4377 4378 /** 4379 * \addtogroup group_sysclk_calclk_funcs 4380 * \{ 4381 */ 4382 /******************************************************************************* 4383 * Function Name: Cy_SysClk_StartClkMeasurementCounters 4384 ****************************************************************************//** 4385 * 4386 * Assigns clocks to the clock measurement counters, and starts counting. The counters 4387 * let you measure a clock frequency using another clock as a reference. There are two 4388 * counters. 4389 * 4390 * - One counter (counter1), which is clocked by clock1, is loaded with an initial 4391 * value and counts down to zero. 4392 * - The second counter (counter2), which is clocked by clock2, counts up until 4393 * the first counter reaches zero. 4394 * 4395 * Either clock1 or clock2 can be a reference clock; the other clock becomes the 4396 * measured clock. The reference clock frequency is always known. \n 4397 * After calling this function, call \ref Cy_SysClk_ClkMeasurementCountersDone() 4398 * to determine when counting is done; that is, counter1 has counted down to zero. 4399 * Then call \ref Cy_SysClk_ClkMeasurementCountersGetFreq() to calculate the frequency 4400 * of the measured clock. 4401 * 4402 * \param clock1 The clock for counter1 4403 * 4404 * \param count1 The initial value for counter1, from which counter1 counts down to zero. 4405 * 4406 * \param clock2 The clock for counter2 4407 * 4408 * \return Error / status code: \n 4409 * CY_SYSCLK_INVALID_STATE if already doing a measurement \n 4410 * CY_SYSCLK_BAD_PARAM if invalid clock input parameter \n 4411 * else CY_SYSCLK_SUCCESS 4412 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 4413 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 4414 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 4415 * uses the PRA driver to change the protected registers. Refer to 4416 * \ref cy_en_pra_status_t for more details. 4417 * 4418 * \note The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF. 4419 * If clock2 frequency is greater than clock1, make sure that count1 is low enough 4420 * that counter2 does not overflow before counter1 reaches zero. 4421 * \note The time to complete a measurement is count1 / clock1 frequency. 4422 * \note The clocks for both counters must have a nonzero frequency, or 4423 * \ref Cy_SysClk_ClkMeasurementCountersGetFreq() incorrectly reports the result of the 4424 * previous measurement. 4425 * \note Do not enter a device low power mode (Sleep, Deep Sleep) while doing a measurement; 4426 * the measured clock frequency may not be accurate. 4427 * 4428 * \funcusage 4429 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_StartClkMeasurementCounters 4430 * 4431 *******************************************************************************/ 4432 cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2); 4433 4434 4435 /******************************************************************************* 4436 * Function Name: Cy_SysClk_ClkMeasurementCountersGetFreq 4437 ****************************************************************************//** 4438 * 4439 * Calculates the frequency of the indicated measured clock (clock1 or clock2). 4440 * - If clock1 is the measured clock, its frequency is: clock1 frequency = (count1 / count2) * clock2 frequency 4441 * - If clock2 is the measured clock, its frequency is: clock2 frequency = (count2 / count1) * clock1 frequency 4442 * 4443 * Call this function only after counting is done; see \ref Cy_SysClk_ClkMeasurementCountersDone(). 4444 * 4445 * \param measuredClock False (0) if the measured clock is clock1; true (1) 4446 * if the measured clock is clock2. 4447 * 4448 * \param refClkFreq The reference clock frequency (clock1 or clock2). 4449 * 4450 * \return The frequency of the measured clock, in Hz. 4451 * \warning The function returns zero, if during measurement device was in the 4452 * Deep Sleep or partially blocking flash operation occurred. It means that 4453 * current measurement is not valid and you should call the 4454 * Cy_SysClk_StartClkMeasurementCounters() function once again. 4455 * 4456 * \funcusage 4457 * Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage. 4458 * 4459 *******************************************************************************/ 4460 uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq); 4461 4462 4463 /******************************************************************************* 4464 * Function Name: Cy_SysClk_ClkMeasurementCountersDone 4465 ****************************************************************************//** 4466 * 4467 * Checks if clock measurement counting is done, that is, counter1 has counted down 4468 * to zero. Call \ref Cy_SysClk_StartClkMeasurementCounters() before calling this function. 4469 * 4470 * \return Status of calibration counters: \n 4471 * true = done \n 4472 * false = not done 4473 * 4474 * \funcusage 4475 * Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage. 4476 * 4477 *******************************************************************************/ 4478 bool Cy_SysClk_ClkMeasurementCountersDone(void); 4479 /** \} group_sysclk_calclk_funcs */ 4480 4481 4482 /* ========================================================================== */ 4483 /* ========================== TRIM SECTION ============================ */ 4484 /* ========================================================================== */ 4485 /** 4486 * \addtogroup group_sysclk_trim_funcs 4487 * \{ 4488 */ 4489 4490 #if defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 4491 4492 /******************************************************************************* 4493 * Function Name: Cy_SysClk_IloTrim 4494 ****************************************************************************//** 4495 * 4496 * Trims the ILO to be as close to 32,768 Hz as possible. 4497 * 4498 * \param iloFreq current ILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters 4499 * and other measurement functions to obtain the current frequency of the ILO. 4500 * 4501 * \return Change in trim value - 0 if done; that is, no change in trim value. 4502 * 4503 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4504 * 4505 * \funcusage 4506 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloTrim 4507 * 4508 *******************************************************************************/ 4509 int32_t Cy_SysClk_IloTrim(uint32_t iloFreq); 4510 #endif 4511 4512 #if defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) 4513 /******************************************************************************* 4514 * Function Name: Cy_SysClk_IloSetTrim 4515 ****************************************************************************//** 4516 * 4517 * Set ILO Trim Value 4518 * 4519 * \param trimVal Trim value to be set for ILO. 4520 * 4521 * \note 4522 * The function is applicable only for a CAT1B Devices. 4523 * 4524 *******************************************************************************/ 4525 void Cy_SysClk_IloSetTrim(uint32_t trimVal); 4526 4527 4528 /******************************************************************************* 4529 * Function Name: Cy_SysClk_IloGetTrim 4530 ****************************************************************************//** 4531 * 4532 * Gets the ILO Trim Value. 4533 * 4534 * \return ILO Trim Value. 4535 * 4536 * \note 4537 * The function is applicable only for a CAT1B Devices. 4538 * 4539 *******************************************************************************/ 4540 uint32_t Cy_SysClk_IloGetTrim(void); 4541 4542 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_DOXYGEN) */ 4543 4544 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 4545 4546 /******************************************************************************* 4547 * Function Name: Cy_SysClk_PiloTrim 4548 ****************************************************************************//** 4549 * 4550 * Trims the PILO to be as close to 32,768 Hz as possible. 4551 * 4552 * \param piloFreq current PILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters 4553 * and other measurement functions to obtain the current frequency of the PILO. 4554 * 4555 * \return Change in trim value; 0 if done, that is, no change in trim value. 4556 * 4557 * \funcusage 4558 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloTrim 4559 * 4560 *******************************************************************************/ 4561 int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq); 4562 4563 /******************************************************************************* 4564 * Function Name: Cy_SysClk_PiloInitialTrim 4565 ****************************************************************************//** 4566 * 4567 * Initial trims the PILO to be as close to 32,768 Hz as possible. 4568 * This function takes ECO ALTHF as reference clock and calculate Fine PILO 4569 * frequency trimming, by using binary search algorithm. 4570 * 4571 * This function requires configured BLE ECO ALTHF clock. 4572 * Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock. 4573 * 4574 * \note 4575 * This function must be call after every power-up. 4576 * 4577 * \funcusage 4578 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloInitialTrimAndUpdateTrimStep 4579 * 4580 *******************************************************************************/ 4581 void Cy_SysClk_PiloInitialTrim(void); 4582 4583 /******************************************************************************* 4584 * Function Name: Cy_SysClk_PiloUpdateTrimStep 4585 ****************************************************************************//** 4586 * 4587 * Calculates and updates the PILO trim step size (stepSize variable). 4588 * The stepSize value is used by \ref Cy_SysClk_PiloTrim function during periodical 4589 * PILO calibration. 4590 * 4591 * This function requires configured BLE ECO ALTHF clock. 4592 * Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock. 4593 * 4594 * \note 4595 * This function must be call after every power-up after call of 4596 * \ref Cy_SysClk_PiloInitialTrim function. 4597 * 4598 * \note 4599 * To achieve best trimming results it is recommended to configure BLE ECO ALTHF 4600 * reference clock to 16 MHz. 4601 * 4602 * \funcusage 4603 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloInitialTrimAndUpdateTrimStep 4604 * 4605 *******************************************************************************/ 4606 void Cy_SysClk_PiloUpdateTrimStep(void); 4607 4608 #endif /* defined (CY_IP_MXS40SRSS) */ 4609 4610 /** \} group_sysclk_trim_funcs */ 4611 4612 4613 /* ========================================================================== */ 4614 /* ====================== POWER MANAGEMENT SECTION ==================== */ 4615 /* ========================================================================== */ 4616 /** 4617 * \addtogroup group_sysclk_pm_funcs 4618 * \{ 4619 */ 4620 /******************************************************************************* 4621 * Function Name: Cy_SysClk_DeepSleepCallback 4622 ****************************************************************************//** 4623 * 4624 * Callback function to be used when entering system Deep Sleep mode. 4625 * This function is applicable if: 4626 * - The FLL is enabled 4627 * - The PLL is enabled and is driven by ECO 4628 * 4629 * This function performs the following: 4630 * 4631 * 1. Before entering Deep Sleep, the clock configuration is saved in SRAM. 4632 * If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the 4633 * source is changed to IMO. \n 4634 * If the FLL is enabled - it is just bypassed. 4635 * 2. Upon wakeup from Deep Sleep, the function waits for ECO stabilization, 4636 * then restores the configuration and waits for the FLL/PLL to regain their 4637 * frequency locks. \n 4638 * If ECO is not used and FLL is enabled - it waits for FLL lock and unbypasses it. 4639 * 4640 * The function prevents entry into Deep Sleep mode if the measurement counters 4641 * are currently counting; see \ref Cy_SysClk_StartClkMeasurementCounters. 4642 * 4643 * This function can be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep. 4644 * To do so, register this function as a callback before calling 4645 * \ref Cy_SysPm_CpuEnterDeepSleep - specify \ref CY_SYSPM_DEEPSLEEP as the callback 4646 * type and call \ref Cy_SysPm_RegisterCallback. 4647 * 4648 * \note 4649 * This function is recommended to be the last callback that is registered. 4650 * Doing so minimizes the time spent on low power mode entry and exit. \n 4651 * This function implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. 4652 * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL. \n 4653 * This function does not support such cases as, for example, FLL is enabled 4654 * but bypassed by user code before entering Deep Sleep. \n 4655 * You can use this callback implementation as an example to design custom low-power 4656 * callbacks for certain user application. 4657 * 4658 * \param callbackParams 4659 * structure with the syspm callback parameters, 4660 * see \ref cy_stc_syspm_callback_params_t. 4661 * 4662 * \param mode 4663 * Callback mode, see \ref cy_en_syspm_callback_mode_t 4664 * 4665 * \return Error / status code; see \ref cy_en_syspm_status_t. Pass if not doing 4666 * a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL 4667 * or PLL to get stable / regain its frequency lock. 4668 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 4669 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 4670 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 4671 * uses the PRA driver to change the protected registers. Refer to 4672 * \ref cy_en_pra_status_t for more details. 4673 * 4674 * \funcusage 4675 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback 4676 * 4677 *******************************************************************************/ 4678 cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode); 4679 /** \} group_sysclk_pm_funcs */ 4680 4681 4682 /* ========================================================================== */ 4683 /* =========================== WCO SECTION ============================ */ 4684 /* ========================================================================== */ 4685 /** 4686 * \addtogroup group_sysclk_wco_enums 4687 * \{ 4688 */ 4689 /** WCO bypass modes */ 4690 typedef enum 4691 { 4692 CY_SYSCLK_WCO_NOT_BYPASSED = 0U, /**< WCO is not bypassed crystal is used */ 4693 CY_SYSCLK_WCO_BYPASSED = 1U /**< WCO is bypassed external clock must be supplied on XTAL pin */ 4694 } cy_en_wco_bypass_modes_t; 4695 4696 #if defined (CY_IP_MXS28SRSS) 4697 /** WCO GM Config */ 4698 /** 4699 * \note 4700 * This enum is available for CAT1B devices. 4701 **/ 4702 typedef enum 4703 { 4704 CY_SYSCLK_WCO_GM_0P5 = 0U, /**< WCO GM - 0.5x */ 4705 CY_SYSCLK_WCO_GM_1P0 = 1U, /**< WCO GM - 1.0x */ 4706 CY_SYSCLK_WCO_GM_1P5 = 2U, /**< WCO GM - 1.5x */ 4707 CY_SYSCLK_WCO_GM_2P0 = 3U, /**< WCO GM - 2.0x */ 4708 CY_SYSCLK_WCO_GM_2P5 = 4U, /**< WCO GM - 2.5x */ 4709 CY_SYSCLK_WCO_GM_3P0 = 5U, /**< WCO GM - 3.0x */ 4710 CY_SYSCLK_WCO_GM_3P5 = 6U, /**< WCO GM - 3.5x */ 4711 CY_SYSCLK_WCO_GM_4P0 = 7U, /**< WCO GM - 4.0x */ 4712 } cy_en_wco_gain_ctrl_modes_t; 4713 #endif /* CY_IP_MXS28SRSS */ 4714 4715 #if defined (CY_IP_MXS40SRSS) 4716 /** \cond BWC */ 4717 /** 4718 * \note 4719 * This enum is available for CAT1A devices. 4720 **/ 4721 typedef enum 4722 { 4723 CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, 4724 CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, 4725 CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO 4726 } cy_en_wco_csv_supervisor_clock_t; 4727 4728 #endif /* CY_IP_MXS40SRSS */ 4729 4730 4731 /** 4732 * Clock supervisor clock loss window. There must be one clock of the supervised 4733 * clock within this many clocks of the supervising clock. 4734 * See registers CLK_CSV_HF_CTL and CLK_CSV_WCO_CTL, bitfield CSV_LOSS_WINDOW. 4735 */ 4736 typedef enum 4737 { 4738 CY_SYSCLK_CSV_LOSS_4_CYCLES = 0U, /**< 1 clock must be seen within 4 cycles of the supervising clock */ 4739 CY_SYSCLK_CSV_LOSS_8_CYCLES = 1U, /**< 1 clock must be seen within 8 cycles of the supervising clock */ 4740 CY_SYSCLK_CSV_LOSS_16_CYCLES = 2U, /**< 1 clock must be seen within 16 cycles of the supervising clock */ 4741 CY_SYSCLK_CSV_LOSS_32_CYCLES = 3U, /**< 1 clock must be seen within 32 cycles of the supervising clock */ 4742 CY_SYSCLK_CSV_LOSS_64_CYCLES = 4U, /**< 1 clock must be seen within 64 cycles of the supervising clock */ 4743 CY_SYSCLK_CSV_LOSS_128_CYCLES = 5U, /**< 1 clock must be seen within 128 cycles of the supervising clock */ 4744 CY_SYSCLK_CSV_LOSS_256_CYCLES = 6U, /**< 1 clock must be seen within 256 cycles of the supervising clock */ 4745 CY_SYSCLK_CSV_LOSS_512_CYCLES = 7U /**< 1 clock must be seen within 512 cycles of the supervising clock */ 4746 } cy_en_csv_loss_window_t; 4747 4748 /** 4749 * Clock supervisor error actions. See register CLK_CSV_HF_CTL[CSV_FREQ_ACTION and CSV_LOSS_ACTION]. 4750 */ 4751 typedef enum 4752 { 4753 CY_SYSCLK_CSV_ERROR_IGNORE = 0U, /**< Ignore the error reported by the clock supervisor */ 4754 CY_SYSCLK_CSV_ERROR_FAULT = 1U, /**< Trigger a fault when an error is reported by the clock supervisor */ 4755 CY_SYSCLK_CSV_ERROR_RESET = 2U, /**< Trigger a reset when an error is reported by the clock supervisor */ 4756 CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3U /**< Trigger a fault then reset when an error is reported by the supervisor */ 4757 } cy_en_csv_error_actions_t; 4758 4759 #if defined (CY_IP_MXS28SRSS) 4760 /** WCO CSV supervisor clock selections */ 4761 /** 4762 * \note 4763 * This enum is available for CAT1B devices. 4764 **/ 4765 typedef enum 4766 { 4767 CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, /**< WCO CSV supervisor clock source is the ILO */ 4768 CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, /**< WCO CSV supervisor clock source is the alternate low-frequency clock (ALTLF) */ 4769 CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO /**< WCO CSV supervisor clock source is the PILO */ 4770 } cy_en_wco_csv_supervisor_clock_t; 4771 4772 /** \endcond */ 4773 4774 /** \} group_sysclk_wco_enums */ 4775 4776 /** \cond BWC */ 4777 4778 /** 4779 * \addtogroup group_sysclk_wco_structs 4780 * \{ 4781 */ 4782 /** 4783 * This structure is used to configure the clock supervisor for the WCO. 4784 */ 4785 /** 4786 * \note 4787 * This structure is available for CAT1B devices. 4788 **/ 4789 typedef struct 4790 { 4791 cy_en_wco_csv_supervisor_clock_t supervisorClock; /**< supervisor clock selection */ 4792 bool enableLossDetection; /**< 1= enabled, 0= disabled. Note that if loss detection is enabled, writes to other register bits are ignored */ 4793 cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ 4794 cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ 4795 } cy_stc_wco_csv_config_t; 4796 4797 #endif /* CY_IP_MXS28SRSS */ 4798 4799 /** \} group_sysclk_wco_structs */ 4800 4801 #if defined (CY_IP_MXS40SRSS) 4802 /** 4803 * \note 4804 * This structure is available for CAT1A devices. 4805 **/ 4806 typedef struct 4807 { 4808 cy_en_wco_csv_supervisor_clock_t supervisorClock; 4809 bool enableLossDetection; 4810 cy_en_csv_loss_window_t lossWindow; 4811 cy_en_csv_error_actions_t lossAction; 4812 } cy_stc_wco_csv_config_t; 4813 /** \endcond */ 4814 #endif /* CY_IP_MXS40SRSS */ 4815 4816 /** 4817 * \addtogroup group_sysclk_wco_funcs 4818 * \{ 4819 */ 4820 /******************************************************************************* 4821 * Function Name: Cy_SysClk_WcoEnable 4822 ****************************************************************************//** 4823 * 4824 * Enables the WCO. 4825 * 4826 * \param timeoutus amount of time in microseconds to wait for the WCO to be ready. 4827 * If WCO is not ready, WCO is stopped. To avoid waiting for WCO ready set this to 0, 4828 * and manually check if WCO is okay using \ref Cy_SysClk_WcoOkay. 4829 * 4830 * \return Error / status code: \n 4831 * CY_SYSCLK_SUCCESS - WCO successfully enabled \n 4832 * CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize 4833 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 4834 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 4835 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 4836 * uses the PRA driver to change the protected registers. Refer to 4837 * \ref cy_en_pra_status_t for more details. 4838 * 4839 * \funcusage 4840 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoEnable 4841 * 4842 *******************************************************************************/ 4843 cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus); 4844 4845 4846 /******************************************************************************* 4847 * Function Name: Cy_SysClk_WcoOkay 4848 ****************************************************************************//** 4849 * 4850 * Reports the status of the WCO_OK bit. 4851 * 4852 * \return 4853 * true = okay \n 4854 * false = not okay 4855 * 4856 * \funcusage 4857 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoOkay 4858 * 4859 *******************************************************************************/ 4860 bool Cy_SysClk_WcoOkay(void); 4861 4862 4863 /******************************************************************************* 4864 * Function Name: Cy_SysClk_WcoDisable 4865 ****************************************************************************//** 4866 * 4867 * Disables the WCO. 4868 * 4869 * \note 4870 * We need to set writable option using Cy_RTC_WriteEnable 4871 * before disabling WCO, and clear writable option after disabling WCO. 4872 * 4873 * \funcusage 4874 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoDisable 4875 * 4876 *******************************************************************************/ 4877 void Cy_SysClk_WcoDisable(void); 4878 4879 4880 #if defined (CY_IP_MXS28SRSS) 4881 /******************************************************************************* 4882 * Function Name: Cy_SysClk_WcoGainControl 4883 ****************************************************************************//** 4884 * 4885 * Sets the GM(Loop Gain Control) for WCO. 4886 * 4887 * \param gmMode \ref cy_en_wco_gain_ctrl_modes_t 4888 * 4889 * \funcusage 4890 * TBD 4891 * 4892 * \note 4893 * This API is available for CAT1B devices. 4894 * 4895 *******************************************************************************/ 4896 void Cy_SysClk_WcoGainControl(cy_en_wco_gain_ctrl_modes_t gmMode); 4897 4898 #endif /* CY_IP_MXS28SRSS */ 4899 4900 /******************************************************************************* 4901 * Function Name: Cy_SysClk_WcoBypass 4902 ****************************************************************************//** 4903 * 4904 * Sets whether the WCO is bypassed or not. If it is bypassed, then a 32-kHz clock 4905 * must be provided on the wco_out pin. 4906 * 4907 * \param bypass \ref cy_en_wco_bypass_modes_t 4908 * 4909 * \funcusage 4910 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoBypass 4911 * 4912 *******************************************************************************/ 4913 void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass); 4914 /** \} group_sysclk_wco_funcs */ 4915 4916 4917 /* ========================================================================== */ 4918 /* ============================ MF SECTION ============================ */ 4919 /* ========================================================================== */ 4920 4921 4922 /** 4923 * \addtogroup group_sysclk_clk_mf_enums 4924 * \{ 4925 */ 4926 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined(CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 4927 4928 /** 4929 * \note 4930 * This Enumeration is available for CAT1B devices. 4931 **/ 4932 /** 4933 * Medium frequency (clkMf) input sources. See CLK_MF_SELECT register, MFCLK_SEL bits. 4934 * Used with functions \ref Cy_SysClk_ClkMfSetSource, and \ref Cy_SysClk_ClkMfGetSource. 4935 */ 4936 #if defined(CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 4937 4938 typedef enum 4939 { 4940 CY_SYSCLK_CLKMF_IN_IMO = 0U, /**< clkMf is sourced by the internal low speed oscillator (IMO) */ 4941 CY_SYSCLK_CLKMF_IN_ILO = 1U, /**< clkMf is sourced by the internal low speed oscillator (ILO) */ 4942 CY_SYSCLK_CLKMF_IN_WCO = 2U, /**< clkMf is sourced by the watch crystal oscillator (WCO) */ 4943 CY_SYSCLK_CLKMF_IN_ALTLF = 3U, /**< clkMf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 4944 CY_SYSCLK_CLKMF_IN_PILO = 4U, /**< clkMf is sourced by the precision low speed oscillator (PILO) */ 4945 CY_SYSCLK_CLKMF_IN_ECO_PRESCALER = 5U, /**< clkMf is sourced by the External Clock Oscillator (ECO Prescaler) */ 4946 CY_SYSCLK_CLKMF_IN_IHO = 6U, /**< clkMf is sourced by the internal high speed oscillator (IHO) */ 4947 } cy_en_clkmf_in_sources_t; 4948 4949 #else 4950 4951 typedef enum 4952 { 4953 CY_SYSCLK_CLKMF_IN_MFO = 0U, /**< clkMf is sourced by the internal low speed oscillator (MFO) */ 4954 CY_SYSCLK_CLKMF_IN_ILO = 1U, /**< clkMf is sourced by the internal low speed oscillator (ILO) */ 4955 CY_SYSCLK_CLKMF_IN_WCO = 2U, /**< clkMf is sourced by the watch crystal oscillator (WCO) */ 4956 CY_SYSCLK_CLKMF_IN_ALTLF = 3U, /**< clkMf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 4957 CY_SYSCLK_CLKMF_IN_PILO = 4U, /**< clkMf is sourced by the precision low speed oscillator (PILO) */ 4958 CY_SYSCLK_CLKMF_IN_ILO1 = 5U, /**< clkMf is sourced by the precision low speed oscillator (ILO1) */ 4959 CY_SYSCLK_CLKMF_IN_ECO_PRESCALER = 6U, /**< clkMf is sourced by the External Clock Oscillator (ECO Prescaler) */ 4960 CY_SYSCLK_CLKMF_IN_LPECO = 7U, /**< clkMf is sourced by the External Clock Oscillator (LPECO) */ 4961 } cy_en_clkmf_in_sources_t; 4962 4963 #endif 4964 4965 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined (CY_DOXYGEN) */ 4966 4967 /** \} group_sysclk_clk_mf_enums */ 4968 4969 /** 4970 * \addtogroup group_sysclk_mf_funcs 4971 * \{ 4972 */ 4973 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 4974 4975 /******************************************************************************* 4976 * Function Name: Cy_SysClk_MfoEnable 4977 ****************************************************************************//** 4978 * 4979 * Enables the MFO. 4980 * 4981 * \param deepSleepEnable enables MFO operation is Deep Sleep low power mode. 4982 * 4983 * \funcusage 4984 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 4985 * 4986 *******************************************************************************/ 4987 void Cy_SysClk_MfoEnable(bool deepSleepEnable); 4988 4989 4990 /******************************************************************************* 4991 * Function Name: Cy_SysClk_MfoIsEnabled 4992 ****************************************************************************//** 4993 * 4994 * Reports whether MFO is enabled or not. 4995 * 4996 * \return 4997 * false - disabled \n 4998 * true - enabled 4999 * 5000 * \funcusage 5001 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 5002 * 5003 *******************************************************************************/ 5004 bool Cy_SysClk_MfoIsEnabled(void); 5005 5006 5007 /******************************************************************************* 5008 * Function Name: Cy_SysClk_MfoDisable 5009 ****************************************************************************//** 5010 * 5011 * Disables the MFO. 5012 * 5013 * \funcusage 5014 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 5015 * 5016 *******************************************************************************/ 5017 void Cy_SysClk_MfoDisable(void); 5018 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 5019 5020 /** \cond internal */ 5021 #define CY_SYSCLK_MF_DIVIDER_MIN (1U) 5022 #define CY_SYSCLK_MF_DIVIDER_MAX (256U) 5023 #define CY_SYSCLK_IS_MF_DIVIDER_VALID(locDiv) ((CY_SYSCLK_MF_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_MF_DIVIDER_MAX)) 5024 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined(CY_IP_MXS22SRSS) 5025 /** 5026 * \note 5027 * This macro is available for CAT1B and CAT1D devices. 5028 **/ 5029 #if defined(CY_IP_MXS22SRSS) 5030 #define CY_SYSCLK_IF_MF_SOURCE_VALID(mfClkSrc) (((mfClkSrc) == CY_SYSCLK_CLKMF_IN_WCO) || \ 5031 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_PILO) || \ 5032 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_IHO) || \ 5033 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ECO_PRESCALER)) 5034 5035 #else 5036 5037 #define CY_SYSCLK_IF_MF_SOURCE_VALID(mfClkSrc) (((mfClkSrc) == CY_SYSCLK_CLKMF_IN_MFO) || \ 5038 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ILO) || \ 5039 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_WCO) || \ 5040 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ALTLF) || \ 5041 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_PILO) || \ 5042 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ILO1) || \ 5043 ((mfClkSrc) == CY_SYSCLK_CLKMF_IN_ECO_PRESCALER)) 5044 5045 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined(CY_IP_MXS22SRSS)*/ 5046 5047 #endif 5048 /** \endcond */ 5049 5050 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined(CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 5051 /******************************************************************************* 5052 * Function Name: Cy_SysClk_ClkMfEnable 5053 ****************************************************************************//** 5054 * 5055 * Enables the CLK_MF. 5056 * 5057 * \funcusage 5058 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5059 * 5060 *******************************************************************************/ 5061 void Cy_SysClk_ClkMfEnable(void); 5062 5063 5064 /******************************************************************************* 5065 * Function Name: Cy_SysClk_ClkMfIsEnabled 5066 ****************************************************************************//** 5067 * 5068 * Reports whether CLK_MF is enabled or not. 5069 * 5070 * \return 5071 * false - disabled \n 5072 * true - enabled 5073 * 5074 * \funcusage 5075 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5076 * 5077 *******************************************************************************/ 5078 bool Cy_SysClk_ClkMfIsEnabled(void); 5079 5080 5081 /******************************************************************************* 5082 * Function Name: Cy_SysClk_ClkMfDisable 5083 ****************************************************************************//** 5084 * 5085 * Disables the CLK_MF. 5086 * 5087 * \funcusage 5088 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 5089 * 5090 *******************************************************************************/ 5091 void Cy_SysClk_ClkMfDisable(void); 5092 5093 5094 /******************************************************************************* 5095 * Function Name: Cy_SysClk_ClkMfSetDivider 5096 ****************************************************************************//** 5097 * 5098 * Sets the clock divider for CLK_MF. 5099 * 5100 * \pre If the CLK_MF is already enabled - it should be disabled 5101 * prior to use this function by \ref Cy_SysClk_ClkMfDisable. 5102 * 5103 * \param divider divider value between 1 and 256. 5104 * 5105 * \funcusage 5106 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5107 * 5108 *******************************************************************************/ 5109 void Cy_SysClk_ClkMfSetDivider(uint32_t divider); 5110 5111 5112 /******************************************************************************* 5113 * Function Name: Cy_SysClk_ClkMfGetDivider 5114 ****************************************************************************//** 5115 * 5116 * Returns the clock divider of CLK_MF. 5117 * 5118 * \return divider value in range 1..256. 5119 * 5120 * \funcusage 5121 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5122 * 5123 *******************************************************************************/ 5124 uint32_t Cy_SysClk_ClkMfGetDivider(void); 5125 5126 5127 /******************************************************************************* 5128 * Function Name: Cy_SysClk_ClkMfGetFrequency 5129 ****************************************************************************//** 5130 * 5131 * Reports the output clock signal frequency of CLK_MF. 5132 * 5133 * \return The frequency, in Hz. 5134 * 5135 * \funcusage 5136 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 5137 * 5138 *******************************************************************************/ 5139 uint32_t Cy_SysClk_ClkMfGetFrequency(void); 5140 5141 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 5142 5143 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) || defined(CY_IP_MXS22SRSS) || defined (CY_DOXYGEN) 5144 5145 /******************************************************************************* 5146 * Function Name: Cy_SysClk_ClkMfSetSource 5147 ****************************************************************************//** 5148 * 5149 * Sets the source for the Medium frequency clock(clkMf). 5150 * 5151 * \param source \ref cy_en_clkmf_in_sources_t 5152 * 5153 * \note 5154 * This API is available for CAT1B devices. 5155 * 5156 *******************************************************************************/ 5157 void Cy_SysClk_ClkMfSetSource(cy_en_clkmf_in_sources_t source); 5158 5159 5160 /******************************************************************************* 5161 * Function Name: Cy_SysClk_ClkMfGetSource 5162 ****************************************************************************//** 5163 * 5164 * Reports the source for the Medium frequency clock (clkMf). 5165 * 5166 * \return \ref cy_en_clkmf_in_sources_t 5167 * 5168 * \note 5169 * This API is available for CAT1B devices. 5170 * 5171 *******************************************************************************/ 5172 cy_en_clkmf_in_sources_t Cy_SysClk_ClkMfGetSource(void); 5173 5174 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS28SRSS) */ 5175 5176 /** \} group_sysclk_mf_funcs */ 5177 5178 /* ========================================================================== */ 5179 /* ========================= clkHf[n] SECTION ========================= */ 5180 /* ========================================================================== */ 5181 /** 5182 * \addtogroup group_sysclk_clk_hf_enums 5183 * \{ 5184 */ 5185 /** 5186 * Selects which clkHf input, or root mux, to configure. 5187 * See CLK_ROOT_SELECT registers, bits ROOT_MUX. 5188 * Used with functions \ref Cy_SysClk_ClkHfSetSource and \ref Cy_SysClk_ClkHfGetSource. 5189 */ 5190 typedef enum 5191 { 5192 CY_SYSCLK_CLKHF_IN_CLKPATH0 = 0U, /**< clkHf input is Clock Path 0 */ 5193 CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1U, /**< clkHf input is Clock Path 1 */ 5194 CY_SYSCLK_CLKHF_IN_CLKPATH2 = 2U, /**< clkHf input is Clock Path 2 */ 5195 CY_SYSCLK_CLKHF_IN_CLKPATH3 = 3U, /**< clkHf input is Clock Path 3 */ 5196 CY_SYSCLK_CLKHF_IN_CLKPATH4 = 4U, /**< clkHf input is Clock Path 4 */ 5197 CY_SYSCLK_CLKHF_IN_CLKPATH5 = 5U, /**< clkHf input is Clock Path 5 */ 5198 CY_SYSCLK_CLKHF_IN_CLKPATH6 = 6U, /**< clkHf input is Clock Path 6 */ 5199 CY_SYSCLK_CLKHF_IN_CLKPATH7 = 7U, /**< clkHf input is Clock Path 7 */ 5200 CY_SYSCLK_CLKHF_IN_CLKPATH8 = 8U, /**< clkHf input is Clock Path 8 */ 5201 CY_SYSCLK_CLKHF_IN_CLKPATH9 = 9U, /**< clkHf input is Clock Path 9 */ 5202 CY_SYSCLK_CLKHF_IN_CLKPATH10 = 10U, /**< clkHf input is Clock Path 10 */ 5203 CY_SYSCLK_CLKHF_IN_CLKPATH11 = 11U, /**< clkHf input is Clock Path 11 */ 5204 CY_SYSCLK_CLKHF_IN_CLKPATH12 = 12U, /**< clkHf input is Clock Path 12 */ 5205 CY_SYSCLK_CLKHF_IN_CLKPATH13 = 13U, /**< clkHf input is Clock Path 13 */ 5206 CY_SYSCLK_CLKHF_IN_CLKPATH14 = 14U, /**< clkHf input is Clock Path 14 */ 5207 CY_SYSCLK_CLKHF_IN_CLKPATH15 = 15U, /**< clkHf input is Clock Path 15 */ 5208 } cy_en_clkhf_in_sources_t; 5209 5210 #if defined (CY_IP_MXS28SRSS) 5211 /** 5212 * clkHf clock supervisor input sources. See register CLK_CSV_HF_CTL[CSV_MUX]. 5213 */ 5214 /** 5215 * \note 5216 * This enum is available for CAT1B devices. 5217 **/ 5218 typedef enum 5219 { 5220 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, /**< Supervising clock is the IMO */ 5221 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, /**< Supervising clock is the external clock */ 5222 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U /**< Supervising clock is clk_althf */ 5223 } cy_en_clkhf_csv_supervisor_clock_t; 5224 #endif /* CY_IP_MXS28SRSS */ 5225 5226 /** \} group_sysclk_clk_hf_enums */ 5227 5228 /** 5229 * \addtogroup group_sysclk_clk_hf_enums 5230 * \{ 5231 */ 5232 /** 5233 * clkHf divider values. See CLK_ROOT_SELECT registers, bits ROOT_DIV. 5234 * Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider. 5235 */ 5236 #if defined (CY_IP_MXS22SRSS) || (defined (CY_MXS40SSRSS_VER_1_2) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) 5237 typedef enum 5238 { 5239 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ 5240 CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U, /**< divide clkHf by 2 */ 5241 CY_SYSCLK_CLKHF_DIVIDE_BY_3 = 2U, /**< divide clkHf by 3 */ 5242 CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 3U, /**< divide clkHf by 4 */ 5243 CY_SYSCLK_CLKHF_DIVIDE_BY_5 = 4U, /**< divide clkHf by 5 */ 5244 CY_SYSCLK_CLKHF_DIVIDE_BY_6 = 5U, /**< divide clkHf by 6 */ 5245 CY_SYSCLK_CLKHF_DIVIDE_BY_7 = 6U, /**< divide clkHf by 7 */ 5246 CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 7U, /**< divide clkHf by 8 */ 5247 CY_SYSCLK_CLKHF_DIVIDE_BY_9 = 8U, /**< divide clkHf by 9 */ 5248 CY_SYSCLK_CLKHF_DIVIDE_BY_10 = 9U, /**< divide clkHf by 10 */ 5249 CY_SYSCLK_CLKHF_DIVIDE_BY_11 = 10U, /**< divide clkHf by 11 */ 5250 CY_SYSCLK_CLKHF_DIVIDE_BY_12 = 11U, /**< divide clkHf by 12 */ 5251 CY_SYSCLK_CLKHF_DIVIDE_BY_13 = 12U, /**< divide clkHf by 13 */ 5252 CY_SYSCLK_CLKHF_DIVIDE_BY_14 = 13U, /**< divide clkHf by 14 */ 5253 CY_SYSCLK_CLKHF_DIVIDE_BY_15 = 14U, /**< divide clkHf by 15 */ 5254 CY_SYSCLK_CLKHF_DIVIDE_BY_16 = 15U, /**< divide clkHf by 16 */ 5255 CY_SYSCLK_CLKHF_MAX_DIVIDER /**< Max divider */ 5256 } cy_en_clkhf_dividers_t; 5257 #else 5258 typedef enum 5259 { 5260 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ 5261 CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U, /**< divide clkHf by 2 */ 5262 CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 2U, /**< divide clkHf by 4 */ 5263 CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 3U, /**< divide clkHf by 8 */ 5264 CY_SYSCLK_CLKHF_MAX_DIVIDER /**< Max divider */ 5265 } cy_en_clkhf_dividers_t; 5266 #endif 5267 /** \} group_sysclk_clk_hf_enums */ 5268 5269 #if defined (CY_IP_MXS40SRSS) 5270 /** \cond BWC */ 5271 typedef enum 5272 { 5273 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, 5274 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, 5275 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U 5276 } cy_en_clkhf_csv_supervisor_clock_t; 5277 5278 typedef struct 5279 { 5280 cy_en_clkhf_csv_supervisor_clock_t supervisorClock; 5281 uint16_t supervisingWindow; 5282 bool enableFrequencyFaultDetection; 5283 uint16_t frequencyLowerLimit; 5284 uint16_t frequencyUpperLimit; 5285 cy_en_csv_error_actions_t frequencyAction; 5286 bool enableLossDetection; 5287 cy_en_csv_loss_window_t lossWindow; 5288 cy_en_csv_error_actions_t lossAction; 5289 } cy_stc_clkhf_csv_config_t; 5290 5291 #if (defined (CY_DEVICE_SECURE)) 5292 /** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ 5293 typedef struct 5294 { 5295 uint32_t clkHf; /**< clkHF */ 5296 cy_en_clkhf_in_sources_t source; /**< Source */ 5297 } cy_stc_pra_clkhfsetsource_t; 5298 5299 /** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ 5300 typedef struct 5301 { 5302 uint32_t clkHf; /**< clkHF */ 5303 cy_en_clkhf_dividers_t divider; /**< divider */ 5304 } cy_stc_pra_clkhfsetdivider_t; 5305 #endif /* (defined (CY_DEVICE_SECURE)) */ 5306 5307 #define altHfFreq (cy_BleEcoClockFreqHz) 5308 /** \endcond */ 5309 #endif /* CY_IP_MXS40SRSS */ 5310 5311 #if defined (CY_IP_MXS28SRSS) 5312 /** \cond BWC */ 5313 /** 5314 * \addtogroup group_sysclk_clk_hf_structs 5315 * \{ 5316 */ 5317 /** 5318 * This structure is used to configure the clock supervisor for clkHf. 5319 */ 5320 /** 5321 * \note 5322 * This structure is available for CAT1B devices. 5323 **/ 5324 typedef struct 5325 { 5326 cy_en_clkhf_csv_supervisor_clock_t supervisorClock; /**< \ref cy_en_clkhf_csv_supervisor_clock_t */ 5327 uint16_t supervisingWindow; /**< Number of supervising clock cycles */ 5328 bool enableFrequencyFaultDetection; /**< 1= enabled, 0= disabled */ 5329 uint16_t frequencyLowerLimit; /**< Lowest frequency in kHz that supervised clock can go */ 5330 uint16_t frequencyUpperLimit; /**< Highest frequency in kHz that supervised clock can go */ 5331 cy_en_csv_error_actions_t frequencyAction; /**< \ref cy_en_csv_error_actions_t */ 5332 bool enableLossDetection; /**< 1= enabled, 0= disabled */ 5333 cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ 5334 cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ 5335 } cy_stc_clkhf_csv_config_t; 5336 /** \} group_sysclk_clk_hf_structs */ 5337 /** \endcond */ 5338 5339 /** \cond INTERNAL */ 5340 /** 5341 * \note 5342 * It is available for CAT1B devices. 5343 **/ 5344 extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */ 5345 /** \endcond */ 5346 #endif /* CY_IP_MXS28SRSS */ 5347 5348 /** 5349 * \addtogroup group_sysclk_clk_hf_funcs 5350 * \{ 5351 */ 5352 5353 5354 /******************************************************************************* 5355 * Function Name: Cy_SysClk_ClkHfEnable 5356 ****************************************************************************//** 5357 * 5358 * Enables the selected clkHf. 5359 * 5360 * \param clkHf Selects which clkHf to enable. 5361 * 5362 * \return \ref cy_en_sysclk_status_t 5363 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5364 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5365 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5366 * uses the PRA driver to change the protected registers. Refer to 5367 * \ref cy_en_pra_status_t for more details. 5368 * 5369 * \funcusage 5370 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 5371 * 5372 *******************************************************************************/ 5373 cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf); 5374 5375 5376 /******************************************************************************* 5377 * Function Name: Cy_SysClk_ClkHfIsEnabled 5378 ****************************************************************************//** 5379 * 5380 * Reports the Enabled/Disabled status of clkHf. 5381 * 5382 * \param clkHf Selects which clkHf to check. 5383 * 5384 * \return Boolean status of clkHf: true - Enabled, false - Disabled. 5385 * 5386 * \funcusage 5387 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable 5388 * 5389 * \note 5390 * This API is available for CAT1A devices. 5391 * 5392 *******************************************************************************/ 5393 bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf); 5394 5395 5396 /******************************************************************************* 5397 * Function Name: Cy_SysClk_ClkHfDisable 5398 ****************************************************************************//** 5399 * 5400 * Disables the selected clkHf. 5401 * 5402 * \param clkHf Selects which clkHf to enable. 5403 * 5404 * \return \ref cy_en_sysclk_status_t 5405 * 5406 * \note clkHf[0] cannot be disabled. 5407 * 5408 * \funcusage 5409 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable 5410 * 5411 *******************************************************************************/ 5412 cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf); 5413 5414 5415 /******************************************************************************* 5416 * Function Name: Cy_SysClk_ClkHfSetSource 5417 ****************************************************************************//** 5418 * 5419 * Selects the source of the selected clkHf. 5420 * 5421 * \param clkHf selects which clkHf mux to configure. 5422 * 5423 * \param source \ref cy_en_clkhf_in_sources_t 5424 * 5425 * \return \ref cy_en_sysclk_status_t 5426 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5427 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5428 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5429 * uses the PRA driver to change the protected registers. Refer to 5430 * \ref cy_en_pra_status_t for more details. 5431 * 5432 * \note 5433 * Call \ref SystemCoreClockUpdate after this function calling 5434 * if it affects the CLK_HF0 frequency. 5435 * 5436 * \note 5437 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 5438 * CLK_HF0 frequency is increasing. 5439 * 5440 * \note 5441 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 5442 * CLK_HF0 frequency is decreasing. 5443 * 5444 * \funcusage 5445 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource 5446 * 5447 * \note 5448 * Take into account the possible platform specific clkHf (and further 5449 * clocking chain links) frequency limitations while using this API. 5450 * 5451 * \note It takes four cycles of the originally selected clock to switch away 5452 * from it. Do not disable the original clock during this time. 5453 * 5454 *******************************************************************************/ 5455 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source); 5456 5457 5458 /******************************************************************************* 5459 * Function Name: Cy_SysClk_ClkHfGetSource 5460 ****************************************************************************//** 5461 * 5462 * Reports the source of the selected clkHf. 5463 * 5464 * \param clkHf selects which clkHf to get the source of. 5465 * 5466 * \return \ref cy_en_clkhf_in_sources_t 5467 * 5468 * \funcusage 5469 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource 5470 * 5471 *******************************************************************************/ 5472 cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); 5473 5474 5475 /******************************************************************************* 5476 * Function Name: Cy_SysClk_ClkHfSetDivider 5477 ****************************************************************************//** 5478 * 5479 * Sets the pre-divider for a clkHf. 5480 * 5481 * \param clkHf selects which clkHf divider to configure. 5482 * 5483 * \param divider \ref cy_en_clkhf_dividers_t 5484 * 5485 * \return \ref cy_en_sysclk_status_t 5486 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 5487 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 5488 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 5489 * uses the PRA driver to change the protected registers. Refer to 5490 * \ref cy_en_pra_status_t for more details. 5491 * 5492 * \note Also call \ref Cy_SysClk_ClkHfSetSource to set the clkHf source. 5493 * 5494 * \note 5495 * Call \ref SystemCoreClockUpdate after this function calling 5496 * if it affects the CLK_HF0 frequency. 5497 * 5498 * \note 5499 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 5500 * CLK_HF0 frequency is increasing. 5501 * 5502 * \note 5503 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 5504 * CLK_HF0 frequency is decreasing. 5505 * 5506 * \note 5507 * Take into account the possible platform specific clkHf (and further 5508 * clocking chain links) frequency limitations while using this API. 5509 * 5510 * \funcusage 5511 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 5512 * 5513 *******************************************************************************/ 5514 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider); 5515 5516 5517 /******************************************************************************* 5518 * Function Name: Cy_SysClk_ClkHfGetDivider 5519 ****************************************************************************//** 5520 * 5521 * Reports the pre-divider value for a clkHf. 5522 * 5523 * \param clkHf selects which clkHf to check divider of. 5524 * 5525 * \return \ref cy_en_clkhf_dividers_t 5526 * 5527 * \funcusage 5528 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 5529 * 5530 *******************************************************************************/ 5531 cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf); 5532 5533 5534 /******************************************************************************* 5535 * Function Name: Cy_SysClk_ClkHfGetFrequency 5536 ****************************************************************************//** 5537 * 5538 * Reports the frequency of the selected clkHf 5539 * 5540 * \param clkHf Selects the clkHf 5541 * 5542 * \return The frequency, in Hz. 5543 * 5544 * \note 5545 * The reported frequency may be zero, which indicates unknown. This happens if 5546 * the source input is dsi_out or clk_altlf. 5547 * 5548 * \note 5549 * Calculates the HF frequency irrespective of whether HF is enabled or not. 5550 * 5551 * \funcusage 5552 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 5553 * 5554 *******************************************************************************/ 5555 uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf); 5556 5557 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) 5558 /******************************************************************************* 5559 * Function Name: Cy_SysClk_ClkHfDirectSel 5560 ****************************************************************************//** 5561 * 5562 * Enable/Disable the direct source selection as IMO for CLK_HF[[n]] 5563 * 5564 * \param clkHf Selects the clkHf 5565 * 5566 * \param enable True - Selects IMO for CAT1B/CAT1C or IHO for CAT1D, False - Selects Root Mux 5567 * 5568 * \return \ref cy_en_sysclk_status_t 5569 * CY_SYSCLK_BAD_PARAM - If clkhf is incorrect. 5570 * CY_SYSCLK_SUCCESS - If successfully Enabled/Disabled. 5571 * 5572 * \note 5573 * This API is available for CAT1B, CAT1C and CAT1D devices. 5574 * 5575 *******************************************************************************/ 5576 cy_en_sysclk_status_t Cy_SysClk_ClkHfDirectSel(uint32_t clkHf, bool enable); 5577 5578 /******************************************************************************* 5579 * Function Name: Cy_SysClk_IsClkHfDirectSelEnabled 5580 ****************************************************************************//** 5581 * 5582 * Checks if direct source selection as IMO for CLK_HF[[n]] is enabled/disabled 5583 * 5584 * \param clkHf Selects the clkHf 5585 * 5586 * \return 5587 * True - IMO selected for CAT1B/CAT1C or IHO for CAT1D, False - Root Mux is selected. 5588 * 5589 * \note 5590 * This API is available for CAT1B, CAT1C and CAT1D devices. 5591 * 5592 *******************************************************************************/ 5593 bool Cy_SysClk_IsClkHfDirectSelEnabled(uint32_t clkHf); 5594 5595 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) */ 5596 5597 /** \} group_sysclk_clk_hf_funcs */ 5598 5599 5600 /* ========================================================================== */ 5601 /* ========================= clk_fast SECTION ========================= */ 5602 /* ========================================================================== */ 5603 /** 5604 * \addtogroup group_sysclk_clk_fast_funcs 5605 * \{ 5606 */ 5607 5608 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 5609 5610 /******************************************************************************* 5611 * Function Name: Cy_SysClk_ClkFastSetDivider 5612 ****************************************************************************//** 5613 * 5614 * Sets the clock divider for the fast clock, which sources the main processor. 5615 * The source of this divider is clkHf[0]. 5616 * 5617 * \param divider divider value between 0 and 255. 5618 * Causes integer division of (divider value + 1), or division by 1 to 256. 5619 * 5620 * \note 5621 * Call \ref SystemCoreClockUpdate after this function calling. 5622 * 5623 * \note 5624 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 5625 * CLK_FAST frequency is increasing. 5626 * 5627 * \note 5628 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 5629 * CLK_FAST frequency is decreasing. 5630 * 5631 * \note 5632 * This API is available only for CAT1A devices. 5633 * 5634 * \funcusage 5635 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 5636 * 5637 *******************************************************************************/ 5638 void Cy_SysClk_ClkFastSetDivider(uint8_t divider); 5639 5640 5641 /******************************************************************************* 5642 * Function Name: Cy_SysClk_ClkFastGetDivider 5643 ****************************************************************************//** 5644 * 5645 * Returns the clock divider for the fast clock. 5646 * 5647 * \return The divider value for the fast clock. 5648 * The integer division done is by (divider value + 1), or division by 1 to 256. 5649 * 5650 * \note 5651 * This API is available only for CAT1A devices. 5652 * 5653 * \funcusage 5654 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 5655 * 5656 *******************************************************************************/ 5657 uint8_t Cy_SysClk_ClkFastGetDivider(void); 5658 5659 5660 /******************************************************************************* 5661 * Function Name: Cy_SysClk_ClkFastGetFrequency 5662 ****************************************************************************//** 5663 * 5664 * Reports the frequency of the fast clock. 5665 * 5666 * \return The frequency, in Hz. 5667 * 5668 * \note 5669 * This API is available only for CAT1A devices. 5670 * 5671 * \funcusage 5672 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 5673 * 5674 *******************************************************************************/ 5675 uint32_t Cy_SysClk_ClkFastGetFrequency(void); 5676 5677 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) */ 5678 5679 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) 5680 5681 /******************************************************************************* 5682 * Function Name: Cy_SysClk_ClkFastSrcSetDivider 5683 ****************************************************************************//** 5684 * 5685 * Sets the clock divider for the fast clock, which sources the main processor. 5686 * The source of this divider is clkHf[0]. 5687 * 5688 * \param clkFastNum 0 for CLOCK_FAST_0 and 1 for CLOCK_FAST_1 5689 * 5690 * \param intDiv Integer divider 5691 * 5692 * \param fracDiv Fractional divider 5693 * 5694 * \note 5695 * Call \ref SystemCoreClockUpdate after this function calling. 5696 * 5697 * \note 5698 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 5699 * CLK_FAST frequency is increasing. 5700 * 5701 * \note 5702 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 5703 * CLK_FAST frequency is decreasing. 5704 * 5705 * \note 5706 * This API is available only for CAT1C devices. 5707 * 5708 *******************************************************************************/ 5709 void Cy_SysClk_ClkFastSrcSetDivider(uint32_t clkFastNum, uint8_t intDiv, uint8_t fracDiv); 5710 5711 5712 /******************************************************************************* 5713 * Function Name: Cy_SysClk_ClkFastSrcGetDivider 5714 ****************************************************************************//** 5715 * 5716 * Returns the Integer and Fractional clock divider for the fast clock. 5717 * 5718 * \param clkFastNum 0 for CLOCK_FAST_0 and 1 for CLOCK_FAST_1 5719 * 5720 * \param dividerIntValue - Integer divider 5721 * 5722 * \param dividerFracValue - Fractional divider 5723 * 5724 * \return None. Loads pointed-to variables. 5725 * 5726 * \note 5727 * This API is available only for CAT1C devices. 5728 * 5729 *******************************************************************************/ 5730 void Cy_SysClk_ClkFastSrcGetDivider(uint32_t clkFastNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue); 5731 5732 5733 /******************************************************************************* 5734 * Function Name: Cy_SysClk_ClkFastSrcGetFrequency 5735 ****************************************************************************//** 5736 * 5737 * Reports the frequency of the fast clock. 5738 * 5739 * \param clkFastNum 0 for CLOCK_FAST_0 and 1 for CLOCK_FAST_1 5740 * 5741 * \return The frequency, in Hz. 5742 * 5743 * \note 5744 * This API is available only for CAT1C devices. 5745 * 5746 *******************************************************************************/ 5747 uint32_t Cy_SysClk_ClkFastSrcGetFrequency(uint32_t clkFastNum); 5748 5749 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) */ 5750 5751 /** \} group_sysclk_clk_fast_funcs */ 5752 5753 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) 5754 5755 /* ========================================================================== */ 5756 /* ======================== PERI SECTION ========================== */ 5757 /* ========================================================================== */ 5758 5759 /** 5760 * \addtogroup group_sysclk_clk_peripheral_enums 5761 * \{ 5762 */ 5763 /** 5764 * Slave control Register Numbers 5765 * Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider. 5766 */ 5767 typedef enum 5768 { 5769 CY_SYSCLK_PERI_GROUP_SL_CTL = 0U, /**<Selects SL_CTL*/ 5770 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 5771 CY_SYSCLK_PERI_GROUP_SL_CTL2 = 1U, /**<Selects SL_CTL2*/ 5772 CY_SYSCLK_PERI_GROUP_SL_CTL3 = 2U, /**<Selects SL_CTL3*/ 5773 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */ 5774 } cy_en_peri_grp_sl_ctl_num_t; 5775 5776 /** \} group_sysclk_clk_peripheral_enums */ 5777 5778 /** \cond internal */ 5779 /* Macro to validate if the SL control register number passed */ 5780 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) 5781 #define CY_SYSCLK_IS_SL_CTL_NUM_VALID(slaveCtl) (((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL) || \ 5782 ((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL2) || \ 5783 ((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL3)) 5784 #else 5785 #define CY_SYSCLK_IS_SL_CTL_NUM_VALID(slaveCtl) (((slaveCtl) == CY_SYSCLK_PERI_GROUP_SL_CTL)) 5786 5787 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */ 5788 5789 /** \endcond */ 5790 5791 5792 /** 5793 * \addtogroup group_sysclk_clk_peripheral_funcs 5794 * \{ 5795 */ 5796 /******************************************************************************* 5797 * Function Name: Cy_SysClk_PeriGroupSetDivider 5798 ****************************************************************************//** 5799 * 5800 * Sets the divider value for a particular group 5801 * 5802 * \return \ref cy_en_sysclk_status_t 5803 * 5804 * \param groupNum Selects the PERI Group Number 5805 * \note 5806 * Input of groupNum parameter will be 5807 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 5808 * /include/\<series\>_config.h) 5809 * CAT1B/CAT1C - group number 5810 * 5811 * \param divider Selects the divider value 5812 * 5813 * \note 5814 * This API is available for CAT1B, CAT1C and CAT1D devices. 5815 * 5816 * \note 5817 * Clock divider functionality is product specific, Refer to TRM before using this API 5818 * Example:- 5819 * For CAT1B devices Group-0 does not have the clock divider functionality. 5820 * For CAT1C devices Group-0,1 and 2 does not have the clock divider functionality. 5821 * For the above not supported groups this API will return success, but write will 5822 * not happen. 5823 * 5824 *******************************************************************************/ 5825 cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetDivider(uint32_t groupNum, uint32_t divider); 5826 5827 5828 /******************************************************************************* 5829 * Function Name: Cy_SysClk_PeriGroupGetDivider 5830 ****************************************************************************//** 5831 * 5832 * Gets the divider value for a particular group 5833 * 5834 * \return Divider value 5835 * 5836 * \param groupNum Selects the PERI Group Number 5837 * \note 5838 * Input of groupNum parameter will be 5839 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 5840 * /include/\<series\>_config.h) 5841 * CAT1B/CAT1C - group number 5842 * 5843 * \note 5844 * This API is available for CAT1B, CAT1C and CAT1D devices. 5845 * 5846 * \note 5847 * Clock divider functionality is product specific, Refer to TRM before using this API 5848 * Example:- 5849 * For CAT1B devices Group-0 does not have the clock divider functionality. 5850 * For CAT1C devices Group-0,1 and 2 does not have the clock divider functionality. 5851 * For the above not supported groups this API returns zero. 5852 * 5853 *******************************************************************************/ 5854 uint32_t Cy_SysClk_PeriGroupGetDivider(uint32_t groupNum); 5855 5856 5857 /******************************************************************************* 5858 * Function Name: Cy_SysClk_PeriGroupSetSlaveCtl 5859 ****************************************************************************//** 5860 * 5861 * Sets the particular Slave Control value for a particular group 5862 * 5863 * \return \ref cy_en_sysclk_status_t 5864 * 5865 * \param groupNum Selects the PERI Group Number 5866 * \note 5867 * Input of groupNum parameter will be 5868 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 5869 * /include/\<series\>_config.h) 5870 * CAT1B/CAT1C - group number 5871 * 5872 * \param slaveCtl Selects the Slave Control Register Number 5873 * 5874 * \param value Value to be written 5875 * 5876 * \note 5877 * This API is available for CAT1B, CAT1C and CAT1D devices. 5878 * 5879 *******************************************************************************/ 5880 cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetSlaveCtl(uint32_t groupNum, cy_en_peri_grp_sl_ctl_num_t slaveCtl, uint32_t value); 5881 5882 /******************************************************************************* 5883 * Function Name: Cy_SysClk_PeriGroupGetSlaveCtl 5884 ****************************************************************************//** 5885 * 5886 * Gets the particular Slave Control value for a particular group 5887 * 5888 * \return Divider value 5889 * 5890 * \param groupNum Selects the PERI Group Number 5891 * \note 5892 * Input of groupNum parameter will be 5893 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 5894 * /include/\<series\>_config.h) 5895 * CAT1B/CAT1C - group number 5896 * 5897 * \param slaveCtl Selects the Slave Control Register Number 5898 * 5899 * \note 5900 * This API is available for CAT1B, CAT1C and CAT1D devices. 5901 * 5902 *******************************************************************************/ 5903 uint32_t Cy_SysClk_PeriGroupGetSlaveCtl(uint32_t groupNum, cy_en_peri_grp_sl_ctl_num_t slaveCtl); 5904 5905 /******************************************************************************* 5906 * Function Name: Cy_SysClk_IsPeriGroupSlaveCtlSet 5907 ****************************************************************************//** 5908 * 5909 * Gets the mask value of particular slave control register for a particular group 5910 * 5911 * \return Divider value 5912 * 5913 * \param groupNum Selects the PERI Group Number 5914 * \note 5915 * Input of groupNum parameter will be 5916 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 5917 * /include/\<series\>_config.h) 5918 * CAT1B/CAT1C - group number 5919 * 5920 * \param slaveCtl Selects the Slave Control Register Number 5921 * 5922 * \param slaveMsk Selects the bit position(s) that needs to be obtained 5923 * 5924 * \note 5925 * This API is available for CAT1B, CAT1C and CAT1D devices. 5926 * 5927 *******************************************************************************/ 5928 bool Cy_SysClk_IsPeriGroupSlaveCtlSet(uint32_t groupNum,cy_en_peri_grp_sl_ctl_num_t slaveCtl, uint32_t slaveMsk); 5929 5930 #if defined (CY_IP_MXS22SRSS) 5931 /******************************************************************************* 5932 * Function Name: Cy_SysClk_PeriGroupSlaveInit 5933 ****************************************************************************//** 5934 * 5935 * Initializes an IP 5936 * 5937 * \param periNum Selects the PERI Number 5938 * 5939 * \param groupNum Selects the PERI Group Number 5940 * \note 5941 * Input of groupNum parameter will be 5942 * CAT1D devices - enum en_peri_grp_t(devices/COMPONENT_CAT1\<subcategory\> 5943 * /include/\<series\>_config.h) 5944 * CAT1B/CAT1C - group number 5945 * 5946 * \param slaveNum Selects the bit position of the IP that needs to be enabled 5947 * 5948 * \param clkHfNum Selects the CLK_HF number that needs to be enabled for 5949 * the IP to get enabled. 5950 * 5951 * \note 5952 * This API is available only for CAT1D devices. 5953 * 5954 *******************************************************************************/ 5955 void Cy_SysClk_PeriGroupSlaveInit(uint32_t periNum, uint32_t groupNum, uint32_t slaveNum, uint32_t clkHfNum); 5956 5957 #endif /* defined (CY_IP_MXS22SRSS) */ 5958 5959 /** \} group_sysclk_clk_peripheral_funcs */ 5960 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) */ 5961 5962 /* ========================================================================== */ 5963 /* ======================== clk_peri SECTION ========================== */ 5964 /* ========================================================================== */ 5965 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) 5966 5967 /** 5968 * \addtogroup group_sysclk_clk_peri_funcs 5969 * \{ 5970 */ 5971 5972 5973 /******************************************************************************* 5974 * Function Name: Cy_SysClk_ClkPeriSetDivider 5975 ****************************************************************************//** 5976 * 5977 * Sets the clock divider for the peripheral clock tree. All peripheral clock 5978 * dividers are sourced from this clock. Also the Cortex M0+ clock divider is 5979 * sourced from this clock. The source of this divider is clkHf[0] 5980 * 5981 * \param divider divider value between 0 and 255 5982 * Causes integer division of (divider value + 1), or division by 1 to 256. 5983 * 5984 * \note 5985 * Call \ref SystemCoreClockUpdate after this function calling. 5986 * 5987 * \note 5988 * This API is available for CAT1A & CAT1C devices. 5989 * 5990 * \funcusage 5991 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 5992 * 5993 *******************************************************************************/ 5994 void Cy_SysClk_ClkPeriSetDivider(uint8_t divider); 5995 5996 5997 /******************************************************************************* 5998 * Function Name: Cy_SysClk_ClkPeriGetFrequency 5999 ****************************************************************************//** 6000 * 6001 * Reports the frequency of the peri clock. 6002 * 6003 * \return The frequency, in Hz. 6004 * 6005 * \note 6006 * This API is available for CAT1A & CAT1C devices. 6007 * 6008 * \funcusage 6009 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 6010 * 6011 *******************************************************************************/ 6012 uint32_t Cy_SysClk_ClkPeriGetFrequency(void); 6013 6014 6015 /******************************************************************************* 6016 * Function Name: Cy_SysClk_ClkPeriGetDivider 6017 ****************************************************************************//** 6018 * 6019 * Returns the clock divider of the peripheral (peri) clock. 6020 * 6021 * \return The divider value. 6022 * The integer division done is by (divider value + 1), or division by 1 to 256. 6023 * 6024 * \note 6025 * This API is available for CAT1A & CAT1C devices. 6026 * 6027 * \funcusage 6028 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 6029 * 6030 *******************************************************************************/ 6031 uint8_t Cy_SysClk_ClkPeriGetDivider(void); 6032 /** \} group_sysclk_clk_peri_funcs */ 6033 6034 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) */ 6035 6036 /* ========================================================================== */ 6037 /* ===================== clk_peripherals SECTION ====================== */ 6038 /* ========================================================================== */ 6039 /** 6040 * \addtogroup group_sysclk_clk_peripheral_enums 6041 * \{ 6042 */ 6043 /** Programmable clock divider types */ 6044 typedef enum 6045 { 6046 CY_SYSCLK_DIV_8_BIT = 0U, /**< Divider Type is an 8 bit divider */ 6047 CY_SYSCLK_DIV_16_BIT = 1U, /**< Divider Type is a 16 bit divider */ 6048 CY_SYSCLK_DIV_16_5_BIT = 2U, /**< Divider Type is a 16.5 bit fractional divider */ 6049 CY_SYSCLK_DIV_24_5_BIT = 3U /**< Divider Type is a 24.5 bit fractional divider */ 6050 } cy_en_divider_types_t; 6051 /** \} group_sysclk_clk_peripheral_enums */ 6052 6053 6054 /** 6055 * \addtogroup group_sysclk_clk_peripheral_funcs 6056 * \{ 6057 */ 6058 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) 6059 6060 /******************************************************************************* 6061 * Function Name: Cy_SysClk_PeriPclkSetDivider 6062 ****************************************************************************//** 6063 * 6064 * Sets one of the programmable clock dividers. This is only used for integer 6065 * dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. 6066 * 6067 * \pre If the specified clock divider is already enabled - it should be disabled 6068 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 6069 * 6070 * \param ipBlock specifies ip block to connect the clock divider to. 6071 * 6072 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6073 * 6074 * \param dividerNum the divider number. 6075 * 6076 * \param dividerValue divider value 6077 * Causes integer division of (divider value + 1), or division by 1 to 256 6078 * (8-bit divider) or 1 to 65536 (16-bit divider). 6079 * 6080 * \return \ref cy_en_sysclk_status_t 6081 * 6082 * \note 6083 * This API is available for CAT1B, CAT1C and CAT1D devices. 6084 * 6085 *******************************************************************************/ 6086 cy_en_sysclk_status_t 6087 Cy_SysClk_PeriPclkSetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, 6088 uint32_t dividerNum, uint32_t dividerValue); 6089 6090 6091 /******************************************************************************* 6092 * Function Name: Cy_SysClk_PeriPclkGetDivider 6093 ****************************************************************************//** 6094 * 6095 * Returns the integer divider value for the specified divider. One works for 6096 * integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional 6097 * divider value 6098 * 6099 * \param ipBlock specifies ip block to connect the clock divider to. 6100 * 6101 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6102 * 6103 * \param dividerNum specifies which divider of the selected type to configure 6104 * 6105 * \return The divider value. 6106 * The integer division done is by (divider value + 1), or division by 1 to 256 6107 * (8-bit divider) or 1 to 65536 (16-bit divider). 6108 * 6109 * \note 6110 * This API is available for CAT1B, CAT1C and CAT1D devices. 6111 * 6112 *******************************************************************************/ 6113 uint32_t Cy_SysClk_PeriPclkGetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 6114 6115 6116 /******************************************************************************* 6117 * Function Name: Cy_SysClk_PeriPclkGetFracDivider 6118 ****************************************************************************//** 6119 * 6120 * Reports the integer and fractional parts of the divider 6121 * 6122 * \param ipBlock specifies ip block to connect the clock divider to. 6123 * 6124 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6125 * 6126 * \param dividerNum specifies which divider of the selected type to configure 6127 * 6128 * \param *dividerIntValue pointer to return integer divider value 6129 * 6130 * \param *dividerFracValue pointer to return fractional divider value 6131 * 6132 * \return None. Loads pointed-to variables. 6133 * 6134 * \note 6135 * This API is available for CAT1B, CAT1C and CAT1D devices. 6136 * 6137 *******************************************************************************/ 6138 void Cy_SysClk_PeriPclkGetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 6139 uint32_t *dividerIntValue, uint32_t *dividerFracValue); 6140 6141 6142 /******************************************************************************* 6143 * Function Name: Cy_SysClk_PeriPclkSetFracDivider 6144 ****************************************************************************//** 6145 * 6146 * Sets one of the programmable clock dividers. This function should only be used 6147 * for fractional clock dividers. 6148 * 6149 * \pre If the specified clock divider is already enabled - it should be disabled 6150 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 6151 * 6152 * \param ipBlock specifies ip block to connect the clock divider to. 6153 * 6154 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6155 * 6156 * \param dividerNum specifies which divider of the selected type to configure 6157 * 6158 * \param dividerIntValue the integer divider value 6159 * The source of the divider is peri_clk, which is a divided version of hf_clk[0]. 6160 * The divider value causes integer division of (divider value + 1), or division 6161 * by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). 6162 * 6163 * \param dividerFracValue the fraction part of the divider 6164 * The fractional divider can be 1-32, thus it divides the clock by 1/32 for each 6165 * count. To divide the clock by 11/32nds set this value to 11. 6166 * 6167 * \return \ref cy_en_sysclk_status_t 6168 * 6169 * \note 6170 * This API is available for CAT1B, CAT1C and CAT1D devices. 6171 * 6172 *******************************************************************************/ 6173 cy_en_sysclk_status_t 6174 Cy_SysClk_PeriPclkSetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 6175 uint32_t dividerIntValue, uint32_t dividerFracValue); 6176 6177 6178 /******************************************************************************* 6179 * Function Name: Cy_SysClk_PeriPclkAssignDivider 6180 ****************************************************************************//** 6181 * 6182 * Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. 6183 * 6184 * \param ipBlock specifies ip block to connect the clock divider to. 6185 * 6186 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6187 * 6188 * \param dividerNum specifies which divider of the selected type to configure 6189 * 6190 * \return \ref cy_en_sysclk_status_t 6191 * 6192 * \note 6193 * This API is available for CAT1B, CAT1C and CAT1D devices. 6194 * 6195 *******************************************************************************/ 6196 cy_en_sysclk_status_t 6197 Cy_SysClk_PeriPclkAssignDivider(en_clk_dst_t ipBlock, 6198 cy_en_divider_types_t dividerType, uint32_t dividerNum); 6199 6200 6201 /******************************************************************************* 6202 * Function Name: Cy_SysClk_PeriPclkGetAssignedDivider 6203 ****************************************************************************//** 6204 * 6205 * Reports which clock divider is assigned to a selected IP block. 6206 * 6207 * \param ipBlock specifies ip block to connect the clock divider to. 6208 * 6209 * \return The divider type and number, where bits [7:6] = type, bits[5:0] = divider 6210 * number within that type 6211 * 6212 * \note 6213 * This API is available for CAT1B, CAT1C and CAT1D devices. 6214 * 6215 *******************************************************************************/ 6216 uint32_t Cy_SysClk_PeriPclkGetAssignedDivider(en_clk_dst_t ipBlock); 6217 6218 6219 /******************************************************************************* 6220 * Function Name: Cy_SysClk_PeriPclkEnableDivider 6221 ****************************************************************************//** 6222 * 6223 * Enables the selected divider. 6224 * 6225 * \param ipBlock specifies ip block to connect the clock divider to. 6226 * 6227 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6228 * 6229 * \param dividerNum specifies which divider of the selected type to configure 6230 * 6231 * \note This function also sets the phase alignment bits such that the enabled 6232 * divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider() 6233 * for information on how to phase-align a divider after it is enabled. 6234 * 6235 * \note 6236 * This API is available for CAT1B, CAT1C and CAT1D devices. 6237 * 6238 *******************************************************************************/ 6239 cy_en_sysclk_status_t 6240 Cy_SysClk_PeriPclkEnableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 6241 6242 6243 /******************************************************************************* 6244 * Function Name: Cy_SysClk_PeriPclkDisableDivider 6245 ****************************************************************************//** 6246 * 6247 * Disables a selected divider. 6248 * 6249 * \param ipBlock specifies ip block to connect the clock divider to. 6250 * 6251 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 6252 * 6253 * \param dividerNum specifies which divider of the selected type to configure. 6254 * 6255 * \note 6256 * This API is available for CAT1B, CAT1C and CAT1D devices. 6257 * 6258 *******************************************************************************/ 6259 cy_en_sysclk_status_t 6260 Cy_SysClk_PeriPclkDisableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 6261 6262 6263 /******************************************************************************* 6264 * Function Name: Cy_SysClk_PeriPclkEnablePhaseAlignDivider 6265 ****************************************************************************//** 6266 * 6267 * First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider), 6268 * then aligns that divider to another programmable divider, and enables the 6269 * selected divider. The divider to align to must already be enabled in order 6270 * to align a divider to it. 6271 * 6272 * \param ipBlock specifies ip block to connect the clock divider to. 6273 * 6274 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 6275 * 6276 * \param dividerNum specifies which divider of the selected type to configure. 6277 * 6278 * \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. 6279 * 6280 * \param dividerNumPA divider number of type specified to phase align to. 6281 * 6282 * \note 6283 * To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA 6284 * to 63. 6285 * 6286 * \note 6287 * This API is available for CAT1B, CAT1C and CAT1D devices. 6288 * 6289 *******************************************************************************/ 6290 cy_en_sysclk_status_t 6291 Cy_SysClk_PeriPclkEnablePhaseAlignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 6292 cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA); 6293 6294 /******************************************************************************* 6295 * Function Name: Cy_SysClk_PeriPclkGetFrequency 6296 ****************************************************************************//** 6297 * 6298 * Reports the frequency of the output of a given peripheral divider. 6299 * 6300 * \param ipBlock specifies ip block to connect the clock divider to. 6301 * 6302 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6303 * 6304 * \param dividerNum specifies which divider of the selected type to configure 6305 * 6306 * \return The frequency, in Hz. 6307 * 6308 * \note 6309 * The reported frequency may be zero, which indicates unknown. This happens if 6310 * the source input is dsi_out or clk_altlf. 6311 * 6312 * \note 6313 * This API is available for CAT1B, CAT1C and CAT1D devices. 6314 * 6315 * \funcusage 6316 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency 6317 * 6318 *******************************************************************************/ 6319 uint32_t Cy_SysClk_PeriPclkGetFrequency(en_clk_dst_t ipBlock, 6320 cy_en_divider_types_t dividerType, 6321 uint32_t dividerNum); 6322 6323 /******************************************************************************* 6324 * Function Name: Cy_SysClk_PeriPclkGetDividerEnabled 6325 ****************************************************************************//** 6326 * 6327 * Reports the enabled/disabled state of the selected divider. 6328 * 6329 * \param ipBlock specifies ip block to connect the clock divider to. 6330 * 6331 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 6332 * 6333 * \param dividerNum specifies which divider of the selected type to configure. 6334 * 6335 * \note 6336 * This API is available for CAT1B, CAT1C and CAT1D devices. 6337 * 6338 *******************************************************************************/ 6339 bool Cy_SysClk_PeriPclkGetDividerEnabled(en_clk_dst_t ipBlock, 6340 cy_en_divider_types_t dividerType, 6341 uint32_t dividerNum); 6342 6343 /******************************************************************************* 6344 * Function Name: Cy_Sysclk_PeriPclkGetClkHfNum 6345 ****************************************************************************//** 6346 * 6347 * Reports the corresponding CLK_HF* number for a particular PERI PCLK group 6348 * 6349 * \param grpNum specifies group number of PERI PCLK block. 6350 * 6351 * \return The CLK_HF* number. 6352 * 6353 * \note 6354 * This API is available for CAT1B, CAT1C and CAT1D devices. 6355 * 6356 *******************************************************************************/ 6357 uint32_t Cy_Sysclk_PeriPclkGetClkHfNum(uint32_t grpNum); 6358 6359 #endif 6360 6361 /******************************************************************************* 6362 * Function Name: Cy_SysClk_PeriphSetDivider 6363 ****************************************************************************//** 6364 * 6365 * Sets one of the programmable clock dividers. This is only used for integer 6366 * dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. 6367 * 6368 * \pre If the specified clock divider is already enabled - it should be disabled 6369 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 6370 * 6371 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6372 * 6373 * \param dividerNum the divider number. 6374 * 6375 * \param dividerValue divider value 6376 * Causes integer division of (divider value + 1), or division by 1 to 256 6377 * (8-bit divider) or 1 to 65536 (16-bit divider). 6378 * 6379 * \return \ref cy_en_sysclk_status_t 6380 * 6381 * \note 6382 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkSetDivider. 6383 * 6384 * \funcusage 6385 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider 6386 * 6387 *******************************************************************************/ 6388 cy_en_sysclk_status_t 6389 Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, 6390 uint32_t dividerNum, uint32_t dividerValue); 6391 6392 6393 /******************************************************************************* 6394 * Function Name: Cy_SysClk_PeriphGetDivider 6395 ****************************************************************************//** 6396 * 6397 * Returns the integer divider value for the specified divider. One works for 6398 * integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional 6399 * divider value 6400 * 6401 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6402 * 6403 * \param dividerNum specifies which divider of the selected type to configure 6404 * 6405 * \return The divider value. 6406 * The integer division done is by (divider value + 1), or division by 1 to 256 6407 * (8-bit divider) or 1 to 65536 (16-bit divider). 6408 * 6409 * \note 6410 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetDivider. 6411 * 6412 * \funcusage 6413 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider 6414 * 6415 *******************************************************************************/ 6416 uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 6417 6418 6419 /******************************************************************************* 6420 * Function Name: Cy_SysClk_PeriphSetFracDivider 6421 ****************************************************************************//** 6422 * 6423 * Sets one of the programmable clock dividers. This function should only be used 6424 * for fractional clock dividers. 6425 * 6426 * \pre If the specified clock divider is already enabled - it should be disabled 6427 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 6428 * 6429 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6430 * 6431 * \param dividerNum specifies which divider of the selected type to configure 6432 * 6433 * \param dividerIntValue the integer divider value 6434 * The source of the divider is peri_clk, which is a divided version of hf_clk[0]. 6435 * The divider value causes integer division of (divider value + 1), or division 6436 * by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). 6437 * 6438 * \param dividerFracValue the fraction part of the divider 6439 * The fractional divider can be 1-32, thus it divides the clock by 1/32 for each 6440 * count. To divide the clock by 11/32nds set this value to 11. 6441 * 6442 * \return \ref cy_en_sysclk_status_t 6443 * 6444 * \note 6445 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkSetFracDivider. 6446 * 6447 * \funcusage 6448 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider 6449 * 6450 *******************************************************************************/ 6451 cy_en_sysclk_status_t 6452 Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 6453 uint32_t dividerIntValue, uint32_t dividerFracValue); 6454 6455 6456 /******************************************************************************* 6457 * Function Name: Cy_SysClk_PeriphGetFracDivider 6458 ****************************************************************************//** 6459 * 6460 * Reports the integer and fractional parts of the divider 6461 * 6462 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6463 * 6464 * \param dividerNum specifies which divider of the selected type to configure 6465 * 6466 * \param *dividerIntValue pointer to return integer divider value 6467 * 6468 * \param *dividerFracValue pointer to return fractional divider value 6469 * 6470 * \return None. Loads pointed-to variables. 6471 * 6472 * \note 6473 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetFracDivider. 6474 * 6475 * \funcusage 6476 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider 6477 * 6478 *******************************************************************************/ 6479 void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 6480 uint32_t *dividerIntValue, uint32_t *dividerFracValue); 6481 6482 6483 /******************************************************************************* 6484 * Function Name: Cy_SysClk_PeriphAssignDivider 6485 ****************************************************************************//** 6486 * 6487 * Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. 6488 * 6489 * \param ipBlock specifies ip block to connect the clock divider to. 6490 * 6491 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6492 * 6493 * \param dividerNum specifies which divider of the selected type to configure 6494 * 6495 * \return \ref cy_en_sysclk_status_t 6496 * 6497 * \note 6498 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkAssignDivider. 6499 * 6500 * \funcusage 6501 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider 6502 * 6503 *******************************************************************************/ 6504 cy_en_sysclk_status_t 6505 Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, 6506 cy_en_divider_types_t dividerType, uint32_t dividerNum); 6507 6508 6509 /******************************************************************************* 6510 * Function Name: Cy_SysClk_PeriphGetAssignedDivider 6511 ****************************************************************************//** 6512 * 6513 * Reports which clock divider is assigned to a selected IP block. 6514 * 6515 * \param ipBlock specifies ip block to connect the clock divider to. 6516 * 6517 * \return The divider type and number, where bits [7:6] = type, bits[5:0] = divider 6518 * number within that type 6519 * 6520 * \note 6521 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetAssignedDivider. 6522 * 6523 * \funcusage 6524 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider 6525 * 6526 *******************************************************************************/ 6527 uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock); 6528 6529 6530 /******************************************************************************* 6531 * Function Name: Cy_SysClk_PeriphEnableDivider 6532 ****************************************************************************//** 6533 * 6534 * Enables the selected divider. 6535 * 6536 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6537 * 6538 * \param dividerNum specifies which divider of the selected type to configure 6539 * 6540 * \note This function also sets the phase alignment bits such that the enabled 6541 * divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider() 6542 * for information on how to phase-align a divider after it is enabled. 6543 * 6544 * \note 6545 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkEnableDivider. 6546 * 6547 * \funcusage 6548 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnableDivider 6549 * 6550 *******************************************************************************/ 6551 cy_en_sysclk_status_t 6552 Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 6553 6554 6555 /******************************************************************************* 6556 * Function Name: Cy_SysClk_PeriphDisableDivider 6557 ****************************************************************************//** 6558 * 6559 * Disables a selected divider. 6560 * 6561 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 6562 * 6563 * \param dividerNum specifies which divider of the selected type to configure. 6564 * 6565 * \note 6566 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkDisableDivider. 6567 * 6568 * \funcusage 6569 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphDisableDivider 6570 * 6571 *******************************************************************************/ 6572 cy_en_sysclk_status_t 6573 Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 6574 6575 6576 /******************************************************************************* 6577 * Function Name: Cy_SysClk_PeriphEnablePhaseAlignDivider 6578 ****************************************************************************//** 6579 * 6580 * First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider), 6581 * then aligns that divider to another programmable divider, and enables the 6582 * selected divider. The divider to align to must already be enabled in order 6583 * to align a divider to it. 6584 * 6585 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 6586 * 6587 * \param dividerNum specifies which divider of the selected type to configure. 6588 * 6589 * \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. 6590 * 6591 * \param dividerNumPA divider number of type specified to phase align to. 6592 * 6593 * \note 6594 * To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA 6595 * to 63. 6596 * 6597 * \note 6598 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkEnablePhaseAlignDivider. 6599 * 6600 * \funcusage 6601 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider 6602 * 6603 *******************************************************************************/ 6604 cy_en_sysclk_status_t 6605 Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 6606 cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA); 6607 6608 6609 /******************************************************************************* 6610 * Function Name: Cy_SysClk_PeriphGetDividerEnabled 6611 ****************************************************************************//** 6612 * 6613 * Reports the enabled/disabled state of the selected divider. 6614 * 6615 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 6616 * 6617 * \param dividerNum specifies which divider of the selected type to configure. 6618 * 6619 * \return The enabled/disabled state; \n 6620 * false = disabled \n 6621 * true = enabled 6622 * 6623 * \note 6624 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetDividerEnabled. 6625 * 6626 * \funcusage 6627 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetDividerEnabled 6628 * 6629 *******************************************************************************/ 6630 bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum); 6631 6632 6633 /******************************************************************************* 6634 * Function Name: Cy_SysClk_PeriphGetFrequency 6635 ****************************************************************************//** 6636 * 6637 * Reports the frequency of the output of a given peripheral divider. 6638 * 6639 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 6640 * 6641 * \param dividerNum specifies which divider of the selected type to configure 6642 * 6643 * \return The frequency, in Hz. 6644 * 6645 * \note 6646 * The reported frequency may be zero, which indicates unknown. This happens if 6647 * the source input is dsi_out or clk_altlf. 6648 * 6649 * \note 6650 * This API is deprecated for CAT1B, CAT1C and CAT1D devices, use Cy_SysClk_PeriPclkGetFrequency. 6651 * 6652 * \funcusage 6653 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency 6654 * 6655 *******************************************************************************/ 6656 uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum); 6657 6658 6659 /** \} group_sysclk_clk_peripheral_funcs */ 6660 6661 6662 /* ========================================================================== */ 6663 /* ========================= clk_slow SECTION ========================= */ 6664 /* ========================================================================== */ 6665 /** 6666 * \addtogroup group_sysclk_clk_slow_funcs 6667 * \{ 6668 */ 6669 6670 #if defined (CY_IP_MXS40SRSS) 6671 6672 /******************************************************************************* 6673 * Function Name: Cy_SysClk_ClkSlowSetDivider 6674 ****************************************************************************//** 6675 * 6676 * Sets the clock divider for the slow clock. 6677 * 6678 * \param divider Divider value between 0 and 255. 6679 * Causes integer division of (divider value + 1), or division by 1 to 256. 6680 * 6681 * \note 6682 * Call \ref SystemCoreClockUpdate after this function calling. 6683 * 6684 * \note 6685 * This API is available for CAT1A & CAT1C devices. 6686 * 6687 * \funcusage 6688 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 6689 * 6690 *******************************************************************************/ 6691 void Cy_SysClk_ClkSlowSetDivider(uint8_t divider); 6692 6693 6694 /******************************************************************************* 6695 * Function Name: Cy_SysClk_ClkSlowGetDivider 6696 ****************************************************************************//** 6697 * 6698 * Reports the divider value for the slow clock. 6699 * 6700 * \return The divider value. 6701 * The integer division done is by (divider value + 1), or division by 1 to 256. 6702 * 6703 * \note 6704 * This API is available for CAT1A & CAT1C devices. 6705 * 6706 * \funcusage 6707 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 6708 * 6709 *******************************************************************************/ 6710 uint8_t Cy_SysClk_ClkSlowGetDivider(void); 6711 6712 6713 /******************************************************************************* 6714 * Function Name: Cy_SysClk_ClkSlowGetFrequency 6715 ****************************************************************************//** 6716 * 6717 * Reports the frequency of the slow clock. 6718 * 6719 * \return The frequency, in Hz. 6720 * 6721 * \note 6722 * This API is available for CAT1A & CAT1C devices. 6723 * 6724 * \funcusage 6725 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 6726 * 6727 *******************************************************************************/ 6728 uint32_t Cy_SysClk_ClkSlowGetFrequency(void); 6729 6730 #endif 6731 6732 /** \} group_sysclk_clk_slow_funcs */ 6733 6734 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_DOXYGEN) 6735 6736 /* ========================================================================== */ 6737 /* ========================= clk_mem SECTION ========================= */ 6738 /* ========================================================================== */ 6739 /** 6740 * \addtogroup group_sysclk_clk_mem_funcs 6741 * \{ 6742 */ 6743 6744 /******************************************************************************* 6745 * Function Name: Cy_SysClk_ClkMemSetDivider 6746 ****************************************************************************//** 6747 * 6748 * Sets the clock divider for the Mem clock. The source of this clock is clkHf[0]. 6749 * 6750 * \param divider Divider value between 0 and 255. 6751 * Causes integer division of (divider value + 1), or division by 1 to 256. 6752 * 6753 * \note 6754 * Call \ref SystemCoreClockUpdate after this function calling. 6755 * 6756 * \note 6757 * This API is available for only CAT1C devices. 6758 * 6759 *******************************************************************************/ 6760 void Cy_SysClk_ClkMemSetDivider(uint8_t divider); 6761 6762 6763 /******************************************************************************* 6764 * Function Name: Cy_SysClk_ClkMemGetDivider 6765 ****************************************************************************//** 6766 * 6767 * Reports the divider value for the Mem clock. 6768 * 6769 * \return The divider value. 6770 * The integer division done is by (divider value + 1), or division by 1 to 256. 6771 * 6772 * \note 6773 * This API is available for only CAT1C devices. 6774 * 6775 *******************************************************************************/ 6776 uint8_t Cy_SysClk_ClkMemGetDivider(void); 6777 6778 6779 /******************************************************************************* 6780 * Function Name: Cy_SysClk_ClkMemGetFrequency 6781 ****************************************************************************//** 6782 * 6783 * Reports the frequency of the Mem clock. 6784 * 6785 * \return The frequency, in Hz. 6786 * 6787 * \note 6788 * This API is available for only CAT1C devices. 6789 * 6790 *******************************************************************************/ 6791 uint32_t Cy_SysClk_ClkMemGetFrequency(void); 6792 6793 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) */ 6794 6795 /** \} group_sysclk_clk_mem_funcs */ 6796 6797 /* ========================================================================== */ 6798 /* =========================== clkLf SECTION ========================== */ 6799 /* ========================================================================== */ 6800 /** 6801 * \addtogroup group_sysclk_clk_lf_enums 6802 * \{ 6803 */ 6804 /** 6805 * Low frequency (clkLf) input sources. See CLK_SELECT register, LFCLK_SEL bits. 6806 * Used with functions \ref Cy_SysClk_ClkLfSetSource, and \ref Cy_SysClk_ClkLfGetSource. 6807 */ 6808 #if defined (CY_IP_MXS22SRSS) 6809 typedef enum 6810 { 6811 CY_SYSCLK_CLKLF_IN_PILO = 0U, /**< clkLf is sourced by the precision low speed oscillator (PILO) */ 6812 CY_SYSCLK_CLKLF_IN_WCO = 1U, /**< clkLf is sourced by the watch crystal oscillator (WCO) */ 6813 CY_SYSCLK_CLKLF_IN_ALTLF = 2U, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 6814 CY_SYSCLK_CLKLF_IN_ECO_PRESCALER = 3U, /**< clkLf is sourced by the External Clock Oscillator (ECO Prescaler) */ 6815 CY_SYSCLK_CLKLF_IN_ILO = 4U, /**< clkLf is sourced by the internal low speed oscillator (ILO) */ 6816 CY_SYSCLK_CLKLF_IN_MAX = 5U /**< clkLf MAX value*/ 6817 } cy_en_clklf_in_sources_t; 6818 6819 #else 6820 typedef enum 6821 { 6822 CY_SYSCLK_CLKLF_IN_ILO = 0U, /**< clkLf is sourced by the internal low speed oscillator (ILO) */ 6823 CY_SYSCLK_CLKLF_IN_WCO = 1U, /**< clkLf is sourced by the watch crystal oscillator (WCO) */ 6824 CY_SYSCLK_CLKLF_IN_ALTLF = 2U, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 6825 CY_SYSCLK_CLKLF_IN_PILO = 3U, /**< clkLf is sourced by the precision low speed oscillator (PILO) */ 6826 CY_SYSCLK_CLKLF_IN_ILO1 = 4U, /**< clkLf is sourced by the internal low speed oscillator (ILO1)*/ 6827 CY_SYSCLK_CLKLF_IN_ECO_PRESCALER = 5U, /**< clkLf is sourced by the External Clock Oscillator (ECO Prescaler) */ 6828 CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER = 6U, /**< clkLf is sourced by the External Clock Oscillator (LP ECO Prescaler) */ 6829 CY_SYSCLK_CLKLF_IN_MAX = 7U /**< clkLf MAX value*/ 6830 } cy_en_clklf_in_sources_t; 6831 6832 #endif /* defined (CY_IP_MXS22SRSS) */ 6833 6834 /** \} group_sysclk_clk_lf_enums */ 6835 6836 /** 6837 * \addtogroup group_sysclk_clk_lf_funcs 6838 * \{ 6839 */ 6840 /******************************************************************************* 6841 * Function Name: Cy_SysClk_ClkLfSetSource 6842 ****************************************************************************//** 6843 * 6844 * Sets the source for the low frequency clock(clkLf). 6845 * 6846 * \param source \ref cy_en_clklf_in_sources_t 6847 * 6848 * \note The watchdog timer (WDT) must be unlocked before calling this function. 6849 * 6850 * \note It takes four cycles of the originally selected clock to switch away 6851 * from it. Do not disable the original clock during this time. 6852 * 6853 * \funcusage 6854 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource 6855 * 6856 *******************************************************************************/ 6857 void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source); 6858 6859 6860 /******************************************************************************* 6861 * Function Name: Cy_SysClk_ClkLfGetSource 6862 ****************************************************************************//** 6863 * 6864 * Reports the source for the low frequency clock (clkLf). 6865 * 6866 * \return \ref cy_en_clklf_in_sources_t 6867 * 6868 * \funcusage 6869 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource 6870 * 6871 *******************************************************************************/ 6872 cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void); 6873 /** \} group_sysclk_clk_lf_funcs */ 6874 6875 6876 /* ========================================================================== */ 6877 /* ======================== clk_timer SECTION ========================= */ 6878 /* ========================================================================== */ 6879 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) || defined (CY_DOXYGEN) 6880 6881 /** 6882 * \addtogroup group_sysclk_clk_timer_enums 6883 * \{ 6884 */ 6885 /** 6886 * Timer clock (clk_timer) input sources. See CLK_TIMER_CTL register, TIMER_SEL 6887 * and TIMER_HF0_DIV bits. Used with functions \ref Cy_SysClk_ClkTimerSetSource, and 6888 * \ref Cy_SysClk_ClkTimerGetSource. 6889 */ 6890 typedef enum 6891 { 6892 CY_SYSCLK_CLKTIMER_IN_IMO = 0x000U, /**< clk_timer is sourced by the internal main oscillator (IMO) */ 6893 CY_SYSCLK_CLKTIMER_IN_HF0_NODIV = 0x001U, /**< clk_timer is sourced by clkHf[0] undivided */ 6894 CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 = 0x101U, /**< clk_timer is sourced by clkHf[0] divided by 2 */ 6895 CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 = 0x201U, /**< clk_timer is sourced by clkHf[0] divided by 4 */ 6896 CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 = 0x301U /**< clk_timer is sourced by clkHf[0] divided by 8 */ 6897 } cy_en_clktimer_in_sources_t; 6898 /** \} group_sysclk_clk_timer_enums */ 6899 6900 /** \cond */ 6901 #define CY_SRSS_CLK_TIMER_CTL_TIMER_Pos (SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos) 6902 #define CY_SRSS_CLK_TIMER_CTL_TIMER_Msk (SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk) 6903 /** \endcond */ 6904 6905 /** 6906 * \addtogroup group_sysclk_clk_timer_funcs 6907 * \{ 6908 */ 6909 6910 /******************************************************************************* 6911 * Function Name: Cy_SysClk_ClkTimerSetSource 6912 ****************************************************************************//** 6913 * 6914 * Sets the source for the timer clock (clk_timer). The timer clock can be used 6915 * as a source for SYSTICK as an alternate clock and one or more of the energy 6916 * profiler counters. 6917 * 6918 * \param source \ref cy_en_clktimer_in_sources_t 6919 * 6920 * \note 6921 * This API is available for CAT1A devices. 6922 * 6923 * \funcusage 6924 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource 6925 * 6926 *******************************************************************************/ 6927 void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source); 6928 6929 6930 /******************************************************************************* 6931 * Function Name: Cy_SysClk_ClkTimerGetSource 6932 ****************************************************************************//** 6933 * 6934 * Reports the source for the timer clock (clk_timer). 6935 * 6936 * \return \ref cy_en_clktimer_in_sources_t 6937 * 6938 * \note 6939 * This API is available for CAT1A devices. 6940 * 6941 * \funcusage 6942 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource 6943 * 6944 *******************************************************************************/ 6945 cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void); 6946 6947 6948 /******************************************************************************* 6949 * Function Name: Cy_SysClk_ClkTimerSetDivider 6950 ****************************************************************************//** 6951 * 6952 * Sets the divider for the timer clock (clk_timer). 6953 * 6954 * \param divider Divider value; valid range is 0 to 255. Divides the selected 6955 * source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1). 6956 * 6957 * \note 6958 * Do not change the divider value while the timer clock is enabled. 6959 * 6960 * \note 6961 * This API is available for CAT1A devices. 6962 * 6963 * \funcusage 6964 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider 6965 * 6966 *******************************************************************************/ 6967 void Cy_SysClk_ClkTimerSetDivider(uint8_t divider); 6968 6969 6970 /******************************************************************************* 6971 * Function Name: Cy_SysClk_ClkTimerGetDivider 6972 ****************************************************************************//** 6973 * 6974 * Reports the divider value for the timer clock (clk_timer). 6975 * 6976 * \return The divider value 6977 * 6978 * \note 6979 * This API is available for CAT1A devices. 6980 * 6981 * \funcusage 6982 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider 6983 * 6984 *******************************************************************************/ 6985 uint8_t Cy_SysClk_ClkTimerGetDivider(void); 6986 6987 6988 /******************************************************************************* 6989 * Function Name: Cy_SysClk_ClkTimerEnable 6990 ****************************************************************************//** 6991 * 6992 * Enables the timer clock (clk_timer). The timer clock can be used as a source 6993 * for SYSTICK and one or more of the energy profiler counters. 6994 * 6995 * \note 6996 * This API is available for CAT1A devices. 6997 * 6998 * 6999 * \funcusage 7000 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable 7001 * 7002 *******************************************************************************/ 7003 void Cy_SysClk_ClkTimerEnable(void); 7004 7005 7006 /******************************************************************************* 7007 * Function Name: Cy_SysClk_ClkTimerDisable 7008 ****************************************************************************//** 7009 * 7010 * Disables the timer clock (clk_timer). 7011 * 7012 * \note 7013 * This API is available for CAT1A devices. 7014 * 7015 * \funcusage 7016 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable 7017 * 7018 *******************************************************************************/ 7019 void Cy_SysClk_ClkTimerDisable(void); 7020 7021 7022 /******************************************************************************* 7023 * Function Name: Cy_SysClk_ClkTimerIsEnabled 7024 ****************************************************************************//** 7025 * 7026 * Reports the Enabled/Disabled status of the Timer. 7027 * 7028 * \return Boolean status of Timer: true - Enabled, false - Disabled. 7029 * 7030 * \funcusage 7031 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable 7032 * 7033 * \note 7034 * This API is available for CAT1A devices. 7035 * 7036 *******************************************************************************/ 7037 bool Cy_SysClk_ClkTimerIsEnabled(void); 7038 7039 7040 /******************************************************************************* 7041 * Function Name: Cy_SysClk_ClkTimerGetFrequency 7042 ****************************************************************************//** 7043 * 7044 * Reports the frequency of the timer clock (clk_timer). 7045 * \note If the the timer clock is not enabled - a zero frequency is reported. 7046 * 7047 * \funcusage 7048 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable 7049 * 7050 * \note 7051 * This API is available for CAT1A devices. 7052 * 7053 *******************************************************************************/ 7054 uint32_t Cy_SysClk_ClkTimerGetFrequency(void); 7055 7056 #endif /*(defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 3)) */ 7057 7058 7059 /** \} group_sysclk_clk_timer_funcs */ 7060 7061 7062 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) 7063 /* ========================================================================== */ 7064 /* ========================= clk_pump SECTION ========================= */ 7065 /* ========================================================================== */ 7066 /** 7067 * \addtogroup group_sysclk_clk_pump_enums 7068 * \{ 7069 */ 7070 7071 /** 7072 * Pump clock (clk_pump) input sources. See CLK_SELECT register, PUMP_SEL bits. 7073 * Used with functions \ref Cy_SysClk_ClkPumpSetSource, and 7074 * \ref Cy_SysClk_ClkPumpGetSource. 7075 */ 7076 /** 7077 * \note 7078 * This enum is available for CAT1A, CAT1B and CAT1C devices. 7079 **/ 7080 typedef enum 7081 { 7082 CY_SYSCLK_PUMP_IN_CLKPATH0 = 0UL, /**< Pump clock input is clock path 0 */ 7083 CY_SYSCLK_PUMP_IN_CLKPATH1 = 1UL, /**< Pump clock input is clock path 1 */ 7084 CY_SYSCLK_PUMP_IN_CLKPATH2 = 2UL, /**< Pump clock input is clock path 2 */ 7085 CY_SYSCLK_PUMP_IN_CLKPATH3 = 3UL, /**< Pump clock input is clock path 3 */ 7086 CY_SYSCLK_PUMP_IN_CLKPATH4 = 4UL, /**< Pump clock input is clock path 4 */ 7087 CY_SYSCLK_PUMP_IN_CLKPATH5 = 5UL, /**< Pump clock input is clock path 5 */ 7088 CY_SYSCLK_PUMP_IN_CLKPATH6 = 6UL, /**< Pump clock input is clock path 6 */ 7089 CY_SYSCLK_PUMP_IN_CLKPATH7 = 7UL, /**< Pump clock input is clock path 7 */ 7090 CY_SYSCLK_PUMP_IN_CLKPATH8 = 8UL, /**< Pump clock input is clock path 8 */ 7091 CY_SYSCLK_PUMP_IN_CLKPATH9 = 9UL, /**< Pump clock input is clock path 9 */ 7092 CY_SYSCLK_PUMP_IN_CLKPATH10 = 10UL, /**< Pump clock input is clock path 10 */ 7093 CY_SYSCLK_PUMP_IN_CLKPATH11 = 11UL, /**< Pump clock input is clock path 11 */ 7094 CY_SYSCLK_PUMP_IN_CLKPATH12 = 12UL, /**< Pump clock input is clock path 12 */ 7095 CY_SYSCLK_PUMP_IN_CLKPATH13 = 13UL, /**< Pump clock input is clock path 13 */ 7096 CY_SYSCLK_PUMP_IN_CLKPATH14 = 14UL, /**< Pump clock input is clock path 14 */ 7097 CY_SYSCLK_PUMP_IN_CLKPATH15 = 15UL /**< Pump clock input is clock path 15 */ 7098 } cy_en_clkpump_in_sources_t; 7099 7100 /** 7101 * Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits. 7102 * Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and 7103 * \ref Cy_SysClk_ClkPumpGetDivider. 7104 */ 7105 /** 7106 * \note 7107 * This enum is available for CAT1A, CAT1B and CAT1C devices. 7108 **/ 7109 typedef enum 7110 { 7111 CY_SYSCLK_PUMP_NO_DIV = 0U, /**< No division on pump clock */ 7112 CY_SYSCLK_PUMP_DIV_2 = 1U, /**< Pump clock divided by 2 */ 7113 CY_SYSCLK_PUMP_DIV_4 = 2U, /**< Pump clock divided by 4 */ 7114 CY_SYSCLK_PUMP_DIV_8 = 3U, /**< Pump clock divided by 8 */ 7115 CY_SYSCLK_PUMP_DIV_16 = 4U /**< Pump clock divided by 16 */ 7116 } cy_en_clkpump_divide_t; 7117 /** \} group_sysclk_clk_pump_enums */ 7118 7119 /** \cond */ 7120 #define CY_SYSCLK_FLL_IS_DIVIDER_VALID(div) (((div) == CY_SYSCLK_PUMP_NO_DIV) || \ 7121 ((div) == CY_SYSCLK_PUMP_DIV_2) || \ 7122 ((div) == CY_SYSCLK_PUMP_DIV_4) || \ 7123 ((div) == CY_SYSCLK_PUMP_DIV_8) || \ 7124 ((div) == CY_SYSCLK_PUMP_DIV_16)) 7125 /** \endcond */ 7126 7127 /** 7128 * \addtogroup group_sysclk_clk_pump_funcs 7129 * \{ 7130 */ 7131 /******************************************************************************* 7132 * Function Name: Cy_SysClk_ClkPumpSetSource 7133 ****************************************************************************//** 7134 * 7135 * Sets the source for the pump clock (clk_pump). The pump clock can be used for 7136 * the analog pumps in the CTBm block. 7137 * 7138 * \param source \ref cy_en_clkpump_in_sources_t 7139 * 7140 * \note 7141 * Do not change the source while the pump clock is enabled. 7142 * 7143 * \funcusage 7144 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource 7145 * 7146 * \note 7147 * This API is available for CAT1A, CAT1B and CAT1C devices. 7148 * 7149 *******************************************************************************/ 7150 void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source); 7151 7152 7153 /******************************************************************************* 7154 * Function Name: Cy_SysClk_ClkPumpGetSource 7155 ****************************************************************************//** 7156 * 7157 * Reports the source for the pump clock (clk_pump). 7158 * 7159 * \return \ref cy_en_clkpump_in_sources_t 7160 * 7161 * \funcusage 7162 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource 7163 * 7164 * \note 7165 * This API is available for CAT1A, CAT1B and CAT1C devices. 7166 * 7167 *******************************************************************************/ 7168 cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void); 7169 7170 7171 /******************************************************************************* 7172 * Function Name: Cy_SysClk_ClkPumpSetDivider 7173 ****************************************************************************//** 7174 * 7175 * Sets the divider of the pump clock (clk_pump). 7176 * 7177 * \param divider \ref cy_en_clkpump_divide_t 7178 * 7179 * \note 7180 * Do not change the divider value while the pump clock is enabled. 7181 * 7182 * \funcusage 7183 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider 7184 * 7185 * \note 7186 * This API is available for CAT1A, CAT1B and CAT1C devices. 7187 * 7188 *******************************************************************************/ 7189 void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider); 7190 7191 7192 /******************************************************************************* 7193 * Function Name: Cy_SysClk_ClkPumpGetDivider 7194 ****************************************************************************//** 7195 * 7196 * Reports the divider value for the pump clock (clk_pump). 7197 * 7198 * \return \ref cy_en_clkpump_divide_t 7199 * 7200 * \funcusage 7201 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider 7202 * 7203 * \note 7204 * This API is available for CAT1A, CAT1B and CAT1C devices. 7205 * 7206 *******************************************************************************/ 7207 cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); 7208 7209 7210 /******************************************************************************* 7211 * Function Name: Cy_SysClk_ClkPumpEnable 7212 ****************************************************************************//** 7213 * 7214 * Enables the pump clock (clk_pump). The pump clock can be used for the analog 7215 * pumps in the CTBm block. 7216 * 7217 * \funcusage 7218 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable 7219 * 7220 * \note 7221 * This API is available for CAT1A, CAT1B and CAT1C devices. 7222 * 7223 *******************************************************************************/ 7224 void Cy_SysClk_ClkPumpEnable(void); 7225 7226 7227 /******************************************************************************* 7228 * Function Name: Cy_SysClk_ClkPumpIsEnabled 7229 ****************************************************************************//** 7230 * 7231 * Reports the Enabled/Disabled status of the ClkPump. 7232 * 7233 * \return Boolean status of ClkPump: true - Enabled, false - Disabled. 7234 * 7235 * \funcusage 7236 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable 7237 * 7238 * \note 7239 * This API is available for CAT1A, CAT1B and CAT1C devices. 7240 * 7241 *******************************************************************************/ 7242 bool Cy_SysClk_ClkPumpIsEnabled(void); 7243 7244 7245 /******************************************************************************* 7246 * Function Name: Cy_SysClk_ClkPumpDisable 7247 ****************************************************************************//** 7248 * 7249 * Disables the pump clock (clk_pump). 7250 * 7251 * \funcusage 7252 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable 7253 * 7254 * \note 7255 * This API is available for CAT1A, CAT1B and CAT1C devices. 7256 * 7257 *******************************************************************************/ 7258 void Cy_SysClk_ClkPumpDisable(void); 7259 7260 7261 /******************************************************************************* 7262 * Function Name: Cy_SysClk_ClkPumpGetFrequency 7263 ****************************************************************************//** 7264 * 7265 * Reports the frequency of the pump clock (clk_pump). 7266 * \note If the the pump clock is not enabled - a zero frequency is reported. 7267 * 7268 * \funcusage 7269 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable 7270 * 7271 * \note 7272 * This API is available for CAT1A, CAT1B and CAT1C devices. 7273 * 7274 *******************************************************************************/ 7275 uint32_t Cy_SysClk_ClkPumpGetFrequency(void); 7276 /** \} group_sysclk_clk_pump_funcs */ 7277 #endif /* defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) */ 7278 7279 /* ========================================================================== */ 7280 /* ========================== clk_bak SECTION ========================= */ 7281 /* ========================================================================== */ 7282 /** 7283 * \addtogroup group_sysclk_clk_bak_enums 7284 * \{ 7285 */ 7286 /** 7287 * Backup domain clock (clk_bak) input sources. See BACKUP->CTL register, 7288 * CLK_SEL bits. Used with functions \ref Cy_SysClk_ClkBakSetSource, and 7289 * \ref Cy_SysClk_ClkBakGetSource. 7290 */ 7291 typedef enum 7292 { 7293 CY_SYSCLK_BAK_IN_WCO, /**< Backup domain clock input is WCO */ 7294 CY_SYSCLK_BAK_IN_CLKLF, /**< Backup domain clock input is clkLf */ 7295 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 3)) || defined (CY_IP_MXS22SRSS) 7296 /** 7297 * \note 7298 * This parameter is available for CAT1B and CAT1C devices. 7299 **/ 7300 CY_SYSCLK_BAK_IN_ILO, /**< Backup domain clock input is ILO */ 7301 /** 7302 * \note 7303 * This parameter is available for CAT1B devices. 7304 **/ 7305 CY_SYSCLK_BAK_IN_LPECO_PRESCALER, /**< Backup domain clock input is LPECO_PRESCALER */ 7306 /** 7307 * \note 7308 * This parameter is available for CAT1B devices. 7309 **/ 7310 CY_SYSCLK_BAK_IN_PILO /**< Backup domain clock input is PILO */ 7311 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS */ 7312 7313 } cy_en_clkbak_in_sources_t; 7314 /** \} group_sysclk_clk_bak_enums */ 7315 7316 7317 /** 7318 * \addtogroup group_sysclk_clk_bak_funcs 7319 * \{ 7320 */ 7321 /******************************************************************************* 7322 * Function Name: Cy_SysClk_ClkBakSetSource 7323 ****************************************************************************//** 7324 * 7325 * Sets the source for the backup domain clock (clk_bak). 7326 * 7327 * \param source \ref cy_en_clkbak_in_sources_t 7328 * 7329 * \note 7330 * clkLf is not available in all power modes. For this reason, WCO is the 7331 * preferred source. If the WCO is routed through the clkLf multiplexer 7332 * (see \ref Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf. 7333 * 7334 * \funcusage 7335 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource 7336 * 7337 *******************************************************************************/ 7338 void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source); 7339 7340 7341 /******************************************************************************* 7342 * Function Name: Cy_SysClk_ClkBakGetSource 7343 ****************************************************************************//** 7344 * 7345 * Reports the source for the backup domain clock (clk_bak). 7346 * 7347 * \return \ref cy_en_clkbak_in_sources_t 7348 * 7349 * \funcusage 7350 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource 7351 * 7352 *******************************************************************************/ 7353 cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void); 7354 /** \} group_sysclk_clk_bak_funcs */ 7355 7356 7357 /** \cond */ 7358 /* Deprecated macros */ 7359 #define CY_SYSCLK_DIV_ROUND(a, b) (CY_SYSLIB_DIV_ROUND((a),(b))) 7360 #define CY_SYSCLK_DIV_ROUNDUP(a, b) (CY_SYSLIB_DIV_ROUNDUP((a),(b))) 7361 /** \endcond */ 7362 7363 /* ========================================================================== */ 7364 /* ========================== Clock Power SECTION =============================*/ 7365 /* ========================================================================== */ 7366 /** 7367 * \addtogroup group_sysclk_clk_pwr_enums 7368 * \{ 7369 */ 7370 #if (defined (CY_IP_MXS40SSRSS) && (CY_MXS40SSRSS_VER_1_2 > 0UL)) || defined(CY_DOXYGEN) 7371 /** 7372 * \note 7373 * This Enumeration is only available for CAT1B(B2) devices. 7374 **/ 7375 /** 7376 * Clock power input sources. See PWRMODE_CLK_SELECT register, PWR_MUX bits. 7377 * Used with functions \ref Cy_SysClk_ClkPwrSetSource, and \ref Cy_SysClk_ClkPwrGetSource. 7378 */ 7379 7380 typedef enum 7381 { 7382 CY_SYSCLK_CLKPWR_IN_IMO = 0U, /**< clkPwr is sourced by the internal main oscillator (IMO) */ 7383 CY_SYSCLK_CLKPWR_IN_IHO = 1U, /**< clkPwr is sourced by the internal high speed oscillator (IHO) */ 7384 } cy_en_clkpwr_in_sources_t; 7385 7386 /** \} group_sysclk_clk_pwr_enums */ 7387 7388 /** \cond internal */ 7389 #define CY_SYSCLK_CLKPWR_DIVIDER_MIN (1U) 7390 #define CY_SYSCLK_CLKPWR_DIVIDER_MAX (256U) 7391 #define CY_SYSCLK_IS_CLKPWR_DIVIDER_VALID(locDiv) ((CY_SYSCLK_CLKPWR_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_CLKPWR_DIVIDER_MAX)) 7392 7393 #define CY_SYSCLK_IF_CLKPWR_SOURCE_VALID(pwrClkSrc) (((pwrClkSrc) == CY_SYSCLK_CLKPWR_IN_IMO) || \ 7394 ((pwrClkSrc) == CY_SYSCLK_CLKPWR_IN_IHO)) 7395 /** \endcond */ 7396 7397 /** 7398 * \addtogroup group_sysclk_clk_pwr_funcs 7399 * \{ 7400 */ 7401 /******************************************************************************* 7402 * Function Name: Cy_SysClk_ClkPwrSetDivider 7403 ****************************************************************************//** 7404 * 7405 * Sets the clock divider for Power clock. 7406 * 7407 * \param divider divider value between 1 and 256. 7408 * 7409 * \funcusage 7410 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetDivider 7411 * 7412 *******************************************************************************/ 7413 void Cy_SysClk_ClkPwrSetDivider(uint32_t divider); 7414 7415 /******************************************************************************* 7416 * Function Name: Cy_SysClk_ClkPwrGetDivider 7417 ****************************************************************************//** 7418 * 7419 * Returns the clock divider of Power clock. 7420 * 7421 * \return divider value in range 1..256. 7422 * 7423 * \funcusage 7424 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetDivider 7425 * 7426 *******************************************************************************/ 7427 uint32_t Cy_SysClk_ClkPwrGetDivider(void); 7428 7429 7430 /******************************************************************************* 7431 * Function Name: Cy_SysClk_ClkPwrGetFrequency 7432 ****************************************************************************//** 7433 * 7434 * Reports the output clock signal frequency of Power clock. 7435 * 7436 * \return The frequency, in Hz. 7437 * 7438 * \funcusage 7439 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetDivider 7440 * 7441 *******************************************************************************/ 7442 uint32_t Cy_SysClk_ClkPwrGetFrequency(void); 7443 7444 7445 /******************************************************************************* 7446 * Function Name: Cy_SysClk_ClkPwrSetSource 7447 ****************************************************************************//** 7448 * 7449 * Sets the source for the Power clock. 7450 * 7451 * \param source \ref cy_en_clkpwr_in_sources_t 7452 * 7453 * \funcusage 7454 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetSource 7455 * 7456 *******************************************************************************/ 7457 void Cy_SysClk_ClkPwrSetSource(cy_en_clkpwr_in_sources_t source); 7458 7459 7460 /******************************************************************************* 7461 * Function Name: Cy_SysClk_ClkPwrGetSource 7462 ****************************************************************************//** 7463 * 7464 * Reports the source for the Power clock. 7465 * 7466 * \return \ref cy_en_clkpwr_in_sources_t 7467 * 7468 * \funcusage 7469 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPwrSetSource 7470 * 7471 *******************************************************************************/ 7472 cy_en_clkpwr_in_sources_t Cy_SysClk_ClkPwrGetSource(void); 7473 #endif 7474 7475 /** \} group_sysclk_clk_pwr_funcs */ 7476 7477 #if defined(__cplusplus) 7478 } 7479 #endif /* __cplusplus */ 7480 7481 #endif /* defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) */ 7482 7483 #endif /* CY_SYSCLK_H */ 7484 7485 /** \} group_sysclk */ 7486 7487 7488 /* [] END OF FILE */ 7489
