1 /***************************************************************************//** 2 * \file cy_sysclk.h 3 * \version 3.30 4 * 5 * Provides an API declaration of the sysclk driver. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2016-2021 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 /** 26 * \addtogroup group_sysclk 27 * \{ 28 * The System Clock (SysClk) driver contains the API for configuring system and 29 * peripheral clocks. 30 * 31 * The functions and other declarations used in this driver are in cy_sysclk.h. 32 * You can include cy_pdl.h to get access to all functions 33 * and declarations in the PDL. 34 * 35 * Firmware uses the API to configure, enable, or disable a clock. 36 * 37 * The clock system includes a variety of resources that can vary per device, including: 38 * - Internal clock sources such as internal oscillators 39 * - External clock sources such as crystal oscillators or a signal on an I/O pin 40 * - Generated clocks such as an FLL, a PLL, and peripheral clocks 41 * 42 * Consult the Technical Reference Manual for your device for details of the 43 * clock system. 44 * 45 * The PDL defines clock system capabilities in:\n 46 * devices/include/\<series\>_config.h. (E.g. 47 * devices/include/psoc6_01_config.h). 48 * User-configurable clock speeds are defined in the file system_<series>.h. 49 * 50 * As an illustration of the clocking system, the following diagram shows the 51 * PSoC 63 series clock tree. The actual tree may vary depending on the device series. 52 * Consult the Technical Reference Manual for your device for details. 53 *  54 * 55 * The sysclk driver supports multiple peripheral clocks, as well as the fast 56 * clock, slow clock, backup domain clock, timer clock, and pump clock. The API 57 * for any given clock contains the functions to manage that clock. Functions 58 * for clock measurement and trimming are also provided. 59 * 60 * \section group_sysclk_configuration Configuration Considerations 61 * The availability of clock functions depend on the availability of the chip 62 * resources that support those functions. Consult the device TRM before 63 * attempting to use these functions. 64 * For PSoC 64 devices the clocks configurations are restricted and limited. 65 * Refer to the PRA driver, and the TRM and datasheet for details. 66 * 67 * \warning 68 * On the diagram above, the yellow muxes are glitch-safe. All glitch-safe 69 * mux transitions take four cycles of the source clock. 70 * It is not allowed to turn off the source clock during that time. 71 * 72 * PSoC 6 power modes limit the maximum clock frequency. 73 * Refer to the SysPm driver and the TRM for details. 74 * 75 * \section group_sysclk_more_information More Information 76 * Refer to the technical reference manual (TRM) and the device datasheet. 77 * 78 * \section group_sysclk_changelog Changelog 79 * <table class="doxtable"> 80 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 81 * <tr> 82 * <td rowspan="3">3.30</td> 83 * <td> 84 * For PSoC64 device, allow CM0+ to call CY_PRA_FUNCTION_CALL_X_X API in functions 85 * accessing FUNCTION_POLICY registers. So that System Configuration structure is 86 * updated with new parameters. 87 * </td> 88 * <td>For PSoC64 device, System configuration can be done from CM0+ application.</td> 89 * </tr> 90 * <tr> 91 * <td>Fixed MISRA 2012 violations.</td> 92 * <td>MISRA 2012 compliance.</td> 93 * </tr> 94 * <tr> 95 * <td>Return type doxygen updated for PSoC64 devices.</td> 96 * <td>Doxygen update for PSoC64 devices.</td> 97 * </tr> 98 * <tr> 99 * <td>3.20</td> 100 * <td>Added new API's \ref Cy_SysClk_FllGetFrequency and \ref Cy_SysClk_PllGetFrequency.</td> 101 * <td>Fetch the FLL and PLL frequency.</td> 102 * </tr> 103 * <tr> 104 * <td>3.10</td> 105 * <td>Support for CM33.</td> 106 * <td>New devices support.</td> 107 * </tr> 108 * <tr> 109 * <td rowspan="2">3.0</td> 110 * <td>The behavior of \ref Cy_SysClk_EcoEnable and \ref Cy_SysClk_PllEnable is changed - 111 * these functions disable the resource in case of enabling failure (timeout).</td> 112 * <td>Usability enhancement.</td> 113 * </tr> 114 * <tr> 115 * <td>The implementation of \ref Cy_SysClk_ClkPathGetSource, 116 * \ref Cy_SysClk_FllConfigure, 117 * \ref Cy_SysClk_FllGetConfiguration, 118 * \ref Cy_SysClk_PllConfigure 119 * and \ref Cy_SysClk_ClkMeasurementCountersGetFreq 120 * is updated in accordance to the MISRA 2012 requirements. No behavioral changes.</td> 121 * <td>MISRA 2012 compliance.</td> 122 * </tr> 123 * <tr> 124 * <td>2.20.1</td> 125 * <td>Updated source code comments.</td> 126 * <td>Documentation update.</td> 127 * </tr> 128 * <tr> 129 * <td rowspan="3">2.20</td> 130 * <td>Added the assertion mechanism to the following functions: 131 * * Cy_SysClk_EcoDisable() 132 * * Cy_SysClk_IloEnable() 133 * * Cy_SysClk_IloHibernateOn() 134 * * Cy_SysClk_PiloEnable() 135 * * Cy_SysClk_PiloDisable() 136 * * Cy_SysClk_WcoDisable() 137 * * Cy_SysClk_WcoBypass() 138 * * Cy_SysClk_ClkFastSetDivider() 139 * * Cy_SysClk_ClkPeriSetDivider() 140 * * Cy_SysClk_ClkLfSetSource() 141 * * Cy_SysClk_ClkTimerSetSource() 142 * * Cy_SysClk_ClkTimerSetDivider() 143 * * Cy_SysClk_ClkTimerEnable() 144 * * Cy_SysClk_ClkTimerDisable() 145 * * Cy_SysClk_ClkPumpSetSource() 146 * * Cy_SysClk_ClkPumpSetDivider() 147 * * Cy_SysClk_ClkPumpEnable() 148 * * Cy_SysClk_ClkPumpDisable() 149 * * Cy_SysClk_ClkBakSetSource() 150 * 151 * Now, the functions described above halt in assertion when a PRA 152 * request returns not successful operation. This change is 153 * applicable only for the PSoC 64 family devices. 154 * </td> 155 * <td>Enhancements for the debugging process.</td> 156 * </tr> 157 * <tr> 158 * <td>Added \ref Cy_SysClk_PiloInitialTrim and \ref Cy_SysClk_PiloUpdateTrimStep functions. 159 * Extended the \ref Cy_SysClk_PiloTrim function to use the step-size value calculated for PILO 160 * based on the \ref Cy_SysClk_PiloInitialTrim and \ref Cy_SysClk_PiloUpdateTrimStep 161 * functions call. </td> 162 * </td> 163 * <td>User experience enhancement.</td> 164 * </tr> 165 * <tr> 166 * <td> 167 * * Added the warning that during a glitch-safe mux, the transition is not allowed 168 * to disable the previous clock source. See more info 169 * in the \ref group_sysclk_configuration. 170 * * Removed Known Issues table. 171 * </td> 172 * <td>Documentation updates.</td> 173 * </tr> 174 * <tr> 175 * <td rowspan="3">2.10</td> 176 * <td>Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return 177 * PRA driver status value.</td> 178 * <td>The SysClk driver uses the PRA driver to change the protected registers. 179 * A SysClk driver function that calls a PRA driver function will return the PRA 180 * error status code if the called PRA function returns an error. In these cases, 181 * refer to PRA return statuses. Refer to functions description for details.</td> 182 * </tr> 183 * <tr> 184 * <td>Updated the code of \ref Cy_SysClk_ClkPathGetFrequency function.</td> 185 * <td>Make the code more error-resistant to user errors for some corner cases.</td> 186 * </tr> 187 * <tr> 188 * <td>Minor documentation updates.</td> 189 * <td>Documentation enhancement.</td> 190 * </tr> 191 * <tr> 192 * <td>2.0</td> 193 * <td>Updated the ECO trimming values calculation algorithm in the \ref Cy_SysClk_EcoConfigure implementation. \n 194 * This change may invalidate the already used crystals, in cases: \n 195 * * The crystal frequency is less than 16 MHz. \n 196 * * The maximum amplitude (internal calculation value) is less than 0.65 V. \n 197 * 198 * For detail, refer the \ref Cy_SysClk_EcoConfigure documentation and the ECO Trimming section of the device TRM.</td> 199 * <td>Enhanced the ECO performance for high-noise conditions that result from simultaneous switching of GPIOs and/or high switching activity on the chip.</td> 200 * </tr> 201 * <tr> 202 * <td>1.60</td> 203 * <td>Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n 204 * \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n 205 * \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n 206 * \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n 207 * \ref Cy_SysClk_ClkPumpGetFrequency.</td> 208 * <td>API enhancement.</td> 209 * </tr> 210 * <tr> 211 * <td>1.50</td> 212 * <td>\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.</td> 213 * <td>API enhancement.</td> 214 * </tr> 215 * <tr> 216 * <td>1.40.2</td> 217 * <td>Update documentation based on collateral review feedback.</td> 218 * <td>User experience enhancement.</td> 219 * </tr> 220 * <tr> 221 * <td>1.40.1</td> 222 * <td>Fix compiler warning.</td> 223 * <td></td> 224 * </tr> 225 * <tr> 226 * <td rowspan="4">1.40</td> 227 * <td>Updated the following functions implementation: \ref Cy_SysClk_PllConfigure and \ref Cy_SysClk_PllEnable.</td> 228 * <td> 229 * Fixed the \ref Cy_SysClk_PllConfigure API function behaviour when it is called with a bypass mode, \n 230 * Fixed the \ref Cy_SysClk_PllEnable API function behaviour when it is called with a zero timeout. 231 * </td> 232 * </tr> 233 * <tr> 234 * <td>Added the following functions: \ref Cy_SysClk_MfoEnable, \ref Cy_SysClk_MfoIsEnabled,\n 235 * \ref Cy_SysClk_MfoDisable, \ref Cy_SysClk_ClkMfEnable, \ref Cy_SysClk_ClkMfIsEnabled,\n 236 * \ref Cy_SysClk_ClkMfDisable, \ref Cy_SysClk_ClkMfGetDivider, \ref Cy_SysClk_ClkMfSetDivider,\n. 237 * \ref Cy_SysClk_ClkMfGetFrequency</td> 238 * <td>New device support.</td> 239 * </tr> 240 * <tr> 241 * <td>Added the following new API functions \ref Cy_SysClk_FllIsEnabled, \ref Cy_SysClk_PllIsEnabled,\n 242 * \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_ClkHfGetFrequency, \ref Cy_SysClk_ClkFastGetFrequency,\n 243 * \ref Cy_SysClk_ClkPeriGetFrequency and \ref Cy_SysClk_ClkSlowGetFrequency</td> 244 * <td>Enhancement based on usability feedback</td> 245 * </tr> 246 * <tr> 247 * <td>Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUP</td> 248 * <td>Macros were moved into \ref group_syslib</td> 249 * </tr> 250 * <tr> 251 * <td rowspan="2">1.30</td> 252 * <td>Updated the following functions implementation: \ref Cy_SysClk_EcoConfigure and \ref Cy_SysClk_FllConfigure.</td> 253 * <td>Math library dependency is removed, the floating-point math is replaced with integer math.</td> 254 * </tr> 255 * <tr> 256 * <td>Updated the following functions implementation: \ref Cy_SysClk_EcoEnable, \ref Cy_SysClk_EcoGetStatus, \ref Cy_SysClk_FllGetConfiguration \n 257 * and \ref Cy_SysClk_DeepSleepCallback. \n 258 * The \ref Cy_SysClk_DeepSleepCallback now implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. \n 259 * The actions that were done in \ref CY_SYSPM_CHECK_READY case are moved to \ref CY_SYSPM_BEFORE_TRANSITION. \n 260 * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL.</td> 261 * <td>Defect fixing.</td> 262 * </tr> 263 * <tr> 264 * <td rowspan="4">1.20</td> 265 * <td>Flattened the organization of the driver source code into the single 266 * source directory and the single include directory. 267 * </td> 268 * <td>Driver library directory-structure simplification.</td> 269 * </tr> 270 * <tr> 271 * <td>Updated \ref Cy_SysClk_FllLocked function description</td> 272 * <td>The SRSS_ver1 HW details clarification</td> 273 * </tr> 274 * <tr> 275 * <td>Removed the following functions: 276 * - Cy_SysClk_FllLostLock 277 * - Cy_SysClk_WcoConfigureCsv 278 * - Cy_SysClk_ClkHfConfigureCsv 279 * </td> 280 * <td>No hardware support for the removed functions.</td> 281 * </tr> 282 * <tr> 283 * <td>Added register access layer. Use register access macros instead 284 * of direct register access using dereferenced pointers.</td> 285 * <td>Makes register access device-independent, so that the PDL does 286 * not need to be recompiled for each supported part number.</td> 287 * </tr> 288 * <tr> 289 * <td>1.11</td> 290 * <td>Updated the following functions. Now they use a semaphore when 291 * try to read the status or configure the SysClk measurement counters: 292 * * Cy_SysClk_StartClkMeasurementCounters() 293 * * Cy_SysClk_ClkMeasurementCountersGetFreq() 294 * 295 * Now Cy_SysClk_ClkMeasurementCountersGetFreq() returns zero value, 296 * if during measurement device was in the Deep Sleep or partially 297 * blocking flash operation occurred </td> 298 * <td>Added arbiter mechanism for correct usage of the SysClk measurement 299 * counters</td> 300 * </tr> 301 * <tr> 302 * <td>1.10.1</td> 303 * <td>Renamed Power Management section to Low Power Callback section</td> 304 * <td>Documentation update and clarification</td> 305 * </tr> 306 * <tr> 307 * <td rowspan="5">1.10</td> 308 * <td>Updated FLL parameter calculation</td> 309 * <td>Support low frequency sources</td> 310 * </tr> 311 * <tr> 312 * <td>Added Cy_SysClk_PiloSetTrim() and Cy_SysclkPiloGetTrim() functions</td> 313 * <td>Support PILO manual trims</td> 314 * </tr> 315 * <tr> 316 * <td>Made Cy_SysClk_FllLostLock() function dependent on SRSS v1</td> 317 * <td>Feature is not supported in SRSS v1</td> 318 * </tr> 319 * <tr> 320 * <td>Updated Cy_SysClk_DeepSleepCallback() to save/restore both FLL and PLL settings</td> 321 * <td>The function should return when the lock is established or a timeout has occurred</td> 322 * </tr> 323 * <tr> 324 * <td>General documentation updates</td> 325 * <td></td> 326 * </tr> 327 * <tr> 328 * <td>1.0</td> 329 * <td>Initial version</td> 330 * <td></td> 331 * </tr> 332 * </table> 333 * 334 * \defgroup group_sysclk_macros Macros 335 * \{ 336 * \} 337 * \defgroup group_sysclk_enums General Enumerated Types 338 * \{ 339 * \defgroup group_sysclk_returns Function return values 340 * \} 341 * \defgroup group_sysclk_ext External Clock Source (EXTCLK) 342 * \{ 343 * The External Clock Source (EXTCLK) is a clock source routed into PSoC 344 * through a GPIO pin. The EXTCLK is a source clock that can be used to 345 * source one or more clock paths (Refer to \ref group_sysclk_path_src). 346 * These clock paths can then source the processors and peripherals in 347 * the device. 348 * 349 * The EXTCLK relies on the presence of an external clock signal applied 350 * to the GPIO pin. The pin must be configured to operate in Digital 351 * High-Z drive mode with input buffer on and HSIOM connection 352 * set to HSIOM_SEL_ACT_4 (P0_0_SRSS_EXT_CLK, P0_5_SRSS_EXT_CLK). 353 * 354 * \defgroup group_sysclk_ext_funcs Functions 355 * \} 356 * \defgroup group_sysclk_eco External Crystal Oscillator (ECO) 357 * \{ 358 * The External Crystal Oscillator (ECO) is a clock source that consists 359 * of an oscillator circuit that drives an external crystal through its 360 * dedicated ECO pins. The ECO is a source clock that can be used to 361 * source one or more clock paths (Refer to \ref group_sysclk_path_src). 362 * These clock paths can then source the processors and peripherals in 363 * the device. 364 * 365 * The ECO relies on the presence of an external crystal. The pins 366 * connected to this crystal must be configured to operate in analog 367 * drive mode with HSIOM connection set to GPIO control (HSIOM_SEL_GPIO). 368 * 369 * \defgroup group_sysclk_eco_funcs Functions 370 * \} 371 * \defgroup group_sysclk_path_src Clock Path Source 372 * \{ 373 * Clock paths are a series of multiplexers that allow a source clock 374 * to drive multiple clocking resources down the chain. These paths are 375 * used for active domain clocks that are not operational during chip 376 * Deep Sleep, hibernate and off modes. Illustrated below is a diagram 377 * of the clock paths for the PSoC 63 series, showing the first three 378 * clock paths. The source clocks for these paths are highlighted in 379 * the red box. 380 * 381 * - IMO: 8 MHz Internal Main Oscillator (Default) 382 * - EXTCLK: External clock (signal brought in through dedicated pins) 383 * - ECO: External Crystal Oscillator (requires external crystal on dedicated pins) 384 * - ALTHF: Select on-chip signals (e.g. \ref group_ble_clk) 385 * - Digital Signal (DSI): Digital signal from a UDB source 386 * 387 * Some clock paths such as path 0 and path 1 have additional resources 388 * that can be utilized to provide a higher frequency clock. For example, 389 * path 0 source clock can be used as the reference clock for the FLL and 390 * path 1 source clock can be used as the reference clock for the PLL. 391 * 392 *  393 * 394 * \note The PDL driver cannot configure a clock path to use Digital Signal 395 * Interconnect (DSI) outputs as sources. This must be done through DSI 396 * configuration tool such as PSoC Creator. 397 * 398 * \defgroup group_sysclk_path_src_funcs Functions 399 * \defgroup group_sysclk_path_src_enums Enumerated Types 400 * \} 401 * \defgroup group_sysclk_fll Frequency Locked Loop (FLL) 402 * \{ 403 * The FLL is a clock generation circuit that can be used to produce a 404 * higher frequency clock from a reference clock. The output clock exhibits 405 * some characteristics of the reference clock such as the accuracy of the 406 * source. However other attributes such as the clock phase are not preserved. 407 * The FLL is similar in purpose to a (Phase locked loop) PLL but they are 408 * not equivalent. 409 * 410 * - They may have different frequency ranges. 411 * - The FLL starts up (locks) faster and consumes less current than the PLL. 412 * - The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz). 413 * - The FLL does not lock phase. The hardware consist of a counter with a 414 * current-controlled oscillator (CCO). The counter counts the number of output 415 * clock edges in a reference clock period and adjusts the CCO until the 416 * expected ratio is achieved (locked). After initial lock, the CCO is 417 * adjusted dynamically to keep the ratio within tolerance. The lock tolerance 418 * is user-adjustable. 419 *  420 * 421 * The SysClk driver supports two models for configuring the FLL. The first 422 * model is to call the Cy_SysClk_FllConfigure() function, which calculates the 423 * necessary parameters for the FLL at run-time. This may be necessary for dynamic 424 * run-time changes to the FLL. However this method is slow as it needs to perform 425 * the calculation before configuring the FLL. The other model is to call 426 * Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values. 427 * This method is faster but requires prior knowledge of the necessary parameters. 428 * Consult the device TRM for the FLL calculation equations. 429 * 430 * \defgroup group_sysclk_fll_funcs Functions 431 * \defgroup group_sysclk_fll_structs Data Structures 432 * \defgroup group_sysclk_fll_enums Enumerated Types 433 * \} 434 * \defgroup group_sysclk_pll Phase Locked Loop (PLL) 435 * \{ 436 * The PLL is a clock generation circuit that can be used to produce a 437 * higher frequency clock from a reference clock. The output clock exhibits 438 * characteristics of the reference clock such as the accuracy of the source 439 * and its phase. The PLL is similar in purpose to a (Frequency locked loop) FLL 440 * but they are not equivalent. 441 * 442 * - They may have different frequency ranges. 443 * - The PLL starts up more slowly and consumes more current than the FLL. 444 * - The PLL requires a higher frequency source clock than PLL. 445 *  446 * 447 * The SysClk driver supports two models for configuring the PLL. The first 448 * model is to call the Cy_SysClk_PllConfigure() function, which calculates the 449 * necessary parameters for the PLL at run-time. This may be necessary for dynamic 450 * run-time changes to the PLL. However this method is slow as it needs to perform 451 * the calculation before configuring the PLL. The other model is to call 452 * Cy_SysClk_PllManualConfigure() function with pre-calculated parameter values. 453 * This method is faster but requires prior knowledge of the necessary parameters. 454 * Consult the device TRM for the PLL calculation equations. 455 * 456 * \defgroup group_sysclk_pll_funcs Functions 457 * \defgroup group_sysclk_pll_structs Data Structures 458 * \} 459 * \defgroup group_sysclk_ilo Internal Low-Speed Oscillator (ILO) 460 * \{ 461 * The ILO operates with no external components and outputs a stable clock at 462 * 32.768 kHz nominal. The ILO is relatively low power and low accuracy. It is 463 * available in all power modes and can be used as a source for the Backup domain clock. 464 *  465 * 466 * To ensure the ILO remains active in Hibernate mode, and across power-on-reset 467 * (POR) or brown out detect (BOD), firmware must call Cy_SysClk_IloHibernateOn(). 468 * 469 * Additionally, the ILO clock can be trimmed to +/- 1.5% of nominal frequency using 470 * a higher precision clock source. Use the \ref group_sysclk_calclk API to measure 471 * the current ILO frequency before trimming. 472 * 473 * \note The ILO is always the source clock for the \ref group_wdt. Therefore: 474 * - The WDT must be unlocked when making an ILO function call in the PDL 475 * - It is recommended to always have the ILO enabled 476 * 477 * \defgroup group_sysclk_ilo_funcs Functions 478 * \} 479 * \defgroup group_sysclk_pilo Precision Internal Low-Speed Oscillator (PILO) 480 * \{ 481 * PILO provides a higher accuracy 32.768 kHz clock than the \ref group_sysclk_ilo "ILO". 482 * When periodically calibrated using a high-accuracy clock such as the 483 * \ref group_sysclk_eco "ECO", the PILO can achieve 250 ppm accuracy of nominal frequency. 484 * The PILO is capable of operating in device Active, Sleep and Deep-Sleep power modes. 485 * It is not available in Hibernate mode. 486 * 487 * The PILO can be used as a source for the \ref group_sysclk_clk_lf. However, 488 * because PILO is disabled in Hibernate mode, RTC timers cannot operate in this mode 489 * when clocked using the PILO. Instead, either the \ref group_sysclk_ilo "ILO" or 490 * \ref group_sysclk_wco "WCO" should be used when hibernate operation is required. 491 * 492 *  493 * 494 * Periodic calibration to a high-accuracy clock (such as ECO) is required to 495 * maintain accuracy. The application should use the functions described in the 496 * \ref group_sysclk_calclk API to measure the current PILO frequency before trimming. 497 * 498 * \defgroup group_sysclk_pilo_funcs Functions 499 * \} 500 * \defgroup group_sysclk_calclk Clock Measurement 501 * \{ 502 * These functions measure the frequency of a specified clock relative to a 503 * reference clock. They are typically called in the following order: 504 * 505 * 1. Specify the measured clock, the count, and the reference clock 506 * 2. Start the counters 507 * 3. Wait for the measurement counter to finish counting 508 * 4. Retrieve the measured frequency 509 * 510 * \note These functions may also be used as part of a clock trimming 511 * process. Refer to the \ref group_sysclk_trim "Clock Trim" API. 512 * 513 * \defgroup group_sysclk_calclk_funcs Functions 514 * \defgroup group_sysclk_calclk_enums Enumerated Types 515 * \defgroup group_sysclk_calclk_structs Data Structures 516 * \} 517 * \defgroup group_sysclk_trim Clock Trim (ILO, PILO) 518 * \{ 519 * These functions perform a single trim operation on the ILO or PILO. Each 520 * function's parameter is the actual frequency of the clock. To measure the 521 * frequency, use the functions described in the \ref group_sysclk_calclk API. 522 * 523 * To trim the clock as close as possible to the target frequency, multiple 524 * calls to the trim function may be needed. A typical usage example is to: 525 * 1. Call the clock measurement functions to get the actual frequency of the clock 526 * 2. Call the trim function, passing in the measured frequency 527 * 3. Repeat the above until the trim function reports that the clock is trimmed to within limits. 528 * 529 * \defgroup group_sysclk_trim_funcs Functions 530 * \} 531 * \defgroup group_sysclk_pm Low Power Callback 532 * \{ 533 * Entering and exiting low power modes require compatible clock configurations 534 * to be set before entering low power and restored upon wake-up and exit. The 535 * SysClk driver provides a Cy_SysClk_DeepSleepCallback() function to support 536 * Deep Sleep mode entry. 537 * 538 * This function can be called either by itself before initiating low-power mode 539 * entry or it can be used in conjunction with the SysPm driver as a registered 540 * callback. To do so, register this function as a callback before calling 541 * Cy_SysPm_DeepSleep(). Specify \ref CY_SYSPM_DEEPSLEEP as the callback type, 542 * and call Cy_SysPm_RegisterCallback(). 543 * 544 * \note If the FLL or PLL source is the ECO, this function must be called. 545 * 546 * \defgroup group_sysclk_pm_funcs Functions 547 * \} 548 * \defgroup group_sysclk_wco Watch Crystal Oscillator (WCO) 549 * \{ 550 * The WCO is a highly accurate 32.768 kHz clock source capable of operating 551 * in all power modes (excluding the Off mode). It is the primary clock source for 552 * the backup domain clock, which is used by the real-time clock (RTC). The 553 * WCO can also be used as a source for the low-frequency clock to support other 554 * low power mode peripherals. 555 * 556 *  557 * 558 * The WCO requires the configuration of the dedicated WCO pins (SRSS_WCO_IN_PIN, 559 * SRSS_WCO_OUT_PIN). These must be configured as Analog Hi-Z drive modes and the 560 * HSIOM selection set to GPIO. The WCO can also be used in bypass mode, where 561 * an external 32.768 kHz square wave is brought in directly through the 562 * SRSS_WCO_OUT_PIN pin. 563 * 564 * \defgroup group_sysclk_wco_funcs Functions 565 * \defgroup group_sysclk_wco_enums Enumerated Types 566 * \} 567 * \defgroup group_sysclk_clk_hf High-Frequency Clocks 568 * \{ 569 * Multiple high frequency clocks (CLK_HF) are available in the device. For example, 570 * PSoC 63 series has five high-frequency root clocks. Each CLK_HF has a particular 571 * connection and chip-specific destination on the device. 572 * 573 * |Name |Description | 574 * |:--------|:-------------------------------------------------------| 575 * |CLK_HF[0]| Root clock for CPUs, PERI, and AHB infrastructure | 576 * |CLK_HF[1]| Root clock for the PDM/PCM and I2S audio subsystem | 577 * |CLK_HF[2]| Root clock for the Serial Memory Interface subsystem | 578 * |CLK_HF[3]| Root clock for USB communications | 579 * |CLK_HF[4]| Clock output on clk_ext pin (when used as an output) | 580 * 581 *  582 * 583 * Note this is a particular example. The actual tree may vary depending on the device series. 584 * Consult the Technical Reference Manual for your device for details. 585 * 586 * High frequency clocks are sourced by path clocks, which should be configured 587 * first. An exception to this rule is CLK_HF[0], which cannot be disabled. 588 * This divided clock drives the core processors and the peripherals in the system. 589 * In order to update its clock source, CLK_HF[0] source must be selected without 590 * disabling the clock. 591 * 592 *  593 * 594 * \defgroup group_sysclk_clk_hf_funcs Functions 595 * \defgroup group_sysclk_clk_hf_enums Enumerated Types 596 * \} 597 * \defgroup group_sysclk_clk_fast Fast Clock 598 * \{ 599 * The fast clock drives the "fast" processor (e.g. Cortex-M4 processor in PSoC 6). 600 * This clock is sourced by CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). 601 * A divider value of 1~256 can be used to further divide the CLK_HF[0] to a 602 * desired clock speed for the processor. 603 * 604 *  605 * 606 * \defgroup group_sysclk_clk_fast_funcs Functions 607 * \} 608 * \defgroup group_sysclk_clk_peri Peripheral Clock 609 * \{ 610 * The peripheral clock is a divided clock of CLK_HF0 (\ref group_sysclk_clk_hf "HF Clocks"). 611 * It is the source clock for the \ref group_sysclk_clk_slow, and most active domain 612 * peripheral clocks (\ref group_sysclk_clk_peripheral). A divider value of 1~256 613 * can be used to further divide the CLK_HF[0] to a desired clock speed for the peripherals. 614 * 615 *  616 * 617 * \defgroup group_sysclk_clk_peri_funcs Functions 618 * \} 619 * \defgroup group_sysclk_clk_peripheral Peripherals Clock Dividers 620 * \{ 621 * There are multiple peripheral clock dividers that, in effect, create 622 * multiple separate peripheral clocks. The available dividers vary per device 623 * series. As an example, for the PSoC 63 series there are 29 dividers: 624 * 625 * - eight 8-bit dividers 626 * - sixteen 16-bit dividers 627 * - four fractional 16.5-bit dividers (16 integer bits, 5 fractional bits) 628 * - one fractional 24.5-bit divider (24 integer bits, 5 fractional bits) 629 * 630 * 631 * The 8-bit and 16-bit dividers are integer dividers. A divider value of 1 632 * means the output frequency matches the input frequency (that is, there is 633 * no change). Otherwise the frequency is divided by the value of the divider. 634 * For example, if the input frequency is 50 MHz, and the divider is value 10, 635 * the output frequency is 5 MHz. 636 * 637 * The five fractional bits supports further precision in 1/32nd increments. For 638 * example, a divider with an integer value of 3 and a fractional value of 639 * 4 (4/32) results in a divider of 3.125. Fractional dividers are useful when 640 * a high-precision clock is required, for example, for a UART/SPI serial 641 * interface. 642 * 643 *  644 * 645 * Each peripheral can connect to any one of the programmable dividers. A 646 * particular peripheral clock divider can drive multiple peripherals. 647 * 648 * The SysClk driver also supports phase aligning two peripheral clock dividers using 649 * Cy_SysClk_PeriphEnablePhaseAlignDivider(). Alignment works for both integer 650 * and fractional dividers. The divider to which a second divider is aligned 651 * must already be enabled. 652 * 653 * \defgroup group_sysclk_clk_peripheral_funcs Functions 654 * \defgroup group_sysclk_clk_peripheral_enums Enumerated Types 655 * \} 656 * \defgroup group_sysclk_clk_slow Slow Clock 657 * \{ 658 * The slow clock is the source clock for the "slow" processor (e.g. Cortex-M0+ in PSoC 6). 659 * This clock is a divided version of the \ref group_sysclk_clk_peri, which in turn is 660 * a divided version of CLK_HF[0] (\ref group_sysclk_clk_hf "HF Clocks"). A divider 661 * value of 1~256 can be used to further divide the Peri clock to a desired clock speed 662 * for the processor. 663 * 664 *  665 * 666 * \defgroup group_sysclk_clk_slow_funcs Functions 667 * \} 668 * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock 669 * \{ 670 * In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is 671 * connected to the system Alternative High-Frequency Clock input. 672 * 673 * \defgroup group_sysclk_alt_hf_funcs Functions 674 * \} 675 * \defgroup group_sysclk_clk_lf Low-Frequency Clock 676 * \{ 677 * The low-frequency clock is the source clock for the \ref group_mcwdt 678 * and can be the source clock for \ref group_sysclk_clk_bak, which drives the 679 * \ref group_rtc. 680 * 681 * The low-frequency clock has three possible source clocks: 682 * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", and 683 * \ref group_sysclk_wco "WCO". 684 * 685 *  686 * 687 * \defgroup group_sysclk_clk_lf_funcs Functions 688 * \defgroup group_sysclk_clk_lf_enums Enumerated Types 689 * \} 690 * \defgroup group_sysclk_clk_timer Timer Clock 691 * \{ 692 * The timer clock can be a source for the alternative clock driving 693 * the \ref group_arm_system_timer. It can also be used as a reference clock 694 * for a counter in the \ref group_energy_profiler "Energy Profiler". 695 * 696 * The timer clock is a divided clock of either the IMO or CLK_HF[0] 697 * (\ref group_sysclk_clk_hf "HF Clocks"). 698 * 699 * \defgroup group_sysclk_clk_timer_funcs Functions 700 * \defgroup group_sysclk_clk_timer_enums Enumerated Types 701 * \} 702 * \defgroup group_sysclk_clk_pump Pump Clock 703 * \{ 704 * The pump clock is a clock source used to provide analog precision in low voltage 705 * applications. Depending on the usage scenario, it may be required to drive the 706 * internal voltage pump for the Continuous Time Block mini (CTBm) in the analog 707 * subsystem. The pump clock is a divided clock of one of the clock paths 708 * (\ref group_sysclk_path_src). 709 * 710 * \defgroup group_sysclk_clk_pump_funcs Functions 711 * \defgroup group_sysclk_clk_pump_enums Enumerated Types 712 * \} 713 * \defgroup group_sysclk_clk_bak Backup Domain Clock 714 * \{ 715 * The backup domain clock drives the \ref group_rtc. 716 * This clock has two possible source clocks: \ref group_sysclk_wco "WCO" 717 * or the \ref group_sysclk_clk_lf. In turn the low frequency clock is sourced by 718 * \ref group_sysclk_ilo "ILO", \ref group_sysclk_pilo "PILO", or 719 * \ref group_sysclk_wco "WCO". Typically the ILO is not suitable as an RTC source, 720 * because of its low accuracy. However the ILO does operate in hibernate mode and 721 * may be used as an alternative to the WCO with a tradeoff in precision. 722 * 723 * \defgroup group_sysclk_clk_bak_funcs Functions 724 * \defgroup group_sysclk_clk_bak_enums Enumerated Types 725 * \} 726 * \defgroup group_sysclk_mf_funcs Medium Frequency Domain Clock 727 * \{ 728 * The Medium Frequency Domain Clock is present only in SRSS_ver1_3. 729 * Consists of MFO - the Medium Frequency Oscillator, 730 * and CLK_MF - the Medium Frequency Clock divider. 731 * This clock chain is designed to source the LCD block 732 * in Deep Sleep mode, see \ref cy_en_seglcd_lsclk_t. 733 * \} 734 */ 735 736 #if !defined (CY_SYSCLK_H) 737 #define CY_SYSCLK_H 738 739 #include "cy_device.h" 740 741 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) 742 #include <stdbool.h> 743 #include "cy_syslib.h" 744 #include "cy_syspm.h" 745 746 #if defined(CY_DEVICE_SECURE) 747 #include "cy_pra.h" 748 #endif /* defined(CY_DEVICE_SECURE) */ 749 750 751 #if defined(__cplusplus) 752 extern "C" { 753 #endif /* __cplusplus */ 754 755 /** 756 * \addtogroup group_sysclk_macros 757 * \{ 758 */ 759 /** Driver major version */ 760 #define CY_SYSCLK_DRV_VERSION_MAJOR 3 761 /** Driver minor version */ 762 #define CY_SYSCLK_DRV_VERSION_MINOR 20 763 /** Sysclk driver identifier */ 764 #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) 765 766 /** ILO clock frequency */ 767 #define CY_SYSCLK_ILO_FREQ (32768UL) /* Hz */ 768 /** WCO clock frequency */ 769 #define CY_SYSCLK_WCO_FREQ (32768UL) /* Hz */ 770 /** PILO clock frequency */ 771 #define CY_SYSCLK_PILO_FREQ (32768UL) /* Hz */ 772 773 /** IMO clock frequency */ 774 #define CY_SYSCLK_IMO_FREQ (8000000UL) /* Hz */ 775 776 /** MFO clock frequency */ 777 #define CY_SYSCLK_MFO_FREQ (2000000UL) /* Hz */ 778 779 /** CY_SYSCLK_PILO_TRIM_STEP is the default PILO TRIM Step value */ 780 #define CY_SYSCLK_PILO_TRIM_STEP (5UL) /* Default PILO TRIM Step size */ 781 782 #if defined (CY_IP_MXS28SRSS) 783 /** 784 * \note 785 * This macro is available for CAT1B devices. 786 **/ 787 /** IHO clock frequency */ 788 #define CY_SYSCLK_IHO_FREQ (48000000UL) /* Hz */ 789 /** 790 * \note 791 * This macro is available for CAT1B devices. 792 **/ 793 /** ECO clock frequency */ 794 #define CY_SYSCLK_ECO_FREQ (4000000UL) /* Hz */ 795 #endif /* CY_IP_MXS28SRSS */ 796 797 /** \} group_sysclk_macros */ 798 799 800 /** 801 * \addtogroup group_sysclk_returns 802 * \{ 803 */ 804 /** Defines general-purpose function return values */ 805 typedef enum 806 { 807 CY_SYSCLK_SUCCESS = 0x00UL, /**< Command completed with no errors */ 808 CY_SYSCLK_BAD_PARAM = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x01UL), /**< Invalid function input parameter */ 809 CY_SYSCLK_TIMEOUT = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x02UL), /**< Timeout occurred */ 810 CY_SYSCLK_INVALID_STATE = (CY_SYSCLK_ID | CY_PDL_STATUS_ERROR | 0x03UL) /**< Clock is in an invalid state */ 811 } cy_en_sysclk_status_t; 812 /** \} group_sysclk_returns */ 813 814 815 /* ========================================================================== */ 816 /* =========================== EXT SECTION ============================ */ 817 /* ========================================================================== */ 818 819 /** \cond INTERNAL */ 820 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) 821 /* Internal storage for external clock frequency user setting */ 822 extern uint32_t cySysClkExtFreq; 823 #endif 824 /** \endcond */ 825 826 /** 827 * \addtogroup group_sysclk_ext_funcs 828 * \{ 829 */ 830 /******************************************************************************* 831 * Function Name: Cy_SysClk_ExtClkSetFrequency 832 ****************************************************************************//** 833 * 834 * Sets the signal frequency of the External Clock Source (EXTCLK) into the 835 * internal storage to be used in \ref Cy_SysClk_ClkHfGetFrequency. 836 * 837 * \param freq The frequency of the External Clock Source. 838 * 839 * \funcusage 840 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency 841 * 842 *******************************************************************************/ 843 void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); 844 845 846 /******************************************************************************* 847 * Function Name: Cy_SysClk_ExtClkGetFrequency 848 ****************************************************************************//** 849 * 850 * Returns the frequency of the External Clock Source (EXTCLK) from the 851 * internal storage. 852 * 853 * \return The frequency of the External Clock Source. 854 * 855 * \funcusage 856 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency 857 * 858 *******************************************************************************/ 859 uint32_t Cy_SysClk_ExtClkGetFrequency(void); 860 /** \} group_sysclk_ext_funcs */ 861 862 /* ========================================================================== */ 863 /* =========================== ECO SECTION ============================ */ 864 /* ========================================================================== */ 865 866 /** 867 * \addtogroup group_sysclk_macros 868 * \{ 869 */ 870 871 /** 872 * \defgroup group_sysclk_ecostatus ECO status 873 * \{ 874 * Constants used for expressing ECO status. 875 */ 876 #define CY_SYSCLK_ECOSTAT_AMPLITUDE 0UL /**< \brief ECO does not have sufficient amplitude */ 877 #define CY_SYSCLK_ECOSTAT_INACCURATE 1UL /**< \brief ECO may not be meeting accuracy and duty cycle specs */ 878 #define CY_SYSCLK_ECOSTAT_STABLE 2UL /**< \brief ECO has fully stabilized */ 879 880 #if defined (CY_IP_MXS28SRSS) 881 /** 882 * \note 883 * This macro is available for CAT1B devices. 884 **/ 885 #define CY_SYSCLK_ECOSTAT_BLE_DISABLED 0UL /**< \brief ECO for BLE is disabled */ 886 /** 887 * \note 888 * This macro is available for CAT1B devices. 889 **/ 890 #define CY_SYSCLK_ECOSTAT_BLE_ENABLED 1UL /**< \brief ECO for BLE is enabled */ 891 #endif /* CY_IP_MXS28SRSS */ 892 893 /** \} group_sysclk_ecostatus */ 894 895 # if (defined (CY_DEVICE_SECURE)) 896 /** 897 * \note 898 * This structure is available for CAT1A devices. 899 **/ 900 /** PRA structure for Cy_SysClk_EcoConfigure function parameters */ 901 typedef struct 902 { 903 uint32_t praClkEcofreq; /**< freq */ 904 uint32_t praCsum; /**< cSum */ 905 uint32_t praEsr; /**< esr */ 906 uint32_t praDriveLevel; /**< drivelevel */ 907 } cy_stc_pra_clk_eco_configure_t; 908 #endif /* (defined (CY_DEVICE_SECURE)) */ 909 910 /** \} group_sysclk_macros */ 911 912 #if defined (CY_IP_MXS40SRSS) 913 /** \cond */ 914 /** 915 * \note 916 * This macro is available for CAT1A devices. 917 **/ 918 #define SRSS_CLK_ECO_STATUS_Msk (SRSS_CLK_ECO_STATUS_ECO_OK_Msk | SRSS_CLK_ECO_STATUS_ECO_READY_Msk) 919 /** \endcond */ 920 #endif /* CY_IP_MXS40SRSS */ 921 922 #if defined (CY_IP_MXS28SRSS) 923 /** \cond */ 924 /** 925 * \note 926 * It is available for CAT1B devices. 927 **/ 928 #define SRSS_CLK_ECO_READY_Msk SRSS_CLK_ECO_STATUS_ECO_CORE_READY_Msk 929 #define SRSS_CLK_ECO_AMP_OK_Msk SRSS_CLK_ECO_STATUS_ECO_CORE_AMP_OK_Msk 930 /** \endcond */ 931 #endif /* CY_IP_MXS28SRSS */ 932 933 934 935 #if defined (CY_IP_MXS28SRSS) 936 /** 937 * \addtogroup group_sysclk_eco_enums 938 * \{ 939 */ 940 /** 941 * ECO enable options for BLE 942 */ 943 /** 944 * \note 945 * This enum is available for CAT1B devices. 946 **/ 947 typedef enum 948 { 949 CY_SYSCLK_ECO_BLESS_CONTROL0 = 0U, /**< 0, 1: hardware controlled by BLESS. */ 950 CY_SYSCLK_ECO_BLESS_CONTROL1 = 1U, /**< 0, 1: hardware controlled by BLESS. */ 951 CY_SYSCLK_ECO_FORCE_ENABLE = 2U, /**< Force ECO enabled for use by BLE */ 952 CY_SYSCLK_ECO_FORCE_DISABLE = 3U, /**< Force ECO disabled for use by BLE */ 953 } cy_en_eco_for_ble_t; 954 /** \} group_sysclk_eco_enums */ 955 #endif /* CY_IP_MXS28SRSS */ 956 957 /** 958 * \addtogroup group_sysclk_eco_funcs 959 * \{ 960 */ 961 /******************************************************************************* 962 * Function Name: Cy_SysClk_EcoConfigure 963 ****************************************************************************//** 964 * 965 * Configures the external crystal oscillator (ECO) trim bits based on crystal 966 * characteristics. This function should be called only when the ECO is disabled. 967 * 968 * \param freq Operating frequency of the crystal in Hz. 969 * Valid range: 16000000...35000000 (16..35 MHz). 970 * 971 * \param cSum The summary capacitance of 972 * C0 (the crystal itself shunt capacitance) and 973 * Cload (the parallel load capacitance), in pF. 974 * So cSum = C0 + Cload. 975 * Valid range: 1...100. 976 * \note 977 * For CAT1B Devices: 978 * cSum stands for crystal load capacitance in pF. 979 * 980 * \param esr Effective series resistance of the crystal in Ohms. 981 * Valid range: 1...1000. 982 * 983 * \param driveLevel Crystal drive level in uW. 984 * Valid range: 1...2000. 985 * 986 * \return Error / status code: \n 987 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 988 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 989 * CY_SYSCLK_INVALID_STATE - ECO already enabled 990 * \note Behavior of this API is IP dependent. \n 991 * On CAT1A device: \n 992 * 993 * For the PSoC 64 devices there are possible situations when function returns 994 * the PRA error status code. This is because for PSoC 64 devices the function 995 * uses the PRA driver to change the protected registers. Refer to 996 * \ref cy_en_pra_status_t for more details. 997 * The following calculations are implemented in the 32-bit integer math: 998 * On PSoC 64 devices the configuration on the PRA driver will be reflected 999 * after \ref Cy_SysClk_EcoEnable call. 1000 * 1001 * \verbatim 1002 * freqKhz = freq / 1000 1003 * maxAmpl = sqrt(drivelevel / 2 / esr) / 3.14 / freqKhz / cSum 1004 * ampSect = INT(5 * 4 * 3.14^2 * freqKhz^2 * cSum^2 * 4 * esr / 1000000000 / 1000000 / 9) 1005 * As a result of the above calculations, max amplitude must be >= 0.65V, and the 1006 * number of amplifier sections must be <= 3, otherwise this function returns with 1007 * a parameter error. 1008 * 1009 * atrim = 15 1010 * agc_en = 1 1011 * wdtrim = 7 1012 * gtrim = ampSect > 1 ? ampSect : ampSect == 1 ? 0 : 1 1013 * rtrim = 0 1014 * ftrim = 3 1015 * \endverbatim 1016 * 1017 * \note 1018 * On CAT1B Device: \n 1019 * 1020 * \verbatim 1021 1022 * No TRIM registers configuration required for CAT1B devices, For legacy API is emptied 1023 * The following calculations are implemented, generally in floating point: 1024 * freqMHz = freq / 1000000 1025 * max amplitude Vpp = 1000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad 1026 * gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1000000000 1027 * Number of amplifier sections = INT(gm_min / 4.5) 1028 * 1029 * As a result of the above calculations, max amplitude must be >= 0.5, and the 1030 * number of amplifier sections must be <= 3, otherwise this function returns with 1031 * a parameter error. 1032 * 1033 * atrim = if (max amplitude < 0.5) then error 1034 * else 2 * the following: 1035 * max amplitude < 0.6: 0 1036 * max amplitude < 0.7: 1 1037 * max amplitude < 0.8: 2 1038 * max amplitude < 0.9: 3 1039 * max amplitude < 1.15: 5 1040 * max amplitude < 1.275: 6 1041 * max amplitude >= 1.275: 7 1042 * wdtrim = if (max amplitude < 0.5) then error 1043 * else 2 * the following: 1044 * max amplitude < 1.2: INT(5 * max amplitude) - 2 1045 * max amplitude >= 1.2: 3 1046 * gtrim = if (number of amplifier sections > 3) then error 1047 * else the following: 1048 * number of amplifier sections > 1: number of amplifier sections 1049 * number of amplifier sections = 1: 0 1050 * number of amplifier sections < 1: 1 1051 * rtrim = if (gtrim = error) then error 1052 * else the following: 1053 * freqMHz > 26.8: 0 1054 * freqMHz > 23.33: 1 1055 * freqMHz > 16.5: 2 1056 * freqMHz <= 16.5: 3 1057 * ftrim = if (atrim = error) then error 1058 * else INT(atrim / 2) 1059 * \endverbatim 1060 * 1061 * \funcusage 1062 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoConfigure 1063 * 1064 *******************************************************************************/ 1065 cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint32_t esr, uint32_t driveLevel); 1066 1067 1068 /******************************************************************************* 1069 * Function Name: Cy_SysClk_EcoEnable 1070 ****************************************************************************//** 1071 * 1072 * Enables the external crystal oscillator (ECO). This function should be called 1073 * after \ref Cy_SysClk_EcoConfigure. 1074 * 1075 * \param timeoutus Amount of time in microseconds to wait for the ECO to stabilize. 1076 * To avoid waiting for stabilization, set this parameter to 0. 1077 * 1078 * \return Error / status code: \n 1079 * CY_SYSCLK_SUCCESS - ECO locked \n 1080 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1081 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1082 * For the PSoC 64 devices there are possible situations when function returns 1083 * the PRA error status code. This is because for PSoC 64 devices the function 1084 * uses the PRA driver to change the protected registers. Refer to 1085 * \ref cy_en_pra_status_t for more details. 1086 * 1087 * \note 1088 * Call \ref SystemCoreClockUpdate after this function calling 1089 * if it affects the CLK_HF0 frequency. 1090 * 1091 * \funcusage 1092 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable 1093 * 1094 *******************************************************************************/ 1095 cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus); 1096 1097 1098 #if defined (CY_IP_MXS28SRSS) 1099 /******************************************************************************* 1100 * Function Name: Cy_SysClk_EcoBleEnable 1101 ****************************************************************************//** 1102 * 1103 * Enables the external crystal oscillator (ECO) for BlueTooth Usage. This function should be called 1104 * after \ref Cy_SysClk_EcoConfigure. 1105 * 1106 * \param control To be selected from \ref cy_en_eco_for_ble_t 1107 * 1108 * \param timeoutus timeoutus 1109 * 1110 * \return Error / status code: \n 1111 * CY_SYSCLK_SUCCESS - ECO locked \n 1112 * CY_SYSCLK_TIMEOUT - ECO timed out and did not lock \n 1113 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1114 * 1115 * \note 1116 * This API is available for CAT1B devices. 1117 * 1118 *******************************************************************************/ 1119 cy_en_sysclk_status_t Cy_SysClk_EcoBleControl(cy_en_eco_for_ble_t control, uint32_t timeoutus); 1120 #endif /* CY_IP_MXS28SRSS */ 1121 1122 /******************************************************************************* 1123 * Function Name: Cy_SysClk_EcoGetFrequency 1124 ****************************************************************************//** 1125 * 1126 * Returns the frequency of the external crystal oscillator (ECO). 1127 * 1128 * \return The frequency of the ECO. 1129 * 1130 * \note If the ECO is not enabled or stable - a zero is returned. 1131 * 1132 * \funcusage 1133 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable 1134 * 1135 * \note 1136 * This API is available for CAT1A devices. 1137 * 1138 *******************************************************************************/ 1139 uint32_t Cy_SysClk_EcoGetFrequency(void); 1140 1141 1142 /******************************************************************************* 1143 * Function Name: Cy_SysClk_EcoDisable 1144 ****************************************************************************//** 1145 * 1146 * Disables the external crystal oscillator (ECO). This function should not be 1147 * called if the ECO is sourcing clkHf[0]. 1148 * 1149 * \funcusage 1150 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoDisable 1151 * 1152 *******************************************************************************/ 1153 void Cy_SysClk_EcoDisable(void); 1154 1155 1156 /******************************************************************************* 1157 * Function Name: Cy_SysClk_EcoGetStatus 1158 ****************************************************************************//** 1159 * 1160 * Reports the current status of the external crystal oscillator (ECO). 1161 * 1162 * \return 1163 * CY_SYSCLK_ECOSTAT_AMPLITUDE = ECO does not have sufficient amplitude \n 1164 * CY_SYSCLK_ECOSTAT_INACCURATE = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications \n 1165 * CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized 1166 * 1167 * \funcusage 1168 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoGetStatus 1169 * 1170 *******************************************************************************/ 1171 uint32_t Cy_SysClk_EcoGetStatus(void); 1172 1173 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) 1174 1175 /******************************************************************************* 1176 * Function Name: Cy_SysClk_EcoBleGetStatus 1177 ****************************************************************************//** 1178 * 1179 * Reports the current status w.r.to BLE of the external crystal oscillator (ECO). 1180 * 1181 * \return 1182 * CY_SYSCLK_ECOSTAT_BLE_ENABLED = ECO for BLE is enabled \n 1183 * CY_SYSCLK_ECOSTAT_BLE_DISABLED = ECO for BLE is not enabled 1184 * 1185 * \note 1186 * This API is available for CAT1B devices. 1187 * 1188 *******************************************************************************/ 1189 uint32_t Cy_SysClk_EcoBleGetStatus(void); 1190 1191 1192 /******************************************************************************* 1193 * Function Name: Cy_SysClk_EcoPrescaleConfigure 1194 ****************************************************************************//** 1195 * 1196 * Configures the external crystal oscillator (ECO) using ECO Prescaler 1197 * Configuration Register and derives clk_eco_prescaler 1198 * 1199 * \param enable ECO Prescaler enable/disable. 1200 * 1201 * \param frac_div 8-bit fraction value. 1202 * 1203 * \param int_div 10-bit integer value. 1204 * 1205 * 1206 * \return Error / status code: \n 1207 * CY_SYSCLK_SUCCESS - ECO configuration completed successfully \n 1208 * CY_SYSCLK_BAD_PARAM - One or more invalid parameters \n 1209 * CY_SYSCLK_INVALID_STATE - ECO already enabled 1210 * 1211 * \note 1212 * This API is available for CAT1B devices. 1213 * 1214 *******************************************************************************/ 1215 cy_en_sysclk_status_t Cy_SysClk_EcoPrescaleConfigure(uint32_t enable, uint32_t frac_div, uint32_t int_div); 1216 #endif 1217 /** \} group_sysclk_eco_funcs */ 1218 1219 1220 /* ========================================================================== */ 1221 /* ==================== INPUT MULTIPLEXER SECTION ===================== */ 1222 /* ========================================================================== */ 1223 /** 1224 * \addtogroup group_sysclk_path_src_enums 1225 * \{ 1226 */ 1227 /** 1228 * Input multiplexer clock sources 1229 */ 1230 1231 1232 typedef enum 1233 { 1234 CY_SYSCLK_CLKPATH_IN_IMO = 0U, /**< Select the IMO as the output of the path mux */ 1235 CY_SYSCLK_CLKPATH_IN_EXT = 1U, /**< Select the EXT as the output of the path mux */ 1236 CY_SYSCLK_CLKPATH_IN_ECO = 2U, /**< Select the ECO as the output of the path mux */ 1237 CY_SYSCLK_CLKPATH_IN_ALTHF = 3U, /**< Select the ALTHF as the output of the path mux */ 1238 1239 CY_SYSCLK_CLKPATH_IN_DSIMUX = 4U, /**< Select the DSI MUX output as the output of the path mux */ 1240 CY_SYSCLK_CLKPATH_IN_LPECO = 5U, /**< Select the LPECO as the output of the path mux */ 1241 CY_SYSCLK_CLKPATH_IN_IHO = 6U, /**< Select the IHO as the output of the path mux */ 1242 CY_SYSCLK_CLKPATH_IN_DSI = 0x100U, /**< Select a DSI signal (0 - 15) as the output of the DSI mux and path mux. 1243 * Make sure the DSI clock sources are available on used device. 1244 */ 1245 CY_SYSCLK_CLKPATH_IN_ILO = 0x110U, /**< Select the ILO (16) as the output of the DSI mux and path mux */ 1246 CY_SYSCLK_CLKPATH_IN_WCO = 0x111U, /**< Select the WCO (17) as the output of the DSI mux and path mux */ 1247 CY_SYSCLK_CLKPATH_IN_ALTLF = 0x112U, /**< Select the ALTLF (18) as the output of the DSI mux and path mux. 1248 * Make sure the ALTLF clock sources in available on used device. 1249 */ 1250 CY_SYSCLK_CLKPATH_IN_PILO = 0x113U, /**< Select the PILO (19) as the output of the DSI mux and path mux. 1251 * Make sure the PILO clock sources in available on used device. 1252 */ 1253 CY_SYSCLK_CLKPATH_IN_ILO1 = 0x114U /**< Select the ILO1(20) as the output of the path mux */ 1254 } cy_en_clkpath_in_sources_t; 1255 1256 1257 #if (defined(CY_DEVICE_SECURE)) 1258 /** 1259 * \note 1260 * This structure is available for CAT1A devices. 1261 **/ 1262 /** PRA structure for Cy_SysClk_ClkPathSetSource function parameters */ 1263 typedef struct 1264 { 1265 uint32_t clk_path; /**< clkpath */ 1266 cy_en_clkpath_in_sources_t source; /**< Source */ 1267 } cy_stc_pra_clkpathsetsource_t; 1268 #endif 1269 1270 /** \} group_sysclk_path_src_enums */ 1271 1272 /** 1273 * \addtogroup group_sysclk_path_src_funcs 1274 * \{ 1275 */ 1276 /******************************************************************************* 1277 * Function Name: Cy_SysClk_ClkPathSetSource 1278 ****************************************************************************//** 1279 * 1280 * Configures the source for the specified clock path. 1281 * 1282 * \param clkPath Selects which clock path to configure; 0 is the first clock 1283 * path, which is the FLL. 1284 * 1285 * \param source \ref cy_en_clkpath_in_sources_t 1286 * 1287 * \return \ref cy_en_sysclk_status_t 1288 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1289 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1290 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1291 * uses the PRA driver to change the protected registers. Refer to 1292 * \ref cy_en_pra_status_t for more details. 1293 * 1294 * \note 1295 * If calling this function changes an FLL or PLL input frequency, disable the FLL 1296 * or PLL before calling this function. After calling this function, call the FLL 1297 * or PLL configure function, for example \ref Cy_SysClk_FllConfigure(). 1298 * 1299 * \note 1300 * Call \ref SystemCoreClockUpdate after this function calling 1301 * if it affects the CLK_HF0 frequency. 1302 * 1303 * \note 1304 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1305 * it affects the CLK_HF0 frequency and the frequency is increasing. 1306 * 1307 * \note 1308 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1309 * it affects the CLK_HF0 frequency and the frequency is decreasing. 1310 * 1311 * \funcusage 1312 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 1313 * 1314 *******************************************************************************/ 1315 cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); 1316 1317 1318 /******************************************************************************* 1319 * Function Name: Cy_SysClk_ClkPathGetSource 1320 ****************************************************************************//** 1321 * 1322 * Reports which source is selected for the path mux. 1323 * 1324 * \param clkPath Selects which clock path to report; 0 is the first clock path, 1325 * which is the FLL. 1326 * 1327 * \return \ref cy_en_clkpath_in_sources_t 1328 * 1329 * \funcusage 1330 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathGetSource 1331 * 1332 *******************************************************************************/ 1333 cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); 1334 1335 1336 /******************************************************************************* 1337 * Function Name: Cy_SysClk_ClkPathMuxGetFrequency 1338 ****************************************************************************//** 1339 * 1340 * Returns the output frequency of the clock path mux. 1341 * 1342 * \return The output frequency of the path mux. 1343 * 1344 * \note If the return value equals zero, that means either: 1345 * - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or 1346 * - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). 1347 * 1348 * \funcusage 1349 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 1350 * 1351 *******************************************************************************/ 1352 uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath); 1353 1354 1355 /******************************************************************************* 1356 * Function Name: Cy_SysClk_ClkPathGetFrequency 1357 ****************************************************************************//** 1358 * 1359 * Returns the output frequency of the clock path mux. 1360 * 1361 * \return The output frequency of the path mux. 1362 * 1363 * \note If the return value equals zero, that means either: 1364 * - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or 1365 * - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). 1366 * 1367 * \funcusage 1368 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable 1369 * 1370 *******************************************************************************/ 1371 uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath); 1372 /** \} group_sysclk_path_src_funcs */ 1373 1374 1375 /* ========================================================================== */ 1376 /* =========================== FLL SECTION ============================ */ 1377 /* ========================================================================== */ 1378 /** 1379 * \addtogroup group_sysclk_fll_enums 1380 * \{ 1381 */ 1382 /** FLL and PLL output mode. 1383 * See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL. 1384 */ 1385 typedef enum 1386 { 1387 CY_SYSCLK_FLLPLL_OUTPUT_AUTO = 0U, /**< Output FLL/PLL input source when not locked, and FLL/PLL output when locked */ 1388 CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1U, /**< Same as AUTO */ 1389 CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2U, /**< Output FLL/PLL input source regardless of lock status */ 1390 CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3U /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable */ 1391 } cy_en_fll_pll_output_mode_t; 1392 1393 1394 /** FLL current-controlled oscillator (CCO) frequency ranges. 1395 * See register CLK_FLL_CONFIG4, bits CCO_RANGE. 1396 */ 1397 typedef enum 1398 { 1399 CY_SYSCLK_FLL_CCO_RANGE0, /**< Target frequency is in range 48 - 64 MHz */ 1400 CY_SYSCLK_FLL_CCO_RANGE1, /**< Target frequency is in range 64 - 85 MHz */ 1401 CY_SYSCLK_FLL_CCO_RANGE2, /**< Target frequency is in range 85 - 113 MHz */ 1402 CY_SYSCLK_FLL_CCO_RANGE3, /**< Target frequency is in range 113 - 150 MHz */ 1403 CY_SYSCLK_FLL_CCO_RANGE4 /**< Target frequency is in range 150 - 200 MHz */ 1404 } cy_en_fll_cco_ranges_t; 1405 /** \} group_sysclk_fll_enums */ 1406 1407 1408 /** 1409 * \addtogroup group_sysclk_fll_structs 1410 * \{ 1411 */ 1412 /** Structure containing information for manual configuration of FLL. 1413 */ 1414 typedef struct 1415 { 1416 uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ 1417 uint16_t refDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ 1418 cy_en_fll_cco_ranges_t ccoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */ 1419 bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */ 1420 uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */ 1421 uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */ 1422 uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */ 1423 uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */ 1424 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ 1425 uint16_t cco_Freq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */ 1426 } cy_stc_fll_manual_config_t; 1427 1428 /** \} group_sysclk_fll_structs */ 1429 1430 /** 1431 * \addtogroup group_sysclk_fll_funcs 1432 * \{ 1433 *//******************************************************************************* 1434 * Function Name: Cy_SysClk_FllConfigure 1435 ****************************************************************************//** 1436 * 1437 * Configures the FLL, for best accuracy optimization. 1438 * 1439 * \param inputFreq frequency of input source, in Hz 1440 * 1441 * \param outputFreq Desired FLL output frequency, in Hz. Allowable range is 1442 * 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide 1443 * by 2 option is required. 1444 * 1445 * \param outputMode \ref cy_en_fll_pll_output_mode_t 1446 * If output mode is bypass, then the output frequency equals the input source 1447 * frequency regardless of the frequency parameter values. 1448 * 1449 * \return Error / status code: \n 1450 * CY_SYSCLK_SUCCESS - FLL successfully configured \n 1451 * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled \n 1452 * CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range 1453 * 1454 * \note 1455 * Call this function after changing the FLL input frequency, for example if 1456 * \ref Cy_SysClk_ClkPathSetSource() is called. 1457 * 1458 * \note 1459 * Do not call this function when the FLL is enabled. If it is called, then this function 1460 * returns with an CY_SYSCLK_INVALID_STATE return value and no register updates. 1461 * 1462 * \note 1463 * Call \ref SystemCoreClockUpdate after this function calling 1464 * if it affects the CLK_HF0 frequency. 1465 * 1466 * \note 1467 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1468 * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. 1469 * 1470 * \note 1471 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1472 * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. 1473 * 1474 * \note 1475 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1476 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 1477 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 1478 * 1479 * \funcusage 1480 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllConfigure 1481 * 1482 *******************************************************************************/ 1483 cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode); 1484 1485 1486 /******************************************************************************* 1487 * Function Name: Cy_SysClk_FllManualConfigure 1488 ****************************************************************************//** 1489 * 1490 * Manually configures the FLL based on user inputs. 1491 * 1492 * \param config \ref cy_stc_fll_manual_config_t 1493 * 1494 * \return Error / status code: \n 1495 * CY_SYSCLK_SUCCESS - FLL successfully configured \n 1496 * CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled 1497 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1498 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1499 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1500 * uses the PRA driver to change the protected registers. Refer to 1501 * \ref cy_en_pra_status_t for more details. 1502 * 1503 * \note 1504 * Call this function after changing the FLL input frequency, for example if 1505 * \ref Cy_SysClk_ClkPathSetSource() is called. 1506 * 1507 * \note 1508 * Do not call this function when the FLL is enabled. If it is called, then this function 1509 * returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates. 1510 * 1511 * \note 1512 * Call \ref SystemCoreClockUpdate after this function calling 1513 * if it affects the CLK_HF0 frequency. 1514 * 1515 * \note 1516 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1517 * the FLL is the source of CLK_HF0 and the FLL frequency is increasing. 1518 * 1519 * \note 1520 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1521 * the FLL is the source of CLK_HF0 and the FLL frequency is decreasing. 1522 * 1523 * \note 1524 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1525 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 1526 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 1527 * 1528 * \funcusage 1529 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllManualConfigure 1530 * 1531 *******************************************************************************/ 1532 cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config); 1533 1534 1535 /******************************************************************************* 1536 * Function Name: Cy_SysClk_FllGetConfiguration 1537 ****************************************************************************//** 1538 * 1539 * Reports the FLL configuration settings. 1540 * 1541 * \param config \ref cy_stc_fll_manual_config_t 1542 * 1543 * \note 1544 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1545 * after \ref Cy_SysClk_FllEnable call. Any call to \ref Cy_SysClk_FllGetConfiguration 1546 * before calling \ref Cy_SysClk_FllEnable returns old configuration values. 1547 * 1548 * \funcusage 1549 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetConfiguration 1550 * 1551 *******************************************************************************/ 1552 void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config); 1553 1554 1555 /******************************************************************************* 1556 * Function Name: Cy_SysClk_FllEnable 1557 ****************************************************************************//** 1558 * 1559 * Enables the FLL. The FLL should be configured before calling this function. 1560 * 1561 * \param timeoutus Amount of time in micro seconds to wait for FLL to lock. 1562 * If lock doesn't occur, the FLL is stopped. To avoid waiting for lock, set this to 0 1563 * and manually check for lock using \ref Cy_SysClk_FllLocked. 1564 * 1565 * \return Error / status code: \n 1566 * CY_SYSCLK_SUCCESS - FLL successfully enabled \n 1567 * CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock 1568 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1569 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1570 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1571 * uses the PRA driver to change the protected registers. Refer to 1572 * \ref cy_en_pra_status_t for more details. 1573 * 1574 * \note 1575 * While waiting for the FLL to lock, the FLL bypass mode is set to \ref CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 1576 * After the FLL is locked, the FLL bypass mdoe is then set to \ref CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT. 1577 * 1578 * \note 1579 * Call \ref SystemCoreClockUpdate after calling this function 1580 * if it affects the CLK_HF0 frequency. 1581 * 1582 * \note 1583 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1584 * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 1585 * 1586 * \funcusage 1587 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable 1588 * 1589 *******************************************************************************/ 1590 cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus); 1591 1592 1593 /******************************************************************************* 1594 * Function Name: Cy_SysClk_FllIsEnabled 1595 ****************************************************************************//** 1596 * 1597 * Reports whether or not the FLL is enabled. 1598 * 1599 * \return 1600 * false = disabled \n 1601 * true = enabled 1602 * 1603 * \funcusage 1604 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable 1605 * 1606 *******************************************************************************/ 1607 bool Cy_SysClk_FllIsEnabled(void); 1608 1609 1610 /******************************************************************************* 1611 * Function Name: Cy_SysClk_FllLocked 1612 ****************************************************************************//** 1613 * 1614 * Reports whether the FLL is locked first time during FLL starting. 1615 * Intended to be used with \ref Cy_SysClk_FllEnable with zero timeout. 1616 * 1617 * \return 1618 * false = not locked \n 1619 * true = locked 1620 * 1621 * \note 1622 * The unlock occurrence may appear during FLL normal operation, so this function 1623 * is not recommended to check the FLL normal operation stability. 1624 * 1625 * \funcusage 1626 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllLocked 1627 * 1628 *******************************************************************************/ 1629 bool Cy_SysClk_FllLocked(void); 1630 1631 1632 /******************************************************************************* 1633 * Function Name: Cy_SysClk_FllDisable 1634 ****************************************************************************//** 1635 * 1636 * Disables the FLL and the CCO. 1637 * 1638 * \return \ref cy_en_sysclk_status_t 1639 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1640 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1641 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1642 * uses the PRA driver to change the protected registers. Refer to 1643 * \ref cy_en_pra_status_t for more details. 1644 * 1645 * \note 1646 * Call \ref SystemCoreClockUpdate after this function calling 1647 * if it affects the CLK_HF0 frequency. 1648 * 1649 * \note 1650 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1651 * the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 1652 * 1653 * \funcusage 1654 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllDisable 1655 * 1656 *******************************************************************************/ 1657 cy_en_sysclk_status_t Cy_SysClk_FllDisable(void); 1658 1659 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) 1660 1661 /******************************************************************************* 1662 * Function Name: Cy_SysClk_FllOutputDividerEnable 1663 ****************************************************************************//** 1664 * 1665 * Enables/Disables the FLL output divider 1666 * 1667 * \param enable 1668 * 1669 *******************************************************************************/ 1670 void Cy_SysClk_FllOutputDividerEnable(bool enable); 1671 #endif 1672 1673 /******************************************************************************* 1674 * Function Name: Cy_SysClk_FllGetFrequency 1675 ****************************************************************************//** 1676 * 1677 * Returns the output frequency of the FLL. 1678 * 1679 * \return The output frequency of FLL. 1680 * 1681 * \note If the return value equals zero, that means FLL is disabled. 1682 * 1683 * \funcusage 1684 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllGetFrequency 1685 * 1686 *******************************************************************************/ 1687 uint32_t Cy_SysClk_FllGetFrequency(void); 1688 /** \} group_sysclk_fll_funcs */ 1689 1690 1691 /* ========================================================================== */ 1692 /* =========================== PLL SECTION ============================ */ 1693 /* ========================================================================== */ 1694 1695 1696 /** 1697 * \addtogroup group_sysclk_pll_structs 1698 * \{ 1699 */ 1700 /** Structure containing information for configuration of a PLL. 1701 */ 1702 typedef struct 1703 { 1704 uint32_t inputFreq; /**< frequency of PLL source, in Hz */ 1705 uint32_t outputFreq; /**< frequency of PLL output, in Hz */ 1706 bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 1707 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ 1708 } cy_stc_pll_config_t; 1709 1710 1711 /** Structure containing information for manual configuration of a PLL. 1712 */ 1713 typedef struct 1714 { 1715 uint8_t feedbackDiv; /**< CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ 1716 uint8_t referenceDiv; /**< CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ 1717 uint8_t outputDiv; /**< CLK_PLL_CONFIG register, OUTPUT_DIV bits */ 1718 bool lfMode; /**< CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 1719 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_PLL_CONFIG register, BYPASS_SEL bits */ 1720 } cy_stc_pll_manual_config_t; 1721 /** \} group_sysclk_pll_structs */ 1722 1723 #if (defined(CY_DEVICE_SECURE)) 1724 1725 /** PRA structure for Cy_SysClk_PllManualConfigure function parameters */ 1726 typedef struct 1727 { 1728 uint32_t clkPath; /**< clkPath */ 1729 cy_stc_pll_manual_config_t *praConfig; /**< config */ 1730 } cy_stc_pra_clk_pll_manconfigure_t; 1731 #endif /* (defined(CY_DEVICE_SECURE)) */ 1732 1733 /** 1734 * \addtogroup group_sysclk_pll_funcs 1735 * \{ 1736 *//******************************************************************************* 1737 * Function Name: Cy_SysClk_PllConfigure 1738 ****************************************************************************//** 1739 * 1740 * Configures a given PLL. 1741 * The configuration formula used is: 1742 * Fout = pll_clk * (P / Q / div_out), where: 1743 * Fout is the desired output frequency 1744 * pll_clk is the frequency of the input source 1745 * P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. 1746 * Q is the reference divider. Its value is in bitfield REFERENCE_DIV. 1747 * div_out is the reference divider. Its value is in bitfield OUTPUT_DIV. 1748 * 1749 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. 1750 * 1751 * \param config \ref cy_stc_pll_config_t 1752 * 1753 * \return Error / status code: \n 1754 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 1755 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled \n 1756 * CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range 1757 * 1758 * \note 1759 * Call this function after changing the PLL input frequency, for example if 1760 * \ref Cy_SysClk_ClkPathSetSource() is called. 1761 * 1762 * \note 1763 * Do not call this function when the PLL is enabled. If it is called, then this function 1764 * returns immediately with an error return value and no register updates. 1765 * 1766 * \note 1767 * Call \ref SystemCoreClockUpdate after this function calling 1768 * if it affects the CLK_HF0 frequency. 1769 * 1770 * \note 1771 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1772 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 1773 * 1774 * \note 1775 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1776 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 1777 * 1778 * \note 1779 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1780 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 1781 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 1782 * 1783 * \funcusage 1784 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllConfigure 1785 * 1786 *******************************************************************************/ 1787 cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config); 1788 1789 1790 /******************************************************************************* 1791 * Function Name: Cy_SysClk_PllManualConfigure 1792 ****************************************************************************//** 1793 * 1794 * Manually configures a PLL based on user inputs. 1795 * 1796 * \param clkPath Selects which PLL to configure. 1 is the first PLL; 0 is invalid. 1797 * 1798 * \param config \ref cy_stc_pll_manual_config_t 1799 * 1800 * \return Error / status code: \n 1801 * CY_SYSCLK_SUCCESS - PLL successfully configured \n 1802 * CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled \n 1803 * CY_SYSCLK_BAD_PARAM - invalid clock path number 1804 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1805 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1806 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1807 * uses the PRA driver to change the protected registers. Refer to 1808 * \ref cy_en_pra_status_t for more details. 1809 * 1810 * \note 1811 * Call this function after changing the PLL input frequency; for example if 1812 * \ref Cy_SysClk_ClkPathSetSource() is called. 1813 * 1814 * \note 1815 * Do not call this function when the PLL is enabled. If it is called, then this function 1816 * returns immediately with an error return value and no register updates. 1817 * 1818 * \note 1819 * Call \ref SystemCoreClockUpdate after this function calling 1820 * if it affects the CLK_HF0 frequency. 1821 * 1822 * \note 1823 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1824 * the PLL is the source of CLK_HF0 and the PLL frequency is increasing. 1825 * 1826 * \note 1827 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1828 * the PLL is the source of CLK_HF0 and the PLL frequency is decreasing. 1829 * 1830 * \note 1831 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1832 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 1833 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 1834 * 1835 * \funcusage 1836 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllManualConfigure 1837 * 1838 *******************************************************************************/ 1839 cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config); 1840 1841 1842 /******************************************************************************* 1843 * Function Name: Cy_SysClk_PllGetConfiguration 1844 ****************************************************************************//** 1845 * 1846 * Reports configuration settings for a PLL. 1847 * 1848 * \param clkPath Selects which PLL to report. 1 is the first PLL; 0 is invalid. 1849 * 1850 * \param config \ref cy_stc_pll_manual_config_t 1851 * 1852 * \return Error / status code: \n 1853 * CY_SYSCLK_SUCCESS - PLL data successfully reported \n 1854 * CY_SYSCLK_BAD_PARAM - invalid clock path number 1855 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1856 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1857 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1858 * uses the PRA driver to change the protected registers. Refer to 1859 * \ref cy_en_pra_status_t for more details. 1860 * 1861 * \note 1862 * On PSoC 64 devices the configuration on the PRA driver will be reflected 1863 * after \ref Cy_SysClk_PllEnable call. Any call to \ref Cy_SysClk_PllGetConfiguration 1864 * before calling \ref Cy_SysClk_PllEnable returns old configuration values. 1865 * 1866 * \funcusage 1867 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetConfiguration 1868 * 1869 *******************************************************************************/ 1870 cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config); 1871 1872 1873 /******************************************************************************* 1874 * Function Name: Cy_SysClk_PllEnable 1875 ****************************************************************************//** 1876 * 1877 * Enables the PLL. The PLL should be configured before calling this function. 1878 * 1879 * \param clkPath Selects which PLL to enable. 1 is the first PLL; 0 is invalid. 1880 * 1881 * \param timeoutus amount of time in microseconds to wait for the PLL to lock. 1882 * If the lock doesn't occur, PLL is stopped. To avoid waiting for lock, set this to 0 1883 * and manually check for lock using \ref Cy_SysClk_PllLocked. 1884 * 1885 * \return Error / status code: \n 1886 * CY_SYSCLK_SUCCESS - PLL successfully enabled \n 1887 * CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock \n 1888 * CY_SYSCLK_BAD_PARAM - invalid clock path number 1889 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1890 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1891 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1892 * uses the PRA driver to change the protected registers. Refer to 1893 * \ref cy_en_pra_status_t for more details. 1894 * 1895 * \note 1896 * Call \ref SystemCoreClockUpdate after this function calling 1897 * if it affects the CLK_HF0 frequency. 1898 * 1899 * \note 1900 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1901 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 1902 * 1903 * \note 1904 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1905 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 1906 * 1907 * \funcusage 1908 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllEnable 1909 * 1910 *******************************************************************************/ 1911 cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus); 1912 1913 1914 /******************************************************************************* 1915 * Function Name: Cy_SysClk_PllIsEnabled 1916 ****************************************************************************//** 1917 * 1918 * Reports whether or not the selected PLL is enabled. 1919 * 1920 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 1921 * 1922 * \return 1923 * false = disabled \n 1924 * true = enabled 1925 * 1926 * \funcusage 1927 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable 1928 * 1929 *******************************************************************************/ 1930 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath); 1931 1932 1933 /******************************************************************************* 1934 * Function Name: Cy_SysClk_PllLocked 1935 ****************************************************************************//** 1936 * 1937 * Reports whether or not the selected PLL is locked. 1938 * 1939 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 1940 * 1941 * \return 1942 * false = not locked \n 1943 * true = locked 1944 * 1945 * \funcusage 1946 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLocked 1947 * 1948 *******************************************************************************/ 1949 bool Cy_SysClk_PllLocked(uint32_t clkPath); 1950 1951 1952 /******************************************************************************* 1953 * Function Name: Cy_SysClk_PllLostLock 1954 ****************************************************************************//** 1955 * 1956 * Reports whether or not the selected PLL lost its lock since the last time this 1957 * function was called. Clears the lost lock indicator. 1958 * 1959 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid. 1960 * 1961 * \return 1962 * false = did not lose lock \n 1963 * true = lost lock 1964 * 1965 * \funcusage 1966 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllLostLock 1967 * 1968 *******************************************************************************/ 1969 bool Cy_SysClk_PllLostLock(uint32_t clkPath); 1970 1971 1972 /******************************************************************************* 1973 * Function Name: Cy_SysClk_PllDisable 1974 ****************************************************************************//** 1975 * 1976 * Disables the selected PLL. 1977 * 1978 * \param clkPath Selects which PLL to disable. 1 is the first PLL; 0 is invalid. 1979 * 1980 * \return Error / status code: \n 1981 * CY_SYSCLK_SUCCESS - PLL successfully disabled \n 1982 * CY_SYSCLK_BAD_PARAM - invalid clock path number 1983 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 1984 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 1985 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 1986 * uses the PRA driver to change the protected registers. Refer to 1987 * \ref cy_en_pra_status_t for more details. 1988 * 1989 * \note 1990 * Call \ref SystemCoreClockUpdate after this function calling 1991 * if it affects the CLK_HF0 frequency. 1992 * 1993 * \note 1994 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 1995 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing. 1996 * 1997 * \note 1998 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 1999 * the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing. 2000 * 2001 * \sideeffect 2002 * This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. 2003 * If AUTO mode should be used, call \ref Cy_SysClk_PllConfigure or 2004 * \ref Cy_SysClk_PllManualConfigure before calling \ref Cy_SysClk_PllEnable. 2005 * 2006 * \funcusage 2007 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllDisable 2008 * 2009 *******************************************************************************/ 2010 cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath); 2011 2012 /******************************************************************************* 2013 * Function Name: Cy_SysClk_PllGetFrequency 2014 ****************************************************************************//** 2015 * 2016 * Returns the output frequency of the PLL. 2017 * 2018 * \param clkPath Selects which PLL to check. 1 is the first PLL; 0 is invalid 2019 * 2020 * \return The output frequency of the path PLL. 2021 * 2022 * \note If the return value equals zero, that means PLL is disabled. 2023 * 2024 * \funcusage 2025 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PllGetFrequency 2026 * 2027 *******************************************************************************/ 2028 uint32_t Cy_SysClk_PllGetFrequency(uint32_t clkPath); 2029 /** \} group_sysclk_pll_funcs */ 2030 2031 2032 #if defined (CY_IP_MXS40SSRSS) 2033 /* ========================================================================== */ 2034 /* =========================== IHO SECTION ============================ */ 2035 /* ========================================================================== */ 2036 2037 /** 2038 * \addtogroup group_sysclk_iho_funcs 2039 * \{ 2040 */ 2041 2042 2043 /******************************************************************************* 2044 * Function Name: Cy_SysClk_IhoEnable 2045 ****************************************************************************//** 2046 * 2047 * Enables the IHO. 2048 * 2049 * \note 2050 * Call \ref SystemCoreClockUpdate after this function calling 2051 * if it affects the CLK_HF0 frequency. 2052 * 2053 * \note 2054 * This API is available for devices having MXS40SSRSS IP. 2055 * 2056 *******************************************************************************/ 2057 void Cy_SysClk_IhoEnable(void); 2058 2059 2060 /******************************************************************************* 2061 * Function Name: Cy_SysClk_IhoIsEnabled 2062 ****************************************************************************//** 2063 * 2064 * Reports whether or not the selected IHO is enabled. 2065 * 2066 * \return 2067 * false = disabled \n 2068 * true = enabled 2069 * 2070 * \note 2071 * This API is available for devices having MXS40SSRSS IP. 2072 * 2073 *******************************************************************************/ 2074 bool Cy_SysClk_IhoIsEnabled(void); 2075 2076 /******************************************************************************* 2077 * Function Name: Cy_SysClk_IhoDisable 2078 ****************************************************************************//** 2079 * 2080 * Disables IHO. 2081 * 2082 * \note 2083 * Call \ref SystemCoreClockUpdate after this function calling 2084 * if it affects the CLK_HF0 frequency. 2085 * 2086 * \note 2087 * This API is available for devices having MXS40SSRSS IP. 2088 * 2089 *******************************************************************************/ 2090 void Cy_SysClk_IhoDisable(void); 2091 /** \} group_sysclk_iho_funcs */ 2092 #endif /* MXS40SSRSS */ 2093 2094 2095 /* ========================================================================== */ 2096 /* =========================== ILO SECTION ============================ */ 2097 /* ========================================================================== */ 2098 /** 2099 * \addtogroup group_sysclk_ilo_funcs 2100 * \{ 2101 */ 2102 2103 /******************************************************************************* 2104 * Function Name: Cy_SysClk_IloEnable 2105 ****************************************************************************//** 2106 * 2107 * Enables the ILO. 2108 * 2109 * \note The watchdog timer (WDT) must be unlocked before calling this function. 2110 * 2111 * \funcusage 2112 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloEnable 2113 * 2114 *******************************************************************************/ 2115 void Cy_SysClk_IloEnable(void); 2116 2117 2118 /******************************************************************************* 2119 * Function Name: Cy_SysClk_IloIsEnabled 2120 ****************************************************************************//** 2121 * 2122 * Reports the Enabled/Disabled status of the ILO. 2123 * 2124 * \return Boolean status of ILO: true - Enabled, false - Disabled. 2125 * 2126 * \funcusage 2127 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable 2128 * 2129 * \note 2130 * This API is available for CAT1A devices. 2131 * 2132 *******************************************************************************/ 2133 bool Cy_SysClk_IloIsEnabled(void); 2134 2135 2136 /******************************************************************************* 2137 * Function Name: Cy_SysClk_IloDisable 2138 ****************************************************************************//** 2139 * 2140 * Disables the ILO. ILO can't be disabled if WDT is enabled. 2141 * 2142 * \return Error / status code: \n 2143 * CY_SYSCLK_SUCCESS - ILO successfully disabled \n 2144 * CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. 2145 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2146 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2147 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2148 * uses the PRA driver to change the protected registers. Refer to 2149 * \ref cy_en_pra_status_t for more details. 2150 * 2151 * \note The watchdog timer (WDT) must be unlocked before calling this function. 2152 * Do not call this function if the WDT is enabled, because the WDT is clocked by 2153 * the ILO. 2154 * 2155 * \funcusage 2156 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable 2157 * 2158 *******************************************************************************/ 2159 cy_en_sysclk_status_t Cy_SysClk_IloDisable(void); 2160 2161 2162 /******************************************************************************* 2163 * Function Name: Cy_SysClk_IloHibernateOn 2164 ****************************************************************************//** 2165 * 2166 * Controls whether the ILO stays on during a hibernate, or through an XRES or 2167 * brown-out detect (BOD) event. 2168 * 2169 * \param on 2170 * true = ILO stays on during hibernate or across XRES/BOD. \n 2171 * false = ILO turns off for hibernate or XRES/BOD. 2172 * 2173 * \note Writes to the register/bit are ignored if the watchdog (WDT) is locked. 2174 * 2175 * \funcusage 2176 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloHibernateOn 2177 * 2178 *******************************************************************************/ 2179 void Cy_SysClk_IloHibernateOn(bool on); 2180 /** \} group_sysclk_ilo_funcs */ 2181 2182 2183 /* ========================================================================== */ 2184 /* =========================== PILO SECTION =========================== */ 2185 /* ========================================================================== */ 2186 /** 2187 * \addtogroup group_sysclk_pilo_funcs 2188 * \{ 2189 */ 2190 /******************************************************************************* 2191 * Function Name: Cy_SysClk_PiloEnable 2192 ****************************************************************************//** 2193 * 2194 * Enables the PILO. 2195 * 2196 * \note This function blocks for 1 millisecond between enabling the PILO and 2197 * releasing the PILO reset. 2198 * 2199 * \funcusage 2200 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloEnable 2201 * 2202 *******************************************************************************/ 2203 void Cy_SysClk_PiloEnable(void); 2204 2205 2206 /******************************************************************************* 2207 * Function Name: Cy_SysClk_PiloIsEnabled 2208 ****************************************************************************//** 2209 * 2210 * Reports the Enabled/Disabled status of the PILO. 2211 * 2212 * \return Boolean status of PILO: true - Enabled, false - Disabled. 2213 * 2214 * \funcusage 2215 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable 2216 * 2217 * \note 2218 * This API is available for CAT1A devices. 2219 * 2220 *******************************************************************************/ 2221 bool Cy_SysClk_PiloIsEnabled(void); 2222 2223 2224 /******************************************************************************* 2225 * Function Name: Cy_SysClk_PiloDisable 2226 ****************************************************************************//** 2227 * 2228 * Disables the PILO. 2229 * 2230 * \funcusage 2231 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable 2232 * 2233 *******************************************************************************/ 2234 void Cy_SysClk_PiloDisable(void); 2235 2236 2237 /******************************************************************************* 2238 * Function Name: Cy_SysClk_PiloSetTrim 2239 ****************************************************************************//** 2240 * 2241 * Sets the PILO trim bits, which adjusts the PILO frequency. This is typically 2242 * done after measuring the PILO frequency; see \ref Cy_SysClk_StartClkMeasurementCounters(). 2243 * 2244 * \funcusage 2245 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim 2246 * 2247 *******************************************************************************/ 2248 void Cy_SysClk_PiloSetTrim(uint32_t trimVal); 2249 2250 2251 /******************************************************************************* 2252 * Function Name: Cy_SysClk_PiloGetTrim 2253 ****************************************************************************//** 2254 * 2255 * Reports the current PILO trim bits value. 2256 * 2257 * \funcusage 2258 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim 2259 * 2260 *******************************************************************************/ 2261 uint32_t Cy_SysClk_PiloGetTrim(void); 2262 /** \} group_sysclk_pilo_funcs */ 2263 2264 2265 /* ========================================================================== */ 2266 /* ========================== ALTHF SECTION =========================== */ 2267 /* ========================================================================== */ 2268 /** 2269 * \addtogroup group_sysclk_alt_hf_funcs 2270 * \{ 2271 */ 2272 2273 /******************************************************************************* 2274 * Function Name: Cy_SysClk_AltHfGetFrequency 2275 ****************************************************************************//** 2276 * 2277 * Reports the frequency of the Alternative High-Frequency Clock 2278 * 2279 * \funcusage 2280 * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() 2281 * 2282 *******************************************************************************/ 2283 uint32_t Cy_SysClk_AltHfGetFrequency(void); 2284 /** \} group_sysclk_alt_hf_funcs */ 2285 2286 2287 /* ========================================================================== */ 2288 /* ========================== ALTLF SECTION =========================== */ 2289 /* ========================================================================== */ 2290 /** \cond For future usage */ 2291 uint32_t Cy_SysClk_AltLfGetFrequency(void); 2292 bool Cy_SysClk_AltLfIsEnabled(void); 2293 /** \endcond */ 2294 2295 2296 /* ========================================================================== */ 2297 /* ==================== CLOCK MEASUREMENT SECTION ===================== */ 2298 /* ========================================================================== */ 2299 /** 2300 * \addtogroup group_sysclk_calclk_enums 2301 * \{ 2302 */ 2303 /** Defines all possible clock sources */ 2304 typedef enum 2305 { 2306 CY_SYSCLK_MEAS_CLK_NC = 0U, 2307 CY_SYSCLK_MEAS_CLK_ILO = 1U, 2308 CY_SYSCLK_MEAS_CLK_WCO = 2U, 2309 CY_SYSCLK_MEAS_CLK_BAK = 3U, 2310 CY_SYSCLK_MEAS_CLK_ALTLF = 4U, 2311 CY_SYSCLK_MEAS_CLK_LFCLK = 5U, 2312 CY_SYSCLK_MEAS_CLK_IMO = 6U, 2313 CY_SYSCLK_MEAS_CLK_SLPCTRL = 7U, 2314 CY_SYSCLK_MEAS_CLK_PILO = 8U, 2315 CY_SYSCLK_MEAS_CLK_ILO1 = 9U, 2316 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER = 10U, 2317 CY_SYSCLK_MEAS_CLK_LPECO = 11U, 2318 CY_SYSCLK_MEAS_CLK_LPECO_PRESCALER = 12U, 2319 CY_SYSCLK_MEAS_CLK_MFO = 13U, 2320 CY_SYSCLK_MEAS_CLK_FAST_CLKS = 0x100U, 2321 CY_SYSCLK_MEAS_CLK_ECO = 0x101U, 2322 CY_SYSCLK_MEAS_CLK_EXT = 0x102U, 2323 CY_SYSCLK_MEAS_CLK_ALTHF = 0x103U, 2324 CY_SYSCLK_MEAS_CLK_TIMERCLK = 0x104U, 2325 CY_SYSCLK_MEAS_CLK_IHO = 0x108U, 2326 CY_SYSCLK_MEAS_CLK_PWR = 0x109U, 2327 CY_SYSCLK_MEAS_CLK_PATH_CLKS = 0x500U, 2328 CY_SYSCLK_MEAS_CLK_PATH0 = 0x500U, 2329 CY_SYSCLK_MEAS_CLK_PATH1 = 0x501U, 2330 CY_SYSCLK_MEAS_CLK_PATH2 = 0x502U, 2331 CY_SYSCLK_MEAS_CLK_PATH3 = 0x503U, 2332 CY_SYSCLK_MEAS_CLK_PATH4 = 0x504U, 2333 CY_SYSCLK_MEAS_CLK_PATH5 = 0x505U, 2334 CY_SYSCLK_MEAS_CLK_PATH6 = 0x506U, 2335 CY_SYSCLK_MEAS_CLK_PATH7 = 0x507U, 2336 CY_SYSCLK_MEAS_CLK_PATH8 = 0x508U, 2337 CY_SYSCLK_MEAS_CLK_PATH9 = 0x509U, 2338 CY_SYSCLK_MEAS_CLK_PATH10 = 0x50AU, 2339 CY_SYSCLK_MEAS_CLK_PATH11 = 0x50BU, 2340 CY_SYSCLK_MEAS_CLK_PATH12 = 0x50CU, 2341 CY_SYSCLK_MEAS_CLK_PATH13 = 0x50DU, 2342 CY_SYSCLK_MEAS_CLK_PATH14 = 0x50EU, 2343 CY_SYSCLK_MEAS_CLK_PATH15 = 0x50FU, 2344 CY_SYSCLK_MEAS_CLK_CLKHFS = 0x600U, 2345 CY_SYSCLK_MEAS_CLK_CLKHF0 = 0x600U, 2346 CY_SYSCLK_MEAS_CLK_CLKHF1 = 0x601U, 2347 CY_SYSCLK_MEAS_CLK_CLKHF2 = 0x602U, 2348 CY_SYSCLK_MEAS_CLK_CLKHF3 = 0x603U, 2349 CY_SYSCLK_MEAS_CLK_CLKHF4 = 0x604U, 2350 CY_SYSCLK_MEAS_CLK_CLKHF5 = 0x605U, 2351 CY_SYSCLK_MEAS_CLK_CLKHF6 = 0x606U, 2352 CY_SYSCLK_MEAS_CLK_CLKHF7 = 0x607U, 2353 CY_SYSCLK_MEAS_CLK_CLKHF8 = 0x608U, 2354 CY_SYSCLK_MEAS_CLK_CLKHF9 = 0x609U, 2355 CY_SYSCLK_MEAS_CLK_CLKHF10 = 0x60AU, 2356 CY_SYSCLK_MEAS_CLK_CLKHF11 = 0x60BU, 2357 CY_SYSCLK_MEAS_CLK_CLKHF12 = 0x60CU, 2358 CY_SYSCLK_MEAS_CLK_CLKHF13 = 0x60DU, 2359 CY_SYSCLK_MEAS_CLK_CLKHF14 = 0x60EU, 2360 CY_SYSCLK_MEAS_CLK_CLKHF15 = 0x60FU, 2361 CY_SYSCLK_MEAS_CLK_LAST_CLK = 0x610U 2362 } cy_en_meas_clks_t; 2363 /** \} group_sysclk_calclk_enums */ 2364 2365 /** 2366 * \addtogroup group_sysclk_calclk_structs 2367 * \{ 2368 */ 2369 #if (defined(CY_DEVICE_SECURE)) 2370 /** PRA structure for Cy_SysClk_StartClkMeasurementCounters function parameters */ 2371 typedef struct 2372 { 2373 cy_en_meas_clks_t clock1; /**< clock1 */ 2374 uint32_t count1; /**< count */ 2375 cy_en_meas_clks_t clock2; /**< clock2 */ 2376 } cy_stc_pra_start_clk_measurement_t; 2377 2378 #endif /* (defined(CY_DEVICE_SECURE)) */ 2379 /** \} group_sysclk_calclk_structs */ 2380 2381 /** 2382 * \addtogroup group_sysclk_calclk_funcs 2383 * \{ 2384 */ 2385 /******************************************************************************* 2386 * Function Name: Cy_SysClk_StartClkMeasurementCounters 2387 ****************************************************************************//** 2388 * 2389 * Assigns clocks to the clock measurement counters, and starts counting. The counters 2390 * let you measure a clock frequency using another clock as a reference. There are two 2391 * counters. 2392 * 2393 * - One counter (counter1), which is clocked by clock1, is loaded with an initial 2394 * value and counts down to zero. 2395 * - The second counter (counter2), which is clocked by clock2, counts up until 2396 * the first counter reaches zero. 2397 * 2398 * Either clock1 or clock2 can be a reference clock; the other clock becomes the 2399 * measured clock. The reference clock frequency is always known. \n 2400 * After calling this function, call \ref Cy_SysClk_ClkMeasurementCountersDone() 2401 * to determine when counting is done; that is, counter1 has counted down to zero. 2402 * Then call \ref Cy_SysClk_ClkMeasurementCountersGetFreq() to calculate the frequency 2403 * of the measured clock. 2404 * 2405 * \param clock1 The clock for counter1 2406 * 2407 * \param count1 The initial value for counter1, from which counter1 counts down to zero. 2408 * 2409 * \param clock2 The clock for counter2 2410 * 2411 * \return Error / status code: \n 2412 * CY_SYSCLK_INVALID_STATE if already doing a measurement \n 2413 * CY_SYSCLK_BAD_PARAM if invalid clock input parameter \n 2414 * else CY_SYSCLK_SUCCESS 2415 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2416 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2417 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2418 * uses the PRA driver to change the protected registers. Refer to 2419 * \ref cy_en_pra_status_t for more details. 2420 * 2421 * \note The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF. 2422 * If clock2 frequency is greater than clock1, make sure that count1 is low enough 2423 * that counter2 does not overflow before counter1 reaches zero. 2424 * \note The time to complete a measurement is count1 / clock1 frequency. 2425 * \note The clocks for both counters must have a nonzero frequency, or 2426 * \ref Cy_SysClk_ClkMeasurementCountersGetFreq() incorrectly reports the result of the 2427 * previous measurement. 2428 * \note Do not enter a device low power mode (Sleep, Deep Sleep) while doing a measurement; 2429 * the measured clock frequency may not be accurate. 2430 * 2431 * \funcusage 2432 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_StartClkMeasurementCounters 2433 * 2434 *******************************************************************************/ 2435 cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2); 2436 2437 2438 /******************************************************************************* 2439 * Function Name: Cy_SysClk_ClkMeasurementCountersGetFreq 2440 ****************************************************************************//** 2441 * 2442 * Calculates the frequency of the indicated measured clock (clock1 or clock2). 2443 * - If clock1 is the measured clock, its frequency is: clock1 frequency = (count1 / count2) * clock2 frequency 2444 * - If clock2 is the measured clock, its frequency is: clock2 frequency = (count2 / count1) * clock1 frequency 2445 * 2446 * Call this function only after counting is done; see \ref Cy_SysClk_ClkMeasurementCountersDone(). 2447 * 2448 * \param measuredClock False (0) if the measured clock is clock1; true (1) 2449 * if the measured clock is clock2. 2450 * 2451 * \param refClkFreq The reference clock frequency (clock1 or clock2). 2452 * 2453 * \return The frequency of the measured clock, in Hz. 2454 * \warning The function returns zero, if during measurement device was in the 2455 * Deep Sleep or partially blocking flash operation occurred. It means that 2456 * current measurement is not valid and you should call the 2457 * Cy_SysClk_StartClkMeasurementCounters() function once again. 2458 * 2459 * \funcusage 2460 * Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage. 2461 * 2462 *******************************************************************************/ 2463 uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq); 2464 2465 2466 /******************************************************************************* 2467 * Function Name: Cy_SysClk_ClkMeasurementCountersDone 2468 ****************************************************************************//** 2469 * 2470 * Checks if clock measurement counting is done, that is, counter1 has counted down 2471 * to zero. Call \ref Cy_SysClk_StartClkMeasurementCounters() before calling this function. 2472 * 2473 * \return Status of calibration counters: \n 2474 * true = done \n 2475 * false = not done 2476 * 2477 * \funcusage 2478 * Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage. 2479 * 2480 *******************************************************************************/ 2481 bool Cy_SysClk_ClkMeasurementCountersDone(void); 2482 /** \} group_sysclk_calclk_funcs */ 2483 2484 2485 /* ========================================================================== */ 2486 /* ========================== TRIM SECTION ============================ */ 2487 /* ========================================================================== */ 2488 /** 2489 * \addtogroup group_sysclk_trim_funcs 2490 * \{ 2491 */ 2492 2493 2494 /******************************************************************************* 2495 * Function Name: Cy_SysClk_IloTrim 2496 ****************************************************************************//** 2497 * 2498 * Trims the ILO to be as close to 32,768 Hz as possible. 2499 * 2500 * \param iloFreq current ILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters 2501 * and other measurement functions to obtain the current frequency of the ILO. 2502 * 2503 * \return Change in trim value - 0 if done; that is, no change in trim value. 2504 * 2505 * \note The watchdog timer (WDT) must be unlocked before calling this function. 2506 * 2507 * \funcusage 2508 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloTrim 2509 * 2510 *******************************************************************************/ 2511 int32_t Cy_SysClk_IloTrim(uint32_t iloFreq); 2512 2513 2514 /******************************************************************************* 2515 * Function Name: Cy_SysClk_PiloTrim 2516 ****************************************************************************//** 2517 * 2518 * Trims the PILO to be as close to 32,768 Hz as possible. 2519 * 2520 * \param piloFreq current PILO frequency. Call \ref Cy_SysClk_StartClkMeasurementCounters 2521 * and other measurement functions to obtain the current frequency of the PILO. 2522 * 2523 * \return Change in trim value; 0 if done, that is, no change in trim value. 2524 * 2525 * \funcusage 2526 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloTrim 2527 * 2528 *******************************************************************************/ 2529 int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq); 2530 2531 /******************************************************************************* 2532 * Function Name: Cy_SysClk_PiloInitialTrim 2533 ****************************************************************************//** 2534 * 2535 * Initial trims the PILO to be as close to 32,768 Hz as possible. 2536 * This function takes ECO ALTHF as reference clock and calculate Fine PILO 2537 * frequency trimming, by using binary search algorithm. 2538 * 2539 * This function requires configured BLE ECO ALTHF clock. 2540 * Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock. 2541 * 2542 * \note 2543 * This function must be call after every power-up. 2544 * 2545 * \note 2546 * The function is applicable only for a PSoC 6 BLE devices. 2547 * 2548 * \funcusage 2549 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloInitialTrimAndUpdateTrimStep 2550 * 2551 *******************************************************************************/ 2552 void Cy_SysClk_PiloInitialTrim(void); 2553 2554 /******************************************************************************* 2555 * Function Name: Cy_SysClk_PiloUpdateTrimStep 2556 ****************************************************************************//** 2557 * 2558 * Calculates and updates the PILO trim step size (stepSize variable). 2559 * The stepSize value is used by \ref Cy_SysClk_PiloTrim function during periodical 2560 * PILO calibration. 2561 * 2562 * This function requires configured BLE ECO ALTHF clock. 2563 * Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock. 2564 * 2565 * \note 2566 * This function must be call after every power-up after call of 2567 * \ref Cy_SysClk_PiloInitialTrim function. 2568 * 2569 * \note 2570 * To achieve best trimming results it is recommended to configure BLE ECO ALTHF 2571 * reference clock to 16 MHz. 2572 * 2573 * \note 2574 * The function is applicable only for a PSoC 6 BLE devices. 2575 * 2576 * \funcusage 2577 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloInitialTrimAndUpdateTrimStep 2578 * 2579 *******************************************************************************/ 2580 void Cy_SysClk_PiloUpdateTrimStep(void); 2581 /** \} group_sysclk_trim_funcs */ 2582 2583 2584 /* ========================================================================== */ 2585 /* ====================== POWER MANAGEMENT SECTION ==================== */ 2586 /* ========================================================================== */ 2587 /** 2588 * \addtogroup group_sysclk_pm_funcs 2589 * \{ 2590 */ 2591 /******************************************************************************* 2592 * Function Name: Cy_SysClk_DeepSleepCallback 2593 ****************************************************************************//** 2594 * 2595 * Callback function to be used when entering system Deep Sleep mode. 2596 * This function is applicable if: 2597 * - The FLL is enabled 2598 * - The PLL is enabled and is driven by ECO 2599 * 2600 * This function performs the following: 2601 * 2602 * 1. Before entering Deep Sleep, the clock configuration is saved in SRAM. 2603 * If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the 2604 * source is changed to IMO. \n 2605 * If the FLL is enabled - it is just bypassed. 2606 * 2. Upon wakeup from Deep Sleep, the function waits for ECO stabilization, 2607 * then restores the configuration and waits for the FLL/PLL to regain their 2608 * frequency locks. \n 2609 * If ECO is not used and FLL is enabled - it waits for FLL lock and unbypasses it. 2610 * 2611 * The function prevents entry into Deep Sleep mode if the measurement counters 2612 * are currently counting; see \ref Cy_SysClk_StartClkMeasurementCounters. 2613 * 2614 * This function can be called during execution of \ref Cy_SysPm_CpuEnterDeepSleep. 2615 * To do so, register this function as a callback before calling 2616 * \ref Cy_SysPm_CpuEnterDeepSleep - specify \ref CY_SYSPM_DEEPSLEEP as the callback 2617 * type and call \ref Cy_SysPm_RegisterCallback. 2618 * 2619 * \note 2620 * This function is recommended to be the last callback that is registered. 2621 * Doing so minimizes the time spent on low power mode entry and exit. \n 2622 * This function implements all four SysPm callback modes \ref cy_en_syspm_callback_mode_t. 2623 * So the \ref cy_stc_syspm_callback_t::skipMode must be set to 0UL. \n 2624 * This function does not support such cases as, for example, FLL is enabled 2625 * but bypassed by user code before entering Deep Sleep. \n 2626 * You can use this callback implementation as an example to design custom low-power 2627 * callbacks for certain user application. 2628 * 2629 * \param callbackParams 2630 * structure with the syspm callback parameters, 2631 * see \ref cy_stc_syspm_callback_params_t. 2632 * 2633 * \param mode 2634 * Callback mode, see \ref cy_en_syspm_callback_mode_t 2635 * 2636 * \return Error / status code; see \ref cy_en_syspm_status_t. Pass if not doing 2637 * a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL 2638 * or PLL to get stable / regain its frequency lock. 2639 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2640 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2641 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2642 * uses the PRA driver to change the protected registers. Refer to 2643 * \ref cy_en_pra_status_t for more details. 2644 * 2645 * \funcusage 2646 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_DeepSleepCallback 2647 * 2648 *******************************************************************************/ 2649 cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams, cy_en_syspm_callback_mode_t mode); 2650 /** \} group_sysclk_pm_funcs */ 2651 2652 2653 /* ========================================================================== */ 2654 /* =========================== WCO SECTION ============================ */ 2655 /* ========================================================================== */ 2656 /** 2657 * \addtogroup group_sysclk_wco_enums 2658 * \{ 2659 */ 2660 /** WCO bypass modes */ 2661 typedef enum 2662 { 2663 CY_SYSCLK_WCO_NOT_BYPASSED = 0U, /**< WCO is not bypassed crystal is used */ 2664 CY_SYSCLK_WCO_BYPASSED = 1U /**< WCO is bypassed external clock must be supplied on XTAL pin */ 2665 } cy_en_wco_bypass_modes_t; 2666 2667 #if defined (CY_IP_MXS28SRSS) 2668 /** WCO GM Config */ 2669 /** 2670 * \note 2671 * This enum is available for CAT1B devices. 2672 **/ 2673 typedef enum 2674 { 2675 CY_SYSCLK_WCO_GM_0P5 = 0U, /**< WCO GM - 0.5x */ 2676 CY_SYSCLK_WCO_GM_1P0 = 1U, /**< WCO GM - 1.0x */ 2677 CY_SYSCLK_WCO_GM_1P5 = 2U, /**< WCO GM - 1.5x */ 2678 CY_SYSCLK_WCO_GM_2P0 = 3U, /**< WCO GM - 2.0x */ 2679 CY_SYSCLK_WCO_GM_2P5 = 4U, /**< WCO GM - 2.5x */ 2680 CY_SYSCLK_WCO_GM_3P0 = 5U, /**< WCO GM - 3.0x */ 2681 CY_SYSCLK_WCO_GM_3P5 = 6U, /**< WCO GM - 3.5x */ 2682 CY_SYSCLK_WCO_GM_4P0 = 7U, /**< WCO GM - 4.0x */ 2683 } cy_en_wco_gain_ctrl_modes_t; 2684 #endif /* CY_IP_MXS28SRSS */ 2685 2686 #if defined (CY_IP_MXS40SRSS) 2687 /** \cond BWC */ 2688 /** 2689 * \note 2690 * This enum is available for CAT1A devices. 2691 **/ 2692 typedef enum 2693 { 2694 CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, 2695 CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, 2696 CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO 2697 } cy_en_wco_csv_supervisor_clock_t; 2698 2699 #endif /* CY_IP_MXS40SRSS */ 2700 2701 2702 /** 2703 * Clock supervisor clock loss window. There must be one clock of the supervised 2704 * clock within this many clocks of the supervising clock. 2705 * See registers CLK_CSV_HF_CTL and CLK_CSV_WCO_CTL, bitfield CSV_LOSS_WINDOW. 2706 */ 2707 typedef enum 2708 { 2709 CY_SYSCLK_CSV_LOSS_4_CYCLES = 0U, /**< 1 clock must be seen within 4 cycles of the supervising clock */ 2710 CY_SYSCLK_CSV_LOSS_8_CYCLES = 1U, /**< 1 clock must be seen within 8 cycles of the supervising clock */ 2711 CY_SYSCLK_CSV_LOSS_16_CYCLES = 2U, /**< 1 clock must be seen within 16 cycles of the supervising clock */ 2712 CY_SYSCLK_CSV_LOSS_32_CYCLES = 3U, /**< 1 clock must be seen within 32 cycles of the supervising clock */ 2713 CY_SYSCLK_CSV_LOSS_64_CYCLES = 4U, /**< 1 clock must be seen within 64 cycles of the supervising clock */ 2714 CY_SYSCLK_CSV_LOSS_128_CYCLES = 5U, /**< 1 clock must be seen within 128 cycles of the supervising clock */ 2715 CY_SYSCLK_CSV_LOSS_256_CYCLES = 6U, /**< 1 clock must be seen within 256 cycles of the supervising clock */ 2716 CY_SYSCLK_CSV_LOSS_512_CYCLES = 7U /**< 1 clock must be seen within 512 cycles of the supervising clock */ 2717 } cy_en_csv_loss_window_t; 2718 2719 /** 2720 * Clock supervisor error actions. See register CLK_CSV_HF_CTL[CSV_FREQ_ACTION and CSV_LOSS_ACTION]. 2721 */ 2722 typedef enum 2723 { 2724 CY_SYSCLK_CSV_ERROR_IGNORE = 0U, /**< Ignore the error reported by the clock supervisor */ 2725 CY_SYSCLK_CSV_ERROR_FAULT = 1U, /**< Trigger a fault when an error is reported by the clock supervisor */ 2726 CY_SYSCLK_CSV_ERROR_RESET = 2U, /**< Trigger a reset when an error is reported by the clock supervisor */ 2727 CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3U /**< Trigger a fault then reset when an error is reported by the supervisor */ 2728 } cy_en_csv_error_actions_t; 2729 2730 #if defined (CY_IP_MXS28SRSS) 2731 /** WCO CSV supervisor clock selections */ 2732 /** 2733 * \note 2734 * This enum is available for CAT1B devices. 2735 **/ 2736 typedef enum 2737 { 2738 CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, /**< WCO CSV supervisor clock source is the ILO */ 2739 CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, /**< WCO CSV supervisor clock source is the alternate low-frequency clock (ALTLF) */ 2740 CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO /**< WCO CSV supervisor clock source is the PILO */ 2741 } cy_en_wco_csv_supervisor_clock_t; 2742 2743 /** \endcond */ 2744 2745 /** \} group_sysclk_wco_enums */ 2746 2747 /** \cond BWC */ 2748 2749 /** 2750 * \addtogroup group_sysclk_wco_structs 2751 * \{ 2752 */ 2753 /** 2754 * This structure is used to configure the clock supervisor for the WCO. 2755 */ 2756 /** 2757 * \note 2758 * This structure is available for CAT1B devices. 2759 **/ 2760 typedef struct 2761 { 2762 cy_en_wco_csv_supervisor_clock_t supervisorClock; /**< supervisor clock selection */ 2763 bool enableLossDetection; /**< 1= enabled, 0= disabled. Note that if loss detection is enabled, writes to other register bits are ignored */ 2764 cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ 2765 cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ 2766 } cy_stc_wco_csv_config_t; 2767 2768 #endif /* CY_IP_MXS28SRSS */ 2769 2770 /** \} group_sysclk_wco_structs */ 2771 2772 #if defined (CY_IP_MXS40SRSS) 2773 /** 2774 * \note 2775 * This structure is available for CAT1A devices. 2776 **/ 2777 typedef struct 2778 { 2779 cy_en_wco_csv_supervisor_clock_t supervisorClock; 2780 bool enableLossDetection; 2781 cy_en_csv_loss_window_t lossWindow; 2782 cy_en_csv_error_actions_t lossAction; 2783 } cy_stc_wco_csv_config_t; 2784 /** \endcond */ 2785 #endif /* CY_IP_MXS40SRSS */ 2786 2787 /** 2788 * \addtogroup group_sysclk_wco_funcs 2789 * \{ 2790 */ 2791 /******************************************************************************* 2792 * Function Name: Cy_SysClk_WcoEnable 2793 ****************************************************************************//** 2794 * 2795 * Enables the WCO. 2796 * 2797 * \param timeoutus amount of time in microseconds to wait for the WCO to be ready. 2798 * If WCO is not ready, WCO is stopped. To avoid waiting for WCO ready set this to 0, 2799 * and manually check if WCO is okay using \ref Cy_SysClk_WcoOkay. 2800 * 2801 * \return Error / status code: \n 2802 * CY_SYSCLK_SUCCESS - WCO successfully enabled \n 2803 * CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize 2804 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 2805 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 2806 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 2807 * uses the PRA driver to change the protected registers. Refer to 2808 * \ref cy_en_pra_status_t for more details. 2809 * 2810 * \funcusage 2811 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoEnable 2812 * 2813 *******************************************************************************/ 2814 cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus); 2815 2816 2817 /******************************************************************************* 2818 * Function Name: Cy_SysClk_WcoOkay 2819 ****************************************************************************//** 2820 * 2821 * Reports the status of the WCO_OK bit. 2822 * 2823 * \return 2824 * true = okay \n 2825 * false = not okay 2826 * 2827 * \funcusage 2828 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoOkay 2829 * 2830 *******************************************************************************/ 2831 bool Cy_SysClk_WcoOkay(void); 2832 2833 2834 /******************************************************************************* 2835 * Function Name: Cy_SysClk_WcoDisable 2836 ****************************************************************************//** 2837 * 2838 * Disables the WCO. 2839 * 2840 * \funcusage 2841 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoDisable 2842 * 2843 *******************************************************************************/ 2844 void Cy_SysClk_WcoDisable(void); 2845 2846 2847 #if defined (CY_IP_MXS28SRSS) 2848 /******************************************************************************* 2849 * Function Name: Cy_SysClk_WcoGainControl 2850 ****************************************************************************//** 2851 * 2852 * Sets the GM(Loop Gain Control) for WCO. 2853 * 2854 * \param gmMode \ref cy_en_wco_gain_ctrl_modes_t 2855 * 2856 * \funcusage 2857 * TBD 2858 * 2859 * \note 2860 * This API is available for CAT1B devices. 2861 * 2862 *******************************************************************************/ 2863 void Cy_SysClk_WcoGainControl(cy_en_wco_gain_ctrl_modes_t gmMode); 2864 2865 #endif /* CY_IP_MXS28SRSS */ 2866 2867 /******************************************************************************* 2868 * Function Name: Cy_SysClk_WcoBypass 2869 ****************************************************************************//** 2870 * 2871 * Sets whether the WCO is bypassed or not. If it is bypassed, then a 32-kHz clock 2872 * must be provided on the wco_out pin. 2873 * 2874 * \param bypass \ref cy_en_wco_bypass_modes_t 2875 * 2876 * \funcusage 2877 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_WcoBypass 2878 * 2879 *******************************************************************************/ 2880 void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass); 2881 /** \} group_sysclk_wco_funcs */ 2882 2883 2884 /* ========================================================================== */ 2885 /* ============================ MF SECTION ============================ */ 2886 /* ========================================================================== */ 2887 /** 2888 * \addtogroup group_sysclk_mf_funcs 2889 * \{ 2890 */ 2891 /******************************************************************************* 2892 * Function Name: Cy_SysClk_MfoEnable 2893 ****************************************************************************//** 2894 * 2895 * Enables the MFO. 2896 * 2897 * \param deepSleepEnable enables MFO operation is Deep Sleep low power mode. 2898 * 2899 * \funcusage 2900 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 2901 * 2902 *******************************************************************************/ 2903 void Cy_SysClk_MfoEnable(bool deepSleepEnable); 2904 2905 2906 /******************************************************************************* 2907 * Function Name: Cy_SysClk_MfoIsEnabled 2908 ****************************************************************************//** 2909 * 2910 * Reports whether MFO is enabled or not. 2911 * 2912 * \return 2913 * false - disabled \n 2914 * true - enabled 2915 * 2916 * \funcusage 2917 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 2918 * 2919 *******************************************************************************/ 2920 bool Cy_SysClk_MfoIsEnabled(void); 2921 2922 2923 /******************************************************************************* 2924 * Function Name: Cy_SysClk_MfoDisable 2925 ****************************************************************************//** 2926 * 2927 * Disables the MFO. 2928 * 2929 * \funcusage 2930 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 2931 * 2932 *******************************************************************************/ 2933 void Cy_SysClk_MfoDisable(void); 2934 2935 2936 /******************************************************************************* 2937 * Function Name: Cy_SysClk_ClkMfEnable 2938 ****************************************************************************//** 2939 * 2940 * Enables the CLK_MF. 2941 * 2942 * \funcusage 2943 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 2944 * 2945 *******************************************************************************/ 2946 void Cy_SysClk_ClkMfEnable(void); 2947 2948 2949 /******************************************************************************* 2950 * Function Name: Cy_SysClk_ClkMfIsEnabled 2951 ****************************************************************************//** 2952 * 2953 * Reports whether CLK_MF is enabled or not. 2954 * 2955 * \return 2956 * false - disabled \n 2957 * true - enabled 2958 * 2959 * \funcusage 2960 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 2961 * 2962 *******************************************************************************/ 2963 bool Cy_SysClk_ClkMfIsEnabled(void); 2964 2965 2966 /******************************************************************************* 2967 * Function Name: Cy_SysClk_ClkMfDisable 2968 ****************************************************************************//** 2969 * 2970 * Disables the CLK_MF. 2971 * 2972 * \funcusage 2973 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfDisable 2974 * 2975 *******************************************************************************/ 2976 void Cy_SysClk_ClkMfDisable(void); 2977 2978 2979 /** \cond internal */ 2980 #define CY_SYSCLK_MF_DIVIDER_MIN (1U) 2981 #define CY_SYSCLK_MF_DIVIDER_MAX (256U) 2982 #define CY_SYSCLK_IS_MF_DIVIDER_VALID(locDiv) ((CY_SYSCLK_MF_DIVIDER_MIN <= (locDiv)) && ((locDiv) <= CY_SYSCLK_MF_DIVIDER_MAX)) 2983 /** \endcond */ 2984 2985 2986 /******************************************************************************* 2987 * Function Name: Cy_SysClk_ClkMfSetDivider 2988 ****************************************************************************//** 2989 * 2990 * Sets the clock divider for CLK_MF. 2991 * 2992 * \pre If the CLK_MF is already enabled - it should be disabled 2993 * prior to use this function by \ref Cy_SysClk_ClkMfDisable. 2994 * 2995 * \param divider divider value between 1 and 256. 2996 * 2997 * \funcusage 2998 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 2999 * 3000 *******************************************************************************/ 3001 void Cy_SysClk_ClkMfSetDivider(uint32_t divider); 3002 3003 3004 /******************************************************************************* 3005 * Function Name: Cy_SysClk_ClkMfGetDivider 3006 ****************************************************************************//** 3007 * 3008 * Returns the clock divider of CLK_MF. 3009 * 3010 * \return divider value in range 1..256. 3011 * 3012 * \funcusage 3013 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 3014 * 3015 *******************************************************************************/ 3016 uint32_t Cy_SysClk_ClkMfGetDivider(void); 3017 3018 3019 /******************************************************************************* 3020 * Function Name: Cy_SysClk_ClkMfGetFrequency 3021 ****************************************************************************//** 3022 * 3023 * Reports the output clock signal frequency of CLK_MF. 3024 * 3025 * \return The frequency, in Hz. 3026 * 3027 * \funcusage 3028 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkMfEnable 3029 * 3030 *******************************************************************************/ 3031 uint32_t Cy_SysClk_ClkMfGetFrequency(void); 3032 /** \} group_sysclk_mf_funcs */ 3033 3034 3035 /* ========================================================================== */ 3036 /* ========================= clkHf[n] SECTION ========================= */ 3037 /* ========================================================================== */ 3038 /** 3039 * \addtogroup group_sysclk_clk_hf_enums 3040 * \{ 3041 */ 3042 /** 3043 * Selects which clkHf input, or root mux, to configure. 3044 * See CLK_ROOT_SELECT registers, bits ROOT_MUX. 3045 * Used with functions \ref Cy_SysClk_ClkHfSetSource and \ref Cy_SysClk_ClkHfGetSource. 3046 */ 3047 typedef enum 3048 { 3049 CY_SYSCLK_CLKHF_IN_CLKPATH0 = 0U, /**< clkHf input is Clock Path 0 */ 3050 CY_SYSCLK_CLKHF_IN_CLKPATH1 = 1U, /**< clkHf input is Clock Path 1 */ 3051 CY_SYSCLK_CLKHF_IN_CLKPATH2 = 2U, /**< clkHf input is Clock Path 2 */ 3052 CY_SYSCLK_CLKHF_IN_CLKPATH3 = 3U, /**< clkHf input is Clock Path 3 */ 3053 CY_SYSCLK_CLKHF_IN_CLKPATH4 = 4U, /**< clkHf input is Clock Path 4 */ 3054 CY_SYSCLK_CLKHF_IN_CLKPATH5 = 5U, /**< clkHf input is Clock Path 5 */ 3055 CY_SYSCLK_CLKHF_IN_CLKPATH6 = 6U, /**< clkHf input is Clock Path 6 */ 3056 CY_SYSCLK_CLKHF_IN_CLKPATH7 = 7U, /**< clkHf input is Clock Path 7 */ 3057 CY_SYSCLK_CLKHF_IN_CLKPATH8 = 8U, /**< clkHf input is Clock Path 8 */ 3058 CY_SYSCLK_CLKHF_IN_CLKPATH9 = 9U, /**< clkHf input is Clock Path 9 */ 3059 CY_SYSCLK_CLKHF_IN_CLKPATH10 = 10U, /**< clkHf input is Clock Path 10 */ 3060 CY_SYSCLK_CLKHF_IN_CLKPATH11 = 11U, /**< clkHf input is Clock Path 11 */ 3061 CY_SYSCLK_CLKHF_IN_CLKPATH12 = 12U, /**< clkHf input is Clock Path 12 */ 3062 CY_SYSCLK_CLKHF_IN_CLKPATH13 = 13U, /**< clkHf input is Clock Path 13 */ 3063 CY_SYSCLK_CLKHF_IN_CLKPATH14 = 14U, /**< clkHf input is Clock Path 14 */ 3064 CY_SYSCLK_CLKHF_IN_CLKPATH15 = 15U, /**< clkHf input is Clock Path 15 */ 3065 } cy_en_clkhf_in_sources_t; 3066 3067 #if defined (CY_IP_MXS28SRSS) 3068 /** 3069 * clkHf clock supervisor input sources. See register CLK_CSV_HF_CTL[CSV_MUX]. 3070 */ 3071 /** 3072 * \note 3073 * This enum is available for CAT1B devices. 3074 **/ 3075 typedef enum 3076 { 3077 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, /**< Supervising clock is the IMO */ 3078 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, /**< Supervising clock is the external clock */ 3079 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U /**< Supervising clock is clk_althf */ 3080 } cy_en_clkhf_csv_supervisor_clock_t; 3081 #endif /* CY_IP_MXS28SRSS */ 3082 3083 /** \} group_sysclk_clk_hf_enums */ 3084 3085 /** 3086 * \addtogroup group_sysclk_clk_hf_enums 3087 * \{ 3088 */ 3089 /** 3090 * clkHf divider values. See CLK_ROOT_SELECT registers, bits ROOT_DIV. 3091 * Used with functions \ref Cy_SysClk_ClkHfSetDivider and \ref Cy_SysClk_ClkHfGetDivider. 3092 */ 3093 typedef enum 3094 { 3095 CY_SYSCLK_CLKHF_NO_DIVIDE = 0U, /**< don't divide clkHf */ 3096 CY_SYSCLK_CLKHF_DIVIDE_BY_2 = 1U, /**< divide clkHf by 2 */ 3097 CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 2U, /**< divide clkHf by 4 */ 3098 CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 3U /**< divide clkHf by 8 */ 3099 } cy_en_clkhf_dividers_t; 3100 3101 /** \} group_sysclk_clk_hf_enums */ 3102 3103 #if defined (CY_IP_MXS40SRSS) 3104 /** \cond BWC */ 3105 typedef enum 3106 { 3107 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, 3108 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, 3109 CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U 3110 } cy_en_clkhf_csv_supervisor_clock_t; 3111 3112 typedef struct 3113 { 3114 cy_en_clkhf_csv_supervisor_clock_t supervisorClock; 3115 uint16_t supervisingWindow; 3116 bool enableFrequencyFaultDetection; 3117 uint16_t frequencyLowerLimit; 3118 uint16_t frequencyUpperLimit; 3119 cy_en_csv_error_actions_t frequencyAction; 3120 bool enableLossDetection; 3121 cy_en_csv_loss_window_t lossWindow; 3122 cy_en_csv_error_actions_t lossAction; 3123 } cy_stc_clkhf_csv_config_t; 3124 3125 #if (defined (CY_DEVICE_SECURE)) 3126 /** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ 3127 typedef struct 3128 { 3129 uint32_t clkHf; /**< clkHF */ 3130 cy_en_clkhf_in_sources_t source; /**< Source */ 3131 } cy_stc_pra_clkhfsetsource_t; 3132 3133 /** PRA structure for Cy_SysClk_ClkHfSetSource function parameters */ 3134 typedef struct 3135 { 3136 uint32_t clkHf; /**< clkHF */ 3137 cy_en_clkhf_dividers_t divider; /**< divider */ 3138 } cy_stc_pra_clkhfsetdivider_t; 3139 #endif /* (defined (CY_DEVICE_SECURE)) */ 3140 3141 #define altHfFreq (cy_BleEcoClockFreqHz) 3142 /** \endcond */ 3143 #endif /* CY_IP_MXS40SRSS */ 3144 3145 #if defined (CY_IP_MXS28SRSS) 3146 /** \cond BWC */ 3147 /** 3148 * \addtogroup group_sysclk_clk_hf_structs 3149 * \{ 3150 */ 3151 /** 3152 * This structure is used to configure the clock supervisor for clkHf. 3153 */ 3154 /** 3155 * \note 3156 * This structure is available for CAT1B devices. 3157 **/ 3158 typedef struct 3159 { 3160 cy_en_clkhf_csv_supervisor_clock_t supervisorClock; /**< \ref cy_en_clkhf_csv_supervisor_clock_t */ 3161 uint16_t supervisingWindow; /**< Number of supervising clock cycles */ 3162 bool enableFrequencyFaultDetection; /**< 1= enabled, 0= disabled */ 3163 uint16_t frequencyLowerLimit; /**< Lowest frequency in kHz that supervised clock can go */ 3164 uint16_t frequencyUpperLimit; /**< Highest frequency in kHz that supervised clock can go */ 3165 cy_en_csv_error_actions_t frequencyAction; /**< \ref cy_en_csv_error_actions_t */ 3166 bool enableLossDetection; /**< 1= enabled, 0= disabled */ 3167 cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ 3168 cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ 3169 } cy_stc_clkhf_csv_config_t; 3170 /** \} group_sysclk_clk_hf_structs */ 3171 /** \endcond */ 3172 3173 /** \cond INTERNAL */ 3174 /** 3175 * \note 3176 * It is available for CAT1B devices. 3177 **/ 3178 extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */ 3179 /** \endcond */ 3180 #endif /* CY_IP_MXS28SRSS */ 3181 3182 /** 3183 * \addtogroup group_sysclk_clk_hf_funcs 3184 * \{ 3185 */ 3186 3187 3188 /******************************************************************************* 3189 * Function Name: Cy_SysClk_ClkHfEnable 3190 ****************************************************************************//** 3191 * 3192 * Enables the selected clkHf. 3193 * 3194 * \param clkHf Selects which clkHf to enable. 3195 * 3196 * \return \ref cy_en_sysclk_status_t 3197 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 3198 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 3199 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 3200 * uses the PRA driver to change the protected registers. Refer to 3201 * \ref cy_en_pra_status_t for more details. 3202 * 3203 * \funcusage 3204 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource 3205 * 3206 *******************************************************************************/ 3207 cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf); 3208 3209 3210 /******************************************************************************* 3211 * Function Name: Cy_SysClk_ClkHfIsEnabled 3212 ****************************************************************************//** 3213 * 3214 * Reports the Enabled/Disabled status of clkHf. 3215 * 3216 * \param clkHf Selects which clkHf to check. 3217 * 3218 * \return Boolean status of clkHf: true - Enabled, false - Disabled. 3219 * 3220 * \funcusage 3221 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable 3222 * 3223 * \note 3224 * This API is available for CAT1A devices. 3225 * 3226 *******************************************************************************/ 3227 bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf); 3228 3229 3230 /******************************************************************************* 3231 * Function Name: Cy_SysClk_ClkHfDisable 3232 ****************************************************************************//** 3233 * 3234 * Disables the selected clkHf. 3235 * 3236 * \param clkHf Selects which clkHf to enable. 3237 * 3238 * \return \ref cy_en_sysclk_status_t 3239 * 3240 * \note clkHf[0] cannot be disabled. 3241 * 3242 * \funcusage 3243 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable 3244 * 3245 *******************************************************************************/ 3246 cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf); 3247 3248 3249 /******************************************************************************* 3250 * Function Name: Cy_SysClk_ClkHfSetSource 3251 ****************************************************************************//** 3252 * 3253 * Selects the source of the selected clkHf. 3254 * 3255 * \param clkHf selects which clkHf mux to configure. 3256 * 3257 * \param source \ref cy_en_clkhf_in_sources_t 3258 * 3259 * \return \ref cy_en_sysclk_status_t 3260 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 3261 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 3262 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 3263 * uses the PRA driver to change the protected registers. Refer to 3264 * \ref cy_en_pra_status_t for more details. 3265 * 3266 * \note 3267 * Call \ref SystemCoreClockUpdate after this function calling 3268 * if it affects the CLK_HF0 frequency. 3269 * 3270 * \note 3271 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3272 * CLK_HF0 frequency is increasing. 3273 * 3274 * \note 3275 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3276 * CLK_HF0 frequency is decreasing. 3277 * 3278 * \funcusage 3279 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource 3280 * 3281 *******************************************************************************/ 3282 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source); 3283 3284 3285 /******************************************************************************* 3286 * Function Name: Cy_SysClk_ClkHfGetSource 3287 ****************************************************************************//** 3288 * 3289 * Reports the source of the selected clkHf. 3290 * 3291 * \param clkHf selects which clkHf to get the source of. 3292 * 3293 * \return \ref cy_en_clkhf_in_sources_t 3294 * 3295 * \funcusage 3296 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetSource 3297 * 3298 *******************************************************************************/ 3299 cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); 3300 3301 3302 /******************************************************************************* 3303 * Function Name: Cy_SysClk_ClkHfSetDivider 3304 ****************************************************************************//** 3305 * 3306 * Sets the pre-divider for a clkHf. 3307 * 3308 * \param clkHf selects which clkHf divider to configure. 3309 * 3310 * \param divider \ref cy_en_clkhf_dividers_t 3311 * 3312 * \return \ref cy_en_sysclk_status_t 3313 * CY_PRA_STATUS_* - For the PSoC 64 devices there are possible situations when 3314 * function returns the PRA error status code \ref cy_en_pra_status_t instead of 3315 * \ref cy_en_sysclk_status_t. This is because for PSoC 64 devices the function 3316 * uses the PRA driver to change the protected registers. Refer to 3317 * \ref cy_en_pra_status_t for more details. 3318 * 3319 * \note Also call \ref Cy_SysClk_ClkHfSetSource to set the clkHf source. 3320 * 3321 * \note 3322 * Call \ref SystemCoreClockUpdate after this function calling 3323 * if it affects the CLK_HF0 frequency. 3324 * 3325 * \note 3326 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3327 * CLK_HF0 frequency is increasing. 3328 * 3329 * \note 3330 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3331 * CLK_HF0 frequency is decreasing. 3332 * 3333 * \funcusage 3334 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 3335 * 3336 *******************************************************************************/ 3337 cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider); 3338 3339 3340 /******************************************************************************* 3341 * Function Name: Cy_SysClk_ClkHfGetDivider 3342 ****************************************************************************//** 3343 * 3344 * Reports the pre-divider value for a clkHf. 3345 * 3346 * \param clkHf selects which clkHf to check divider of. 3347 * 3348 * \return \ref cy_en_clkhf_dividers_t 3349 * 3350 * \funcusage 3351 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 3352 * 3353 *******************************************************************************/ 3354 cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf); 3355 3356 3357 /******************************************************************************* 3358 * Function Name: Cy_SysClk_ClkHfGetFrequency 3359 ****************************************************************************//** 3360 * 3361 * Reports the frequency of the selected clkHf 3362 * 3363 * \param clkHf Selects the clkHf 3364 * 3365 * \return The frequency, in Hz. 3366 * 3367 * \note 3368 * The reported frequency may be zero, which indicates unknown. This happens if 3369 * the source input is dsi_out or clk_altlf. 3370 * 3371 * \funcusage 3372 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfSetDivider 3373 * 3374 *******************************************************************************/ 3375 uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf); 3376 3377 3378 /** \} group_sysclk_clk_hf_funcs */ 3379 3380 3381 /* ========================================================================== */ 3382 /* ========================= clk_fast SECTION ========================= */ 3383 /* ========================================================================== */ 3384 /** 3385 * \addtogroup group_sysclk_clk_fast_funcs 3386 * \{ 3387 */ 3388 3389 3390 /******************************************************************************* 3391 * Function Name: Cy_SysClk_ClkFastSetDivider 3392 ****************************************************************************//** 3393 * 3394 * Sets the clock divider for the fast clock, which sources the main processor. 3395 * The source of this divider is clkHf[0]. 3396 * 3397 * \param divider divider value between 0 and 255. 3398 * Causes integer division of (divider value + 1), or division by 1 to 256. 3399 * 3400 * \note 3401 * Call \ref SystemCoreClockUpdate after this function calling. 3402 * 3403 * \note 3404 * Call \ref Cy_SysLib_SetWaitStates before calling this function if 3405 * CLK_FAST frequency is increasing. 3406 * 3407 * \note 3408 * Call \ref Cy_SysLib_SetWaitStates after calling this function if 3409 * CLK_FAST frequency is decreasing. 3410 * 3411 * \funcusage 3412 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 3413 * 3414 *******************************************************************************/ 3415 void Cy_SysClk_ClkFastSetDivider(uint8_t divider); 3416 3417 3418 /******************************************************************************* 3419 * Function Name: Cy_SysClk_ClkFastGetDivider 3420 ****************************************************************************//** 3421 * 3422 * Returns the clock divider for the fast clock. 3423 * 3424 * \return The divider value for the fast clock. 3425 * The integer division done is by (divider value + 1), or division by 1 to 256. 3426 * 3427 * \funcusage 3428 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 3429 * 3430 *******************************************************************************/ 3431 uint8_t Cy_SysClk_ClkFastGetDivider(void); 3432 3433 3434 /******************************************************************************* 3435 * Function Name: Cy_SysClk_ClkFastGetFrequency 3436 ****************************************************************************//** 3437 * 3438 * Reports the frequency of the fast clock. 3439 * 3440 * \return The frequency, in Hz. 3441 * 3442 * \funcusage 3443 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkFastSetDivider 3444 * 3445 *******************************************************************************/ 3446 uint32_t Cy_SysClk_ClkFastGetFrequency(void); 3447 3448 3449 /** \} group_sysclk_clk_fast_funcs */ 3450 3451 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) 3452 3453 /* ========================================================================== */ 3454 /* ======================== PERI SECTION ========================== */ 3455 /* ========================================================================== */ 3456 /** 3457 * \addtogroup group_sysclk_clk_peri_grp_funcs 3458 * \{ 3459 */ 3460 /******************************************************************************* 3461 * Function Name: Cy_SysClk_PeriGroupSetDivider 3462 ****************************************************************************//** 3463 * 3464 * Sets the divider value for a particular group 3465 * 3466 * \return \ref cy_en_sysclk_status_t 3467 * 3468 * \funcusage 3469 * TBD 3470 * 3471 * \note 3472 * This API is available for CAT1B devices. 3473 * 3474 *******************************************************************************/ 3475 cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetDivider(uint8_t groupNum, int8_t divider); 3476 3477 3478 /******************************************************************************* 3479 * Function Name: Cy_SysClk_PeriGroupGetDivider 3480 ****************************************************************************//** 3481 * 3482 * Gets the divider value for a particular group 3483 * 3484 * \return Divider value 3485 * 3486 * \funcusage 3487 * TBD 3488 * 3489 * \note 3490 * This API is available for CAT1B devices. 3491 * 3492 *******************************************************************************/ 3493 int8_t Cy_SysClk_PeriGroupGetDivider(uint8_t groupNum); 3494 3495 3496 /******************************************************************************* 3497 * Function Name: Cy_SysClk_PeriGroupSetSlaveCtl 3498 ****************************************************************************//** 3499 * 3500 * Sets the Slave Control value for a particular group 3501 * 3502 * \return \ref cy_en_sysclk_status_t 3503 * 3504 * \funcusage 3505 * TBD 3506 * 3507 * \note 3508 * This API is available for CAT1B devices. 3509 * 3510 *******************************************************************************/ 3511 cy_en_sysclk_status_t Cy_SysClk_PeriGroupSetSlaveCtl(uint8_t groupNum, uint32_t slaveCtl); 3512 3513 3514 /******************************************************************************* 3515 * Function Name: Cy_SysClk_PeriGroupGetSlaveCtl 3516 ****************************************************************************//** 3517 * 3518 * Gets the divider value for a particular group 3519 * 3520 * \return Divider value 3521 * 3522 * \funcusage 3523 * TBD 3524 * 3525 * \note 3526 * This API is available for CAT1B devices. 3527 * 3528 *******************************************************************************/ 3529 uint32_t Cy_SysClk_PeriGroupGetSlaveCtl(uint8_t groupNum); 3530 /** \} group_sysclk_clk_peri_grp_funcs */ 3531 #endif 3532 3533 /* ========================================================================== */ 3534 /* ======================== clk_peri SECTION ========================== */ 3535 /* ========================================================================== */ 3536 /** 3537 * \addtogroup group_sysclk_clk_peri_funcs 3538 * \{ 3539 */ 3540 3541 3542 /******************************************************************************* 3543 * Function Name: Cy_SysClk_ClkPeriSetDivider 3544 ****************************************************************************//** 3545 * 3546 * Sets the clock divider for the peripheral clock tree. All peripheral clock 3547 * dividers are sourced from this clock. Also the Cortex M0+ clock divider is 3548 * sourced from this clock. The source of this divider is clkHf[0] 3549 * 3550 * \param divider divider value between 0 and 255 3551 * Causes integer division of (divider value + 1), or division by 1 to 256. 3552 * 3553 * \note 3554 * Call \ref SystemCoreClockUpdate after this function calling. 3555 * 3556 * \funcusage 3557 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 3558 * 3559 *******************************************************************************/ 3560 void Cy_SysClk_ClkPeriSetDivider(uint8_t divider); 3561 3562 3563 /******************************************************************************* 3564 * Function Name: Cy_SysClk_ClkPeriGetFrequency 3565 ****************************************************************************//** 3566 * 3567 * Reports the frequency of the peri clock. 3568 * 3569 * \return The frequency, in Hz. 3570 * 3571 * \funcusage 3572 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 3573 * 3574 *******************************************************************************/ 3575 uint32_t Cy_SysClk_ClkPeriGetFrequency(void); 3576 3577 3578 3579 3580 /******************************************************************************* 3581 * Function Name: Cy_SysClk_ClkPeriGetDivider 3582 ****************************************************************************//** 3583 * 3584 * Returns the clock divider of the peripheral (peri) clock. 3585 * 3586 * \return The divider value. 3587 * The integer division done is by (divider value + 1), or division by 1 to 256. 3588 * 3589 * \funcusage 3590 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPeriSetDivider 3591 * 3592 *******************************************************************************/ 3593 uint8_t Cy_SysClk_ClkPeriGetDivider(void); 3594 /** \} group_sysclk_clk_peri_funcs */ 3595 3596 3597 /* ========================================================================== */ 3598 /* ===================== clk_peripherals SECTION ====================== */ 3599 /* ========================================================================== */ 3600 /** 3601 * \addtogroup group_sysclk_clk_peripheral_enums 3602 * \{ 3603 */ 3604 /** Programmable clock divider types */ 3605 typedef enum 3606 { 3607 CY_SYSCLK_DIV_8_BIT = 0U, /**< Divider Type is an 8 bit divider */ 3608 CY_SYSCLK_DIV_16_BIT = 1U, /**< Divider Type is a 16 bit divider */ 3609 CY_SYSCLK_DIV_16_5_BIT = 2U, /**< Divider Type is a 16.5 bit fractional divider */ 3610 CY_SYSCLK_DIV_24_5_BIT = 3U /**< Divider Type is a 24.5 bit fractional divider */ 3611 } cy_en_divider_types_t; 3612 /** \} group_sysclk_clk_peripheral_enums */ 3613 3614 3615 /** 3616 * \addtogroup group_sysclk_clk_peripheral_funcs 3617 * \{ 3618 */ 3619 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) 3620 3621 /******************************************************************************* 3622 * Function Name: Cy_SysClk_PeriPclkSetDivider 3623 ****************************************************************************//** 3624 * 3625 * Sets one of the programmable clock dividers. This is only used for integer 3626 * dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. 3627 * 3628 * \pre If the specified clock divider is already enabled - it should be disabled 3629 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 3630 * 3631 * \param ipBlock specifies ip block to connect the clock divider to. 3632 * 3633 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3634 * 3635 * \param dividerNum the divider number. 3636 * 3637 * \param dividerValue divider value 3638 * Causes integer division of (divider value + 1), or division by 1 to 256 3639 * (8-bit divider) or 1 to 65536 (16-bit divider). 3640 * 3641 * \return \ref cy_en_sysclk_status_t 3642 * 3643 * \note 3644 * This API is available for CAT1B devices. 3645 * 3646 *******************************************************************************/ 3647 cy_en_sysclk_status_t 3648 Cy_SysClk_PeriPclkSetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, 3649 uint32_t dividerNum, uint32_t dividerValue); 3650 3651 3652 /******************************************************************************* 3653 * Function Name: Cy_SysClk_PeriPclkGetDivider 3654 ****************************************************************************//** 3655 * 3656 * Returns the integer divider value for the specified divider. One works for 3657 * integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional 3658 * divider value 3659 * 3660 * \param ipBlock specifies ip block to connect the clock divider to. 3661 * 3662 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3663 * 3664 * \param dividerNum specifies which divider of the selected type to configure 3665 * 3666 * \return The divider value. 3667 * The integer division done is by (divider value + 1), or division by 1 to 256 3668 * (8-bit divider) or 1 to 65536 (16-bit divider). 3669 * 3670 * \note 3671 * This API is available for CAT1B devices. 3672 * 3673 *******************************************************************************/ 3674 uint32_t Cy_SysClk_PeriPclkGetDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 3675 3676 3677 /******************************************************************************* 3678 * Function Name: Cy_SysClk_PeriPclkGetFracDivider 3679 ****************************************************************************//** 3680 * 3681 * Reports the integer and fractional parts of the divider 3682 * 3683 * \param ipBlock specifies ip block to connect the clock divider to. 3684 * 3685 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3686 * 3687 * \param dividerNum specifies which divider of the selected type to configure 3688 * 3689 * \param *dividerIntValue pointer to return integer divider value 3690 * 3691 * \param *dividerFracValue pointer to return fractional divider value 3692 * 3693 * \return None. Loads pointed-to variables. 3694 * 3695 * \note 3696 * This API is available for CAT1B devices. 3697 * 3698 *******************************************************************************/ 3699 void Cy_SysClk_PeriPclkGetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 3700 uint32_t *dividerIntValue, uint32_t *dividerFracValue); 3701 3702 3703 /******************************************************************************* 3704 * Function Name: Cy_SysClk_PeriPclkSetFracDivider 3705 ****************************************************************************//** 3706 * 3707 * Sets one of the programmable clock dividers. This function should only be used 3708 * for fractional clock dividers. 3709 * 3710 * \pre If the specified clock divider is already enabled - it should be disabled 3711 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 3712 * 3713 * \param ipBlock specifies ip block to connect the clock divider to. 3714 * 3715 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3716 * 3717 * \param dividerNum specifies which divider of the selected type to configure 3718 * 3719 * \param dividerIntValue the integer divider value 3720 * The source of the divider is peri_clk, which is a divided version of hf_clk[0]. 3721 * The divider value causes integer division of (divider value + 1), or division 3722 * by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). 3723 * 3724 * \param dividerFracValue the fraction part of the divider 3725 * The fractional divider can be 1-32, thus it divides the clock by 1/32 for each 3726 * count. To divide the clock by 11/32nds set this value to 11. 3727 * 3728 * \return \ref cy_en_sysclk_status_t 3729 * 3730 * \note 3731 * This API is available for CAT1B devices. 3732 * 3733 *******************************************************************************/ 3734 cy_en_sysclk_status_t 3735 Cy_SysClk_PeriPclkSetFracDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 3736 uint32_t dividerIntValue, uint32_t dividerFracValue); 3737 3738 3739 /******************************************************************************* 3740 * Function Name: Cy_SysClk_PeriPclkAssignDivider 3741 ****************************************************************************//** 3742 * 3743 * Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. 3744 * 3745 * \param ipBlock specifies ip block to connect the clock divider to. 3746 * 3747 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3748 * 3749 * \param dividerNum specifies which divider of the selected type to configure 3750 * 3751 * \return \ref cy_en_sysclk_status_t 3752 * 3753 * \note 3754 * This API is available for CAT1B devices. 3755 * 3756 *******************************************************************************/ 3757 cy_en_sysclk_status_t 3758 Cy_SysClk_PeriPclkAssignDivider(en_clk_dst_t ipBlock, 3759 cy_en_divider_types_t dividerType, uint32_t dividerNum); 3760 3761 3762 /******************************************************************************* 3763 * Function Name: Cy_SysClk_PeriPclkGetAssignedDivider 3764 ****************************************************************************//** 3765 * 3766 * Reports which clock divider is assigned to a selected IP block. 3767 * 3768 * \param ipBlock specifies ip block to connect the clock divider to. 3769 * 3770 * \return The divider type and number, where bits [7:6] = type, bits[5:0] = divider 3771 * number within that type 3772 * 3773 * \note 3774 * This API is available for CAT1B devices. 3775 * 3776 *******************************************************************************/ 3777 uint32_t Cy_SysClk_PeriPclkGetAssignedDivider(en_clk_dst_t ipBlock); 3778 3779 3780 /******************************************************************************* 3781 * Function Name: Cy_SysClk_PeriPclkEnableDivider 3782 ****************************************************************************//** 3783 * 3784 * Enables the selected divider. 3785 * 3786 * \param ipBlock specifies ip block to connect the clock divider to. 3787 * 3788 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3789 * 3790 * \param dividerNum specifies which divider of the selected type to configure 3791 * 3792 * \note This function also sets the phase alignment bits such that the enabled 3793 * divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider() 3794 * for information on how to phase-align a divider after it is enabled. 3795 * 3796 * \note 3797 * This API is available for CAT1B devices. 3798 * 3799 *******************************************************************************/ 3800 cy_en_sysclk_status_t 3801 Cy_SysClk_PeriPclkEnableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 3802 3803 3804 /******************************************************************************* 3805 * Function Name: Cy_SysClk_PeriPclkDisableDivider 3806 ****************************************************************************//** 3807 * 3808 * Disables a selected divider. 3809 * 3810 * \param ipBlock specifies ip block to connect the clock divider to. 3811 * 3812 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 3813 * 3814 * \param dividerNum specifies which divider of the selected type to configure. 3815 * 3816 * \note 3817 * This API is available for CAT1B devices. 3818 * 3819 *******************************************************************************/ 3820 cy_en_sysclk_status_t 3821 Cy_SysClk_PeriPclkDisableDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 3822 3823 3824 /******************************************************************************* 3825 * Function Name: Cy_SysClk_PeriPclkEnablePhaseAlignDivider 3826 ****************************************************************************//** 3827 * 3828 * First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider), 3829 * then aligns that divider to another programmable divider, and enables the 3830 * selected divider. The divider to align to must already be enabled in order 3831 * to align a divider to it. 3832 * 3833 * \param ipBlock specifies ip block to connect the clock divider to. 3834 * 3835 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 3836 * 3837 * \param dividerNum specifies which divider of the selected type to configure. 3838 * 3839 * \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. 3840 * 3841 * \param dividerNumPA divider number of type specified to phase align to. 3842 * 3843 * \note 3844 * To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA 3845 * to 63. 3846 * 3847 * \note 3848 * This API is available for CAT1B devices. 3849 * 3850 *******************************************************************************/ 3851 cy_en_sysclk_status_t 3852 Cy_SysClk_PeriPclkEnablePhaseAlignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum, 3853 cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA); 3854 #endif 3855 3856 /******************************************************************************* 3857 * Function Name: Cy_SysClk_PeriphSetDivider 3858 ****************************************************************************//** 3859 * 3860 * Sets one of the programmable clock dividers. This is only used for integer 3861 * dividers. Use \ref Cy_SysClk_PeriphSetFracDivider for setting factional dividers. 3862 * 3863 * \pre If the specified clock divider is already enabled - it should be disabled 3864 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 3865 * 3866 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3867 * 3868 * \param dividerNum the divider number. 3869 * 3870 * \param dividerValue divider value 3871 * Causes integer division of (divider value + 1), or division by 1 to 256 3872 * (8-bit divider) or 1 to 65536 (16-bit divider). 3873 * 3874 * \return \ref cy_en_sysclk_status_t 3875 * 3876 * \funcusage 3877 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider 3878 * 3879 *******************************************************************************/ 3880 cy_en_sysclk_status_t 3881 Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, 3882 uint32_t dividerNum, uint32_t dividerValue); 3883 3884 3885 /******************************************************************************* 3886 * Function Name: Cy_SysClk_PeriphGetDivider 3887 ****************************************************************************//** 3888 * 3889 * Returns the integer divider value for the specified divider. One works for 3890 * integer dividers. Use \ref Cy_SysClk_PeriphGetFracDivider to get the fractional 3891 * divider value 3892 * 3893 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3894 * 3895 * \param dividerNum specifies which divider of the selected type to configure 3896 * 3897 * \return The divider value. 3898 * The integer division done is by (divider value + 1), or division by 1 to 256 3899 * (8-bit divider) or 1 to 65536 (16-bit divider). 3900 * 3901 * \funcusage 3902 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetDivider 3903 * 3904 *******************************************************************************/ 3905 uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 3906 3907 3908 /******************************************************************************* 3909 * Function Name: Cy_SysClk_PeriphSetFracDivider 3910 ****************************************************************************//** 3911 * 3912 * Sets one of the programmable clock dividers. This function should only be used 3913 * for fractional clock dividers. 3914 * 3915 * \pre If the specified clock divider is already enabled - it should be disabled 3916 * prior to use this function by \ref Cy_SysClk_PeriphDisableDivider. 3917 * 3918 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3919 * 3920 * \param dividerNum specifies which divider of the selected type to configure 3921 * 3922 * \param dividerIntValue the integer divider value 3923 * The source of the divider is peri_clk, which is a divided version of hf_clk[0]. 3924 * The divider value causes integer division of (divider value + 1), or division 3925 * by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider). 3926 * 3927 * \param dividerFracValue the fraction part of the divider 3928 * The fractional divider can be 1-32, thus it divides the clock by 1/32 for each 3929 * count. To divide the clock by 11/32nds set this value to 11. 3930 * 3931 * \return \ref cy_en_sysclk_status_t 3932 * 3933 * \funcusage 3934 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider 3935 * 3936 *******************************************************************************/ 3937 cy_en_sysclk_status_t 3938 Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 3939 uint32_t dividerIntValue, uint32_t dividerFracValue); 3940 3941 3942 /******************************************************************************* 3943 * Function Name: Cy_SysClk_PeriphGetFracDivider 3944 ****************************************************************************//** 3945 * 3946 * Reports the integer and fractional parts of the divider 3947 * 3948 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3949 * 3950 * \param dividerNum specifies which divider of the selected type to configure 3951 * 3952 * \param *dividerIntValue pointer to return integer divider value 3953 * 3954 * \param *dividerFracValue pointer to return fractional divider value 3955 * 3956 * \return None. Loads pointed-to variables. 3957 * 3958 * \funcusage 3959 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphSetFracDivider 3960 * 3961 *******************************************************************************/ 3962 void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 3963 uint32_t *dividerIntValue, uint32_t *dividerFracValue); 3964 3965 3966 /******************************************************************************* 3967 * Function Name: Cy_SysClk_PeriphAssignDivider 3968 ****************************************************************************//** 3969 * 3970 * Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB. 3971 * 3972 * \param ipBlock specifies ip block to connect the clock divider to. 3973 * 3974 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 3975 * 3976 * \param dividerNum specifies which divider of the selected type to configure 3977 * 3978 * \return \ref cy_en_sysclk_status_t 3979 * 3980 * \funcusage 3981 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider 3982 * 3983 *******************************************************************************/ 3984 cy_en_sysclk_status_t 3985 Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, 3986 cy_en_divider_types_t dividerType, uint32_t dividerNum); 3987 3988 3989 /******************************************************************************* 3990 * Function Name: Cy_SysClk_PeriphGetAssignedDivider 3991 ****************************************************************************//** 3992 * 3993 * Reports which clock divider is assigned to a selected IP block. 3994 * 3995 * \param ipBlock specifies ip block to connect the clock divider to. 3996 * 3997 * \return The divider type and number, where bits [7:6] = type, bits[5:0] = divider 3998 * number within that type 3999 * 4000 * \funcusage 4001 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphAssignDivider 4002 * 4003 *******************************************************************************/ 4004 uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock); 4005 4006 4007 /******************************************************************************* 4008 * Function Name: Cy_SysClk_PeriphEnableDivider 4009 ****************************************************************************//** 4010 * 4011 * Enables the selected divider. 4012 * 4013 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 4014 * 4015 * \param dividerNum specifies which divider of the selected type to configure 4016 * 4017 * \note This function also sets the phase alignment bits such that the enabled 4018 * divider is aligned to clk_peri. See \ref Cy_SysClk_PeriphDisableDivider() 4019 * for information on how to phase-align a divider after it is enabled. 4020 * 4021 * \funcusage 4022 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnableDivider 4023 * 4024 *******************************************************************************/ 4025 cy_en_sysclk_status_t 4026 Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 4027 4028 4029 /******************************************************************************* 4030 * Function Name: Cy_SysClk_PeriphDisableDivider 4031 ****************************************************************************//** 4032 * 4033 * Disables a selected divider. 4034 * 4035 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 4036 * 4037 * \param dividerNum specifies which divider of the selected type to configure. 4038 * 4039 * \funcusage 4040 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphDisableDivider 4041 * 4042 *******************************************************************************/ 4043 cy_en_sysclk_status_t 4044 Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum); 4045 4046 4047 /******************************************************************************* 4048 * Function Name: Cy_SysClk_PeriphEnablePhaseAlignDivider 4049 ****************************************************************************//** 4050 * 4051 * First disables a selected divider (\ref Cy_SysClk_PeriphDisableDivider), 4052 * then aligns that divider to another programmable divider, and enables the 4053 * selected divider. The divider to align to must already be enabled in order 4054 * to align a divider to it. 4055 * 4056 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 4057 * 4058 * \param dividerNum specifies which divider of the selected type to configure. 4059 * 4060 * \param dividerTypePA type of divider to phase-align to; \ref cy_en_divider_types_t. 4061 * 4062 * \param dividerNumPA divider number of type specified to phase align to. 4063 * 4064 * \note 4065 * To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA 4066 * to 63. 4067 * 4068 * \funcusage 4069 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphEnablePhaseAlignDivider 4070 * 4071 *******************************************************************************/ 4072 cy_en_sysclk_status_t 4073 Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, 4074 cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA); 4075 4076 4077 /******************************************************************************* 4078 * Function Name: Cy_SysClk_PeriphGetDividerEnabled 4079 ****************************************************************************//** 4080 * 4081 * Reports the enabled/disabled atate of the selected divider. 4082 * 4083 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t. 4084 * 4085 * \param dividerNum specifies which divider of the selected type to configure. 4086 * 4087 * \return The enabled/disabled state; \n 4088 * false = disabled \n 4089 * true = enabled 4090 * 4091 * \funcusage 4092 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetDividerEnabled 4093 * 4094 *******************************************************************************/ 4095 bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum); 4096 4097 4098 /******************************************************************************* 4099 * Function Name: Cy_SysClk_PeriphGetFrequency 4100 ****************************************************************************//** 4101 * 4102 * Reports the frequency of the output of a given peripheral divider. 4103 * 4104 * \param dividerType specifies which type of divider to use; \ref cy_en_divider_types_t 4105 * 4106 * \param dividerNum specifies which divider of the selected type to configure 4107 * 4108 * \return The frequency, in Hz. 4109 * 4110 * \note 4111 * The reported frequency may be zero, which indicates unknown. This happens if 4112 * the source input is dsi_out or clk_altlf. 4113 * 4114 * \funcusage 4115 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PeriphGetFrequency 4116 * 4117 *******************************************************************************/ 4118 uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum); 4119 4120 4121 /** \} group_sysclk_clk_peripheral_funcs */ 4122 4123 4124 /* ========================================================================== */ 4125 /* ========================= clk_slow SECTION ========================= */ 4126 /* ========================================================================== */ 4127 /** 4128 * \addtogroup group_sysclk_clk_slow_funcs 4129 * \{ 4130 */ 4131 4132 4133 /******************************************************************************* 4134 * Function Name: Cy_SysClk_ClkSlowSetDivider 4135 ****************************************************************************//** 4136 * 4137 * Sets the clock divider for the slow clock. The source of this clock is the 4138 * peripheral clock (clkPeri), which is sourced from clkHf[0]. 4139 * 4140 * \param divider Divider value between 0 and 255. 4141 * Causes integer division of (divider value + 1), or division by 1 to 256. 4142 * 4143 * \note 4144 * Call \ref SystemCoreClockUpdate after this function calling. 4145 * 4146 * \funcusage 4147 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 4148 * 4149 *******************************************************************************/ 4150 void Cy_SysClk_ClkSlowSetDivider(uint8_t divider); 4151 4152 4153 /******************************************************************************* 4154 * Function Name: Cy_SysClk_ClkSlowGetDivider 4155 ****************************************************************************//** 4156 * 4157 * Reports the divider value for the slow clock. 4158 * 4159 * \return The divider value. 4160 * The integer division done is by (divider value + 1), or division by 1 to 256. 4161 * 4162 * \funcusage 4163 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 4164 * 4165 *******************************************************************************/ 4166 uint8_t Cy_SysClk_ClkSlowGetDivider(void); 4167 4168 4169 /******************************************************************************* 4170 * Function Name: Cy_SysClk_ClkSlowGetFrequency 4171 ****************************************************************************//** 4172 * 4173 * Reports the frequency of the slow clock. 4174 * 4175 * \return The frequency, in Hz. 4176 * 4177 * \funcusage 4178 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkSlowSetDivider 4179 * 4180 *******************************************************************************/ 4181 uint32_t Cy_SysClk_ClkSlowGetFrequency(void); 4182 4183 4184 /** \} group_sysclk_clk_slow_funcs */ 4185 4186 4187 /* ========================================================================== */ 4188 /* =========================== clkLf SECTION ========================== */ 4189 /* ========================================================================== */ 4190 /** 4191 * \addtogroup group_sysclk_clk_lf_enums 4192 * \{ 4193 */ 4194 /** 4195 * Low frequency (clkLf) input sources. See CLK_SELECT register, LFCLK_SEL bits. 4196 * Used with functions \ref Cy_SysClk_ClkLfSetSource, and \ref Cy_SysClk_ClkLfGetSource. 4197 */ 4198 typedef enum 4199 { 4200 CY_SYSCLK_CLKLF_IN_ILO = 0U, /**< clkLf is sourced by the internal low speed oscillator (ILO) */ 4201 CY_SYSCLK_CLKLF_IN_WCO = 1U, /**< clkLf is sourced by the watch crystal oscillator (WCO) */ 4202 CY_SYSCLK_CLKLF_IN_ALTLF = 2U, /**< clkLf is sourced by the Alternate Low Frequency Clock (ALTLF) */ 4203 CY_SYSCLK_CLKLF_IN_PILO = 3U, /**< clkLf is sourced by the precision low speed oscillator (PILO) */ 4204 4205 #if defined (CY_IP_MXS28SRSS) 4206 /** 4207 * \note 4208 * This paramter is available for CAT1B devices. 4209 **/ 4210 CY_SYSCLK_CLKLF_IN_ILO1 = 4U, /**< clkLf is sourced by the internal low speed oscillator (ILO1), not present */ 4211 /** 4212 * \note 4213 * This paramter is available for CAT1B devices. 4214 **/ 4215 CY_SYSCLK_CLKLF_IN_ECO_PRESCALER = 5U, /**< clkLf is sourced by the External Clock Oscillator (ECO Prescaler) */ 4216 /** 4217 * \note 4218 * This paramter is available for CAT1B devices. 4219 **/ 4220 CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER = 6U /**< clkLf is sourced by the External Clock Oscillator (LP ECO Prescaler), not present */ 4221 #endif /* CY_IP_MXS28SRSS */ 4222 4223 } cy_en_clklf_in_sources_t; 4224 /** \} group_sysclk_clk_lf_enums */ 4225 4226 /** 4227 * \addtogroup group_sysclk_clk_lf_funcs 4228 * \{ 4229 */ 4230 /******************************************************************************* 4231 * Function Name: Cy_SysClk_ClkLfSetSource 4232 ****************************************************************************//** 4233 * 4234 * Sets the source for the low frequency clock(clkLf). 4235 * 4236 * \param source \ref cy_en_clklf_in_sources_t 4237 * 4238 * \note The watchdog timer (WDT) must be unlocked before calling this function. 4239 * 4240 * \funcusage 4241 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource 4242 * 4243 *******************************************************************************/ 4244 void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source); 4245 4246 4247 /******************************************************************************* 4248 * Function Name: Cy_SysClk_ClkLfGetSource 4249 ****************************************************************************//** 4250 * 4251 * Reports the source for the low frequency clock (clkLf). 4252 * 4253 * \return \ref cy_en_clklf_in_sources_t 4254 * 4255 * \funcusage 4256 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkLfSetSource 4257 * 4258 *******************************************************************************/ 4259 cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void); 4260 /** \} group_sysclk_clk_lf_funcs */ 4261 4262 4263 /* ========================================================================== */ 4264 /* ======================== clk_timer SECTION ========================= */ 4265 /* ========================================================================== */ 4266 /** 4267 * \addtogroup group_sysclk_clk_timer_enums 4268 * \{ 4269 */ 4270 /** 4271 * Timer clock (clk_timer) input sources. See CLK_TIMER_CTL register, TIMER_SEL 4272 * and TIMER_HF0_DIV bits. Used with functions \ref Cy_SysClk_ClkTimerSetSource, and 4273 * \ref Cy_SysClk_ClkTimerGetSource. 4274 */ 4275 typedef enum 4276 { 4277 CY_SYSCLK_CLKTIMER_IN_IMO = 0x000U, /**< clk_timer is sourced by the internal main oscillator (IMO) */ 4278 CY_SYSCLK_CLKTIMER_IN_HF0_NODIV = 0x001U, /**< clk_timer is sourced by clkHf[0] undivided */ 4279 CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 = 0x101U, /**< clk_timer is sourced by clkHf[0] divided by 2 */ 4280 CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 = 0x201U, /**< clk_timer is sourced by clkHf[0] divided by 4 */ 4281 CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 = 0x301U /**< clk_timer is sourced by clkHf[0] divided by 8 */ 4282 } cy_en_clktimer_in_sources_t; 4283 /** \} group_sysclk_clk_timer_enums */ 4284 4285 /** \cond */ 4286 #define CY_SRSS_CLK_TIMER_CTL_TIMER_Pos (SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos) 4287 #define CY_SRSS_CLK_TIMER_CTL_TIMER_Msk (SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk | SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk) 4288 /** \endcond */ 4289 4290 /** 4291 * \addtogroup group_sysclk_clk_timer_funcs 4292 * \{ 4293 */ 4294 4295 4296 /******************************************************************************* 4297 * Function Name: Cy_SysClk_ClkTimerSetSource 4298 ****************************************************************************//** 4299 * 4300 * Sets the source for the timer clock (clk_timer). The timer clock can be used 4301 * as a source for SYSTICK as an alternate clock and one or more of the energy 4302 * profiler counters. 4303 * 4304 * \param source \ref cy_en_clktimer_in_sources_t 4305 * 4306 * \funcusage 4307 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource 4308 * 4309 *******************************************************************************/ 4310 void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source); 4311 4312 4313 /******************************************************************************* 4314 * Function Name: Cy_SysClk_ClkTimerGetSource 4315 ****************************************************************************//** 4316 * 4317 * Reports the source for the timer clock (clk_timer). 4318 * 4319 * \return \ref cy_en_clktimer_in_sources_t 4320 * 4321 * \funcusage 4322 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetSource 4323 * 4324 *******************************************************************************/ 4325 cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void); 4326 4327 4328 /******************************************************************************* 4329 * Function Name: Cy_SysClk_ClkTimerSetDivider 4330 ****************************************************************************//** 4331 * 4332 * Sets the divider for the timer clock (clk_timer). 4333 * 4334 * \param divider Divider value; valid range is 0 to 255. Divides the selected 4335 * source (\ref Cy_SysClk_ClkTimerSetSource) by the (value + 1). 4336 * 4337 * \note 4338 * Do not change the divider value while the timer clock is enabled. 4339 * 4340 * \funcusage 4341 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider 4342 * 4343 *******************************************************************************/ 4344 void Cy_SysClk_ClkTimerSetDivider(uint8_t divider); 4345 4346 4347 /******************************************************************************* 4348 * Function Name: Cy_SysClk_ClkTimerGetDivider 4349 ****************************************************************************//** 4350 * 4351 * Reports the divider value for the timer clock (clk_timer). 4352 * 4353 * \return The divider value 4354 * 4355 * \funcusage 4356 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerSetDivider 4357 * 4358 *******************************************************************************/ 4359 uint8_t Cy_SysClk_ClkTimerGetDivider(void); 4360 4361 4362 /******************************************************************************* 4363 * Function Name: Cy_SysClk_ClkTimerEnable 4364 ****************************************************************************//** 4365 * 4366 * Enables the timer clock (clk_timer). The timer clock can be used as a source 4367 * for SYSTICK and one or more of the energy profiler counters. 4368 * 4369 * \funcusage 4370 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable 4371 * 4372 *******************************************************************************/ 4373 void Cy_SysClk_ClkTimerEnable(void); 4374 4375 4376 /******************************************************************************* 4377 * Function Name: Cy_SysClk_ClkTimerIsEnabled 4378 ****************************************************************************//** 4379 * 4380 * Reports the Enabled/Disabled status of the Timer. 4381 * 4382 * \return Boolean status of Timer: true - Enabled, false - Disabled. 4383 * 4384 * \funcusage 4385 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable 4386 * 4387 * \note 4388 * This API is available for CAT1A devices. 4389 * 4390 *******************************************************************************/ 4391 bool Cy_SysClk_ClkTimerIsEnabled(void); 4392 4393 4394 /******************************************************************************* 4395 * Function Name: Cy_SysClk_ClkTimerDisable 4396 ****************************************************************************//** 4397 * 4398 * Disables the timer clock (clk_timer). 4399 * 4400 * \funcusage 4401 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable 4402 * 4403 *******************************************************************************/ 4404 void Cy_SysClk_ClkTimerDisable(void); 4405 4406 4407 /******************************************************************************* 4408 * Function Name: Cy_SysClk_ClkTimerGetFrequency 4409 ****************************************************************************//** 4410 * 4411 * Reports the frequency of the timer clock (clk_timer). 4412 * \note If the the timer clock is not enabled - a zero frequency is reported. 4413 * 4414 * \funcusage 4415 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable 4416 * 4417 * \note 4418 * This API is available for CAT1A devices. 4419 * 4420 *******************************************************************************/ 4421 uint32_t Cy_SysClk_ClkTimerGetFrequency(void); 4422 4423 4424 /** \} group_sysclk_clk_timer_funcs */ 4425 4426 4427 /* ========================================================================== */ 4428 /* ========================= clk_pump SECTION ========================= */ 4429 /* ========================================================================== */ 4430 /** 4431 * \addtogroup group_sysclk_clk_pump_enums 4432 * \{ 4433 */ 4434 4435 /** 4436 * Pump clock (clk_pump) input sources. See CLK_SELECT register, PUMP_SEL bits. 4437 * Used with functions \ref Cy_SysClk_ClkPumpSetSource, and 4438 * \ref Cy_SysClk_ClkPumpGetSource. 4439 */ 4440 /** 4441 * \note 4442 * This enum is available for CAT1A devices. 4443 **/ 4444 typedef enum 4445 { 4446 CY_SYSCLK_PUMP_IN_CLKPATH0 = 0UL, /**< Pump clock input is clock path 0 */ 4447 CY_SYSCLK_PUMP_IN_CLKPATH1 = 1UL, /**< Pump clock input is clock path 1 */ 4448 CY_SYSCLK_PUMP_IN_CLKPATH2 = 2UL, /**< Pump clock input is clock path 2 */ 4449 CY_SYSCLK_PUMP_IN_CLKPATH3 = 3UL, /**< Pump clock input is clock path 3 */ 4450 CY_SYSCLK_PUMP_IN_CLKPATH4 = 4UL, /**< Pump clock input is clock path 4 */ 4451 CY_SYSCLK_PUMP_IN_CLKPATH5 = 5UL, /**< Pump clock input is clock path 5 */ 4452 CY_SYSCLK_PUMP_IN_CLKPATH6 = 6UL, /**< Pump clock input is clock path 6 */ 4453 CY_SYSCLK_PUMP_IN_CLKPATH7 = 7UL, /**< Pump clock input is clock path 7 */ 4454 CY_SYSCLK_PUMP_IN_CLKPATH8 = 8UL, /**< Pump clock input is clock path 8 */ 4455 CY_SYSCLK_PUMP_IN_CLKPATH9 = 9UL, /**< Pump clock input is clock path 9 */ 4456 CY_SYSCLK_PUMP_IN_CLKPATH10 = 10UL, /**< Pump clock input is clock path 10 */ 4457 CY_SYSCLK_PUMP_IN_CLKPATH11 = 11UL, /**< Pump clock input is clock path 11 */ 4458 CY_SYSCLK_PUMP_IN_CLKPATH12 = 12UL, /**< Pump clock input is clock path 12 */ 4459 CY_SYSCLK_PUMP_IN_CLKPATH13 = 13UL, /**< Pump clock input is clock path 13 */ 4460 CY_SYSCLK_PUMP_IN_CLKPATH14 = 14UL, /**< Pump clock input is clock path 14 */ 4461 CY_SYSCLK_PUMP_IN_CLKPATH15 = 15UL /**< Pump clock input is clock path 15 */ 4462 } cy_en_clkpump_in_sources_t; 4463 4464 /** 4465 * Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits. 4466 * Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and 4467 * \ref Cy_SysClk_ClkPumpGetDivider. 4468 */ 4469 typedef enum 4470 { 4471 CY_SYSCLK_PUMP_NO_DIV = 0U, /**< No division on pump clock */ 4472 CY_SYSCLK_PUMP_DIV_2 = 1U, /**< Pump clock divided by 2 */ 4473 CY_SYSCLK_PUMP_DIV_4 = 2U, /**< Pump clock divided by 4 */ 4474 CY_SYSCLK_PUMP_DIV_8 = 3U, /**< Pump clock divided by 8 */ 4475 CY_SYSCLK_PUMP_DIV_16 = 4U /**< Pump clock divided by 16 */ 4476 } cy_en_clkpump_divide_t; 4477 /** \} group_sysclk_clk_pump_enums */ 4478 4479 /** \cond */ 4480 #define CY_SYSCLK_FLL_IS_DIVIDER_VALID(div) (((div) == CY_SYSCLK_PUMP_NO_DIV) || \ 4481 ((div) == CY_SYSCLK_PUMP_DIV_2) || \ 4482 ((div) == CY_SYSCLK_PUMP_DIV_4) || \ 4483 ((div) == CY_SYSCLK_PUMP_DIV_8) || \ 4484 ((div) == CY_SYSCLK_PUMP_DIV_16)) 4485 /** \endcond */ 4486 4487 /** 4488 * \addtogroup group_sysclk_clk_pump_funcs 4489 * \{ 4490 */ 4491 /******************************************************************************* 4492 * Function Name: Cy_SysClk_ClkPumpSetSource 4493 ****************************************************************************//** 4494 * 4495 * Sets the source for the pump clock (clk_pump). The pump clock can be used for 4496 * the analog pumps in the CTBm block. 4497 * 4498 * \param source \ref cy_en_clkpump_in_sources_t 4499 * 4500 * \note 4501 * Do not change the source while the pump clock is enabled. 4502 * 4503 * \funcusage 4504 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource 4505 * 4506 *******************************************************************************/ 4507 void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source); 4508 4509 4510 /******************************************************************************* 4511 * Function Name: Cy_SysClk_ClkPumpGetSource 4512 ****************************************************************************//** 4513 * 4514 * Reports the source for the pump clock (clk_pump). 4515 * 4516 * \return \ref cy_en_clkpump_in_sources_t 4517 * 4518 * \funcusage 4519 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetSource 4520 * 4521 *******************************************************************************/ 4522 cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void); 4523 4524 4525 /******************************************************************************* 4526 * Function Name: Cy_SysClk_ClkPumpSetDivider 4527 ****************************************************************************//** 4528 * 4529 * Sets the divider of the pump clock (clk_pump). 4530 * 4531 * \param divider \ref cy_en_clkpump_divide_t 4532 * 4533 * \note 4534 * Do not change the divider value while the pump clock is enabled. 4535 * 4536 * \funcusage 4537 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider 4538 * 4539 *******************************************************************************/ 4540 void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider); 4541 4542 4543 /******************************************************************************* 4544 * Function Name: Cy_SysClk_ClkPumpGetDivider 4545 ****************************************************************************//** 4546 * 4547 * Reports the divider value for the pump clock (clk_pump). 4548 * 4549 * \return \ref cy_en_clkpump_divide_t 4550 * 4551 * \funcusage 4552 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpSetDivider 4553 * 4554 *******************************************************************************/ 4555 cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); 4556 4557 4558 /******************************************************************************* 4559 * Function Name: Cy_SysClk_ClkPumpEnable 4560 ****************************************************************************//** 4561 * 4562 * Enables the pump clock (clk_pump). The pump clock can be used for the analog 4563 * pumps in the CTBm block. 4564 * 4565 * \funcusage 4566 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable 4567 * 4568 *******************************************************************************/ 4569 void Cy_SysClk_ClkPumpEnable(void); 4570 4571 4572 /******************************************************************************* 4573 * Function Name: Cy_SysClk_ClkPumpIsEnabled 4574 ****************************************************************************//** 4575 * 4576 * Reports the Enabled/Disabled status of the ClkPump. 4577 * 4578 * \return Boolean status of ClkPump: true - Enabled, false - Disabled. 4579 * 4580 * \funcusage 4581 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable 4582 * 4583 * \note 4584 * This API is available for CAT1A devices. 4585 * 4586 *******************************************************************************/ 4587 bool Cy_SysClk_ClkPumpIsEnabled(void); 4588 4589 4590 /******************************************************************************* 4591 * Function Name: Cy_SysClk_ClkPumpDisable 4592 ****************************************************************************//** 4593 * 4594 * Disables the pump clock (clk_pump). 4595 * 4596 * \funcusage 4597 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable 4598 * 4599 *******************************************************************************/ 4600 void Cy_SysClk_ClkPumpDisable(void); 4601 4602 4603 /******************************************************************************* 4604 * Function Name: Cy_SysClk_ClkPumpGetFrequency 4605 ****************************************************************************//** 4606 * 4607 * Reports the frequency of the pump clock (clk_pump). 4608 * \note If the the pump clock is not enabled - a zero frequency is reported. 4609 * 4610 * \funcusage 4611 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable 4612 * 4613 * \note 4614 * This API is available for CAT1A devices. 4615 * 4616 *******************************************************************************/ 4617 uint32_t Cy_SysClk_ClkPumpGetFrequency(void); 4618 /** \} group_sysclk_clk_pump_funcs */ 4619 4620 4621 /* ========================================================================== */ 4622 /* ========================== clk_bak SECTION ========================= */ 4623 /* ========================================================================== */ 4624 /** 4625 * \addtogroup group_sysclk_clk_bak_enums 4626 * \{ 4627 */ 4628 /** 4629 * Backup domain clock (clk_bak) input sources. See BACKUP->CTL register, 4630 * CLK_SEL bits. Used with functions \ref Cy_SysClk_ClkBakSetSource, and 4631 * \ref Cy_SysClk_ClkBakGetSource. 4632 */ 4633 /** 4634 * \note 4635 * THis enum is available for CAT1A devices. 4636 **/ 4637 typedef enum 4638 { 4639 CY_SYSCLK_BAK_IN_WCO, /**< Backup domain clock input is WCO */ 4640 4641 #if defined (CY_IP_MXS40SRSS) 4642 /** 4643 * \note 4644 * This parameter is available for CAT1A devices. 4645 **/ 4646 CY_SYSCLK_BAK_IN_CLKLF /**< Backup domain clock input is clkLf */ 4647 #endif /* CY_IP_MXS40SRSS */ 4648 4649 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) 4650 /** 4651 * \note 4652 * This parameter is available for CAT1B devices. 4653 **/ 4654 CY_SYSCLK_BAK_IN_ALTBAK, /**< Backup domain clock input is ALTBAK */ 4655 /** 4656 * \note 4657 * This parameter is available for CAT1B devices. 4658 **/ 4659 CY_SYSCLK_BAK_IN_ILO, /**< Backup domain clock input is ILO */ 4660 /** 4661 * \note 4662 * This parameter is available for CAT1B devices. 4663 **/ 4664 CY_SYSCLK_BAK_IN_LPECO_PRESCALER, /**< Backup domain clock input is LPECO_PRESCALER */ 4665 /** 4666 * \note 4667 * This parameter is available for CAT1B devices. 4668 **/ 4669 CY_SYSCLK_BAK_IN_PILO /**< Backup domain clock input is PILO */ 4670 #endif /* CY_IP_MXS28SRSS */ 4671 4672 } cy_en_clkbak_in_sources_t; 4673 /** \} group_sysclk_clk_bak_enums */ 4674 4675 4676 /** 4677 * \addtogroup group_sysclk_clk_bak_funcs 4678 * \{ 4679 */ 4680 /******************************************************************************* 4681 * Function Name: Cy_SysClk_ClkBakSetSource 4682 ****************************************************************************//** 4683 * 4684 * Sets the source for the backup domain clock (clk_bak). 4685 * 4686 * \param source \ref cy_en_clkbak_in_sources_t 4687 * 4688 * \note 4689 * clkLf is not available in all power modes. For this reason, WCO is the 4690 * preferred source. If the WCO is routed through the clkLf multiplexer 4691 * (see \ref Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf. 4692 * 4693 * \funcusage 4694 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource 4695 * 4696 *******************************************************************************/ 4697 void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source); 4698 4699 4700 /******************************************************************************* 4701 * Function Name: Cy_SysClk_ClkBakGetSource 4702 ****************************************************************************//** 4703 * 4704 * Reports the source for the backup domain clock (clk_bak). 4705 * 4706 * \return \ref cy_en_clkbak_in_sources_t 4707 * 4708 * \funcusage 4709 * \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkBakSetSource 4710 * 4711 *******************************************************************************/ 4712 cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void); 4713 /** \} group_sysclk_clk_bak_funcs */ 4714 4715 4716 /** \cond */ 4717 /* Deprecated macros */ 4718 #define CY_SYSCLK_DIV_ROUND(a, b) (CY_SYSLIB_DIV_ROUND((a),(b))) 4719 #define CY_SYSCLK_DIV_ROUNDUP(a, b) (CY_SYSLIB_DIV_ROUNDUP((a),(b))) 4720 /** \endcond */ 4721 4722 4723 #if defined(__cplusplus) 4724 } 4725 #endif /* __cplusplus */ 4726 4727 #endif /* CY_IP_MXS28SRSS */ 4728 4729 #endif /* CY_SYSCLK_H */ 4730 4731 /** \} group_sysclk */ 4732 4733 4734 /* [] END OF FILE */ 4735
