1 /***************************************************************************//**
2 * \file cy_smif.h
3 * \version 2.60
4 *
5 * Provides an API declaration of the Cypress SMIF driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2022 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_smif
27 * \{
28 * The SPI-based communication interface to the external quad SPI (QSPI)
29 * high-speed memory devices.
30 *
31 * The functions and other declarations used in this driver are in cy_smif.h and
32 * cy_smif_memslot.h (if used). If you are using the ModusToolbox QSPI Configurator,
33 * also include cycfg_qspi_memslot.h.
34 *
35 * **SMIF: Serial Memory Interface**: This IP block implements an SPI-based
36 * communication interface for interfacing external memory devices to PSoC.
37 * The SMIF supports SPI, dual SPI (DSPI), quad SPI (QSPI), dual QSPI and octal SPI.
38 *
39 * Features
40 * - Standard SPI Master interface
41 * - Supports single/dual/quad/octal SPI memory devices
42 * - Supports dual quad SPI mode
43 * - Design-time configurable support for multiple (up to 4) external serial
44 * memory devices
45 * - eXecute-In-Place (XIP) operation mode for both read and write accesses
46 * with 4KB XIP read cache and on-the-fly encryption and decryption
47 * - Supports external serial memory initialization via
48 * <a href="https://www.jedec.org/standards-documents/docs/jesd216b" target="_blank">
49 * Serial Flash Discoverable Parameters (SFDP)</a> standard
50 *
51 * The primary usage model for the SMIF is that of an external memory interface.
52 * The SMIF is capable of interfacing with different types of memory, up to four
53 * types.
54 *
55 * \b SMIF driver is divided into three layers
56 * - cy_smif.h API
57 * - cy_smif_memslot.h API
58 * - SMIF configuration structures
59 *
60 * The SMIF API is divided into the low-level functions and memory-slot functions. Use
61 * the low level API for the SMIF block initialization and for implementing a generic
62 * SPI communication interface using the SMIF block.
63 *
64 * The memory slot API has functions to implement the basic memory operations such as
65 * program, read, erase etc. These functions are implemented using the memory
66 * parameters in the memory device configuration data structure. The
67 * Cy_SMIF_MemInit() API initializes all the memory slots based on the settings
68 * in the array.
69 *
70 * \image html smif_3_0_p01_layers.png
71 *
72 * \note
73 * Above image is applicable only for SMIF v3 IP.
74 *
75 * \image html smif_1_0_p01_layers.png
76 *
77 * \note
78 * Above image is applicable only for SMIF v1 IP.
79 *
80 * SMIF Configuration Tool is a stand-alone application, which is a part of PDL
81 * (Creator) and could be found in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool
82 * (e.g. for PDL 3.0.0 and Windows OS PDL/3.0.0/tools/win/SMIFConfigurationTool).
83 *
84 * In ModusToolbox this tool is called QSPI Configurator. QSPI Configurator is a part of
85 * PSoC 6 Software Library and can be found in \<ModusToolbox\>/tools/qspi-configurator-1.1
86 *
87 * Tool generates *.c and *.h file with configuration structures. These configuration
88 * structures are input parameters for cy_smif_memslot API level
89 *
90 * \warning The driver is not responsible for external memory persistence. You cannot edit
91 * a buffer during the Read/Write operations. If there is a memory error, the SMIF ip block
92 * can require a reset. To determine if this has happened, check the SMIF
93 * busy status using Cy_SMIF_BusyCheck() and implement a timeout. Reset the SMIF
94 * block by toggling CTL.ENABLED. Then reconfigure the SMIF block.
95 *
96 * For the Write operation, check that the SMIF driver has completed
97 * transferring by calling Cy_SMIF_BusyCheck(). Also, check that the memory is
98 * available with Cy_SMIF_MemIsBusy() before proceeding.
99 *
100 * Simple example of external flash memory programming using low level SMIF API.
101 * All steps mentioned in example below are incorporated in
102 * \ref Cy_SMIF_MemCmdWriteEnable(), \ref Cy_SMIF_MemCmdProgram(), and
103 * \ref Cy_SMIF_MemIsBusy() of the
104 * \ref group_smif_mem_slot_functions "memory slot level API".
105 * \warning Example is simplified, without checks of error conditions.
106 * \note Flash memories need erase operation before programming. Refer to
107 * external memory datasheet for specific memory commands.
108 *
109 * \snippet smif/snippet/main.c SMIF_API: Write example
110 *
111 * For the Read operation, before accessing the read buffer, check that it is ready
112 * by calling Cy_SMIF_GetTxFifoStatus().
113 *
114 * Simple example of external flash memory read using low level SMIF API. All
115 * steps mentioned in example below are incorporated in
116 * \ref Cy_SMIF_MemCmdRead() of the
117 * \ref group_smif_mem_slot_functions "memory slot level API".
118 * \warning Example is simplified, without checks of error conditions.
119 * \note Refer to external memory datasheet for specific memory commands.
120 *
121 * \snippet smif/snippet/main.c SMIF_API: Read example
122 *
123 * The user should invalidate the cache by calling Cy_SMIF_CacheInvalidate() when
124 * switching from the MMIO mode to XIP mode.
125 *
126 * \section group_smif_configuration Configuration Considerations
127 *
128 * PDL API has common parameters: base, context, config described in
129 * \ref page_getting_started_pdl_design "PDL Design" section.
130 *
131 * See the documentation for Cy_SMIF_Init() and Cy_SMIF_MemInit() for details
132 * on the required configuration structures and other initialization topics.
133 *
134 * The normal (MMIO) mode is used for implementing a generic SPI/DSPI/QSPI/dual
135 * QSPI/octal SPI communication interface using the SMIF block. This
136 * interface can be used to implement special commands like Program/Erase of
137 * flash, memory device configuration, sleep mode entry for memory devices or
138 * other special commands specific to the memory device. The transfer width
139 * (SPI/DSPI/QSPI/octal SPI) of a transmission is a parameter set for each
140 * transmit/receive operation. So these can be changed at run time.
141 *
142 * In a typical memory interface with flash memory, the SMIF is used in the
143 * memory mode when reading from the memory and it switches to the normal mode when
144 * writing to flash memory.
145 * A typical memory device has multiple types of commands.
146 *
147 * The SMIF interface can be used to transmit different types of commands. Each
148 * command has different phases: command, dummy cycles, and transmit and receive
149 * data which require separate APIs.
150 *
151 * \subsection group_smif_init SMIF Initialization
152 * Create interrupt function and allocate memory for SMIF context
153 * structure
154 * \snippet smif/snippet/main.c SMIF_INIT: context and interrupt
155 * SMIF driver initialization for low level API usage (cysmif.h)
156 * \snippet smif/snippet/main.c SMIF_INIT: low level
157 * Additional steps to initialize SMIF driver for memory slot level API usage
158 * (cy_smif_memslot.h).
159 * \snippet smif/snippet/main.c SMIF_INIT: memslot level
160 * \note Example does not include initialization of all needed configuration
161 * structures (\ref cy_stc_smif_mem_device_cfg_t, \ref cy_stc_smif_mem_cmd_t).
162 * SMIF/QSPI Configuration tool generates all configuration structures needed for
163 * memslot level API usage.
164 *
165 * \subsection group_smif_xip_init SMIF XIP Initialization
166 * The eXecute In Place (XIP) is a mode of operation where read or write commands
167 * to the memory device are directed through the SMIF without any use of API
168 * function calls. In this mode the SMIF block maps the AHB bus-accesses to
169 * external memory device addresses to make it behave similar to internal memory.
170 * This allows the CPU to execute code directly from external memory. This mode
171 * is not limited to code and is suitable also for data read and write accesses.
172 * The memory regions available for XIP addresses allocation are defined
173 * in a linker script file (.ld).
174 *
175 * With SMIF V3 IP, MMIO mode transactions are also allowed when the device is set
176 * to XIP mode. However, only blocking SMIF API's are expected to be used for erase or
177 * program operations as external flash will be busy for such operation and may not be
178 * available for XIP at that moment. Blocking API's will ensure the transaction is complete
179 * and then switch back to XIP.
180 *
181 * \snippet smif/snippet/main.c SMIF_INIT: XIP
182 * \note Example of input parameters initialization is in \ref group_smif_init
183 * section.
184 * \warning Functions that called from external memory should be declared with
185 * long call attribute.
186 *
187 * \subsection group_smif_xip_crypto SMIF XIP On-the-fly encryption
188 * In XIP mode, a cryptography component supports on-the-fly encryption for write data and
189 * on-the-fly decryption for read data. On-the-fly encryption/decryption in XIP mode can be
190 * enabled by setting the flags \ref CY_SMIF_FLAG_CRYPTO_ENABLE.
191 * Encryption and decryption are based on the AES-128 forward block cipher: advanced
192 * encryption standard blockcipher with a 128-bit key. KEY[127:0] is a secret (private) key
193 * programmed into the CRYPTO_KEY3,...,CRYPTO_KEY0 registers using \ref Cy_SMIF_SetCryptoKey.
194 * These registers are software write-only. A software read returns 0. In the SMIF hardware,
195 * by applying AES-128 with KEY[127:0] on a plaintext PT[127:0], we get a ciphertext CT[127:0].
196 * In XIP mode, the XIP address is used as the plaintext PT[]. The resulting ciphertext CT[]
197 * is used on-the-fly and not software accessible. The XIP address is extended with the
198 * CRYPTO_INPUT3, ..., CRYPTO_INPUT0 registers. \ref Cy_SMIF_SetCryptoIV can be used to set
199 * initialization vector (96-bits).
200 * In XIP mode, the resulting ciphertext CT[] (of the encrypted address) is XORed with the memory
201 * transfers read data or write data. Note that the AES-128 block cipher is on the address of the
202 * data and not on the data itself.
203 *
204 * \image html smif_xip_mode_functionality.png
205 *
206 * \subsection group_smif_usage_rules Rules for PSoC6 QSPI/SMIF Block Usage
207 * 1. All operations must use one or more dummy cycles between the PSoC 6 Command
208 * and Address phase (when the PSoC 6 MCU drives the data pins) and the device's
209 * Response phase (when the device drives the same data pins). Bus contention may
210 * occur if no (zero) dummy cycles are used.
211 * 2. Any transfer that does not allow dummy cycles (such as Register Status
212 * Reads) must use the single-bit transfer mode. In single-bit mode, the PSoC 6
213 * drives the Command on the Data0 line and the device responds on the Data1
214 * line, so bus contention cannot occur.
215 *
216 * \section group_smif_more_information More Information
217 *
218 * More information regarding the Serial Memory Interface can be found in the component
219 * datasheet and the Technical Reference Manual (TRM).
220 * More information regarding the SMIF Configuration Tool are in SMIF
221 * Configuration Tool User Guide located in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool/
222 * folder
223 *
224 * \section group_smif_changelog Changelog
225 * <table class="doxtable">
226 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
227 * <tr>
228 * <td rowspan="3">2.60</td>
229 * <td>Modified private APIs </td>
230 * <td>MISRA-10.6 violation and Bug fixes.</td>
231 * </tr>
232 * <tr>
233 * <td>Added new API \ref Cy_SMIF_SetSelectedDelayTapSel and \ref Cy_SMIF_GetSelectedDelayTapSel.</td>
234 * <td>Support for CAT1D devices.</td>
235 * </tr>
236 * <tr>
237 * <td>Modified \ref Cy_SMIF_MemWrite and \ref Cy_SMIF_MemDeInit APIs.</td>
238 * <td>Code Enhancement.</td>
239 * </tr>
240 * <tr>
241 * <td>2.50</td>
242 * <td>Future functionality support for Hyperbus devices.</td>
243 * <td>Code Enhancements.</td>
244 * </tr>
245 * <tr>
246 * <td rowspan="4">2.40</td>
247 * <td>Enhanced \ref Cy_SMIF_MemEraseSector to compute sector boundary for erase operation and \n
248 * Minor Bug fixes.
249 * </td>
250 * <td>Code Enhancements.</td>
251 * </tr>
252 * <tr>
253 * <td>Added new API \ref Cy_SMIF_MemCmdPowerDown and \ref Cy_SMIF_MemCmdReleasePowerDown.</td>
254 * <td>Reduce power consumption.</td>
255 * </tr>
256 * <tr>
257 * <td>Added new API \ref Cy_SMIF_DeviceTransfer_SetMergeTimeout and \ref Cy_SMIF_DeviceTransfer_ClearMergeTimeout.</td>
258 * <td>Allow user to configure merge timeout.</td>
259 * </tr>
260 * <tr>
261 * <td>Removed Bridge API support.</td>
262 * <td>Removed feature not supported in existing devices.</td>
263 * </tr>
264 * <tr>
265 * <td rowspan="5">2.30</td>
266 * <td>Octal SDR and DDR support using SFDP mode.</td>
267 * <td>Octal device support.</td>
268 * </tr>
269 * <tr>
270 * <td>Move SFDP related functionality to cy_smif_sfdp.c. </td>
271 * <td>Code Enhancements.</td>
272 * </tr>
273 * <tr>
274 * <td>Added support for new product families</td>
275 * <td>Support for CAT1B and CAT1C devices.</td>
276 * </tr>
277 * <tr>
278 * <td>Added new API's:\n
279 * \ref Cy_SMIF_MemInitSfdpMode()\n
280 * \ref Cy_SMIF_SetCryptoIV()\n
281 * \ref Cy_SMIF_SetCryptoKey()\n
282 * \ref Cy_SMIF_ConvertSlaveSlotToIndex()\n
283 * \ref Cy_SMIF_SetCryptoEnable()\n
284 * \ref Cy_SMIF_SetCryptoDisable()\n
285 * \ref Cy_SMIF_SetReadyPollingDelay()\n
286 *
287 * Following macros renamed:\n
288 * CY_SMIF_WRITE_STATUS_REG2_CMD to CY_SMIF_WRITE_STATUS_REG2_T1_CMD.</td>
289 * <td>Support for SFDP 1.0 devices.</td>
290 * </tr>
291 * <tr>
292 * <td>Added new API's for CAT1D devices\n
293 * \ref Cy_SMIF_SetRxCaptureMode()\n
294 * Cy_SMIF_Bridge_Enable()\n
295 * Cy_SMIF_Bridge_SetPortPriority()\n
296 * Cy_SMIF_Bridge_SetSimpleRemapRegion()\n
297 * Cy_SMIF_Bridge_SetInterleavingRemapRegion()\n
298 * \ref Cy_SMIF_MemOctalEnable()\n
299 </td>
300 * <td>Support for CAT1D devices.</td>
301 * </tr>
302 * <tr>
303 * <td>2.20</td>
304 * <td>Bug fixes in \ref Cy_SMIF_MemEraseSector for Hybrid memory configuration.
305 * Updated \ref Cy_SMIF_MemIsReady to use \ref Cy_SysLib_Rtos_Delay and \ref Cy_SysLib_Rtos_DelayUs.</td>
306 * <td>Code enhancement.</td>
307 * </tr>
308 * <tr>
309 * <td>2.10</td>
310 * <td>New silicon family support.</td>
311 * <td>Added extended API for DDR support.</td>
312 * </tr>
313 * <tr>
314 * <td rowspan="4">2.0</td>
315 * <td>Reworked the \ref Cy_SMIF_MemRead and \ref Cy_SMIF_MemWrite functions to use polling instead of interrupts.</td>
316 * <td>Extend the usability of these functions.</td>
317 * </tr>
318 * <tr>
319 * <td>Reworked the length-parameter check in the \ref Cy_SMIF_MemEraseSector function.
320 * The Erase operation is not performed and \ref CY_SMIF_SUCCESS is no longer returned when the sectors are not aligned.</td>
321 * <td>Fix the user error-handling of the length parameter.</td>
322 * </tr>
323 * <tr>
324 * <td>Fixed the address-parameter check in the \ref Cy_SMIF_MemLocateHybridRegion function.
325 * \ref CY_SMIF_SUCCESS or \ref CY_SMIF_NOT_HYBRID_MEM is no longer returned when the address exceeds the memory size.</td>
326 * <td>Address a defect.</td>
327 * </tr>
328 * <tr>
329 * <td>Fixed MISRA 2012 violations.</td>
330 * <td>MISRA 2012 compliance.</td>
331 * </tr>
332 * <tr>
333 * <td>1.50.1</td>
334 * <td>Minor documentation updates. </td>
335 * <td>Documentation improvement. </td>
336 * </tr>
337 * <tr>
338 * <td>1.50</td>
339 * <td>Added a new function: \ref Cy_SMIF_MemLocateHybridRegion.\n
340 * Added a new structure \ref cy_stc_smif_hybrid_region_info_t.\n
341 * Updated the \ref Cy_SMIF_MemEraseSector and \ref Cy_SMIF_MemCmdSectorErase functions.\n
342 * Updated the \ref Cy_SMIF_MemSfdpDetect function. \n
343 * Updated the \ref cy_stc_smif_mem_device_cfg_t structure.</td>
344 * <td>Support for memories with hybrid regions.</td>
345 * </tr>
346 * <tr>
347 * <td rowspan="2">1.40.1</td>
348 * <td>The \ref Cy_SMIF_MemInit is changed. </td>
349 * <td>Corrected a false assertion during initialization in SFDP mode.</td>
350 * </tr>
351 * <tr>
352 * <td>Minor documentation updates. </td>
353 * <td></td>
354 * </tr>
355 * <tr>
356 * <td rowspan="5">1.40</td>
357 * <td>The following functions are renamed:\n
358 * Cy_SMIF_GetTxfrStatus into Cy_SMIF_GetTransferStatus;\n
359 * Cy_SMIF_Memslot_Init into Cy_SMIF_MemInit;\n
360 * Cy_SMIF_Memslot_DeInit into Cy_SMIF_MemDeInit;\n
361 * Cy_SMIF_Memslot_CmdWriteEnable into Cy_SMIF_MemCmdWriteEnable;\n
362 * Cy_SMIF_Memslot_CmdWriteDisable into Cy_SMIF_MemCmdWriteDisable;\n
363 * Cy_SMIF_Memslot_IsBusy into Cy_SMIF_MemIsBusy;\n
364 * Cy_SMIF_Memslot_QuadEnable into Cy_SMIF_MemQuadEnable;\n
365 * Cy_SMIF_Memslot_CmdReadSts into Cy_SMIF_MemCmdReadStatus;\n
366 * Cy_SMIF_Memslot_CmdWriteSts into Cy_SMIF_MemCmdWriteStatus;\n
367 * Cy_SMIF_Memslot_CmdChipErase into Cy_SMIF_MemCmdChipErase;\n
368 * Cy_SMIF_Memslot_CmdSectorErase into Cy_SMIF_MemCmdSectorErase;\n
369 * Cy_SMIF_Memslot_SfdpDetect into Cy_SMIF_MemSfdpDetect;\n
370 * Cy_SMIF_Memslot_CmdProgram into Cy_SMIF_MemCmdProgram;\n
371 * Cy_SMIF_Memslot_CmdRead into Cy_SMIF_MemCmdRead.\n
372 * The following ENUMa are renamed:\n
373 * CY_SMIF_SEND_CMPLT into CY_SMIF_SEND_COMPLETE;\n
374 * CY_SMIF_REC_CMPLT into CY_SMIF_RX_COMPLETE;\n
375 * CY_SMIF_REC_BUSY into CY_SMIF_RX_BUSY;\n
376 * CY_SMIF_SEL_INV_INTERNAL_CLK into CY_SMIF_SEL_INVERTED_INTERNAL_CLK;\n
377 * CY_SMIF_SEL_INV_FEEDBACK_CLK into CY_SMIF_SEL_INVERTED_FEEDBACK_CLK;\n
378 * cy_en_smif_cache_en_t into cy_en_smif_cache_t.\n
379 * The following MACROs are renamed:\n
380 * CY_SMIF_FLAG_WR_EN into CY_SMIF_FLAG_WRITE_ENABLE;\n
381 * CY_SMIF_FLAG_CRYPTO_EN into CY_SMIF_FLAG_CRYPTO_ENABLE;\n
382 * CY_SMIF_SFDP_SING_BYTE_00 into CY_SMIF_SFDP_SIGNATURE_BYTE_00;\n
383 * CY_SMIF_SFDP_SING_BYTE_01 into CY_SMIF_SFDP_SIGNATURE_BYTE_01;\n
384 * CY_SMIF_SFDP_SING_BYTE_02 into CY_SMIF_SFDP_SIGNATURE_BYTE_02;\n
385 * CY_SMIF_SFDP_SING_BYTE_03 into CY_SMIF_SFDP_SIGNATURE_BYTE_03;\n
386 * CY_SMIF_WR_STS_REG1_CMD into CY_SMIF_WRITE_STATUS_REG1_CMD;\n
387 * CY_SMIF_WR_DISABLE_CMD into CY_SMIF_WRITE_DISABLE_CMD;\n
388 * CY_SMIF_RD_STS_REG1_CMD into CY_SMIF_READ_STATUS_REG1_CMD;\n
389 * CY_SMIF_WR_ENABLE_CMD into CY_SMIF_WRITE_ENABLE_CMD;\n
390 * CY_SMIF_RD_STS_REG2_T1_CMD into CY_SMIF_READ_STATUS_REG2_T1_CMD;\n
391 * CY_SMIF_WR_STS_REG2_CMD into CY_SMIF_WRITE_STATUS_REG2_CMD;\n
392 * CY_SMIF_RD_STS_REG2_T2_CMD into CY_SMIF_READ_STATUS_REG2_T2_CMD;\n
393 * CY_SMIF_QE_BIT_STS_REG2_T1 into CY_SMIF_QE_BIT_STATUS_REG2_T1;\n
394 * CY_SMIF_STS_REG_BUSY_MASK into CY_SMIF_STATUS_REG_BUSY_MASK.\n
395 * </td>
396 * <td rowspan="2">Documentation improvement.</td>
397 * </tr>
398 * <tr>
399 * <td>Updated the description of the Cy_SMIF_MemInit() function.
400 * Updated the Cy_SMIF_Encrypt() function usage example.
401 * </td>
402 * </tr>
403 * <tr>
404 * <td>The type of arguments that are not modified by the functions are set to const.
405 * </td>
406 * <td>Usability improvement.
407 * </td>
408 * </tr>
409 * <tr>
410 * <td>The Cy_SMIF_MemSfdpDetect() function is updated to support new
411 * commands for 4 bytes addressing.
412 * </td>
413 * <td>Memory devices with new 4 byte addressing commands support.
414 * </td>
415 * </tr>
416 * <tr>
417 * <td>Added the blocking functions which take care of the
418 * busy-status check of the memory:
419 * - \ref Cy_SMIF_MemIsReady
420 * - \ref Cy_SMIF_MemIsQuadEnabled
421 * - \ref Cy_SMIF_MemEnableQuadMode
422 * - \ref Cy_SMIF_MemRead
423 * - \ref Cy_SMIF_MemWrite
424 * - \ref Cy_SMIF_MemEraseSector
425 * - \ref Cy_SMIF_MemEraseChip
426 * </td>
427 * <td>Added new high-level blocking functions.
428 * </td>
429 * </tr>
430 * <tr>
431 * <td rowspan="5">1.30</td>
432 * <td>The CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk value is changed to 0x0000FFFFUL.</td>
433 * <td rowspan="4">Driver maintenance.</td>
434 * </tr>
435 * <tr>
436 * <td>Added the check of the size parameter in the Cy_SMIF_TransmitData() function.</td>
437 * </tr>
438 * <tr>
439 * <td>Added conditional check for presence of the SMIF hardware IP.</td>
440 * </tr>
441 * <tr>
442 * <td>Fixed the wrong erase command in the SFDP protocol for devices with Erase Type 3.</td>
443 * </tr>
444 * <tr>
445 * <td>Updated the General Description section with minor changes.
446 * Updated the ordering of the parameters descriptions for some functions.
447 * Added the text saying that the Cy_SMIF_MemInit() function is applicable
448 * to use the external memory as memory-mapped to PSoC (XIP mode).
449 * Added the snippet for the Cy_SMIF_Encrypt() function to show how to use this function.
450 * Added below the picture in the Low-Level Functions section the sequence of PDL
451 * functions required in a Read or Write transaction.
452 * Added the text below the picture about the address.
453 * Updated DUMMY COUNT in this picture.
454 * Added checking of the size parameter in the Cy_SMIF_TransmitData() function.
455 * </td>
456 * <td>Documentation improvement.</td>
457 * </tr>
458 * <tr>
459 * <td>1.20.1</td>
460 * <td>Added upper limit to size parameter in several functions.</td>
461 * <td>Documentation improvement.</td>
462 * </tr>
463 * <tr>
464 * <td rowspan="3">1.20</td>
465 * <td>Flattened the organization of the driver source code into the single
466 * source directory and the single include directory.
467 * </td>
468 * <td>Driver library directory-structure simplification.</td>
469 * </tr>
470 * <tr>
471 * <td>Added a new return status and transfer width option for the case when the memory command is not supported.</td>
472 * <td>Improved the memory command structure usability.</td>
473 * </tr>
474 * <tr>
475 * <td>Added register access layer. Use register access macros instead
476 * of direct register access using dereferenced pointers.</td>
477 * <td>Makes register access device-independent, so that the PDL does
478 * not need to be recompiled for each supported part number.</td>
479 * </tr>
480 * <tr>
481 * <td rowspan="2">1.11</td>
482 * <td>Fixed internal function that writes to the SMIF FIFO</td>
483 * <td>The write function stuck in the loop when write speed in external
484 * memory is significantly lower than PSoC CPU core speed and write
485 * transfer is not finished during the single function call.
486 * </td>
487 * </tr>
488 * <tr>
489 * <td>Added optional mode part to the program command flow</td>
490 * <td>Extend usability of program command</td>
491 * </tr>
492 * <tr>
493 * <td>1.10.1</td>
494 * <td>Added Low Power Callback section</td>
495 * <td>Documentation update and clarification</td>
496 * </tr>
497 * <tr>
498 * <td>1.10</td>
499 * <td>Fix write to external memory from CM0+ core. Add checks of API input parameters.
500 * Minor documentation updates</td>
501 * <td></td>
502 * </tr>
503 * <tr>
504 * <td>1.0</td>
505 * <td>Initial version</td>
506 * <td></td>
507 * </tr>
508 * </table>
509 *
510 * \defgroup group_smif_macros Macros
511 * \{
512 * \defgroup group_smif_macros_status Status Macros
513 * \defgroup group_smif_macros_cmd Command Macros
514 * \defgroup group_smif_macros_flags External Memory Flags
515 * \defgroup group_smif_macros_sfdp SFDP Macros
516 * \defgroup group_smif_macros_isr Interrupt Macros
517 * \}
518 * \defgroup group_smif_functions Functions
519 * \{
520 * \defgroup group_smif_low_level_functions Low Level Functions
521 * \{
522 * The SMIF interface can be used to transmit different types of commands.
523 * Each command has different phases: command, dummy cycles, and transmit and receive data which require separate APIs.
524 *
525 * During the time that Slave Select line is active (LOW) the clock signal (CLK) is toggled while command information is first
526 * transferred on the data (IO) signals from the master to the slave. The clock continues to toggle during any period required for
527 * information access in the slave. The clock continues to toggle during the transfer of read data from the slave to the master
528 * or write data from the master to the slave. When the master has transferred the desired amount of data, the master drives the
529 * Slave Select line inactive (HIGH).
530 * Basic flow for read/write commands using \ref Cy_SMIF_TransmitCommand, \ref Cy_SMIF_TransmitData, \ref Cy_SMIF_ReceiveData and
531 * \ref Cy_SMIF_SendDummyCycles with a Quad SPI interface.
532 *
533 * \image html smif_1_0_p03_rw_cmd.png
534 *
535 * The sequence of the PDL functions required in a read or write transaction is:
536 * \ref Cy_SMIF_TransmitCommand() ->
537 * \ref Cy_SMIF_SendDummyCycles() ->
538 * \ref Cy_SMIF_ReceiveData() / \ref Cy_SMIF_TransmitData() ->
539 * \ref Cy_SMIF_BusyCheck().
540 * The address is sent as part of the Cy_SMIF_TransmitCommand() function.
541 * No separate function call is required.
542 *
543 * \}
544 * \defgroup group_smif_mem_slot_functions Memory Slot Functions
545 * \defgroup group_smif_functions_syspm_callback Low Power Callback
546 * \}
547 * \defgroup group_smif_data_structures Data Structures
548 * \{
549 * \defgroup group_smif_data_structures_memslot SMIF Memory Description Structures
550 * General hierarchy of memory structures are:
551 *
552 * \image html smif_3_0_p02_memslot_stc.png
553 *
554 * \note
555 * Above image is applicable only for SMIF v3 IP.
556 *
557 * \image html smif_1_0_p02_memslot_stc.png
558 *
559 * \note
560 * Above image is applicable only for SMIF v1 IP.
561 *
562 * Top structure is \ref cy_stc_smif_block_config_t, which could have links up to
563 * 4 \ref cy_stc_smif_mem_config_t which describes each connected to the SMIF
564 * external memory.
565 * \}
566 * \defgroup group_smif_enums Enumerated Types
567 */
568
569 #if !defined (CY_SMIF_H)
570 #define CY_SMIF_H
571
572 #include "cy_device.h"
573
574 #if defined (CY_IP_MXSMIF)
575
576 #include <stdint.h>
577 #include <stdbool.h>
578 #include <stddef.h>
579 #include "cy_syslib.h"
580 #include "cy_syspm.h"
581
582 #if defined(__cplusplus)
583 extern "C" {
584 #endif
585
586 /***************************************
587 * Constants
588 ****************************************/
589
590 /**
591 * \addtogroup group_smif_macros
592 * \{
593 */
594
595 /** The driver major version */
596 #define CY_SMIF_DRV_VERSION_MAJOR 2
597
598 /** The driver minor version */
599 #define CY_SMIF_DRV_VERSION_MINOR 60
600
601 /** One microsecond timeout for Cy_SMIF_TimeoutRun() */
602 #define CY_SMIF_WAIT_1_UNIT (1U)
603
604 /** The SMIF driver ID, reported as part of an unsuccessful API return status
605 * \ref cy_en_smif_status_t */
606 #define CY_SMIF_ID CY_PDL_DRV_ID(0x2CUL)
607
608
609 /**
610 * \addtogroup group_smif_macros_isr
611 * \{
612 */
613
614 /** Enable XIP_ALIGNMENT_ERROR interrupt see TRM for details */
615 #define CY_SMIF_ALIGNMENT_ERROR (SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk)
616 /** Enable RX_DATA_FIFO_UNDERFLOW interrupt see TRM for details */
617 #define CY_SMIF_RX_DATA_FIFO_UNDERFLOW (SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk)
618 /** Enable TX_DATA_FIFO_OVERFLOW interrupt see TRM for details */
619 #define CY_SMIF_TX_DATA_FIFO_OVERFLOW (SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk)
620 /** Enable TX_CMD_FIFO_OVERFLOW interrupt see TRM for details */
621 #define CY_SMIF_TX_COMMAND_FIFO_OVERFLOW (SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk)
622 /** Enable TR_TX_REQ interrupt see TRM for details */
623 #define CY_SMIF_TX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_TX_REQ_Msk)
624 /** Enable TR_RX_REQ interrupt see TRM for details */
625 #define CY_SMIF_RX_DATA_FIFO_LEVEL_TRIGGER (SMIF_INTR_TR_RX_REQ_Msk)
626
627 /** \} group_smif_macros_isr */
628
629 /** \cond INTERNAL */
630
631 #if ((CY_IP_MXSMIF_VERSION==2) || (CY_IP_MXSMIF_VERSION==3))
632 #define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk SMIF_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk
633 #define SMIF_RX_DATA_FIFO_CTL SMIF_RX_DATA_MMIO_FIFO_CTL
634 #define SMIF_RX_DATA_FIFO_RD4 SMIF_RX_DATA_MMIO_FIFO_RD4
635 #define SMIF_RX_DATA_FIFO_RD1 SMIF_RX_DATA_MMIO_FIFO_RD1
636 #define SMIF_RX_DATA_FIFO_RD2 SMIF_RX_DATA_MMIO_FIFO_RD2
637 #endif /* CY_IP_MXSMIF_VERSION */
638
639 #if (CY_IP_MXSMIF_VERSION==2)
640 /* SMIF IP V2 do not use register name MMIO */
641 #define SMIF_TX_CMD_MMIO_FIFO_WR SMIF_TX_CMD_FIFO_WR
642 #define SMIF_TX_DATA_MMIO_FIFO_WR1ODD SMIF_TX_DATA_FIFO_WR1ODD
643 #define SMIF_TX_DATA_MMIO_FIFO_WR1 SMIF_TX_DATA_FIFO_WR1
644 #endif
645
646 #if (CY_IP_MXSMIF_VERSION==3)
647 #define SMIF_TX_DATA_FIFO_CTL SMIF_TX_DATA_MMIO_FIFO_CTL
648 #define SMIF_TX_DATA_FIFO_WR4 SMIF_TX_DATA_MMIO_FIFO_WR4
649 #define SMIF_TX_DATA_FIFO_WR1 SMIF_TX_DATA_MMIO_FIFO_WR1
650 #define SMIF_TX_DATA_FIFO_WR2 SMIF_TX_DATA_MMIO_FIFO_WR2
651 #define SMIF_CRYPTO_CMD_START_Msk SMIF_SMIF_CRYPTO_CRYPTO_CMD_START_Msk
652 #define SMIF_CRYPTO_CMD_START_Pos SMIF_SMIF_CRYPTO_CRYPTO_CMD_START_Pos
653 #endif /* CY_IP_MXSMIF_VERSION */
654
655 #define CY_SMIF_CMD_FIFO_TX_MODE (0UL)
656 #define CY_SMIF_CMD_FIFO_TX_COUNT_MODE (1UL)
657 #define CY_SMIF_CMD_FIFO_RX_COUNT_MODE (2UL)
658 #define CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE (3UL)
659
660 #if (CY_IP_MXSMIF_VERSION>=2)
661 #define CY_SMIF_TX_CMD_FIFO_STATUS_RANGE (8U)
662 #else
663 #define CY_SMIF_TX_CMD_FIFO_STATUS_RANGE (4U)
664 #endif /* CY_IP_MXSMIF_VERSION */
665
666 #define CY_SMIF_TX_DATA_FIFO_STATUS_RANGE (8U)
667 #define CY_SMIF_RX_DATA_FIFO_STATUS_RANGE (8U)
668
669 #define CY_SMIF_ONE_BYTE (1U)
670 #define CY_SMIF_TWO_BYTES (2U)
671 #define CY_SMIF_THREE_BYTES (3U)
672 #define CY_SMIF_FOUR_BYTES (4U)
673 #define CY_SMIF_FIVE_BYTES (5U)
674 #define CY_SMIF_SIX_BYTES (6U)
675 #define CY_SMIF_SEVEN_BYTES (7U)
676 #define CY_SMIF_EIGHT_BYTES (8U)
677
678 #define CY_SMIF_CRYPTO_FIRST_WORD (0U)
679 #define CY_SMIF_CRYPTO_SECOND_WORD (4U)
680 #define CY_SMIF_CRYPTO_THIRD_WORD (8U)
681 #define CY_SMIF_CRYPTO_FOURTH_WORD (12U)
682
683 #define CY_SMIF_CRYPTO_START (1UL)
684 #define CY_SMIF_CRYPTO_COMPLETED (0UL)
685 #define CY_SMIF_CRYPTO_ADDR_MASK (0xFFFFFFF0UL)
686 #define CY_SMIF_AES128_BYTES (16U)
687
688 #define CY_SMIF_CTL_REG_DEFAULT (0x00000300U) /* 3 - [13:12] CLOCK_IF_RX_SEL */
689
690 #define CY_SMIF_SFDP_FAIL (0x08U)
691 #define CY_SMIF_SFDP_FAIL_SS0_POS (0x00U)
692 #define CY_SMIF_SFDP_FAIL_SS1_POS (0x01U)
693 #define CY_SMIF_SFDP_FAIL_SS2_POS (0x02U)
694 #define CY_SMIF_SFDP_FAIL_SS3_POS (0x03U)
695
696 #define CY_SMIF_MAX_DESELECT_DELAY (7U)
697 #define CY_SMIF_MAX_TX_TR_LEVEL (8U)
698 #define CY_SMIF_MAX_RX_TR_LEVEL (8U)
699
700 #define CY_SMIF_MODE_VALID(mode) ((CY_SMIF_NORMAL == (cy_en_smif_mode_t)(mode)) || \
701 (CY_SMIF_MEMORY == (cy_en_smif_mode_t)(mode)))
702 #define CY_SMIF_BLOCK_EVENT_VALID(event) ((CY_SMIF_BUS_ERROR == (cy_en_smif_error_event_t)(event)) || \
703 (CY_SMIF_WAIT_STATES == (cy_en_smif_error_event_t)(event)))
704 #if (CY_IP_MXSMIF_VERSION>=2)
705 #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_OUTPUT_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
706 (CY_SMIF_SEL_INVERTED_OUTPUT_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
707 (CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
708 (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
709 (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
710 (CY_SMIF_SEL_INVERTED_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) ||\
711 (CY_SMIF_SEL_INVERTED_SPHB_RWDS_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
712 (CY_SMIF_SEL_SPHB_RWDS_CLK == (cy_en_smif_clk_select_t)(clkSel)))
713 #else
714 #define CY_SMIF_CLOCK_SEL_VALID(clkSel) ((CY_SMIF_SEL_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
715 (CY_SMIF_SEL_INVERTED_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
716 (CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
717 (CY_SMIF_SEL_INVERTED_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)))
718 #endif /* CY_IP_MXSMIF_VERSION */
719
720 #define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY)
721 #define CY_SMIF_SLAVE_SEL_VALID(ss) ((CY_SMIF_SLAVE_SELECT_0 == (ss)) || \
722 (CY_SMIF_SLAVE_SELECT_1 == (ss)) || \
723 (CY_SMIF_SLAVE_SELECT_2 == (ss)) || \
724 (CY_SMIF_SLAVE_SELECT_3 == (ss)))
725 #define CY_SMIF_DATA_SEL_VALID(ss) ((CY_SMIF_DATA_SEL0 == (ss)) || \
726 (CY_SMIF_DATA_SEL1 == (ss)) || \
727 (CY_SMIF_DATA_SEL2 == (ss)) || \
728 (CY_SMIF_DATA_SEL3 == (ss)))
729 #define CY_SMIF_TXFR_WIDTH_VALID(width) ((CY_SMIF_WIDTH_SINGLE == (width)) || \
730 (CY_SMIF_WIDTH_DUAL == (width)) || \
731 (CY_SMIF_WIDTH_QUAD == (width)) || \
732 (CY_SMIF_WIDTH_OCTAL == (width)) || \
733 (CY_SMIF_WIDTH_NA == (width)))
734 #define CY_SMIF_CMD_PARAM_VALID(param, paramSize) (((paramSize) > 0U)? (NULL != (param)) : (true))
735
736 #define CY_SMIF_WIDTH_NA_VALID(paramWidth, paramSize) (((paramSize) > 0U)? \
737 (CY_SMIF_WIDTH_NA != (paramWidth)) : (true))
738 #define CY_SMIF_CMD_DATA_RATE_VALID(rate) ((CY_SMIF_SDR == (rate)) || \
739 (CY_SMIF_DDR == (rate)))
740 #define CY_SMIF_CMD_PARAM_DATA_RATE_VALID(rate) ((CY_SMIF_SDR == (rate)) || \
741 (CY_SMIF_DDR == (rate)))
742 #define CY_SMIF_DATA_DATA_RATE_VALID(rate) ((CY_SMIF_SDR == (rate)) || \
743 (CY_SMIF_DDR == (rate)))
744
745 #define CY_SMIF_BUFFER_SIZE_MAX (65536UL)
746 #define CY_SMIF_BUF_SIZE_VALID(size) (((CY_SMIF_BUFFER_SIZE_MAX) >= (size)) && ((0UL) < (size)))
747
748 /***************************************
749 * Command FIFO Register
750 ***************************************/
751
752 #if (CY_IP_MXSMIF_VERSION>=2)
753 /* SMIF->TX_CMD_FIFO_MMIO_WR Commands Fields */
754 #define CY_SMIF_CMD_MMIO_FIFO_WR_MODE_Pos (24UL) /* [26:24] Command data mode */
755 #define CY_SMIF_CMD_MMIO_FIFO_WR_MODE_Msk (0x07000000UL) /* DATA[26:24] Command data mode */
756
757 #define CY_SMIF_CMD_MMIO_FIFO_WR_SS_Pos (20UL) /* [23:20] Slave select */
758 #define CY_SMIF_CMD_MMIO_FIFO_WR_SS_Msk (0x00F00000UL) /* DATA[23:20] Slave select */
759
760 #define CY_SMIF_CMD_MMIO_FIFO_WR_LAST_BYTE_Pos (19UL) /* [19] Last byte */
761 #define CY_SMIF_CMD_MMIO_FIFO_WR_LAST_BYTE_Msk (0x00080000UL) /* DATA[19] Last byte */
762
763 #define CY_SMIF_CMD_MMIO_FIFO_WR_DATA_RATE_Pos (18UL) /* [18] Data Rate */
764 #define CY_SMIF_CMD_MMIO_FIFO_WR_DATA_RATE_Msk (0x00040000UL) /* DATA[18] Data Rate */
765
766 #define CY_SMIF_CMD_MMIO_FIFO_WR_WIDTH_Pos (16UL) /* [17:16] Transfer width */
767 #define CY_SMIF_CMD_MMIO_FIFO_WR_WIDTH_Msk (0x00030000UL) /* DATA[17:16] Transfer width */
768
769 #define CY_SMIF_CMD_MMIO_FIFO_WR_TXDATA_BYTE_2_Pos (8UL) /* [15:8] */
770 #define CY_SMIF_CMD_MMIO_FIFO_WR_TXDATA_BYTE_2_Msk (0x0000FF00UL) /* DATA[15:8] second byte */
771
772 #define CY_SMIF_CMD_MMIO_FIFO_WR_TXDATA_BYTE_1_Pos (0UL) /* [7:0] first byte */
773 #define CY_SMIF_CMD_MMIO_FIFO_WR_TXDATA_BYTE_1_Msk (0x000000FFUL) /* DATA[7:0] first byte */
774
775 #define CY_SMIF_CMD_MMIO_FIFO_WR_DUMMY_Pos (0UL) /* [0] Dummy count */
776 #define CY_SMIF_CMD_MMIO_FIFO_WR_DUMMY_Msk (0x0000FFFFUL) /* DATA[15:0] Dummy count */
777
778 #define CY_SMIF_CMD_MMIO_FIFO_WR_TX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] TX count */
779 #define CY_SMIF_CMD_MMIO_FIFO_WR_TX_COUNT_Pos (0UL) /* [0] TX count */
780
781 #define CY_SMIF_CMD_MMIO_FIFO_WR_RX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] RX count */
782 #define CY_SMIF_CMD_MMIO_FIFO_WR_RX_COUNT_Pos (0UL) /* [0] RX count */
783
784 #define CY_SMIF_CMD_MMIO_FIFO_WR_DUMMY_RWDS_Msk (0x00800000UL) /* DATA[23] Dummy RWDS */
785 #define CY_SMIF_CMD_MMIO_FIFO_WR_DUMMY_RWDS_Pos (23UL) /* [23] Dummy RWDS */
786 #else
787 /* SMIF->TX_CMD_FIFO_WR */
788 #define CY_SMIF_TX_CMD_FIFO_WR_MODE_POS (18U) /* [19:18] Command data mode */
789 #define CY_SMIF_TX_CMD_FIFO_WR_WIDTH_POS (16U) /* [17:16] Transfer width */
790 #define CY_SMIF_TX_CMD_FIFO_WR_LAST_BYTE_POS (15U) /* [15] Last byte */
791 #define CY_SMIF_TX_CMD_FIFO_WR_SS_POS (8U) /* [11:8] Slave select */
792 #define CY_SMIF_TX_CMD_FIFO_WR_TXDATA_POS (0U) /* [0] Transmitted byte */
793 #define CY_SMIF_TX_CMD_FIFO_WR_DUMMY_POS (0U) /* [0] Dummy count */
794 #define CY_SMIF_TX_CMD_FIFO_WR_TX_COUNT_POS (0U) /* [0] TX count */
795 #define CY_SMIF_TX_CMD_FIFO_WR_RX_COUNT_POS (0U) /* [0] RX count */
796
797 /* SMIF->TX_CMD_FIFO_WR Commands Fields */
798 #define CY_SMIF_CMD_FIFO_WR_MODE_Pos (18UL) /* [19:18] Command data mode */
799 #define CY_SMIF_CMD_FIFO_WR_MODE_Msk (0x000C0000UL) /* DATA[19:18] Command data mode */
800
801 #define CY_SMIF_CMD_FIFO_WR_WIDTH_Pos (16UL) /* [17:16] Transfer width */
802 #define CY_SMIF_CMD_FIFO_WR_WIDTH_Msk (0x00030000UL) /* DATA[17:16] Transfer width */
803
804 #define CY_SMIF_CMD_FIFO_WR_LAST_BYTE_Pos (15UL) /* [15] Last byte */
805 #define CY_SMIF_CMD_FIFO_WR_LAST_BYTE_Msk (0x00008000UL) /* DATA[15] Last byte */
806
807 #define CY_SMIF_CMD_FIFO_WR_SS_Pos (8UL) /* [11:8] Slave select */
808 #define CY_SMIF_CMD_FIFO_WR_SS_Msk (0x00000F00UL) /* DATA[11:8] Slave select */
809
810 #define CY_SMIF_CMD_FIFO_WR_TXDATA_Pos (0UL) /* [0] Transmitted byte */
811 #define CY_SMIF_CMD_FIFO_WR_TXDATA_Msk (0x000000FFUL) /* DATA[7:0] Transmitted byte */
812 #define CY_SMIF_CMD_FIFO_WR_DUMMY_Pos (0UL) /* [0] Dummy count */
813 #define CY_SMIF_CMD_FIFO_WR_DUMMY_Msk (0x0000FFFFUL) /* DATA[15:0] Dummy count */
814 #define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] TX count */
815 #define CY_SMIF_CMD_FIFO_WR_TX_COUNT_Pos (0UL) /* [0] TX count */
816 #define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Msk (0x0000FFFFUL) /* DATA[15:0] RX count */
817 #define CY_SMIF_CMD_FIFO_WR_RX_COUNT_Pos (0UL) /* [0] RX count */
818 #endif /* CY_IP_MXSMIF_VERSION */
819
820 #if (CY_IP_MXSMIF_VERSION == 5u)
821 #define CY_SMIF_CORE_0_HF 3U
822 #define CY_SMIF_CORE_1_HF 4U
823 #endif
824
825 /** \endcond */
826 /** \} group_smif_macros */
827
828
829 /**
830 * \addtogroup group_smif_enums
831 * \{
832 */
833
834 /** The Transfer width options for the command, data, the address and the mode. */
835 typedef enum
836 {
837 CY_SMIF_WIDTH_SINGLE = 0U, /**< Single SPI mode. */
838 CY_SMIF_WIDTH_DUAL = 1U, /**< Dual SPI mode. */
839 CY_SMIF_WIDTH_QUAD = 2U, /**< Quad SPI mode. */
840 CY_SMIF_WIDTH_OCTAL = 3U, /**< Octal SPI mode. */
841 CY_SMIF_WIDTH_NA = 0xFFU /**< The specific width parameter is not applicable for this memory command. */
842 } cy_en_smif_txfr_width_t;
843
844 /** The SMIF error-event selection. */
845 typedef enum
846 {
847 /**< Generates a bus error. */
848 CY_SMIF_BUS_ERROR = 0UL,
849 /** Stalls the bus with the wait states. This option will increase the
850 * interrupt latency.
851 */
852 CY_SMIF_WAIT_STATES = 1UL
853 } cy_en_smif_error_event_t;
854
855 /** Specifies the delay line used for RX data capturing with */
856 typedef enum
857 {
858 CY_SMIF_1_NEW_SEL_PER_TAP = 0, /**< 1 of these new delay cells per tap providing:
859 granularity of max. ~0.22ns */
860 CY_SMIF_1_SEL_PER_TAP = 1, /**< 1 cell per tap providing:
861 granularity of max. ~0.4ns */
862 CY_SMIF_2_SEL_PER_TAP = 2, /**< 2 cells per tap providing:
863 granularity of max. ~0.8ns */
864 CY_SMIF_4_SEL_PER_TAP = 3, /**< 4 cells per tap providing:
865 granularity of max. ~1.6ns */
866 CY_SMIF_NO_DELAY_SEL = 0xFF,/**< No delay line (disabled) */
867 } cy_en_smif_delay_line_t;
868
869 /** The data line-selection options for a slave device. */
870 typedef enum
871 {
872 /**
873 * smif.spi_data[0] = DATA0, smif.spi_data[1] = DATA1, ..., smif.spi_data[7] = DATA7.
874 * This value is allowed for the SPI, DSPI, QSPI, dual QSPI, and octal SPI modes.
875 */
876 CY_SMIF_DATA_SEL0 = 0,
877 /**
878 * smif.spi_data[2] = DATA0, smif.spi_data[3] = DATA1.
879 * This value is only allowed for the SPI and DSPI modes.
880 */
881 CY_SMIF_DATA_SEL1 = 1,
882 /**
883 * smif.spi_data[4] = DATA0, smif.spi_data[5] = DATA1, ..., smif.spi_data[7] = DATA3.
884 * This value is only allowed for the SPI, DSPI, QSPI and dual QSPI modes.
885 */
886 CY_SMIF_DATA_SEL2 = 2,
887 /**
888 * smif.spi_data[6] = DATA0, smif.spi_data[7] = DATA1.
889 * This value is only allowed for the SPI and DSPI modes.
890 */
891 CY_SMIF_DATA_SEL3 = 3
892 } cy_en_smif_data_select_t;
893
894 /** The SMIF modes to work with an external memory. */
895 typedef enum
896 {
897 CY_SMIF_NORMAL, /**< Command mode (MMIO mode). */
898 CY_SMIF_MEMORY /**< XIP (eXecute In Place) mode. */
899 } cy_en_smif_mode_t;
900
901 /**
902 * \note
903 * This enum is available for CAT1B, CAT1C and CAT1D devices.
904 **/
905 typedef enum
906 {
907 CY_SMIF_DELAY_TAP_DISABLE = 0, /**< The SMIF Delay tap disable */
908 CY_SMIF_DELAY_TAP_ENABLE = 1, /**< The SMIF Delay tap enable */
909 } cy_en_smif_delay_tap_t;
910
911 /** The SMIF transfer status return values. */
912 typedef enum
913 {
914 CY_SMIF_STARTED, /**< The SMIF started. */
915 CY_SMIF_SEND_COMPLETE, /**< The data transmission is complete. */
916 CY_SMIF_SEND_BUSY, /**< The data transmission is in progress. */
917 CY_SMIF_RX_COMPLETE, /**< The data reception is completed. */
918 CY_SMIF_RX_BUSY, /**< The data reception is in progress. */
919 CY_SMIF_XIP_ERROR, /**< An XIP alignment error. */
920 CY_SMIF_CMD_ERROR, /**< A TX CMD FIFO overflow. */
921 CY_SMIF_TX_ERROR, /**< A TX DATA FIFO overflow. */
922 CY_SMIF_RX_ERROR /**< An RX DATA FIFO underflow. */
923
924 } cy_en_smif_txfr_status_t;
925
926 /** The SMIF API return values. */
927 typedef enum
928 {
929 CY_SMIF_SUCCESS = 0x00U, /**< Successful SMIF operation. */
930 CY_SMIF_CMD_FIFO_FULL = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x01U, /**< The command is cancelled. The command FIFO is full. */
931 CY_SMIF_EXCEED_TIMEOUT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x02U, /**< The SMIF operation timeout exceeded. */
932 /**
933 * The device does not have a QE bit. The device detects
934 * 1-1-4 and 1-4-4 Reads based on the instruction.
935 */
936 CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U,
937 CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U, /**< The SMIF API received the wrong parameter */
938 CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U, /**< The external memory does not support SFDP (JESD216B). */
939 CY_SMIF_NOT_HYBRID_MEM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x06U, /**< The external memory is not hybrid */
940 CY_SMIF_SFDP_CORRUPTED_TABLE = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x07U, /**< The SFDP table is corrupted */
941 /** Failed to initialize the slave select 0 external memory by auto detection (SFDP). */
942 CY_SMIF_SFDP_SS0_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
943 ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS0_POS),
944 /** Failed to initialize the slave select 1 external memory by auto detection (SFDP). */
945 CY_SMIF_SFDP_SS1_FAILED = CY_SMIF_ID | CY_PDL_STATUS_ERROR |
946 ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS1_POS),
947 /** Failed to initialize the slave select 2 external memory by auto detection (SFDP). */
948 CY_SMIF_SFDP_SS2_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
949 ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS2_POS),
950 /** Failed to initialize the slave select 3 external memory by auto detection (SFDP). */
951 CY_SMIF_SFDP_SS3_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR |
952 ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS3_POS),
953 /** The command API is not supported for this memory device. */
954 CY_SMIF_CMD_NOT_FOUND = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x80U,
955 /** SFDP Buffer Insufficient. */
956 CY_SMIF_SFDP_BUFFER_INSUFFICIENT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x81U,
957 /**
958 * The device does not have a OE bit. The device detects
959 * 1-1-8 and 1-8-8 Reads based on the instruction.
960 */
961 CY_SMIF_NO_OE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x82U,
962 /** SMIF is currently busy and cannot accept the request */
963 CY_SMIF_BUSY = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x83U,
964 CY_SMIF_GENERAL_ERROR = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x84U, /**< Some general error */
965 } cy_en_smif_status_t;
966
967 /** The SMIF slave select definitions for the driver API. Each slave select is
968 * represented by an enumeration that has the bit corresponding to the slave
969 * select number set. */
970 typedef enum
971 {
972 CY_SMIF_SLAVE_SELECT_0 = 1U, /**< The SMIF slave select 0 */
973 CY_SMIF_SLAVE_SELECT_1 = 2U, /**< The SMIF slave select 1 */
974 CY_SMIF_SLAVE_SELECT_2 = 4U, /**< The SMIF slave select 2 */
975 CY_SMIF_SLAVE_SELECT_3 = 8U /**< The SMIF slave select 3 */
976 } cy_en_smif_slave_select_t;
977
978 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
979 /** Specifies receive capture mode. */
980 /**
981 * \note
982 * This enum is available for CAT1D devices.
983 **/
984 typedef enum
985 {
986 CY_SMIF_SEL_NORMAL_SPI = 0U, /**< Normal SPI without DLP. */
987 CY_SMIF_SEL_NORMAL_SPI_WITH_DLP = 1U, /**< Normal SPI with DLP (Data Learning Pattern). */
988 CY_SMIF_SEL_XSPI_HYPERBUS_WITH_DQS = 2U, /**< xSPI or HYPER BUS with Data strobe line. */
989 } cy_en_smif_capture_mode_t;
990 #endif
991
992 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
993
994 /** Specifies the clock source for the receiver clock. */
995 /**
996 * \note
997 * This enum is available for CAT1B and CAT1C devices.
998 **/
999 typedef enum
1000 {
1001 CY_SMIF_SEL_OUTPUT_CLK = 0U, /**< The SMIF output clock */
1002 CY_SMIF_SEL_INVERTED_OUTPUT_CLK = 1U, /**< The SMIF inverted output clock */
1003 CY_SMIF_SEL_FEEDBACK_CLK = 2U, /**< The SMIF feedback clock */
1004 CY_SMIF_SEL_INVERTED_FEEDBACK_CLK = 3U, /**< The SMIF feedback inverted clock */
1005 CY_SMIF_SEL_INTERNAL_CLK = 4U, /**< The SMIF internal clock */
1006 CY_SMIF_SEL_INVERTED_INTERNAL_CLK = 5U, /**< The SMIF internal inverted clock */
1007 CY_SMIF_SEL_INVERTED_SPHB_RWDS_CLK = 6U, /**< The SMIF internal inverted clock */
1008 CY_SMIF_SEL_SPHB_RWDS_CLK = 7U, /**< The SMIF internal inverted clock */
1009 } cy_en_smif_clk_select_t;
1010 #endif
1011 #if (CY_IP_MXSMIF_VERSION==1) || defined (CY_DOXYGEN)
1012 /**
1013 * \note
1014 * This enum is available for CAT1A devices.
1015 **/
1016 typedef enum
1017 {
1018 CY_SMIF_SEL_INTERNAL_CLK = 0U, /**< The SMIF internal clock */
1019 CY_SMIF_SEL_INVERTED_INTERNAL_CLK = 1U, /**< The SMIF internal inverted clock */
1020 CY_SMIF_SEL_FEEDBACK_CLK = 2U, /**< The SMIF feedback clock */
1021 CY_SMIF_SEL_INVERTED_FEEDBACK_CLK = 3U /**< The SMIF feedback inverted clock */
1022 } cy_en_smif_clk_select_t;
1023 #endif /* CY_IP_MXSMIF_VERSION */
1024
1025 /** Specifies enabled type of SMIF cache. */
1026 typedef enum
1027 {
1028 CY_SMIF_CACHE_SLOW = 1U, /**< The SMIF slow cache (in the clk_slow domain) see TRM for details */
1029 CY_SMIF_CACHE_FAST = 2U, /**< The SMIF fast cache (in the clk_fast domain) see TRM for details */
1030 CY_SMIF_CACHE_BOTH = 3U /**< The SMIF both caches */
1031 } cy_en_smif_cache_t;
1032
1033 /** Specifies the quad enable requirement case.
1034 * JEDEC Basic Flash Parameter Table: 15th DWORD
1035 **/
1036 typedef enum
1037 {
1038 CY_SMIF_SFDP_QER_0 = 0, /**< No QE Bit */
1039 CY_SMIF_SFDP_QER_1 = 1, /**< Bit 1 of Status Register 2 - Write uses 2 bytes using 01h */
1040 CY_SMIF_SFDP_QER_2 = 2, /**< Bit 6 of Status Register 1 - Write uses 1 byte */
1041 CY_SMIF_SFDP_QER_3 = 3, /**< Bit 7 of Status Register 2- Write uses 1 byte */
1042 CY_SMIF_SFDP_QER_4 = 4, /**< Bit 1 of Status Register 2 - Write uses 1 or 2 bytes */
1043 CY_SMIF_SFDP_QER_5 = 5, /**< Bit 1 of Status Register 2 - Write status uses 01h */
1044 CY_SMIF_SFDP_QER_6 = 6, /**< Bit 1 of Status Register 2 - Write uses 1 byte using 31h */
1045 } cy_en_smif_qer_t;
1046
1047 /** Specifies the memory interface frequency range of operation.
1048 **/
1049 typedef enum
1050 {
1051 CY_SMIF_100MHZ_OPERATION = 0, /**< 100 MHz default operation */
1052 CY_SMIF_133MHZ_OPERATION = 1, /**< 133 MHz operation */
1053 CY_SMIF_166MHZ_OPERATION = 2, /**< 166 MHz operation */
1054 CY_SMIF_200MHZ_OPERATION = 3, /**< 200 MHz operation */
1055 } cy_en_smif_interface_freq_t;
1056
1057 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
1058 /** Specifies the data rate. */
1059 /**
1060 * \note
1061 * This enum is available for CAT1B, CAT1C and CAT1D devices.
1062 **/
1063 typedef enum
1064 {
1065 CY_SMIF_SDR = 0, /**< The SMIF Single Data Rate (SDR) */
1066 CY_SMIF_DDR = 1, /**< The SMIF Double Data Rate (DDR) */
1067 } cy_en_smif_data_rate_t;
1068
1069 /** Specifies the presence of the field. */
1070 /**
1071 * \note
1072 * This enum is available for CAT1B, CAT1C and CAT1D devices.
1073 **/
1074 typedef enum
1075 {
1076 CY_SMIF_NOT_PRESENT = 0,
1077 CY_SMIF_PRESENT_1BYTE = 1,
1078 CY_SMIF_PRESENT_2BYTE = 2,
1079 } cy_en_smif_field_presence_t;
1080
1081 /** Specifies the merge transaction timeout in terms of clock cycles. */
1082 /**
1083 * \note
1084 * This enum is available for CAT1B, CAT1C and CAT1D devices.
1085 **/
1086 typedef enum
1087 {
1088 CY_SMIF_MERGE_TIMEOUT_1_CYCLE = 0,
1089 CY_SMIF_MERGE_TIMEOUT_16_CYCLES = 1,
1090 CY_SMIF_MERGE_TIMEOUT_256_CYCLES = 2,
1091 CY_SMIF_MERGE_TIMEOUT_4096_CYCLES = 3,
1092 CY_SMIF_MERGE_TIMEOUT_65536_CYCLES = 4,
1093 } cy_en_smif_merge_timeout_t;
1094
1095 #endif /* CY_IP_MXSMIF_VERSION */
1096
1097 /** Specifies the data line index. */
1098 typedef enum
1099 {
1100 CY_SMIF_DATA_BIT0_TAP_SEL = 0U, /**< Data line zero. */
1101 CY_SMIF_DATA_BIT1_TAP_SEL = 1U, /**< Data line one. */
1102 CY_SMIF_DATA_BIT2_TAP_SEL = 2U, /**< Data line two. */
1103 CY_SMIF_DATA_BIT3_TAP_SEL = 3U, /**< Data line three. */
1104 CY_SMIF_DATA_BIT4_TAP_SEL = 4U, /**< Data line four. */
1105 CY_SMIF_DATA_BIT5_TAP_SEL = 5U, /**< Data line five. */
1106 CY_SMIF_DATA_BIT6_TAP_SEL = 6U, /**< Data line six. */
1107 CY_SMIF_DATA_BIT7_TAP_SEL = 7U, /**< Data line seven. */
1108 } cy_en_smif_mem_data_line_t;
1109
1110
1111 /** \cond INTERNAL */
1112 /*******************************************************************************
1113 * These are legacy macros. They are left here just for backward compatibility.
1114 * Do not use them in new designs.
1115 *******************************************************************************/
1116
1117 #define CY_SMIF_SEND_CMPLT CY_SMIF_SEND_COMPLETE
1118 #define CY_SMIF_REC_CMPLT CY_SMIF_RX_COMPLETE
1119 #define CY_SMIF_REC_BUSY CY_SMIF_RX_BUSY
1120 #define CY_SMIF_SEL_INV_INTERNAL_CLK CY_SMIF_SEL_INVERTED_INTERNAL_CLK
1121 #define CY_SMIF_SEL_INV_FEEDBACK_CLK CY_SMIF_SEL_INVERTED_FEEDBACK_CLK
1122 #define cy_en_smif_cache_en_t cy_en_smif_cache_t
1123 #define Cy_SMIF_GetTxfrStatus Cy_SMIF_GetTransferStatus
1124
1125 /** \endcond */
1126
1127 /** \} group_smif_enums */
1128
1129
1130 /**
1131 * \addtogroup group_smif_data_structures
1132 * \{
1133 */
1134
1135 /***************************************************************************//**
1136 *
1137 * The SMIF user callback function type called at the end of a transfer.
1138 *
1139 * \param event
1140 * The event which caused a callback call.
1141 *
1142 *******************************************************************************/
1143 typedef void (*cy_smif_event_cb_t)(uint32_t event);
1144
1145
1146 /** The SMIF configuration structure. */
1147 typedef struct
1148 {
1149 uint32_t mode; /**< Specifies the mode of operation \ref cy_en_smif_mode_t. */
1150 uint32_t deselectDelay; /**< Specifies the minimum duration of SPI de-selection between SPI transfers:
1151 * - "0": 1 clock cycle.
1152 * - "1": 2 clock cycles.
1153 * - "2": 3 clock cycles.
1154 * - "3": 4 clock cycles.
1155 * - "4": 5 clock cycles.
1156 * - "5": 6 clock cycles.
1157 * - "6": 7 clock cycles.
1158 * - "7": 8 clock cycles. */
1159 uint32_t rxClockSel; /**< Specifies the clock source for the receiver
1160 * clock \ref cy_en_smif_clk_select_t. */
1161 uint32_t blockEvent; /**< Specifies what happens when there is a Read
1162 * from an empty RX FIFO or a Write to a full
1163 * TX FIFO. \ref cy_en_smif_error_event_t. */
1164 cy_en_smif_delay_tap_t delayTapEnable; /**< Delay tap can be enabled or disabled \ref cy_en_smif_delay_tap_t. */
1165 cy_en_smif_delay_line_t delayLineSelect; /**< set line selection which is input. \ref cy_en_smif_delay_line_t */
1166 } cy_stc_smif_config_t;
1167
1168 /** The SMIF internal context data. The user must not modify it. */
1169 typedef struct
1170 {
1171 uint8_t const volatile * volatile txBufferAddress; /**< The pointer to the data to transfer */
1172 uint32_t txBufferSize; /**< The size of the data to transmit in bytes */
1173 /**
1174 * The transfer counter. The number of the transmitted bytes = txBufferSize - txBufferCounter
1175 */
1176 uint32_t volatile txBufferCounter;
1177 uint8_t volatile * volatile rxBufferAddress; /**< The pointer to the variable where the received data is stored */
1178 uint32_t rxBufferSize; /**< The size of the data to be received in bytes */
1179 /**
1180 * The transfer counter. The number of the received bytes = rxBufferSize - rxBufferCounter
1181 */
1182 uint32_t volatile rxBufferCounter;
1183 /**
1184 * The status of the transfer. The transmitting / receiving is completed / in progress
1185 */
1186 uint32_t volatile transferStatus;
1187 cy_smif_event_cb_t volatile txCompleteCb; /**< The user-defined callback executed at the completion of a transmission */
1188 cy_smif_event_cb_t volatile rxCompleteCb; /**< The user-defined callback executed at the completion of a reception */
1189 /**
1190 * The timeout in microseconds for the blocking functions. This timeout value applies to all blocking APIs.
1191 */
1192 uint32_t timeout;
1193 /**
1194 * The timeout in microseconds for polling memory device on its readiness.
1195 */
1196 uint16_t memReadyPollDealy;
1197 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
1198 /**
1199 * \note
1200 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
1201 **/
1202 cy_en_smif_data_rate_t preCmdDataRate; /**< preferred command data rate */
1203 /**
1204 * \note
1205 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
1206 **/
1207 cy_en_smif_txfr_width_t preCmdWidth; /**< preferred command data rate */
1208 /**
1209 * \note
1210 * This parameter is available for CAT1B, CAT1C and CAT1D devices.
1211 **/
1212 cy_en_smif_data_rate_t preXIPDataRate; /**< preferred XIP data rate */
1213 /**
1214 * \note
1215 * This parameter is available for CAT1B, CAT1C and CAT1D devices for Hyperflash/HyperRAM.
1216 **/
1217 uint32_t dummyCycles; /**< preferred dummy cycles per transaction */
1218 /** Determines if the device is memory-mapped, enables the Autodetect
1219 * using the SFDP, enables the write capability, or enables the crypto
1220 * support for this memory slave */
1221 uint32_t flags;
1222 #endif /* CY_IP_MXSMIF_VERSION */
1223 } cy_stc_smif_context_t;
1224
1225 /** \} group_smif_data_structures */
1226
1227
1228 /**
1229 * \addtogroup group_smif_low_level_functions
1230 * \{
1231 */
1232
1233 cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base, cy_stc_smif_config_t const *config,
1234 uint32_t timeout,
1235 cy_stc_smif_context_t *context);
1236 void Cy_SMIF_DeInit(SMIF_Type *base);
1237 void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect,
1238 cy_en_smif_data_select_t dataSelect);
1239 void Cy_SMIF_SetMode(SMIF_Type *base, cy_en_smif_mode_t mode);
1240 cy_en_smif_mode_t Cy_SMIF_GetMode(SMIF_Type const *base);
1241 cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
1242 uint8_t cmd,
1243 cy_en_smif_txfr_width_t cmdTxfrWidth,
1244 uint8_t const cmdParam[], uint32_t paramSize,
1245 cy_en_smif_txfr_width_t paramTxfrWidth,
1246 cy_en_smif_slave_select_t slaveSelect, uint32_t completeTxfr,
1247 cy_stc_smif_context_t const *context);
1248 cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base,
1249 uint8_t const *txBuffer, uint32_t size,
1250 cy_en_smif_txfr_width_t transferWidth,
1251 cy_smif_event_cb_t TxCompleteCb,
1252 cy_stc_smif_context_t *context);
1253 cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
1254 uint8_t const *txBuffer,
1255 uint32_t size,
1256 cy_en_smif_txfr_width_t transferWidth,
1257 cy_stc_smif_context_t const *context);
1258 cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base,
1259 uint8_t *rxBuffer, uint32_t size,
1260 cy_en_smif_txfr_width_t transferWidth,
1261 cy_smif_event_cb_t RxCompleteCb,
1262 cy_stc_smif_context_t *context);
1263 cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking(SMIF_Type *base,
1264 uint8_t *rxBuffer,
1265 uint32_t size,
1266 cy_en_smif_txfr_width_t transferWidth,
1267 cy_stc_smif_context_t const *context);
1268 cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base, uint32_t cycles);
1269 uint32_t Cy_SMIF_GetTransferStatus(SMIF_Type const *base, cy_stc_smif_context_t const *context);
1270 void Cy_SMIF_Enable(SMIF_Type *base, cy_stc_smif_context_t *context);
1271
1272 #if (CY_IP_MXSMIF_VERSION>=2) || defined (CY_DOXYGEN)
1273 cy_en_smif_status_t Cy_SMIF_TransmitCommand_Ext(SMIF_Type *base,
1274 uint16_t cmd,
1275 bool isCommand2byte,
1276 cy_en_smif_txfr_width_t cmdTxfrWidth,
1277 cy_en_smif_data_rate_t cmdDataRate,
1278 uint8_t const cmdParam[],
1279 uint32_t paramSize,
1280 cy_en_smif_txfr_width_t paramTxfrWidth,
1281 cy_en_smif_data_rate_t paramDataRate,
1282 cy_en_smif_slave_select_t slaveSelect,
1283 uint32_t completeTxfr,
1284 cy_stc_smif_context_t const *context);
1285
1286 cy_en_smif_status_t Cy_SMIF_TransmitData_Ext(SMIF_Type *base,
1287 uint8_t const *txBuffer,
1288 uint32_t size,
1289 cy_en_smif_txfr_width_t transferWidth,
1290 cy_en_smif_data_rate_t dataDataRate,
1291 cy_smif_event_cb_t TxCmpltCb,
1292 cy_stc_smif_context_t *context);
1293
1294 cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking_Ext(SMIF_Type *base,
1295 uint8_t const *txBuffer,
1296 uint32_t size,
1297 cy_en_smif_txfr_width_t transferWidth,
1298 cy_en_smif_data_rate_t dataDataRate,
1299 cy_stc_smif_context_t const *context);
1300
1301 cy_en_smif_status_t Cy_SMIF_ReceiveData_Ext(SMIF_Type *base,
1302 uint8_t *rxBuffer,
1303 uint32_t size,
1304 cy_en_smif_txfr_width_t transferWidth,
1305 cy_en_smif_data_rate_t dataRate,
1306 cy_smif_event_cb_t RxCmpltCb,
1307 cy_stc_smif_context_t *context);
1308
1309 cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking_Ext(SMIF_Type *base,
1310 uint8_t *rxBuffer,
1311 uint32_t size,
1312 cy_en_smif_txfr_width_t transferWidth,
1313 cy_en_smif_data_rate_t dataRate,
1314 cy_stc_smif_context_t const *context);
1315
1316 cy_en_smif_status_t Cy_SMIF_SendDummyCycles_Ext(SMIF_Type *base,
1317 cy_en_smif_txfr_width_t transferWidth,
1318 cy_en_smif_data_rate_t dataRate,
1319 uint32_t cycles);
1320 void Cy_SMIF_DeviceTransfer_SetMergeTimeout(SMIF_Type *base, cy_en_smif_slave_select_t slave, cy_en_smif_merge_timeout_t timeout);
1321 void Cy_SMIF_DeviceTransfer_ClearMergeTimeout(SMIF_Type *base, cy_en_smif_slave_select_t slave);
1322
1323 #if (CY_IP_MXSMIF_VERSION == 2U)
1324 cy_en_smif_status_t Cy_SMIF_Set_DelayTapSel(SMIF_Type *base, uint8_t tapSel);
1325 uint8_t Cy_SMIF_Get_DelayTapSel(SMIF_Type *base);
1326 #endif /* (CY_IP_MXSMIF_VERSION==2) */
1327 #endif /* CY_IP_MXSMIF_VERSION>=2*/
1328
1329 __STATIC_INLINE void Cy_SMIF_Disable(SMIF_Type *base);
1330 __STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt);
1331 __STATIC_INLINE uint32_t Cy_SMIF_GetInterruptMask(SMIF_Type const *base);
1332 __STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const *base);
1333 __STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatus(SMIF_Type const *base);
1334 __STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt);
1335 __STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt);
1336 __STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
1337 __STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level);
1338 __STATIC_INLINE uint32_t Cy_SMIF_GetCmdFifoStatus(SMIF_Type const *base);
1339 __STATIC_INLINE uint32_t Cy_SMIF_GetTxFifoStatus(SMIF_Type const *base);
1340 __STATIC_INLINE uint32_t Cy_SMIF_GetRxFifoStatus(SMIF_Type const *base);
1341 cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
1342 uint32_t address,
1343 uint8_t data[],
1344 uint32_t size,
1345 cy_stc_smif_context_t const *context);
1346 __STATIC_INLINE bool Cy_SMIF_BusyCheck(SMIF_Type const *base);
1347 __STATIC_INLINE void Cy_SMIF_Interrupt(SMIF_Type *base, cy_stc_smif_context_t *context);
1348 cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
1349 cy_en_smif_status_t Cy_SMIF_CacheDisable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
1350 cy_en_smif_status_t Cy_SMIF_CachePrefetchingEnable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
1351 cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base, cy_en_smif_cache_t cacheType);
1352 cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base, cy_en_smif_cache_t cacheType);
1353 void Cy_SMIF_SetCryptoKey(SMIF_Type *base, uint32_t *key);
1354 void Cy_SMIF_SetCryptoIV(SMIF_Type *base, uint32_t *nonce);
1355 cy_en_smif_status_t Cy_SMIF_SetCryptoEnable(SMIF_Type *base, cy_en_smif_slave_select_t slaveId);
1356 cy_en_smif_status_t Cy_SMIF_SetCryptoDisable(SMIF_Type *base, cy_en_smif_slave_select_t slaveId);
1357 cy_en_smif_status_t Cy_SMIF_ConvertSlaveSlotToIndex(cy_en_smif_slave_select_t ss, uint32_t *device_idx);
1358 #if (CY_IP_MXSMIF_VERSION>=5) || defined (CY_DOXYGEN)
1359 void Cy_SMIF_SetRxCaptureMode(SMIF_Type *base, cy_en_smif_capture_mode_t mode);
1360 cy_en_smif_status_t Cy_SMIF_SetMasterDLP(SMIF_Type *base, uint16 dlp, uint8_t size);
1361 uint16_t Cy_SMIF_GetMasterDLP(SMIF_Type *base);
1362 uint8_t Cy_SMIF_GetMasterDLPSize(SMIF_Type *base);
1363 uint8_t Cy_SMIF_GetTapNumCapturedCorrectDLP(SMIF_Type *base, uint8_t bit);
1364 #endif
1365 #if (CY_IP_MXSMIF_VERSION>=5) || defined (CY_DOXYGEN)
1366 void Cy_SMIF_SetSelectedDelayTapSel(SMIF_Type *base, cy_en_smif_slave_select_t slave,
1367 cy_en_smif_mem_data_line_t data_line, uint8_t tapSel);
1368 uint8_t Cy_SMIF_GetSelectedDelayTapSel(SMIF_Type *base, cy_en_smif_slave_select_t slave,
1369 cy_en_smif_mem_data_line_t data_line);
1370 #endif
1371 /** \addtogroup group_smif_functions_syspm_callback
1372 * The driver supports SysPm callback for Deep Sleep and Hibernate transition.
1373 * \{
1374 */
1375 #if defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
1376 cy_en_syspm_status_t Cy_SMIF_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
1377 cy_en_syspm_status_t Cy_SMIF_HibernateCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
1378 #endif
1379 /** \} */
1380
1381
1382 /***************************************
1383 * Internal SMIF function declarations
1384 ****************************************/
1385 /** \cond INTERNAL */
1386 __STATIC_INLINE void Cy_SMIF_PushTxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context); /**< Writes transmitted data into the FIFO. */
1387 __STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context); /**< Reads received data from the FIFO. */
1388 __STATIC_INLINE uint32_t Cy_SMIF_PackBytesArray(uint8_t const buff[], bool fourBytes);
1389 __STATIC_INLINE void Cy_SMIF_UnPackByteArray(uint32_t inValue, uint8_t outBuff[], bool fourBytes);
1390 __STATIC_INLINE cy_en_smif_status_t Cy_SMIF_TimeoutRun(uint32_t *timeoutUnits);
1391 __STATIC_INLINE SMIF_DEVICE_Type volatile * Cy_SMIF_GetDeviceBySlot(SMIF_Type *base,
1392 cy_en_smif_slave_select_t slaveSelect);
1393 /** \endcond */
1394
1395 /** \} group_smif_low_level_functions */
1396
1397
1398 /**
1399 * \addtogroup group_smif_low_level_functions
1400 * \{
1401 */
1402
1403 /*******************************************************************************
1404 * Function Name: Cy_SMIF_Disable
1405 ****************************************************************************//**
1406 *
1407 * Disables the operation of the SMIF block. The SMIF block can be disabled only
1408 * when it is not in the active state. Use the Cy_SMIF_BusyCheck() API to check
1409 * it before calling this API. Make sure the clock supplied to SMIF block is also
1410 * disabled before calling this API using \ref Cy_SysClk_ClkHfDisable
1411 *
1412 * \param base
1413 * Holds the base address of the SMIF block registers.
1414 *
1415 *******************************************************************************/
Cy_SMIF_Disable(SMIF_Type * base)1416 __STATIC_INLINE void Cy_SMIF_Disable(SMIF_Type *base)
1417 {
1418 SMIF_CTL(base) &= ~SMIF_CTL_ENABLED_Msk;
1419
1420 }
1421
1422
1423 /*******************************************************************************
1424 * Function Name: Cy_SMIF_SetInterruptMask
1425 ****************************************************************************//**
1426 *
1427 * This function is used to set an interrupt mask for the SMIF Interrupt.
1428 *
1429 * \param base
1430 * Holds the base address of the SMIF block registers.
1431 *
1432 * \param interrupt
1433 * This is the mask for different source options that can be masked. See
1434 * \ref group_smif_macros_isr "Interrupt Macros" for possible values.
1435 *
1436 *******************************************************************************/
Cy_SMIF_SetInterruptMask(SMIF_Type * base,uint32_t interrupt)1437 __STATIC_INLINE void Cy_SMIF_SetInterruptMask(SMIF_Type *base, uint32_t interrupt)
1438 {
1439 SMIF_INTR_MASK(base) = interrupt;
1440 }
1441
1442
1443 /*******************************************************************************
1444 * Function Name: Cy_SMIF_GetInterruptMask
1445 ****************************************************************************//**
1446 *
1447 * This function is used to read an interrupt mask for the SMIF Interrupt.
1448 *
1449 * \param base
1450 * Holds the base address of the SMIF block registers.
1451 *
1452 * \return Returns the mask set for the SMIF interrupt.
1453 *
1454 *******************************************************************************/
Cy_SMIF_GetInterruptMask(SMIF_Type const * base)1455 __STATIC_INLINE uint32_t Cy_SMIF_GetInterruptMask(SMIF_Type const *base)
1456 {
1457 return (SMIF_INTR_MASK(base));
1458 }
1459
1460
1461 /*******************************************************************************
1462 * Function Name: Cy_SMIF_GetInterruptStatusMasked
1463 ****************************************************************************//**
1464 *
1465 * This function is used to read an active masked interrupt. This function can
1466 * be used in the interrupt service-routine to find which source triggered the
1467 * interrupt.
1468 *
1469 * \param base
1470 * Holds the base address of the SMIF block registers.
1471 *
1472 * \return Returns a word with bits set at positions corresponding to the
1473 * interrupts triggered in the system.
1474 *
1475 *******************************************************************************/
Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const * base)1476 __STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatusMasked(SMIF_Type const *base)
1477 {
1478 return (SMIF_INTR_MASKED(base));
1479 }
1480
1481
1482 /*******************************************************************************
1483 * Function Name: Cy_SMIF_GetInterruptStatus
1484 ****************************************************************************//**
1485 *
1486 * This function is used to read an active interrupt. This status is the unmasked
1487 * result, so will also show interrupts that will not generate active interrupts.
1488 *
1489 * \param base
1490 * Holds the base address of the SMIF block registers.
1491 *
1492 * \return Returns a word with bits set at positions corresponding to the
1493 * interrupts triggered in the system.
1494 *
1495 *******************************************************************************/
Cy_SMIF_GetInterruptStatus(SMIF_Type const * base)1496 __STATIC_INLINE uint32_t Cy_SMIF_GetInterruptStatus(SMIF_Type const *base)
1497 {
1498 return (SMIF_INTR(base));
1499 }
1500
1501
1502 /*******************************************************************************
1503 * Function Name: Cy_SMIF_SetInterrupt
1504 ****************************************************************************//**
1505 *
1506 * This function is used to set an interrupt source. This function can be used
1507 * to activate interrupts through the software.
1508 *
1509 * \note Interrupt sources set using this interrupt will generate interrupts only
1510 * if they are not masked.
1511 *
1512 * \param base
1513 * Holds the base address of the SMIF block registers.
1514 *
1515 * \param interrupt
1516 * An encoded integer with a bit set corresponding to the interrupt to be
1517 * triggered. See \ref group_smif_macros_isr "Interrupt Macros" for possible
1518 * values.
1519 *
1520 *******************************************************************************/
Cy_SMIF_SetInterrupt(SMIF_Type * base,uint32_t interrupt)1521 __STATIC_INLINE void Cy_SMIF_SetInterrupt(SMIF_Type *base, uint32_t interrupt)
1522 {
1523 SMIF_INTR_SET(base) = interrupt;
1524 }
1525
1526
1527 /*******************************************************************************
1528 * Function Name: Cy_SMIF_ClearInterrupt
1529 ****************************************************************************//**
1530 *
1531 * This function is used to clear an interrupt source. This function can be used
1532 * in the user code to clear all pending interrupts.
1533 *
1534 * \param base
1535 * Holds the base address of the SMIF block registers.
1536 *
1537 * \param interrupt
1538 * An encoded integer with a bit set corresponding to the interrupt that must
1539 * be cleared. See \ref group_smif_macros_isr "Interrupt Macros" for possible
1540 * values.
1541 *
1542 *******************************************************************************/
Cy_SMIF_ClearInterrupt(SMIF_Type * base,uint32_t interrupt)1543 __STATIC_INLINE void Cy_SMIF_ClearInterrupt(SMIF_Type *base, uint32_t interrupt)
1544 {
1545 SMIF_INTR(base) = interrupt;
1546
1547 /* Ensure that the initial Write has been flushed out to the hardware. */
1548 interrupt = SMIF_INTR(base);
1549 }
1550
1551
1552 /*******************************************************************************
1553 * Function Name: Cy_SMIF_SetTxFifoTriggerLevel()
1554 ****************************************************************************//**
1555 *
1556 * This function is used to set a trigger level for the TX FIFO. This value must
1557 * be an integer between 0 and 7. For the normal mode only.
1558 * The triggering is active when TX_DATA_FIFO_STATUS <= level.
1559 *
1560 * \param base
1561 * Holds the base address of the SMIF block registers.
1562 *
1563 * \param level
1564 * The trigger level to set (0-8).
1565 *
1566 *******************************************************************************/
Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type * base,uint32_t level)1567 __STATIC_INLINE void Cy_SMIF_SetTxFifoTriggerLevel(SMIF_Type *base, uint32_t level)
1568 {
1569 CY_ASSERT_L2(level <= CY_SMIF_MAX_TX_TR_LEVEL);
1570 SMIF_TX_DATA_FIFO_CTL(base) = level;
1571 }
1572
1573
1574 /*******************************************************************************
1575 * Function Name: Cy_SMIF_SetRxFifoTriggerLevel()
1576 ****************************************************************************//**
1577 *
1578 * This function is used to set a trigger level for the RX FIFO. This value must
1579 * be an integer between 0 and 7. For the normal mode only.
1580 * The triggering is active when RX_DATA_FIFOSTATUS > level.
1581 *
1582 * \param base
1583 * Holds the base address of the SMIF block registers.
1584 *
1585 * \param level
1586 * The trigger level to set(0-8).
1587 *
1588 *******************************************************************************/
Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type * base,uint32_t level)1589 __STATIC_INLINE void Cy_SMIF_SetRxFifoTriggerLevel(SMIF_Type *base, uint32_t level)
1590 {
1591 CY_ASSERT_L2(level <= CY_SMIF_MAX_RX_TR_LEVEL);
1592 SMIF_RX_DATA_FIFO_CTL(base) = level;
1593 }
1594
1595
1596 /*******************************************************************************
1597 * Function Name: Cy_SMIF_GetCmdFifoStatus()
1598 ****************************************************************************//**
1599 *
1600 * This function is used to read the status of the CMD FIFO.
1601 *
1602 * \param base
1603 * Holds the base address of the SMIF block registers.
1604 *
1605 * \return Returns the number of the entries in the CMD FIFO.
1606 *
1607 *******************************************************************************/
Cy_SMIF_GetCmdFifoStatus(SMIF_Type const * base)1608 __STATIC_INLINE uint32_t Cy_SMIF_GetCmdFifoStatus(SMIF_Type const *base)
1609 {
1610 #if (CY_IP_MXSMIF_VERSION>=3)
1611 return (_FLD2VAL(SMIF_TX_CMD_MMIO_FIFO_STATUS_USED4, SMIF_TX_CMD_MMIO_FIFO_STATUS(base)));
1612 #elif (CY_IP_MXSMIF_VERSION == 2)
1613 return (_FLD2VAL(SMIF_TX_CMD_FIFO_STATUS_USED4, SMIF_TX_CMD_FIFO_STATUS(base)));
1614 #else
1615 return (_FLD2VAL(SMIF_TX_CMD_FIFO_STATUS_USED3, SMIF_TX_CMD_FIFO_STATUS(base)));
1616 #endif /* CY_IP_MXSMIF_VERSION */
1617 }
1618
1619
1620 /*******************************************************************************
1621 * Function Name: Cy_SMIF_GetTxFifoStatus()
1622 ****************************************************************************//**
1623 *
1624 * This function is used to read the status of the TX FIFO.
1625 *
1626 * \param base
1627 * Holds the base address of the SMIF block registers.
1628 *
1629 * \return Returns the number of the entries in the TX FIFO.
1630 *
1631 *******************************************************************************/
Cy_SMIF_GetTxFifoStatus(SMIF_Type const * base)1632 __STATIC_INLINE uint32_t Cy_SMIF_GetTxFifoStatus(SMIF_Type const *base)
1633 {
1634 #if (CY_IP_MXSMIF_VERSION>=3)
1635 return (_FLD2VAL(SMIF_TX_DATA_MMIO_FIFO_STATUS_USED4, SMIF_TX_DATA_MMIO_FIFO_STATUS(base)));
1636 #else
1637 return (_FLD2VAL(SMIF_TX_DATA_FIFO_STATUS_USED4, SMIF_TX_DATA_FIFO_STATUS(base)));
1638 #endif /* CY_IP_MXSMIF_VERSION */
1639 }
1640
1641
1642 /*******************************************************************************
1643 * Function Name: Cy_SMIF_GetRxFifoStatus()
1644 ****************************************************************************//**
1645 *
1646 * This function is used to read the status of the RX FIFO.
1647 *
1648 * \param base
1649 * Holds the base address of the SMIF block registers.
1650 *
1651 * \return Returns the number of the entries in the RX FIFO.
1652 *
1653 *******************************************************************************/
Cy_SMIF_GetRxFifoStatus(SMIF_Type const * base)1654 __STATIC_INLINE uint32_t Cy_SMIF_GetRxFifoStatus(SMIF_Type const *base)
1655 {
1656 #if (CY_IP_MXSMIF_VERSION>=2)
1657 return (_FLD2VAL(SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4, SMIF_RX_DATA_MMIO_FIFO_STATUS(base)));
1658 #else
1659 return (_FLD2VAL(SMIF_RX_DATA_FIFO_STATUS_USED4, SMIF_RX_DATA_FIFO_STATUS(base)));
1660 #endif /* CY_IP_MXSMIF_VERSION */
1661 }
1662
1663
1664 /*******************************************************************************
1665 * Function Name: Cy_SMIF_BusyCheck
1666 ****************************************************************************//**
1667 *
1668 * This function provides the status of the IP block (False - not busy,
1669 * True - busy).
1670 *
1671 * \param base
1672 * Holds the base address of the SMIF block registers.
1673 *
1674 * \return Returns an IP block status.
1675 *
1676 *******************************************************************************/
Cy_SMIF_BusyCheck(SMIF_Type const * base)1677 __STATIC_INLINE bool Cy_SMIF_BusyCheck(SMIF_Type const *base)
1678 {
1679 return (1UL == _FLD2VAL(SMIF_STATUS_BUSY, SMIF_STATUS(base)));
1680 }
1681
1682
1683 /*******************************************************************************
1684 * Function Name: Cy_SMIF_Interrupt
1685 ****************************************************************************//**
1686 *
1687 * The Interrupt Service Routine for the SMIF. The interrupt code will be
1688 * responsible for the FIFO operations on FIFO interrupts during ongoing transfers.
1689 * The user must place a call to this interrupt function in the interrupt
1690 * routine corresponding to the interrupt attached to the SMIF. If the
1691 * user does not do this, will break: the functionality of all the API functions in
1692 * the SMIF driver that use SMIF interrupts to affect transfers.
1693 *
1694 * \param base
1695 * Holds the base address of the SMIF block registers.
1696 *
1697 * \param context
1698 * Passes a configuration structure that contains the transfer parameters of the
1699 * SMIF block.
1700 *
1701 * \globalvars
1702 * - context->txBufferAddress - The pointer to the data to be transferred.
1703 *
1704 * - context->txBufferSize - The size of txBuffer.
1705 *
1706 * - context->txBufferCounter - The number of data entries left to be transferred.
1707 *
1708 * All the Global variables described above are used when the Software Buffer is
1709 * used.
1710 *
1711 *******************************************************************************/
Cy_SMIF_Interrupt(SMIF_Type * base,cy_stc_smif_context_t * context)1712 __STATIC_INLINE void Cy_SMIF_Interrupt(SMIF_Type *base, cy_stc_smif_context_t *context)
1713 {
1714 uint32_t interruptStatus = Cy_SMIF_GetInterruptStatusMasked(base);
1715
1716 /* Check which interrupt occurred */
1717 if (0U != (interruptStatus & SMIF_INTR_TR_TX_REQ_Msk))
1718 {
1719 /* Send data */
1720 Cy_SMIF_PushTxFifo(base, context);
1721
1722 Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TR_TX_REQ_Msk);
1723 }
1724 else if (0U != (interruptStatus & SMIF_INTR_TR_RX_REQ_Msk))
1725 {
1726 /* Receive data */
1727 Cy_SMIF_PopRxFifo(base, context);
1728
1729 Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TR_RX_REQ_Msk);
1730 }
1731 else if (0U != (interruptStatus & SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk))
1732 {
1733 /* An XIP alignment error */
1734 context->transferStatus = (uint32_t) CY_SMIF_XIP_ERROR;
1735
1736 Cy_SMIF_ClearInterrupt(base, SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk);
1737 }
1738
1739 else if (0U != (interruptStatus & SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk))
1740 {
1741 /* TX CMD FIFO overflow */
1742 context->transferStatus = (uint32_t) CY_SMIF_CMD_ERROR;
1743
1744 Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk);
1745 }
1746
1747 else if (0U != (interruptStatus & SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk))
1748 {
1749 /* A TX DATA FIFO overflow */
1750 context->transferStatus = (uint32_t) CY_SMIF_TX_ERROR;
1751
1752 Cy_SMIF_ClearInterrupt(base, SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk);
1753 }
1754
1755 else if (0U != (interruptStatus & SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk))
1756 {
1757 /* RX DATA FIFO underflow */
1758 context->transferStatus = (uint32_t) CY_SMIF_RX_ERROR;
1759
1760 Cy_SMIF_ClearInterrupt(base, SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk);
1761 }
1762 else
1763 {
1764 /* Processing of errors */
1765 }
1766 }
1767
1768
1769 /*******************************************************************************
1770 * Internal SMIF in-line functions
1771 *******************************************************************************/
1772
1773 /** \cond INTERNAL */
1774
1775 /*******************************************************************************
1776 * Function Name: Cy_SMIF_PushTxFifo
1777 ***************************************************************************//***
1778 *
1779 * \internal
1780 *
1781 * \param baseaddr
1782 * Holds the base address of the SMIF block registers.
1783 *
1784 * \param context
1785 * Passes a configuration structure that contains the transfer parameters of the
1786 * SMIF block.
1787 *
1788 * This function writes data in the TX FIFO SMIF buffer by 4, 2, or 1 bytes based
1789 * on the residual number of bytes and the available space in the TX FIFO.
1790 *
1791 *******************************************************************************/
Cy_SMIF_PushTxFifo(SMIF_Type * baseaddr,cy_stc_smif_context_t * context)1792 __STATIC_INLINE void Cy_SMIF_PushTxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context)
1793 {
1794 /* The variable that shows which is smaller: the free FIFO size or amount of bytes to be sent */
1795 uint32_t writeBytes;
1796 uint32_t freeFifoBytes;
1797 uint32_t buffCounter = context->txBufferCounter;
1798 uint8_t *buff = (uint8_t*) context->txBufferAddress;
1799
1800 freeFifoBytes = CY_SMIF_TX_DATA_FIFO_STATUS_RANGE - Cy_SMIF_GetTxFifoStatus(baseaddr);
1801 writeBytes = (freeFifoBytes > buffCounter)? buffCounter: freeFifoBytes;
1802
1803 /* Check that after a FIFO Write, no data/FIFO space remains */
1804 while (0U != writeBytes)
1805 {
1806 /* The first main use case for long transfers */
1807 if (writeBytes == CY_SMIF_EIGHT_BYTES)
1808 {
1809 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
1810 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], true);
1811 }
1812 /* The second main use case for short transfers */
1813 else if(writeBytes == CY_SMIF_ONE_BYTE)
1814 {
1815 #if (CY_IP_MXSMIF_VERSION>=2)
1816 if((context->preCmdDataRate == CY_SMIF_DDR) &&(context->preCmdWidth == CY_SMIF_WIDTH_OCTAL))
1817 {
1818 SMIF_TX_DATA_MMIO_FIFO_WR1ODD(baseaddr) = buff[0U];
1819 }
1820 else
1821 {
1822 SMIF_TX_DATA_MMIO_FIFO_WR1(baseaddr) = buff[0U];
1823 }
1824 #else
1825 SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[0U];
1826 #endif /* CY_IP_MXSMIF_VERSION */
1827 }
1828 else if(writeBytes == CY_SMIF_TWO_BYTES)
1829 {
1830 SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], false);
1831 }
1832 else if(writeBytes == CY_SMIF_THREE_BYTES)
1833 {
1834 SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], false);
1835 SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[2U];
1836 }
1837 else if(writeBytes == CY_SMIF_FOUR_BYTES)
1838 {
1839 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
1840 }
1841 else if(writeBytes == CY_SMIF_FIVE_BYTES)
1842 {
1843 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
1844 SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[4U];
1845 }
1846 else if(writeBytes == CY_SMIF_SIX_BYTES)
1847 {
1848 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
1849 SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], false);
1850 }
1851 else if(writeBytes == CY_SMIF_SEVEN_BYTES)
1852 {
1853 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
1854 SMIF_TX_DATA_FIFO_WR2(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], false);
1855 SMIF_TX_DATA_FIFO_WR1(baseaddr) = buff[6U];
1856 }
1857 else /* The future IP block with FIFO > 8*/
1858 {
1859 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[0U], true);
1860 SMIF_TX_DATA_FIFO_WR4(baseaddr) = Cy_SMIF_PackBytesArray(&buff[4U], true);
1861 writeBytes = CY_SMIF_EIGHT_BYTES;
1862 }
1863 buff = &buff[writeBytes];
1864 buffCounter -= writeBytes;
1865 /* Check if we already got new data in TX_FIFO */
1866 freeFifoBytes = CY_SMIF_TX_DATA_FIFO_STATUS_RANGE - Cy_SMIF_GetTxFifoStatus(baseaddr);
1867 writeBytes = (freeFifoBytes > buffCounter)? buffCounter: freeFifoBytes;
1868 }
1869
1870 /* Save changes in the context */
1871 context->txBufferAddress = buff;
1872 context->txBufferCounter = buffCounter;
1873
1874 /* Check if all bytes are sent */
1875 if (0u == buffCounter)
1876 {
1877 #if (CY_IP_MXSMIF_VERSION >= 5) /* DRIVERS-12031 */
1878 Cy_SMIF_SetTxFifoTriggerLevel(baseaddr, 0U);
1879 #endif
1880
1881 /* Disable the TR_TX_REQ interrupt */
1882 Cy_SMIF_SetInterruptMask(baseaddr, Cy_SMIF_GetInterruptMask(baseaddr) & ~SMIF_INTR_TR_TX_REQ_Msk);
1883
1884 context->transferStatus = (uint32_t) CY_SMIF_SEND_COMPLETE;
1885 if (NULL != context->txCompleteCb)
1886 {
1887 context->txCompleteCb((uint32_t) CY_SMIF_SEND_COMPLETE);
1888 }
1889 }
1890 }
1891
1892
1893 /*******************************************************************************
1894 * Function Name: Cy_SMIF_PopRxFifo
1895 ***************************************************************************//***
1896 *
1897 * \internal
1898 *
1899 * \param baseaddr
1900 * Holds the base address of the SMIF block registers.
1901 *
1902 * \param context
1903 * Passes a configuration structure that contains the transfer parameters of the
1904 * SMIF block.
1905 *
1906 * This function reads data from the RX FIFO SMIF buffer by 4, 2, or 1 bytes
1907 * based on the data availability in the RX FIFO and amount of bytes to be
1908 * received.
1909 *
1910 *******************************************************************************/
Cy_SMIF_PopRxFifo(SMIF_Type * baseaddr,cy_stc_smif_context_t * context)1911 __STATIC_INLINE void Cy_SMIF_PopRxFifo(SMIF_Type *baseaddr, cy_stc_smif_context_t *context)
1912 {
1913 /* The variable that shows which is smaller: the free FIFO size or amount of bytes to be received */
1914 uint32_t readBytes;
1915 uint32_t loadedFifoBytes;
1916 uint32_t buffCounter = context->rxBufferCounter;
1917 uint8_t *buff = (uint8_t*) context->rxBufferAddress;
1918
1919 loadedFifoBytes = Cy_SMIF_GetRxFifoStatus(baseaddr);
1920 readBytes = (loadedFifoBytes > buffCounter)? buffCounter: loadedFifoBytes;
1921
1922 /* Check that after a FIFO Read, no new data is available */
1923 while (0U != readBytes)
1924 {
1925 if (readBytes == CY_SMIF_EIGHT_BYTES)
1926 {
1927 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
1928 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[4U], true);
1929 }
1930 else if(readBytes == CY_SMIF_ONE_BYTE)
1931 {
1932 buff[0U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
1933 }
1934 else if(readBytes == CY_SMIF_TWO_BYTES)
1935 {
1936 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[0U], false);
1937 }
1938 else if(readBytes == CY_SMIF_THREE_BYTES)
1939 {
1940 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[0U], false);
1941 buff[2U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
1942 }
1943 else if(readBytes == CY_SMIF_FOUR_BYTES)
1944 {
1945 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
1946 }
1947 else if(readBytes == CY_SMIF_FIVE_BYTES)
1948 {
1949 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
1950 buff[4U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
1951 }
1952 else if(readBytes == CY_SMIF_SIX_BYTES)
1953 {
1954 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
1955 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[4U], false);
1956 }
1957 else if(readBytes == CY_SMIF_SEVEN_BYTES)
1958 {
1959 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
1960 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD2(baseaddr), &buff[4U], false);
1961 buff[6U] = (uint8_t)SMIF_RX_DATA_FIFO_RD1(baseaddr);
1962 }
1963 else /* The IP block FIFO > 8*/
1964 {
1965 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[0U], true);
1966 Cy_SMIF_UnPackByteArray(SMIF_RX_DATA_FIFO_RD4(baseaddr), &buff[4U], true);
1967 readBytes = CY_SMIF_EIGHT_BYTES;
1968 }
1969
1970 buff = &buff[readBytes];
1971 buffCounter -= readBytes;
1972 /* Check if we already got new data in RX_FIFO */
1973 loadedFifoBytes = Cy_SMIF_GetRxFifoStatus(baseaddr);
1974 readBytes = (loadedFifoBytes > buffCounter)? buffCounter: loadedFifoBytes;
1975 }
1976
1977 /* Save changes in the context */
1978 context->rxBufferAddress = buff;
1979 context->rxBufferCounter = buffCounter;
1980
1981 /* Check if all bytes are received */
1982 if (0UL == buffCounter)
1983 {
1984 /* Disable the TR_RX_REQ interrupt */
1985 Cy_SMIF_SetInterruptMask(baseaddr, Cy_SMIF_GetInterruptMask(baseaddr) & ~SMIF_INTR_TR_RX_REQ_Msk);
1986 context->transferStatus = (uint32_t) CY_SMIF_RX_COMPLETE;
1987 if (NULL != context->rxCompleteCb)
1988 {
1989 context->rxCompleteCb((uint32_t) CY_SMIF_RX_COMPLETE);
1990 }
1991 }
1992
1993 context->rxBufferCounter = buffCounter;
1994 }
1995
1996
1997 /*******************************************************************************
1998 * Function Name: Cy_SMIF_PackBytesArray
1999 ***************************************************************************//***
2000 *
2001 * \internal
2002 *
2003 * This function packs 0-numBytes of the buff byte array into a 4-byte value.
2004 *
2005 * \param buff
2006 * The byte array to pack.
2007 *
2008 * \param fourBytes
2009 * - True: The pack is for a 32-bit value.
2010 * - False: The pack is for a 16-bit value.
2011 *
2012 * \return
2013 * The 4-byte value packed from the byte array.
2014 *
2015 *******************************************************************************/
Cy_SMIF_PackBytesArray(uint8_t const buff[],bool fourBytes)2016 __STATIC_INLINE uint32_t Cy_SMIF_PackBytesArray(uint8_t const buff[], bool fourBytes)
2017 {
2018 uint32_t result = 0UL;
2019
2020 result = ((uint32_t)buff[1UL] << 8UL) | (uint32_t)buff[0UL];
2021
2022 if(fourBytes)
2023 {
2024 result |= ((uint32_t)buff[3UL] << 24UL) | ((uint32_t)buff[2UL] << 16UL);
2025 }
2026
2027 return result;
2028 }
2029
2030
2031 /*******************************************************************************
2032 * Function Name: Cy_SMIF_UnPackByteArray
2033 ***************************************************************************//***
2034 *
2035 * \internal
2036 *
2037 * This function unpacks 0-numBytes from a 4-byte value into the byte array outBuff.
2038 *
2039 * \param smifReg
2040 * The 4-byte value to unpack.
2041 *
2042 * \param outBuff
2043 * The byte array to fill.
2044 *
2045 * \param fourBytes
2046 * - The True unpack is for a 32-bit value.
2047 * - The False unpack is for a 16-bit value.
2048 *
2049 *******************************************************************************/
Cy_SMIF_UnPackByteArray(uint32_t inValue,uint8_t outBuff[],bool fourBytes)2050 __STATIC_INLINE void Cy_SMIF_UnPackByteArray(uint32_t inValue, uint8_t outBuff[], bool fourBytes)
2051 {
2052 outBuff[0UL] = (uint8_t)(inValue & 0xFFUL);
2053 outBuff[1UL] = (uint8_t)((inValue >> 8UL ) & 0xFFUL);
2054
2055 if(fourBytes)
2056 {
2057 outBuff[2UL] = (uint8_t)((inValue >> 16UL) & 0xFFUL);
2058 outBuff[3UL] = (uint8_t)((inValue >> 24UL) & 0xFFUL);
2059 }
2060 }
2061
2062
2063 /*******************************************************************************
2064 * Function Name: Cy_SMIF_TimeoutRun
2065 ****************************************************************************//**
2066 *
2067 * \internal
2068 *
2069 * This function checks if the timeout is expired. Use the Cy_SysLib_DelayUs() function for
2070 * implementation.
2071 *
2072 * \param timeoutUnits
2073 * The pointer to the timeout. The timeout measured in microseconds is multiplied by
2074 * CY_SMIF_WAIT_1_UNIT.
2075 *
2076 * \return
2077 * A timeout status:
2078 * - \ref CY_SMIF_SUCCESS - The timeout has not expired or input timeoutUnits is 0.
2079 * - \ref CY_SMIF_EXCEED_TIMEOUT - The timeout has expired.
2080 *
2081 *******************************************************************************/
Cy_SMIF_TimeoutRun(uint32_t * timeoutUnits)2082 __STATIC_INLINE cy_en_smif_status_t Cy_SMIF_TimeoutRun(uint32_t *timeoutUnits)
2083 {
2084 cy_en_smif_status_t status = CY_SMIF_SUCCESS;
2085 if (*timeoutUnits > 0u)
2086 {
2087 Cy_SysLib_DelayUs(CY_SMIF_WAIT_1_UNIT);
2088 --(*timeoutUnits);
2089 status = (0u == (*timeoutUnits))? CY_SMIF_EXCEED_TIMEOUT: CY_SMIF_SUCCESS;
2090 }
2091 return status;
2092 }
2093
2094
2095 /*******************************************************************************
2096 * Function Name: Cy_SMIF_GetDeviceBySlot
2097 ****************************************************************************//**
2098 *
2099 * \internal
2100 * This function returns the address of the SMIF device registers structure by the slave
2101 * slot number.
2102 *
2103 * \param base
2104 * Holds the base address of the SMIF block registers.
2105 *
2106 * \param slaveSelect
2107 * The slave device ID. This number is either CY_SMIF_SLAVE_SELECT_0 or
2108 * CY_SMIF_SLAVE_SELECT_1 or CY_SMIF_SLAVE_SELECT_2 or CY_SMIF_SLAVE_SELECT_3
2109 * (\ref cy_en_smif_slave_select_t). It defines the slave-select line to use
2110 * during the transmission.
2111 *
2112 *******************************************************************************/
Cy_SMIF_GetDeviceBySlot(SMIF_Type * base,cy_en_smif_slave_select_t slaveSelect)2113 __STATIC_INLINE SMIF_DEVICE_Type volatile * Cy_SMIF_GetDeviceBySlot(SMIF_Type *base,
2114 cy_en_smif_slave_select_t slaveSelect)
2115 {
2116 SMIF_DEVICE_Type volatile *device;
2117 /* Connect the slave to its data lines */
2118 switch (slaveSelect)
2119 {
2120 case CY_SMIF_SLAVE_SELECT_0:
2121 device = &(SMIF_DEVICE_IDX(base, 0));
2122 break;
2123 case CY_SMIF_SLAVE_SELECT_1:
2124 device = &(SMIF_DEVICE_IDX(base, 1));
2125 break;
2126 case CY_SMIF_SLAVE_SELECT_2:
2127 device = &(SMIF_DEVICE_IDX(base, 2));
2128 break;
2129 case CY_SMIF_SLAVE_SELECT_3:
2130 device = &(SMIF_DEVICE_IDX(base, 3));
2131 break;
2132 default:
2133 /* A user error */
2134 device = NULL;
2135 break;
2136 }
2137
2138 return device;
2139 }
2140 /** \endcond */
2141 /** \} group_smif_low_level_functions */
2142
2143 #if defined(__cplusplus)
2144 }
2145 #endif
2146
2147 #endif /* CY_IP_MXSMIF */
2148
2149 #endif /* (CY_SMIF_H) */
2150
2151 /** \} group_smif */
2152
2153
2154 /* [] END OF FILE */
2155
