1 /***************************************************************************//**
2 * \file cy_scb_common.h
3 * \version 3.20
4 *
5 * Provides common API declarations of the SCB driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_scb
27 * \{
28 * The Serial Communications Block (SCB) supports three serial communication
29 * protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver
30 * Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of
31 * the protocols is supported by an SCB at any given time.
32 *
33 * The functions and other declarations used in this driver are in cy_scb_spi.h,
34 * cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h
35 * to get access to all functions and declarations in the PDL.
36
37 * \defgroup group_scb_common Common
38 * \defgroup group_scb_ezi2c EZI2C (SCB)
39 * \defgroup group_scb_i2c I2C (SCB)
40 * \defgroup group_scb_spi SPI (SCB)
41 * \defgroup group_scb_uart UART (SCB)
42 * \} */
43
44 /**
45 * \addtogroup group_scb
46 * \{
47 *
48 ********************************************************************************
49 * \section group_scb_more_information More Information
50 ********************************************************************************
51 * For more information on the SCB peripheral, refer to the technical reference
52 * manual (TRM).
53 *
54 *******************************************************************************
55 * \section group_scb_common_changelog Changelog
56 *******************************************************************************
57 * <table class="doxtable">
58 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
59 * <tr>
60 * <td rowspan="2">3.20</td>
61 * <td>Added APIs \ref Cy_SCB_UART_EnableSingleWireHalfDuplex, \ref Cy_SCB_UART_DisableSingleWireHalfDuplex.
62 * - Updated struct \ref cy_stc_scb_uart_config_t.
63 * </td>
64 * <td>UART half duplex mode implementation. Bug fixes.</td>
65 * </tr>
66 * <tr>
67 * <td>Added API \ref Cy_SCB_SPI_Transfer_Buffer and new macros.
68 * - Updated struct \ref cy_stc_scb_spi_context_t.</td>
69 * <td>Added support for SPI transfer with different length and bug fixes for buffer transfer with different sizes.</td>
70 * </tr>
71 * <tr>
72 * <td>3.10.1</td>
73 * <td>Minor documentation updates.</td>
74 * <td>Documentation enhancement.</td>
75 * </tr>
76 * <tr>
77 * <td>3.10</td>
78 * <td>Fixed MISRA 2012 violations.</td>
79 * <td>MISRA 2012 compliance.</td>
80 * </tr>
81 * <tr>
82 * <td rowspan="2">3.0</td>
83 * <td>Updated \ref Cy_SCB_SPI_Init and other internal data handling functions to handle wide range of data widths.</td>
84 * <td>Defect fixing.</td>
85 * </tr>
86 * <tr>
87 * <td>Minor documentation updates.</td>
88 * <td>Documentation enhancement.</td>
89 * </tr>
90 * <tr>
91 * <td rowspan="2">2.90</td>
92 * <td>A new API, \ref Cy_SCB_SetEzI2CMode, has been added to help set the hardware EZ mode for the I2C protocol.</td>
93 * <td>The HW EZ Mode for the I2C protocol can be enabled or disabled.</td>
94 * </tr>
95 * <tr>
96 * <td>Newly added APIs \ref Cy_SCB_I2C_SetStretchThreshold to set the stretch threshold value,
97 * \ref Cy_SCB_I2C_GetStretchCount to get the stretch count,
98 * \ref Cy_SCB_I2C_IsStretchDetected to detect if I2C SCL is stretched,
99 * \ref Cy_SCB_I2C_IsSyncDetected to check if synchronization is detected on I2C SCL.
100 * \ref Cy_SCB_I2C_IsStretching to check if DUT is stretching the I2C SCL.</td>
101 * <td>New device support.</td>
102 * </tr>
103 * <tr>
104 * <td>2.80</td>
105 * <td>Updated the behaviour of \ref Cy_SCB_UART_SetEnableMsbFirst and \ref Cy_SCB_UART_GetEnableMsbFirst functions.
106 * Now the value of enableMsbFirst is being set and fetched correctly.
107 * <td>Defect fixing.</td>
108 * </tr>
109 * <tr>
110 * <td rowspan="2">2.70</td>
111 * <td>Newly added API's for runtime parameter set/get functionality which include
112 * \ref Cy_SCB_UART_SetOverSample to set oversample bits of UART,
113 * \ref Cy_SCB_UART_GetOverSample to add return value of oversample,
114 * \ref Cy_SCB_UART_GetDataWidth to get data width,
115 * \ref Cy_SCB_UART_SetDataWidth to set data width,
116 * \ref Cy_SCB_UART_GetParity to get parity,
117 * \ref Cy_SCB_UART_SetParity to set parity,
118 * \ref Cy_SCB_UART_GetStopBits to get stop bits,
119 * \ref Cy_SCB_UART_SetStopBits to set stop bits,
120 * \ref Cy_SCB_UART_GetDropOnParityError to get drop on parity error,
121 * \ref Cy_SCB_UART_SetDropOnParityError to set drop on parity error,
122 * \ref Cy_SCB_UART_GetEnableMsbFirst to get enable MSB first and
123 * \ref Cy_SCB_UART_SetEnableMsbFirst to set enable MSB first.</td>
124 * <td>Runtime Parameter update.</td>
125 * </tr>
126 * <tr>
127 * <td>Newly added API's which include
128 * \ref Cy_SCB_Get_RxDataWidth to return the RX data width,
129 * \ref Cy_SCB_Get_TxDataWidth to return the TX data width,
130 * \ref Cy_SCB_SetMemWidth to set the RX and TX FIFOs byte mode/halfword/word mode.
131 * Updated Structures \ref cy_stc_scb_uart_config_t, \ref cy_en_scb_spi_parity_t, \ref cy_stc_scb_spi_config_t.</td>
132 * <td>New device support.</td>
133 * </tr>
134 * <tr>
135 * <td rowspan="2">2.60</td>
136 * <td>Fixed the \ref Cy_SCB_UART_GetNumInRingBuffer function to
137 * return correct number of the elements in ring buffer.</td>
138 * <td> \ref Cy_SCB_UART_GetNumInRingBuffer function works incorrectly, when
139 * write pointer of the ring buffer is behind the read pointer.</td>
140 * </tr>
141 * <tr>
142 * <td>Fixed/Documented MISRA 2012 violations.</td>
143 * <td>MISRA 2012 compliance.</td>
144 * </tr>
145 * <tr>
146 * <td>2.50</td>
147 * <td>Fixed the \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function to
148 * properly configure the polarity of the slave select line.</td>
149 * <td> \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function works incorrectly.</td>
150 * </tr>
151 * <tr>
152 * <td>2.40.2</td>
153 * <td>Minor documentation updates.</td>
154 * <td>Documentation enhancement.</td>
155 * </tr>
156 * <tr>
157 * <td rowspan="2">2.40</td>
158 * <td>Update level selection logic of RX FIFO trigger in the Cy_SCB_UART_Receive().</td>
159 * <td>Fix possible stuck if the RTS level is less than the RX FIFO level.</td>
160 * </tr>
161 * <tr>
162 * <td>Exclude self-test assertion macros under release build profile.</td>
163 * <td>Avoid dependency on CY_ASSERT macro implementation.</td>
164 * </tr>
165 * <tr>
166 * <td>2.30.1</td>
167 * <td>Added header guards CY_IP_MXSCB.</td>
168 * <td>To enable the PDL compilation with wounded out IP blocks.</td>
169 * </tr>
170 * <tr>
171 * <td rowspan="5">2.30</td>
172 * <td>Fixed MISRA violation.</td>
173 * <td>MISRA compliance.</td>
174 * </tr>
175 * <tr>
176 * <td>Changed values CY_SCB_SPI_CPHA0_CPOL1 and CY_SCB_SPI_CPHA1_CPOL0 in enum \ref cy_en_scb_spi_sclk_mode_t.</td>
177 * <td>The incorrect values in \ref cy_en_scb_spi_sclk_mode_t caused incorrect initialization of the combination of
178 * phases and polarity: "CHPA = 0, CPOL = 1" and "CHPA = 1, CPOL = 0".
179 * </td>
180 * </tr>
181 * <tr>
182 * <td>Added new CY_SCB_UART_RECEIVE_NOT_EMTPY and CY_SCB_UART_TRANSMIT_EMTPY callback events \ref group_scb_uart_macros_callback_events.</td>
183 * <td>Extended the driver callback events to support the MBED-OS.</td>
184 * </tr>
185 * <tr>
186 * <td>Merged SCB changelogs for each mode into one changelog.</td>
187 * <td>Changelog optimization.</td>
188 * </tr>
189 * <tr>
190 * <td>Merged SCB MISRA-C Compliance sections for each mode into one section.</td>
191 * <td>To optimize the SCB MISRA-C Compliance sections.</td>
192 * </tr>
193 * <tr>
194 * <td> 2.20.1</td>
195 * <td>Documentation of the MISRA rule violation.</td>
196 * <td>MISRA compliance.</td>
197 * </tr>
198 * <tr>
199 * <td rowspan="4">2.20</td>
200 * <td>Flattened the organization of the driver source code into the single
201 * source directory and the single include directory.
202 * </td>
203 * <td>Driver library directory-structure simplification.</td>
204 * </tr>
205 * <tr>
206 * <td>Added register access layer. Use register access macros instead
207 * of direct register access using dereferenced pointers.</td>
208 * <td>Makes register access device-independent, so that the PDL does
209 * not need to be recompiled for each supported part number.</td>
210 * </tr>
211 * <tr>
212 * <td>Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle
213 * fields to the \ref cy_stc_scb_i2c_config_t configuration structure.
214 * </td>
215 * <td>Added the I2C master data rate configuration using the configuration structure.
216 * </td>
217 * </tr>
218 * <tr>
219 * <td>Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates
220 * greater than 400 kbps in Master and Master-Slave modes. \n
221 * Added verification that clk_scb is within the valid range for the desired data rate.
222 * </td>
223 * <td>The analog filter was enabled for all data rates in Master and Master-Slave modes.
224 * This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter.
225 * </td>
226 * </tr>
227 * <tr>
228 * <td rowspan="4"> 2.10</td>
229 * <td>Fixed the ReStart condition generation sequence for a write
230 * transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
231 * <td>The driver can notify about a zero length write transaction completion
232 * before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
233 * function execution was interrupted between setting the restart
234 * generation command and writing the address byte into the TX FIFO.</td>
235 * </tr>
236 * <tr>
237 * <td>Added the slave- and master-specific interrupt functions:
238 * \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt.
239 * </td>
240 * <td>Improved the interrupt configuration options for the I2C slave and
241 * master mode configurations.</td>
242 * </tr>
243 * <tr>
244 * <td>Updated the Start condition generation sequence in the \ref
245 * Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
246 * <td></td>
247 * </tr>
248 * <tr>
249 * <td>Updated the ReStart condition generation sequence for a write
250 * transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.</td>
251 * <td></td>
252 * </tr>
253 * <tr>
254 * <td rowspan="9"> 2.0</td>
255 * <td>Added parameters validation for public API.
256 * <td></td>
257 * </tr>
258 * <tr>
259 * <td>Fixed functions which return interrupt status to return only defined
260 * set of interrupt statuses.</td>
261 * <td></td>
262 * </tr>
263 * <tr>
264 * <td>Added missing "cy_cb_" to the callback function type names.</td>
265 * <td></td>
266 * </tr>
267 * <tr>
268 * <td>Replaced variables that have limited range of values with enumerated
269 * types.</td>
270 * <td></td>
271 * </tr>
272 * <tr>
273 * <td>Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition
274 * generation.</td>
275 * <td></td>
276 * </tr>
277 * <tr>
278 * <td>Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and
279 * \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering
280 * low power mode when RX FIFO is not empty.</td>
281 * <td>The callbacks allowed entering device into low power mode when RX FIFO
282 * had data.</td>
283 * </tr>
284 * <tr>
285 * <td>Fixed SPI callback notification when error event occurred.</td>
286 * <td>The SPI callback passed incorrect event value if error event occurred.</td>
287 * </tr>
288 * <tr>
289 * <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
290 * generate the ReStart condition when the previous transaction was
291 * a write.</td>
292 * <td>The master interpreted the address byte written into the TX FIFO as a
293 * data byte and continued a write transaction. The ReStart condition was
294 * generated after the master completed transferring the data byte.
295 * The SCL line was stretched by the master waiting for the address byte
296 * to be written into the TX FIFO after the ReStart condition generation.
297 * The following timeout detection released the bus from the master
298 * control.</td>
299 * </tr>
300 * <tr>
301 * <td>Fixed the slave operation after the address byte was NACKed by the
302 * firmware.</td>
303 * <td>The observed slave operation failure depends on whether Level 2 assert
304 * is enabled or not. Enabled: the device stuck in the fault handler due
305 * to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
306 * the slave sets the transaction completion status and notifies on the
307 * transaction completion event after the address was NACKed. The failure
308 * is observed only when the slave is configured to accept an address in
309 * the RX FIFO.</td>
310 * </tr>
311 * <tr>
312 * <td>1.0</td>
313 * <td>Initial version.</td>
314 * <td></td>
315 * </tr>
316 * </table>
317 */
318
319 /** \} group_scb */
320 /**
321 * \addtogroup group_scb_common
322 * \{
323 *
324 * Common API for the Serial Communication Block.
325 *
326 * This is the common API that provides an interface to the SCB hardware.
327 * The I2C, SPI, and UART drivers use this common API.
328 * Most users will use individual drivers and do not need to use the common
329 * API for the SCB. However, you can use the common SCB API to implement
330 * a custom driver based on the SCB hardware.
331 *
332 * The functions and other declarations used in this part of the driver are in
333 * cy_scb_common.h. You can include either of cy_scb_spi.h, cy_scb_uart.h,
334 * cy_scb_ezi2c.h, cy_scb_i2c.h depending on the desired functionality.
335 * You can also include cy_pdl.h to get access to all functions and declarations
336 * in the PDL.
337 *
338 *******************************************************************************
339 * \section group_scb_common_configuration Configuration Considerations
340 ********************************************************************************
341 * This is not a driver and it does not require configuration.
342 *
343 * \defgroup group_scb_common_macros Macros
344 * \defgroup group_scb_common_functions Functions
345 * \defgroup group_scb_common_data_structures Data Structures
346 *
347 */
348
349 #if !defined(CY_SCB_COMMON_H)
350 #define CY_SCB_COMMON_H
351
352 #include "cy_device.h"
353
354 #if (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB))
355
356 #include <stdint.h>
357 #include <stddef.h>
358 #include <stdbool.h>
359 #include "cy_syslib.h"
360 #include "cy_syspm.h"
361
362 #if defined(__cplusplus)
363 extern "C" {
364 #endif
365
366
367 /*******************************************************************************
368 * Function Prototypes
369 *******************************************************************************/
370
371 /**
372 * \addtogroup group_scb_common_functions
373 * \{
374 */
375 __STATIC_FORCEINLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base);
376 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
377 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base);
378 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base);
379 __STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base);
380
381 __STATIC_FORCEINLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data);
382 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
383 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base);
384 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base);
385 __STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base);
386 __STATIC_INLINE void Cy_SCB_ClearTxFifo (CySCB_Type *base);
387
388 __STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode);
389
390 __STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base);
391
392 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base);
393 __STATIC_INLINE void Cy_SCB_SetRxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
394 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask (CySCB_Type const *base);
395 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base);
396 __STATIC_INLINE void Cy_SCB_ClearRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
397 __STATIC_INLINE void Cy_SCB_SetRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
398
399 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base);
400 __STATIC_INLINE void Cy_SCB_SetTxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
401 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask (CySCB_Type const *base);
402 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base);
403 __STATIC_INLINE void Cy_SCB_ClearTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
404 __STATIC_INLINE void Cy_SCB_SetTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
405
406 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base);
407 __STATIC_INLINE void Cy_SCB_SetMasterInterruptMask (CySCB_Type *base, uint32_t interruptMask);
408 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask (CySCB_Type const *base);
409 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base);
410 __STATIC_INLINE void Cy_SCB_ClearMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
411 __STATIC_INLINE void Cy_SCB_SetMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
412
413 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base);
414 __STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask (CySCB_Type *base, uint32_t interruptMask);
415 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask (CySCB_Type const *base);
416 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base);
417 __STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
418 __STATIC_INLINE void Cy_SCB_SetSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
419
420 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base);
421 __STATIC_INLINE void Cy_SCB_SetI2CInterruptMask (CySCB_Type *base, uint32_t interruptMask);
422 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask (CySCB_Type const *base);
423 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base);
424 __STATIC_INLINE void Cy_SCB_ClearI2CInterrupt (CySCB_Type *base, uint32_t interruptMask);
425
426 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base);
427 __STATIC_INLINE void Cy_SCB_SetSpiInterruptMask (CySCB_Type *base, uint32_t interruptMask);
428 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask (CySCB_Type const *base);
429 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base);
430 __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt (CySCB_Type *base, uint32_t interruptMask);
431
432
433 /*******************************************************************************
434 * Internal Function Prototypes
435 *******************************************************************************/
436
437 /** \cond INTERNAL */
438 void Cy_SCB_ReadArrayNoCheck (CySCB_Type const *base, void *buffer, uint32_t size);
439 uint32_t Cy_SCB_ReadArray (CySCB_Type const *base, void *buffer, uint32_t size);
440 void Cy_SCB_ReadArrayBlocking (CySCB_Type const *base, void *buffer, uint32_t size);
441 uint32_t Cy_SCB_Write (CySCB_Type *base, uint32_t data);
442 void Cy_SCB_WriteArrayNoCheck (CySCB_Type *base, void *buffer, uint32_t size);
443 uint32_t Cy_SCB_WriteArray (CySCB_Type *base, void *buffer, uint32_t size);
444 void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
445 void Cy_SCB_WriteString (CySCB_Type *base, char_t const string[]);
446 void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size);
447 uint32_t Cy_SCB_WriteDefaultArray (CySCB_Type *base, uint32_t txData, uint32_t size);
448
449 __STATIC_INLINE uint32_t Cy_SCB_GetFifoSize (CySCB_Type const *base);
450 __STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base);
451 __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base);
452 __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base);
453 __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
454 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
455 __STATIC_INLINE uint32_t Cy_SCB_Get_RxDataWidth(CySCB_Type const *base);
456 __STATIC_INLINE uint32_t Cy_SCB_Get_TxDataWidth(CySCB_Type const *base);
457 #endif /* CY_IP_MXSCB_VERSION */
458 /** \endcond */
459
460 /** \} group_scb_common_functions */
461
462
463 /*******************************************************************************
464 * API Constants
465 *******************************************************************************/
466
467 /**
468 * \addtogroup group_scb_common_macros
469 * \{
470 */
471
472 /** Driver major version */
473 #define CY_SCB_DRV_VERSION_MAJOR (3)
474
475 /** Driver minor version */
476 #define CY_SCB_DRV_VERSION_MINOR (20)
477
478 /** SCB driver identifier */
479 #define CY_SCB_ID CY_PDL_DRV_ID(0x2AU)
480
481 /** Position for SCB driver sub mode */
482 #define CY_SCB_SUB_MODE_Pos (13UL)
483
484 /** EZI2C mode identifier */
485 #define CY_SCB_EZI2C_ID (0x0UL << CY_SCB_SUB_MODE_Pos)
486
487 /** I2C mode identifier */
488 #define CY_SCB_I2C_ID (0x1UL << CY_SCB_SUB_MODE_Pos)
489
490 /** SPI mode identifier */
491 #define CY_SCB_SPI_ID (0x2UL << CY_SCB_SUB_MODE_Pos)
492
493 /** UART mode identifier */
494 #define CY_SCB_UART_ID (0x3UL << CY_SCB_SUB_MODE_Pos)
495
496 /**
497 * \defgroup group_scb_common_macros_intr_cause SCB Interrupt Causes
498 * \{
499 */
500 /** Interrupt from Master interrupt sources */
501 #define CY_SCB_MASTER_INTR SCB_INTR_CAUSE_M_Msk
502
503 /** Interrupt from Slave interrupt sources */
504 #define CY_SCB_SLAVE_INTR SCB_INTR_CAUSE_S_Msk
505
506 /** Interrupt from TX interrupt sources */
507 #define CY_SCB_TX_INTR SCB_INTR_CAUSE_TX_Msk
508
509 /** Interrupt from RX interrupt sources */
510 #define CY_SCB_RX_INTR SCB_INTR_CAUSE_RX_Msk
511
512 /** Interrupt from I2C externally clocked interrupt sources */
513 #define CY_SCB_I2C_INTR SCB_INTR_CAUSE_I2C_EC_Msk
514
515 /** Interrupt from SPI externally clocked interrupt sources */
516 #define CY_SCB_SPI_INTR SCB_INTR_CAUSE_SPI_EC_Msk
517 /** \} group_scb_common_macros_intr_cause */
518
519 /**
520 * \defgroup group_scb_common_macros_tx_intr TX Interrupt Statuses
521 * \{
522 */
523 /**
524 * The number of data elements in the TX FIFO is less than the value
525 * of the TX FIFO level
526 */
527 #define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk
528
529 /** The TX FIFO is not full */
530 #define CY_SCB_TX_INTR_NOT_FULL SCB_INTR_TX_NOT_FULL_Msk
531
532 /** The TX FIFO is empty */
533 #define CY_SCB_TX_INTR_EMPTY SCB_INTR_TX_EMPTY_Msk
534
535 /** An attempt to write to a full TX FIFO */
536 #define CY_SCB_TX_INTR_OVERFLOW SCB_INTR_TX_OVERFLOW_Msk
537
538 /** An attempt to read from an empty TX FIFO */
539 #define CY_SCB_TX_INTR_UNDERFLOW SCB_INTR_TX_UNDERFLOW_Msk
540
541 /** The UART transfer is complete: all data elements from the TX FIFO are sent
542 */
543 #define CY_SCB_TX_INTR_UART_DONE SCB_INTR_TX_UART_DONE_Msk
544
545 /** SmartCard only: UART received a NACK */
546 #define CY_SCB_TX_INTR_UART_NACK SCB_INTR_TX_UART_NACK_Msk
547
548 /**
549 * SmartCard only: the value on the TX line of the UART does not match the
550 * value on the RX line
551 */
552 #define CY_SCB_TX_INTR_UART_ARB_LOST SCB_INTR_TX_UART_ARB_LOST_Msk
553 /** \} group_scb_common_macros_tx_intr */
554
555 /**
556 * \defgroup group_scb_common_macros_rx_intr RX Interrupt Statuses
557 * \{
558 */
559 /**
560 * The number of data elements in the RX FIFO is greater than the value of the
561 * RX FIFO level
562 */
563 #define CY_SCB_RX_INTR_LEVEL SCB_INTR_RX_TRIGGER_Msk
564
565 /** The RX FIFO is not empty */
566 #define CY_SCB_RX_INTR_NOT_EMPTY SCB_INTR_RX_NOT_EMPTY_Msk
567
568 /** The RX FIFO is full */
569 #define CY_SCB_RX_INTR_FULL SCB_INTR_RX_FULL_Msk
570
571 /** An attempt to write to a full RX FIFO */
572 #define CY_SCB_RX_INTR_OVERFLOW SCB_INTR_RX_OVERFLOW_Msk
573
574 /** An attempt to read from an empty RX FIFO */
575 #define CY_SCB_RX_INTR_UNDERFLOW SCB_INTR_RX_UNDERFLOW_Msk
576
577 /** A UART framing error detected */
578 #define CY_SCB_RX_INTR_UART_FRAME_ERROR SCB_INTR_RX_FRAME_ERROR_Msk
579
580 /** A UART parity error detected */
581 #define CY_SCB_RX_INTR_UART_PARITY_ERROR SCB_INTR_RX_PARITY_ERROR_Msk
582
583 /** A UART break detected */
584 #define CY_SCB_RX_INTR_UART_BREAK_DETECT SCB_INTR_RX_BREAK_DETECT_Msk
585 /** \} group_scb_common_macros_rx_intr */
586
587 /**
588 * \defgroup group_scb_common_macros_slave_intr Slave Interrupt Statuses
589 * \{
590 */
591 /**
592 * I2C slave lost arbitration: the value driven on the SDA line is not the same
593 * as the value observed on the SDA line
594 */
595 #define CY_SCB_SLAVE_INTR_I2C_ARB_LOST SCB_INTR_S_I2C_ARB_LOST_Msk
596
597 /** The I2C slave received a NAK */
598 #define CY_SCB_SLAVE_INTR_I2C_NACK SCB_INTR_S_I2C_NACK_Msk
599
600 /** The I2C slave received an ACK */
601 #define CY_SCB_SLAVE_INTR_I2C_ACK SCB_INTR_S_I2C_ACK_Msk
602
603 /**
604 * A Stop or Repeated Start event for a write transfer intended for this slave
605 * was detected.
606 */
607 #define CY_SCB_SLAVE_INTR_I2C_WRITE_STOP SCB_INTR_S_I2C_WRITE_STOP_Msk
608
609 /** A Stop or Repeated Start event intended for this slave was detected */
610 #define CY_SCB_SLAVE_INTR_I2C_STOP SCB_INTR_S_I2C_STOP_Msk
611
612 /** The I2C slave received a Start condition */
613 #define CY_SCB_SLAVE_INTR_I2C_START SCB_INTR_S_I2C_START_Msk
614
615 /** The I2C slave received the matching address */
616 #define CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH SCB_INTR_S_I2C_ADDR_MATCH_Msk
617
618 /** The I2C Slave received the general call address */
619 #define CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR SCB_INTR_S_I2C_GENERAL_Msk
620
621 /** The I2C slave bus error (detection of unexpected Start or Stop condition) */
622 #define CY_SCB_SLAVE_INTR_I2C_BUS_ERROR SCB_INTR_S_I2C_BUS_ERROR_Msk
623
624 /**
625 * The SPI slave select line is deselected at an expected time during an
626 * SPI transfer.
627 */
628 #define CY_SCB_SLAVE_INTR_SPI_BUS_ERROR SCB_INTR_S_SPI_BUS_ERROR_Msk
629 /** \} group_scb_common_macros_slave_intr */
630
631 /**
632 * \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses
633 * \{
634 */
635 /** The I2C master lost arbitration */
636 #define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk
637
638 /** The I2C master received a NACK */
639 #define CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk
640
641 /** The I2C master received an ACK */
642 #define CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk
643
644 /** The I2C master generated a Stop */
645 #define CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk
646
647 /** The I2C master bus error (detection of unexpected START or STOP condition)
648 */
649 #define CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk
650
651 /**
652 * The SPI master transfer is complete: all data elements transferred from the
653 * TX FIFO and TX shift register.
654 */
655 #define CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk
656 /** \} group_scb_common_macros_master_intr */
657
658 /**
659 * \defgroup group_scb_common_macros_i2c_intr I2C Interrupt Statuses
660 * \{
661 */
662 /**
663 * Wake up request: the I2C slave received the matching address.
664 * Note that this interrupt source triggers in active mode.
665 */
666 #define CY_SCB_I2C_INTR_WAKEUP SCB_INTR_I2C_EC_WAKE_UP_Msk
667 /** \} group_scb_common_macros_i2c_intr */
668
669 /**
670 * \defgroup group_scb_common_macros_SpiIntrStatuses SPI Interrupt Statuses
671 * \{
672 */
673 /**
674 * Wake up request: the SPI slave detects an active edge of the slave select
675 * signal. Note that this interrupt source triggers in active mode.
676 */
677 #define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk
678 /** \} group_scb_common_macros_SpiIntrStatuses */
679
680
681 /*******************************************************************************
682 * Internal Constants
683 *******************************************************************************/
684
685 /** \cond INTERNAL */
686
687 /* Default registers values */
688 #define CY_SCB_CTRL_DEF_VAL (_VAL2FLD(SCB_CTRL_OVS, 15UL) | \
689 _VAL2FLD(SCB_CTRL_MODE, 3UL))
690
691 #define CY_SCB_I2C_CTRL_DEF_VAL (_VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
692 _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
693 _VAL2FLD(SCB_I2C_CTRL_M_READY_DATA_ACK, 1UL) | \
694 _VAL2FLD(SCB_I2C_CTRL_M_NOT_READY_DATA_NACK, 1UL) | \
695 _VAL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, 1UL) | \
696 _VAL2FLD(SCB_I2C_CTRL_S_READY_ADDR_ACK, 1UL) | \
697 _VAL2FLD(SCB_I2C_CTRL_S_READY_DATA_ACK, 1UL) | \
698 _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK, 1UL) | \
699 _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_DATA_NACK, 1UL))
700
701 #define CY_SCB_I2C_CFG_DEF_VAL (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 3UL) | \
702 _VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_SEL, 1UL) | \
703 _VAL2FLD(SCB_I2C_CFG_SCL_IN_FILT_SEL, 1UL) | \
704 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT0_TRIM, 2UL) | \
705 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT1_TRIM, 2UL) | \
706 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT2_TRIM, 2UL))
707
708 #define CY_SCB_SPI_CTRL_DEF_VAL _VAL2FLD(SCB_SPI_CTRL_MODE, 3UL)
709 #define CY_SCB_UART_CTRL_DEF_VAL _VAL2FLD(SCB_UART_CTRL_MODE, 3UL)
710
711 #define CY_SCB_UART_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, 2UL) | \
712 _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, 10UL))
713
714 #define CY_SCB_UART_TX_CTRL_DEF_VAL _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, 2UL)
715
716 #define CY_SCB_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, 7UL) | \
717 _VAL2FLD(SCB_RX_CTRL_MSB_FIRST, 1UL))
718
719 #define CY_SCB_TX_CTRL_DEF_VAL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, 7UL) | \
720 _VAL2FLD(SCB_TX_CTRL_MSB_FIRST, 1UL))
721
722 /* SCB CTRL modes */
723 #define CY_SCB_CTRL_MODE_I2C (0UL)
724 #define CY_SCB_CTRL_MODE_SPI (1UL)
725 #define CY_SCB_CTRL_MODE_UART (2UL)
726
727 /* The position and mask to set the I2C mode */
728 #define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos
729 #define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \
730 SCB_I2C_CTRL_MASTER_MODE_Msk)
731
732 /* Cypress ID #282226:
733 * SCB_I2C_CFG_SDA_IN_FILT_TRIM[1]: SCB clock enable (1), clock disable (0).
734 */
735 #define CY_SCB_I2C_CFG_CLK_ENABLE_Msk (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 2UL))
736
737 /* I2C has fixed data width */
738 #define CY_SCB_I2C_DATA_WIDTH (7UL)
739
740 /* RX and TX control register values */
741 #define CY_SCB_I2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
742 SCB_RX_CTRL_MSB_FIRST_Msk)
743 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION<=2)) && (!defined (CY_IP_MXS22SCB)))
744 #define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
745 SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk)
746 #else
747 #define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
748 SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk | \
749 SCB_TX_CTRL_OPEN_DRAIN_SCL_Msk)
750 #endif
751 /* The position and mask to make an address byte */
752 #define CY_SCB_I2C_ADDRESS_Pos (1UL)
753 #define CY_SCB_I2C_ADDRESS_Msk (0xFEUL)
754
755 /* SPI slave select polarity */
756 #define CY_SCB_SPI_CTRL_SSEL_POLARITY_Pos SCB_SPI_CTRL_SSEL_POLARITY0_Pos
757 #define CY_SCB_SPI_CTRL_SSEL_POLARITY_Msk (SCB_SPI_CTRL_SSEL_POLARITY0_Msk | \
758 SCB_SPI_CTRL_SSEL_POLARITY1_Msk | \
759 SCB_SPI_CTRL_SSEL_POLARITY2_Msk | \
760 SCB_SPI_CTRL_SSEL_POLARITY3_Msk)
761
762 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
763 /* SPI parity and parity enable combination */
764 #define CY_SCB_SPI_RX_CTRL_SET_PARITY_Msk (SCB_SPI_RX_CTRL_PARITY_ENABLED_Msk | \
765 SCB_SPI_RX_CTRL_PARITY_Msk)
766 #define CY_SCB_SPI_RX_CTRL_SET_PARITY_Pos SCB_SPI_RX_CTRL_PARITY_Pos
767
768 #define CY_SCB_SPI_TX_CTRL_SET_PARITY_Msk (SCB_SPI_TX_CTRL_PARITY_ENABLED_Msk | \
769 SCB_SPI_TX_CTRL_PARITY_Msk)
770 #define CY_SCB_SPI_TX_CTRL_SET_PARITY_Pos SCB_SPI_TX_CTRL_PARITY_Pos
771 #endif /* CY_IP_MXSCB_VERSION */
772
773 /* SPI clock modes: CPHA and CPOL */
774 #define CY_SCB_SPI_CTRL_CLK_MODE_Pos SCB_SPI_CTRL_CPHA_Pos
775 #define CY_SCB_SPI_CTRL_CLK_MODE_Msk (SCB_SPI_CTRL_CPHA_Msk | SCB_SPI_CTRL_CPOL_Msk)
776
777 /* UART parity and parity enable combination */
778 #define CY_SCB_UART_RX_CTRL_SET_PARITY_Msk (SCB_UART_RX_CTRL_PARITY_ENABLED_Msk | \
779 SCB_UART_RX_CTRL_PARITY_Msk)
780 #define CY_SCB_UART_RX_CTRL_SET_PARITY_Pos SCB_UART_RX_CTRL_PARITY_Pos
781
782 #define CY_SCB_UART_TX_CTRL_SET_PARITY_Msk (SCB_UART_TX_CTRL_PARITY_ENABLED_Msk | \
783 SCB_UART_TX_CTRL_PARITY_Msk)
784 #define CY_SCB_UART_TX_CTRL_SET_PARITY_Pos SCB_UART_TX_CTRL_PARITY_Pos
785
786 /* Max number of bits for byte mode */
787 #define CY_SCB_BYTE_WIDTH (8UL)
788
789 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
790 /* Max number of bits for HALF WORD mode */
791 #define CY_SCB_HALF_WORD_WIDTH (16UL)
792
793 /* Max number of bits for WORD mode */
794 #define CY_SCB_WORD_WIDTH (32UL)
795
796 /*SCB Mem width modes */
797 #define CY_SCB_MEM_WIDTH_BYTE (0UL)
798 #define CY_SCB_MEM_WIDTH_HALFWORD (1UL)
799 #define CY_SCB_MEM_WIDTH_WORD (2UL)
800 #endif /* ((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) */
801
802 /* Single unit to wait */
803 #define CY_SCB_WAIT_1_UNIT (1U)
804
805 /* Clear interrupt sources */
806 #define CY_SCB_CLEAR_ALL_INTR_SRC (0UL)
807
808 /* Hardware FIFO size: EZ_DATA_NR / 4 = (512 / 4) = 128 */
809 #define CY_SCB_FIFO_SIZE (128UL)
810
811 /* Provides a list of allowed sources */
812 #define CY_SCB_TX_INTR_MASK (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_NOT_FULL | CY_SCB_TX_INTR_EMPTY | \
813 CY_SCB_TX_INTR_OVERFLOW | CY_SCB_TX_INTR_UNDERFLOW | CY_SCB_TX_INTR_UART_DONE | \
814 CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
815
816 #define CY_SCB_RX_INTR_MASK (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_FULL | \
817 CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UNDERFLOW | \
818 CY_SCB_RX_INTR_UART_FRAME_ERROR | CY_SCB_RX_INTR_UART_PARITY_ERROR | \
819 CY_SCB_RX_INTR_UART_BREAK_DETECT)
820
821
822 #define CY_SCB_SLAVE_INTR_MASK (CY_SCB_SLAVE_INTR_I2C_ARB_LOST | CY_SCB_SLAVE_INTR_I2C_NACK | CY_SCB_SLAVE_INTR_I2C_ACK | \
823 CY_SCB_SLAVE_INTR_I2C_WRITE_STOP | CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_START | \
824 CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
825 CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_SPI_BUS_ERROR)
826
827 #define CY_SCB_MASTER_INTR_MASK (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_NACK | \
828 CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_STOP | \
829 CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_SPI_DONE)
830
831 #define CY_SCB_I2C_INTR_MASK CY_SCB_I2C_INTR_WAKEUP
832
833 #define CY_SCB_SPI_INTR_MASK CY_SCB_SPI_INTR_WAKEUP
834
835 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
836 #define CY_SCB_IS_MEMWIDTH_VALID(memwidth) ((memwidth) <= CY_SCB_MEM_WIDTH_WORD)
837 #endif /* CY_IP_MXSCB_VERSION */
838
839 #define CY_SCB_IS_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) )
840 #define CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level) ((level) < Cy_SCB_GetFifoSize(base))
841
842 #define CY_SCB_IS_I2C_ADDR_VALID(addr) ( (0U == ((addr) & 0x80U)) )
843 #define CY_SCB_IS_BUFFER_VALID(buffer, size) ( (NULL != (buffer)) && ((size) > 0UL) )
844 #define CY_SCB_IS_I2C_BUFFER_VALID(buffer, size) ( (0UL == (size)) ? true : (NULL != (buffer)) )
845 /** \endcond */
846
847 /** \} group_scb_common_macros */
848
849
850 /*******************************************************************************
851 * In-line Function Implementation
852 *******************************************************************************/
853
854 /**
855 * \addtogroup group_scb_common_functions
856 * \{
857 */
858
859 /*******************************************************************************
860 * Function Name: Cy_SCB_ReadRxFifo
861 ****************************************************************************//**
862 *
863 * Reads a data element directly out of the RX FIFO.
864 * This function does not check whether the RX FIFO has data before reading it.
865 *
866 * \param base
867 * The pointer to the SCB instance.
868 *
869 * \return
870 * Data from RX FIFO.
871 *
872 *******************************************************************************/
Cy_SCB_ReadRxFifo(CySCB_Type const * base)873 __STATIC_FORCEINLINE uint32_t Cy_SCB_ReadRxFifo(CySCB_Type const *base)
874 {
875 return (SCB_RX_FIFO_RD(base));
876 }
877
878 /*******************************************************************************
879 * Function Name: Cy_SCB_SetRxFifoLevel
880 ****************************************************************************//**
881 *
882 * Sets the RX FIFO level. When there are more data elements in the RX FIFO than
883 * this level, the RX FIFO level interrupt is triggered.
884 *
885 * \param base
886 * The pointer to the SCB instance.
887 *
888 * \param level
889 * When there are more data elements in the FIFO than this level, the RX level
890 * interrupt is triggered.
891 *
892 *******************************************************************************/
Cy_SCB_SetRxFifoLevel(CySCB_Type * base,uint32_t level)893 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level)
894 {
895 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
896
897 CY_REG32_CLR_SET(SCB_RX_FIFO_CTRL(base), SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level);
898 }
899
900
901 /*******************************************************************************
902 * Function Name: Cy_SCB_GetNumInRxFifo
903 ****************************************************************************//**
904 *
905 * Returns the number of data elements currently in the RX FIFO.
906 *
907 * \param base
908 * The pointer to the SCB instance.
909 *
910 * \return
911 * The number or data elements in RX FIFO.
912 *
913 *******************************************************************************/
Cy_SCB_GetNumInRxFifo(CySCB_Type const * base)914 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base)
915 {
916 return _FLD2VAL(SCB_RX_FIFO_STATUS_USED, SCB_RX_FIFO_STATUS(base));
917 }
918
919
920 /*******************************************************************************
921 * Function Name: Cy_SCB_GetRxSrValid
922 ****************************************************************************//**
923 *
924 * Returns the status of the RX FIFO Shift Register valid bit.
925 *
926 * \param base
927 * The pointer to the SCB instance.
928 *
929 * \return
930 * 1 - RX shift register valid; 0 - RX shift register not valid.
931 *
932 *******************************************************************************/
Cy_SCB_GetRxSrValid(CySCB_Type const * base)933 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
934 {
935 return _FLD2VAL(SCB_RX_FIFO_STATUS_SR_VALID, SCB_RX_FIFO_STATUS(base));
936 }
937
938
939 /*******************************************************************************
940 * Function Name: Cy_SCB_ClearRxFifo
941 ****************************************************************************//**
942 *
943 * Clears the RX FIFO and shifter.
944 *
945 * \param base
946 * The pointer to the SCB instance.
947 *
948 * \note
949 * If there is partial data in the shifter, it is cleared and lost.
950 *
951 *******************************************************************************/
Cy_SCB_ClearRxFifo(CySCB_Type * base)952 __STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
953 {
954 SCB_RX_FIFO_CTRL(base) |= (uint32_t) SCB_RX_FIFO_CTRL_CLEAR_Msk;
955 SCB_RX_FIFO_CTRL(base) &= (uint32_t) ~SCB_RX_FIFO_CTRL_CLEAR_Msk;
956
957 (void) SCB_RX_FIFO_CTRL(base);
958 }
959
960
961 /*******************************************************************************
962 * Function Name: Cy_SCB_WriteTxFifo
963 ****************************************************************************//**
964 *
965 * Writes data directly into the TX FIFO.
966 * This function does not check whether the TX FIFO is not full before writing
967 * into it.
968 *
969 * \param base
970 * The pointer to the SCB instance.
971 *
972 * \param data
973 * Data to write to the TX FIFO.
974 *
975 *******************************************************************************/
Cy_SCB_WriteTxFifo(CySCB_Type * base,uint32_t data)976 __STATIC_FORCEINLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data)
977 {
978 SCB_TX_FIFO_WR(base) = data;
979 }
980
981
982 /*******************************************************************************
983 * Function Name: Cy_SCB_SetTxFifoLevel
984 ****************************************************************************//**
985 *
986 * Sets the TX FIFO level. When there are fewer data elements in the TX FIFO than
987 * this level, the TX FIFO level interrupt is triggered.
988 *
989 * \param base
990 * The pointer to the SCB instance.
991 *
992 * \param level
993 * When there are fewer data elements in the FIFO than this level, the TX level
994 * interrupt is triggered.
995 *
996 *******************************************************************************/
Cy_SCB_SetTxFifoLevel(CySCB_Type * base,uint32_t level)997 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level)
998 {
999 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
1000
1001 CY_REG32_CLR_SET(SCB_TX_FIFO_CTRL(base), SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level);
1002 }
1003
1004
1005 /*******************************************************************************
1006 * Function Name: Cy_SCB_GetNumInTxFifo
1007 ****************************************************************************//**
1008 *
1009 * Returns the number of data elements currently in the TX FIFO.
1010 *
1011 * \param base
1012 * The pointer to the SCB instance.
1013 *
1014 * \return
1015 * The number or data elements in the TX FIFO.
1016 *
1017 *******************************************************************************/
Cy_SCB_GetNumInTxFifo(CySCB_Type const * base)1018 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base)
1019 {
1020 return _FLD2VAL(SCB_TX_FIFO_STATUS_USED, SCB_TX_FIFO_STATUS(base));
1021 }
1022
1023
1024 /*******************************************************************************
1025 * Function Name: Cy_SCB_GetTxSrValid
1026 ****************************************************************************//**
1027 *
1028 * Returns the status of the TX FIFO Shift Register valid bit.
1029 *
1030 * \param base
1031 * The pointer to the SCB instance.
1032 *
1033 * \return
1034 * 1 - TX shift register valid; 0 - TX shift register not valid.
1035 *
1036 *******************************************************************************/
Cy_SCB_GetTxSrValid(CySCB_Type const * base)1037 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
1038 {
1039 return _FLD2VAL(SCB_TX_FIFO_STATUS_SR_VALID, SCB_TX_FIFO_STATUS(base));
1040 }
1041
1042
1043 /*******************************************************************************
1044 * Function Name: Cy_SCB_IsTxComplete
1045 ****************************************************************************//**
1046 *
1047 * Checks whether the TX FIFO and Shifter are empty and there is no more data to send.
1048 *
1049 * \param base
1050 * Pointer to SPI the SCB instance.
1051 *
1052 * \return
1053 * If true, transmission complete. If false, transmission is not complete.
1054 *
1055 *******************************************************************************/
Cy_SCB_IsTxComplete(CySCB_Type const * base)1056 __STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base)
1057 {
1058 return (0UL == (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base)));
1059 }
1060
1061
1062 /*******************************************************************************
1063 * Function Name: Cy_SCB_ClearTxFifo
1064 ****************************************************************************//**
1065 *
1066 * Clears the TX FIFO.
1067 *
1068 * \param base
1069 * The pointer to the SCB instance.
1070 *
1071 * \note
1072 * The TX FIFO clear operation also clears the shift register. Thus the shifter
1073 * could be cleared in the middle of a data element transfer. Thia results in
1074 * "ones" being sent on the bus for the remainder of the transfer.
1075 *
1076 *******************************************************************************/
Cy_SCB_ClearTxFifo(CySCB_Type * base)1077 __STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base)
1078 {
1079 SCB_TX_FIFO_CTRL(base) |= (uint32_t) SCB_TX_FIFO_CTRL_CLEAR_Msk;
1080 SCB_TX_FIFO_CTRL(base) &= (uint32_t) ~SCB_TX_FIFO_CTRL_CLEAR_Msk;
1081
1082 (void) SCB_TX_FIFO_CTRL(base);
1083 }
1084
1085
1086 /*******************************************************************************
1087 * Function Name: Cy_SCB_SetByteMode
1088 ****************************************************************************//**
1089 *
1090 * Sets whether the RX and TX FIFOs are in byte mode.
1091 * The FIFOs are either 16-bit wide or 8-bit wide (byte mode).
1092 * When the FIFO is in byte mode it is twice as deep. See the device datasheet
1093 * for FIFO depths.
1094 *
1095 * \param base
1096 * The pointer to the SCB instance.
1097 *
1098 * \param byteMode
1099 * If true, TX and RX FIFOs are 8-bit wide. If false, the FIFOs are 16-bit wide.
1100 *
1101 *******************************************************************************/
Cy_SCB_SetByteMode(CySCB_Type * base,bool byteMode)1102 __STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode)
1103 {
1104 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
1105 SCB_CTRL(base) &= ~SCB_CTRL_MEM_WIDTH_Msk;
1106 if (byteMode)
1107 {
1108 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, CY_SCB_MEM_WIDTH_BYTE);
1109 }
1110 else
1111 {
1112 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, CY_SCB_MEM_WIDTH_HALFWORD);
1113 }
1114 #elif(defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION==1))
1115 if (byteMode)
1116 {
1117 SCB_CTRL(base) |= SCB_CTRL_BYTE_MODE_Msk;
1118 }
1119 else
1120 {
1121 SCB_CTRL(base) &= ~SCB_CTRL_BYTE_MODE_Msk;
1122 }
1123 #endif /* ((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) */
1124 }
1125
1126 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
1127 /*******************************************************************************
1128 * Function Name: Cy_SCB_SetMemWidth
1129 ****************************************************************************//**
1130 *
1131 * Sets the RX and TX FIFOs byte mode/halfword/word mode.
1132 * The FIFOs are either 8-bit(byte),16-bit(halfword) or 32-bit (word) wide.
1133 * See the device datasheet for FIFO depths.
1134 *
1135 * \param base
1136 * The pointer to the SCB instance.
1137 *
1138 * \param MemWidthMode
1139 * If 0x0, TX and RX FIFOs are 8-bit wide.
1140 * If 0x1, the FIFOs are 16-bit wide.
1141 * If 0x2, the FIFOs are 32-bit wide.
1142 *
1143 * \note
1144 * This API is available for CAT1B, CAT1C and CAT1D devices.
1145 *
1146 *******************************************************************************/
Cy_SCB_SetMemWidth(CySCB_Type * base,uint32_t MemWidthMode)1147 __STATIC_INLINE void Cy_SCB_SetMemWidth(CySCB_Type *base, uint32_t MemWidthMode)
1148 {
1149 CY_ASSERT_L2(CY_SCB_IS_MEMWIDTH_VALID(MemWidthMode));
1150
1151 SCB_CTRL(base) &= ~SCB_CTRL_MEM_WIDTH_Msk;
1152
1153 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, MemWidthMode);
1154 }
1155 #endif /* CY_IP_MXSCB_VERSION */
1156
1157 /*******************************************************************************
1158 * Function Name: Cy_SCB_GetInterruptCause
1159 ****************************************************************************//**
1160 *
1161 * Returns the mask of bits showing the source of the current triggered
1162 * interrupt. This is useful for modes of operation where an interrupt can
1163 * be generated by conditions in multiple interrupt source registers.
1164 *
1165 * \param base
1166 * The pointer to the SCB instance.
1167 *
1168 * \return
1169 * The mask with the OR of the following conditions that have been triggered.
1170 * See \ref group_scb_common_macros_intr_cause for the set of constants.
1171 *
1172 *******************************************************************************/
Cy_SCB_GetInterruptCause(CySCB_Type const * base)1173 __STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base)
1174 {
1175 return (SCB_INTR_CAUSE(base));
1176 }
1177
1178
1179 /*******************************************************************************
1180 * Function Name: Cy_SCB_GetRxInterruptStatus
1181 ****************************************************************************//**
1182 *
1183 * Returns the RX interrupt request register. This register contains the current
1184 * status of the RX interrupt sources.
1185 *
1186 * \param base
1187 * The pointer to the SCB instance.
1188 *
1189 * \return
1190 * The current status of the RX interrupt sources. Each constant is a bit field
1191 * value. The value returned may have multiple bits set to indicate the
1192 * current status.
1193 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1194 *
1195 *******************************************************************************/
Cy_SCB_GetRxInterruptStatus(CySCB_Type const * base)1196 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base)
1197 {
1198 return (SCB_INTR_RX(base) & CY_SCB_RX_INTR_MASK);
1199 }
1200
1201
1202 /*******************************************************************************
1203 * Function Name: Cy_SCB_SetRxInterruptMask
1204 ****************************************************************************//**
1205 *
1206 * Writes the RX interrupt mask register. This register configures which bits
1207 * from the RX interrupt request register can trigger an interrupt event.
1208 *
1209 * \param base
1210 * The pointer to the SCB instance.
1211 *
1212 * \param interruptMask
1213 * Enabled RX interrupt sources.
1214 * See \ref group_scb_common_macros_rx_intr.
1215 *
1216 *******************************************************************************/
Cy_SCB_SetRxInterruptMask(CySCB_Type * base,uint32_t interruptMask)1217 __STATIC_INLINE void Cy_SCB_SetRxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1218 {
1219 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1220
1221 SCB_INTR_RX_MASK(base) = interruptMask;
1222 }
1223
1224
1225 /*******************************************************************************
1226 * Function Name: Cy_SCB_GetRxInterruptMask
1227 ****************************************************************************//**
1228 *
1229 * Returns the RX interrupt mask register. This register specifies which bits
1230 * from the RX interrupt request register trigger can an interrupt event.
1231 *
1232 * \param base
1233 * The pointer to the SCB instance.
1234 *
1235 * \return
1236 * Enabled RX interrupt sources.
1237 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1238 *
1239 *******************************************************************************/
Cy_SCB_GetRxInterruptMask(CySCB_Type const * base)1240 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask(CySCB_Type const *base)
1241 {
1242 return (SCB_INTR_RX_MASK(base));
1243 }
1244
1245
1246 /*******************************************************************************
1247 * Function Name: Cy_SCB_GetRxInterruptStatusMasked
1248 ****************************************************************************//**
1249 *
1250 * Returns the RX interrupt masked request register. This register contains
1251 * a logical AND of corresponding bits from the RX interrupt request and
1252 * mask registers.
1253 * This function is intended to be used in the interrupt service routine to
1254 * identify which of the enabled RX interrupt sources caused the interrupt event.
1255 *
1256 * \param base
1257 * The pointer to the SCB instance.
1258 *
1259 * \return
1260 * The current status of enabled RX interrupt sources.
1261 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1262 *
1263 *******************************************************************************/
Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const * base)1264 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base)
1265 {
1266 return (SCB_INTR_RX_MASKED(base));
1267 }
1268
1269
1270 /*******************************************************************************
1271 * Function Name: Cy_SCB_ClearRxInterrupt
1272 ****************************************************************************//**
1273 *
1274 * Clears the RX interrupt sources in the interrupt request register.
1275 *
1276 * \param base
1277 * The pointer to the SCB instance.
1278 *
1279 * \param interruptMask
1280 * The RX interrupt sources to be cleared.
1281 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1282 *
1283 * \note
1284 * - CY_SCB_INTR_RX_FIFO_LEVEL interrupt source is not cleared when
1285 * the RX FIFO has more entries than the level.
1286 * - CY_SCB_INTR_RX_NOT_EMPTY interrupt source is not cleared when the
1287 * RX FIFO is not empty.
1288 * - CY_SCB_INTR_RX_FULL interrupt source is not cleared when the
1289 * RX FIFO is full.
1290 *
1291 *******************************************************************************/
Cy_SCB_ClearRxInterrupt(CySCB_Type * base,uint32_t interruptMask)1292 __STATIC_INLINE void Cy_SCB_ClearRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1293 {
1294 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1295
1296 SCB_INTR_RX(base) = interruptMask;
1297 (void) SCB_INTR_RX(base);
1298 }
1299
1300
1301 /*******************************************************************************
1302 * Function Name: Cy_SCB_SetRxInterrupt
1303 ****************************************************************************//**
1304 *
1305 * Sets the RX interrupt sources in the interrupt request register.
1306 *
1307 * \param base
1308 * The pointer to the SCB instance.
1309 *
1310 * \param interruptMask
1311 * The RX interrupt sources to set in the RX interrupt request register.
1312 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1313 *
1314 *******************************************************************************/
Cy_SCB_SetRxInterrupt(CySCB_Type * base,uint32_t interruptMask)1315 __STATIC_INLINE void Cy_SCB_SetRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1316 {
1317 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1318
1319 SCB_INTR_RX_SET(base) = interruptMask;
1320 }
1321
1322
1323 /*******************************************************************************
1324 * Function Name: Cy_SCB_GetTxInterruptStatus
1325 ****************************************************************************//**
1326 *
1327 * Returns the TX interrupt request register. This register contains the current
1328 * status of the TX interrupt sources.
1329 *
1330 * \param base
1331 * The pointer to the SCB instance.
1332 *
1333 * \return
1334 * The current status of TX interrupt sources.
1335 * Each constant is a bit field value. The value returned may have multiple
1336 * bits set to indicate the current status.
1337 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1338 *
1339 *******************************************************************************/
Cy_SCB_GetTxInterruptStatus(CySCB_Type const * base)1340 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base)
1341 {
1342 return (SCB_INTR_TX(base) & CY_SCB_TX_INTR_MASK);
1343 }
1344
1345
1346 /*******************************************************************************
1347 * Function Name: Cy_SCB_SetTxInterruptMask
1348 ****************************************************************************//**
1349 *
1350 * Writes the TX interrupt mask register. This register configures which bits
1351 * from the TX interrupt request register can trigger an interrupt event.
1352 *
1353 * \param base
1354 * The pointer to the SCB instance.
1355 *
1356 * \param interruptMask
1357 * Enabled TX interrupt sources.
1358 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1359 *
1360 *******************************************************************************/
Cy_SCB_SetTxInterruptMask(CySCB_Type * base,uint32_t interruptMask)1361 __STATIC_INLINE void Cy_SCB_SetTxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1362 {
1363 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1364
1365 SCB_INTR_TX_MASK(base) = interruptMask;
1366 }
1367
1368
1369 /*******************************************************************************
1370 * Function Name: Cy_SCB_GetTxInterruptMask
1371 ****************************************************************************//**
1372 *
1373 * Returns the TX interrupt mask register. This register specifies which
1374 * bits from the TX interrupt request register can trigger an interrupt event.
1375 *
1376 * \param base
1377 * The pointer to the SCB instance.
1378 *
1379 * \return
1380 * Enabled TX interrupt sources.
1381 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1382 *
1383 *******************************************************************************/
Cy_SCB_GetTxInterruptMask(CySCB_Type const * base)1384 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask(CySCB_Type const *base)
1385 {
1386 return (SCB_INTR_TX_MASK(base));
1387 }
1388
1389
1390 /*******************************************************************************
1391 * Function Name: Cy_SCB_GetTxInterruptStatusMasked
1392 ****************************************************************************//**
1393 *
1394 * Returns the TX interrupt masked request register. This register contains
1395 * a logical AND of corresponding bits from the TX interrupt request and
1396 * mask registers.
1397 * This function is intended to be used in the interrupt service routine to
1398 * identify which of enabled TX interrupt sources caused the interrupt event.
1399 *
1400 * \param base
1401 * The pointer to the SCB instance.
1402 *
1403 * \return
1404 * The current status of enabled TX interrupt sources.
1405 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1406 *
1407 *******************************************************************************/
Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const * base)1408 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base)
1409 {
1410 return (SCB_INTR_TX_MASKED(base));
1411 }
1412
1413
1414 /*******************************************************************************
1415 * Function Name: Cy_SCB_ClearTxInterrupt
1416 ****************************************************************************//**
1417 *
1418 * Clears the TX interrupt sources in the interrupt request register.
1419 *
1420 * \param base
1421 * The pointer to the SCB instance.
1422 *
1423 * \param interruptMask
1424 * The TX interrupt sources to be cleared.
1425 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1426 *
1427 * \note
1428 * - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the
1429 * TX FIFO has fewer entries than the TX level.
1430 * - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the
1431 * TX FIFO has empty entries in the TX FIFO.
1432 * - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the
1433 * TX FIFO is empty.
1434 * - CY_SCB_INTR_TX_UNDERFLOW interrupt source is not cleared when the
1435 * TX FIFO is empty. Put data into the TX FIFO before clearing it.
1436 *
1437 *******************************************************************************/
Cy_SCB_ClearTxInterrupt(CySCB_Type * base,uint32_t interruptMask)1438 __STATIC_INLINE void Cy_SCB_ClearTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1439 {
1440 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1441
1442 SCB_INTR_TX(base) = interruptMask;
1443 (void) SCB_INTR_TX(base);
1444 }
1445
1446
1447 /*******************************************************************************
1448 * Function Name: Cy_SCB_SetTxInterrupt
1449 ****************************************************************************//**
1450 *
1451 * Sets TX interrupt sources in the interrupt request register.
1452 *
1453 * \param base
1454 * The pointer to the SCB instance.
1455 *
1456 * \param interruptMask
1457 * The TX interrupt sources to set in the TX interrupt request register.
1458 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1459 *
1460 *******************************************************************************/
Cy_SCB_SetTxInterrupt(CySCB_Type * base,uint32_t interruptMask)1461 __STATIC_INLINE void Cy_SCB_SetTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1462 {
1463 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1464
1465 SCB_INTR_TX_SET(base) = interruptMask;
1466 }
1467
1468
1469 /*******************************************************************************
1470 * Function Name: Cy_SCB_GetMasterInterruptStatus
1471 ****************************************************************************//**
1472 *
1473 * Returns the master interrupt request register. This register contains the current
1474 * status of the master interrupt sources.
1475 *
1476 * \param base
1477 * The pointer to the SCB instance.
1478 *
1479 * \return
1480 * The current status of the master interrupt sources.
1481 * Each constant is a bit field value. The value returned may have multiple
1482 * bits set to indicate the current status.
1483 * See \ref group_scb_common_macros_master_intr for the set of constants.
1484 *
1485 *******************************************************************************/
Cy_SCB_GetMasterInterruptStatus(CySCB_Type const * base)1486 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base)
1487 {
1488 return (SCB_INTR_M(base) & CY_SCB_MASTER_INTR_MASK);
1489 }
1490
1491
1492 /*******************************************************************************
1493 * Function Name: Cy_SCB_SetMasterInterruptMask
1494 ****************************************************************************//**
1495 *
1496 * Writes the master interrupt mask register. This register specifies which bits
1497 * from the master interrupt request register can trigger an interrupt event.
1498 *
1499 * \param base
1500 * The pointer to the SCB instance.
1501 *
1502 * \param interruptMask
1503 * The master interrupt sources to be enable.
1504 * See \ref group_scb_common_macros_master_intr for the set of constants.
1505 *
1506 *******************************************************************************/
Cy_SCB_SetMasterInterruptMask(CySCB_Type * base,uint32_t interruptMask)1507 __STATIC_INLINE void Cy_SCB_SetMasterInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1508 {
1509 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1510
1511 SCB_INTR_M_MASK(base) = interruptMask;
1512 }
1513
1514
1515 /*******************************************************************************
1516 * Function Name: Cy_SCB_GetMasterInterruptMask
1517 ****************************************************************************//**
1518 *
1519 * Returns the master interrupt mask register. This register specifies which bits
1520 * from the master interrupt request register can trigger an interrupt event.
1521 *
1522 * \param base
1523 * The pointer to the SCB instance.
1524 *
1525 * \return
1526 * Enabled master interrupt sources.
1527 * See \ref group_scb_common_macros_master_intr for the set of constants.
1528 *
1529 *******************************************************************************/
Cy_SCB_GetMasterInterruptMask(CySCB_Type const * base)1530 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask(CySCB_Type const *base)
1531 {
1532 return (SCB_INTR_M_MASK(base));
1533 }
1534
1535
1536 /*******************************************************************************
1537 * Function Name: Cy_SCB_GetMasterInterruptStatusMasked
1538 ****************************************************************************//**
1539 *
1540 * Returns the master interrupt masked request register. This register contains a
1541 * logical AND of corresponding bits from the master interrupt request and mask
1542 * registers.
1543 * This function is intended to be used in the interrupt service routine to
1544 * identify which of the enabled master interrupt sources caused the interrupt
1545 * event.
1546 *
1547 * \param base
1548 * The pointer to the SCB instance.
1549 *
1550 * \return
1551 * The current status of enabled master interrupt sources.
1552 * See \ref group_scb_common_macros_master_intr for the set of constants.
1553 *
1554 *******************************************************************************/
Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const * base)1555 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base)
1556 {
1557 return (SCB_INTR_M_MASKED(base));
1558 }
1559
1560
1561 /*******************************************************************************
1562 * Function Name: Cy_SCB_ClearMasterInterrupt
1563 ****************************************************************************//**
1564 *
1565 * Clears master interrupt sources in the interrupt request register.
1566 *
1567 * \param base
1568 * The pointer to the SCB instance.
1569 *
1570 * \param interruptMask
1571 * The master interrupt sources to be cleared.
1572 * See \ref group_scb_common_macros_master_intr for the set of constants.
1573 *
1574 *******************************************************************************/
Cy_SCB_ClearMasterInterrupt(CySCB_Type * base,uint32_t interruptMask)1575 __STATIC_INLINE void Cy_SCB_ClearMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
1576 {
1577 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1578
1579 SCB_INTR_M(base) = interruptMask;
1580 (void) SCB_INTR_M(base);
1581 }
1582
1583
1584 /*******************************************************************************
1585 * Function Name: Cy_SCB_SetMasterInterrupt
1586 ****************************************************************************//**
1587 *
1588 * Sets master interrupt sources in the interrupt request register.
1589 *
1590 * \param base
1591 * The pointer to the SCB instance.
1592 *
1593 * \param interruptMask
1594 * The master interrupt sources to set in the master interrupt request register.
1595 * See \ref group_scb_common_macros_master_intr for the set of constants.
1596 *
1597 *******************************************************************************/
Cy_SCB_SetMasterInterrupt(CySCB_Type * base,uint32_t interruptMask)1598 __STATIC_INLINE void Cy_SCB_SetMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
1599 {
1600 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1601
1602 SCB_INTR_M_SET(base) = interruptMask;
1603 }
1604
1605
1606 /*******************************************************************************
1607 * Function Name: Cy_SCB_GetSlaveInterruptStatus
1608 ****************************************************************************//**
1609 *
1610 * Returns the slave interrupt request register. This register contains the current
1611 * status of the slave interrupt sources.
1612 *
1613 * \param base
1614 * The pointer to the SCB instance.
1615 *
1616 * \return
1617 * The current status of the slave interrupt sources.
1618 * Each constant is a bit field value. The value returned may have multiple
1619 * bits set to indicate the current status.
1620 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1621 *
1622 *******************************************************************************/
Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const * base)1623 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base)
1624 {
1625 return (SCB_INTR_S(base) & CY_SCB_SLAVE_INTR_MASK);
1626 }
1627
1628
1629 /*******************************************************************************
1630 * Function Name: Cy_SCB_SetSlaveInterruptMask
1631 ****************************************************************************//**
1632 *
1633 * Writes slave interrupt mask register.
1634 * This register specifies which bits from the slave interrupt request register
1635 * can trigger an interrupt event.
1636 *
1637 * \param base
1638 * The pointer to the SCB instance.
1639 *
1640 * \param interruptMask
1641 * Enabled slave interrupt sources.
1642 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1643 *
1644 *******************************************************************************/
Cy_SCB_SetSlaveInterruptMask(CySCB_Type * base,uint32_t interruptMask)1645 __STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1646 {
1647 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1648
1649 SCB_INTR_S_MASK(base) = interruptMask;
1650 }
1651
1652
1653 /*******************************************************************************
1654 * Function Name: Cy_SCB_GetSlaveInterruptMask
1655 ****************************************************************************//**
1656 *
1657 * Returns the slave interrupt mask register.
1658 * This register specifies which bits from the slave interrupt request register
1659 * can trigger an interrupt event.
1660 *
1661 * \param base
1662 * The pointer to the SCB instance.
1663 *
1664 * \return
1665 * Enabled slave interrupt sources.
1666 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1667 *
1668 *******************************************************************************/
Cy_SCB_GetSlaveInterruptMask(CySCB_Type const * base)1669 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask(CySCB_Type const *base)
1670 {
1671 return (SCB_INTR_S_MASK(base));
1672 }
1673
1674
1675 /*******************************************************************************
1676 * Function Name: Cy_SCB_GetSlaveInterruptStatusMasked
1677 ****************************************************************************//**
1678 *
1679 * Returns the slave interrupt masked request register. This register contains a
1680 * logical AND of corresponding bits from the slave interrupt request and mask
1681 * registers.
1682 * This function is intended to be used in the interrupt service routine to
1683 * identify which of enabled slave interrupt sources caused the interrupt
1684 * event.
1685 *
1686 * \param base
1687 * The pointer to the SCB instance.
1688 *
1689 * \return
1690 * The current status of enabled slave interrupt sources.
1691 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1692 *
1693 *******************************************************************************/
Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const * base)1694 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base)
1695 {
1696 return (SCB_INTR_S_MASKED(base));
1697 }
1698
1699
1700 /*******************************************************************************
1701 * Function Name: Cy_SCB_ClearSlaveInterrupt
1702 ****************************************************************************//**
1703 *
1704 * Clears the slave interrupt sources in the interrupt request register.
1705 *
1706 * \param base
1707 * The pointer to the SCB instance.
1708 *
1709 * \param interruptMask
1710 * Slave interrupt sources to be cleared.
1711 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1712 *
1713 *******************************************************************************/
Cy_SCB_ClearSlaveInterrupt(CySCB_Type * base,uint32_t interruptMask)1714 __STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
1715 {
1716 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1717
1718 SCB_INTR_S(base) = interruptMask;
1719 (void) SCB_INTR_S(base);
1720 }
1721
1722
1723 /*******************************************************************************
1724 * Function Name: Cy_SCB_SetSlaveInterrupt
1725 ****************************************************************************//**
1726 *
1727 * Sets slave interrupt sources in the interrupt request register.
1728 *
1729 * \param base
1730 * The pointer to the SCB instance.
1731 *
1732 * \param interruptMask
1733 * The slave interrupt sources to set in the slave interrupt request register
1734 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1735 *
1736 *******************************************************************************/
Cy_SCB_SetSlaveInterrupt(CySCB_Type * base,uint32_t interruptMask)1737 __STATIC_INLINE void Cy_SCB_SetSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
1738 {
1739 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1740
1741 SCB_INTR_S_SET(base) = interruptMask;
1742 }
1743
1744
1745 /*******************************************************************************
1746 * Function Name: Cy_SCB_GetI2CInterruptStatus
1747 ****************************************************************************//**
1748 *
1749 * Returns the I2C interrupt request register. This register contains the
1750 * current status of the I2C interrupt sources.
1751 *
1752 * \param base
1753 * The pointer to the SCB instance.
1754 *
1755 * \return
1756 * The current status of the I2C interrupt sources. Each constant is a bit
1757 * field value.
1758 * The value returned may have multiple bits set to indicate the current status.
1759 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1760 *
1761 *******************************************************************************/
Cy_SCB_GetI2CInterruptStatus(CySCB_Type const * base)1762 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base)
1763 {
1764 return (SCB_INTR_I2C_EC(base) & CY_SCB_I2C_INTR_MASK);
1765 }
1766
1767
1768 /*******************************************************************************
1769 * Function Name: Cy_SCB_SetI2CInterruptMask
1770 ****************************************************************************//**
1771 *
1772 * Writes the I2C interrupt mask register. This register specifies which bits
1773 * from the I2C interrupt request register can trigger an interrupt event.
1774 *
1775 * \param base
1776 * The pointer to the SCB instance.
1777 *
1778 * \param interruptMask
1779 * Enabled I2C interrupt sources.
1780 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1781 *
1782 *******************************************************************************/
Cy_SCB_SetI2CInterruptMask(CySCB_Type * base,uint32_t interruptMask)1783 __STATIC_INLINE void Cy_SCB_SetI2CInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1784 {
1785 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
1786
1787 SCB_INTR_I2C_EC_MASK(base) = interruptMask;
1788 }
1789
1790
1791 /*******************************************************************************
1792 * Function Name: Cy_SCB_GetI2CInterruptMask
1793 ****************************************************************************//**
1794 *
1795 * Returns the I2C interrupt mask register. This register specifies which bits
1796 * from the I2C interrupt request register can trigger an interrupt event.
1797 *
1798 * \param base
1799 * The pointer to the SCB instance.
1800 *
1801 * \return
1802 * Enabled I2C interrupt sources.
1803 * See \ref group_scb_common_macros_i2c_intr.
1804 *
1805 *******************************************************************************/
Cy_SCB_GetI2CInterruptMask(CySCB_Type const * base)1806 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask(CySCB_Type const *base)
1807 {
1808 return (SCB_INTR_I2C_EC_MASK(base));
1809 }
1810
1811
1812 /*******************************************************************************
1813 * Function Name: Cy_SCB_GetI2CInterruptStatusMasked
1814 ****************************************************************************//**
1815 *
1816 * Returns the I2C interrupt masked request register. This register contains
1817 * a logical AND of corresponding bits from I2C interrupt request and mask
1818 * registers.
1819 * This function is intended to be used in the interrupt service routine to
1820 * identify which of enabled I2C interrupt sources caused the interrupt event.
1821 *
1822 * \param base
1823 * The pointer to the SCB instance.
1824 *
1825 * \return
1826 * The current status of enabled I2C interrupt sources.
1827 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1828 *
1829 *******************************************************************************/
Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const * base)1830 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base)
1831 {
1832 return (SCB_INTR_I2C_EC_MASKED(base));
1833 }
1834
1835
1836 /*******************************************************************************
1837 * Function Name: Cy_SCB_ClearI2CInterrupt
1838 ****************************************************************************//**
1839 *
1840 * Clears I2C interrupt sources in the interrupt request register.
1841 *
1842 * \param base
1843 * The pointer to the SCB instance.
1844 *
1845 * \param interruptMask
1846 * The I2C interrupt sources to be cleared.
1847 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1848 *
1849 *******************************************************************************/
Cy_SCB_ClearI2CInterrupt(CySCB_Type * base,uint32_t interruptMask)1850 __STATIC_INLINE void Cy_SCB_ClearI2CInterrupt(CySCB_Type *base, uint32_t interruptMask)
1851 {
1852 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
1853
1854 SCB_INTR_I2C_EC(base) = interruptMask;
1855 (void) SCB_INTR_I2C_EC(base);
1856 }
1857
1858
1859 /*******************************************************************************
1860 * Function Name: Cy_SCB_GetSpiInterruptStatus
1861 ****************************************************************************//**
1862 *
1863 * Returns the SPI interrupt request register. This register contains the current
1864 * status of the SPI interrupt sources.
1865 *
1866 * \param base
1867 * The pointer to the SCB instance.
1868 *
1869 * \return
1870 * The current status of SPI interrupt sources. Each constant is a bit field value.
1871 * The value returned may have multiple bits set to indicate the current status
1872 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1873 *
1874 *******************************************************************************/
Cy_SCB_GetSpiInterruptStatus(CySCB_Type const * base)1875 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base)
1876 {
1877 return (SCB_INTR_SPI_EC(base) & CY_SCB_SPI_INTR_MASK);
1878 }
1879
1880
1881 /*******************************************************************************
1882 * Function Name: Cy_SCB_SetSpiInterruptMask
1883 ****************************************************************************//**
1884 *
1885 * Writes the SPI interrupt mask register. This register specifies which
1886 * bits from the SPI interrupt request register can trigger an interrupt event.
1887 *
1888 * \param base
1889 * The pointer to the SCB instance.
1890 *
1891 * \param interruptMask
1892 * Enabled SPI interrupt sources.
1893 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1894 *
1895 *******************************************************************************/
Cy_SCB_SetSpiInterruptMask(CySCB_Type * base,uint32_t interruptMask)1896 __STATIC_INLINE void Cy_SCB_SetSpiInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1897 {
1898 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
1899
1900 SCB_INTR_SPI_EC_MASK(base) = interruptMask;
1901 }
1902
1903
1904 /*******************************************************************************
1905 * Function Name: Cy_SCB_GetSpiInterruptMask
1906 ****************************************************************************//**
1907 *
1908 * Returns the SPI interrupt mask register. This register specifies which bits
1909 * from the SPI interrupt request register can trigger an interrupt event.
1910 *
1911 * \param base
1912 * The pointer to the SCB instance.
1913 *
1914 * \return
1915 * Enabled SPI interrupt sources.
1916 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1917 *
1918 *******************************************************************************/
Cy_SCB_GetSpiInterruptMask(CySCB_Type const * base)1919 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask(CySCB_Type const *base)
1920 {
1921 return (SCB_INTR_SPI_EC_MASK(base));
1922 }
1923
1924
1925 /*******************************************************************************
1926 * Function Name: Cy_SCB_GetSpiInterruptStatusMasked
1927 ****************************************************************************//**
1928 *
1929 * Returns the SPI interrupt masked request register. This register contains
1930 * a logical AND of corresponding bits from the SPI interrupt request and
1931 * mask registers.
1932 * This function is intended to be used in the interrupt service routine to
1933 * identify which of enabled SPI interrupt sources caused the interrupt event.
1934 *
1935 * \param base
1936 * The pointer to the SCB instance.
1937 *
1938 * \return
1939 * The current status of enabled SPI interrupt sources.
1940 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1941 *
1942 *******************************************************************************/
Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const * base)1943 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base)
1944 {
1945 return (SCB_INTR_SPI_EC_MASKED(base));
1946 }
1947
1948
1949 /*******************************************************************************
1950 * Function Name: Cy_SCB_ClearSpiInterrupt
1951 ****************************************************************************//**
1952 *
1953 * Clears SPI interrupt sources in the interrupt request register.
1954 *
1955 * \param base
1956 * The pointer to the SCB instance.
1957 *
1958 * \param interruptMask
1959 * The SPI interrupt sources to be cleared.
1960 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1961 *
1962 *******************************************************************************/
Cy_SCB_ClearSpiInterrupt(CySCB_Type * base,uint32_t interruptMask)1963 __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interruptMask)
1964 {
1965 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
1966
1967 SCB_INTR_SPI_EC(base) = interruptMask;
1968 (void) SCB_INTR_SPI_EC(base);
1969 }
1970
1971 /** \cond INTERNAL */
1972 /*******************************************************************************
1973 * Function Name: Cy_SCB_GetFifoSize
1974 ****************************************************************************//**
1975 *
1976 * Returns the RX and TX FIFO depth.
1977 *
1978 * \param base
1979 * The pointer to the SCB instance.
1980 *
1981 * \return
1982 * FIFO depth.
1983 *
1984 *******************************************************************************/
Cy_SCB_GetFifoSize(CySCB_Type const * base)1985 __STATIC_INLINE uint32_t Cy_SCB_GetFifoSize(CySCB_Type const *base)
1986 {
1987 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
1988 {return (((uint32_t)(CY_SCB_FIFO_SIZE)) >> _FLD2VAL(SCB_CTRL_MEM_WIDTH, SCB_CTRL(base)));}
1989 #elif(defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION==1))
1990 {return (_FLD2BOOL(SCB_CTRL_BYTE_MODE, SCB_CTRL(base)) ? (CY_SCB_FIFO_SIZE) : (CY_SCB_FIFO_SIZE / 2UL));}
1991 #else
1992 return 0;
1993 #endif /* ((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) */
1994
1995 }
1996
1997
1998 /*******************************************************************************
1999 * Function Name: Cy_SCB_IsRxDataWidthByte
2000 ****************************************************************************//**
2001 *
2002 * Returns true if the RX data width is a byte (8 bits).
2003 *
2004 * \param base
2005 * The pointer to the SCB instance.
2006 *
2007 * \return
2008 * True if the RX data width is a byte (8 bits).
2009 *
2010 *******************************************************************************/
Cy_SCB_IsRxDataWidthByte(CySCB_Type const * base)2011 __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base)
2012 {
2013 return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
2014 }
2015
2016 /** \endcond */
2017
2018 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
2019 /*******************************************************************************
2020 * Function Name: Cy_SCB_Get_RxDataWidth
2021 ****************************************************************************//**
2022 *
2023 * Returns the RX data width.
2024 *
2025 * \param base
2026 * The pointer to the SCB instance.
2027 *
2028 * \return
2029 * RX data width.
2030 *
2031 *
2032 * \note
2033 * This API is available for CAT1B, CAT1C and CAT1D devices.
2034 *
2035 *******************************************************************************/
Cy_SCB_Get_RxDataWidth(CySCB_Type const * base)2036 __STATIC_INLINE uint32_t Cy_SCB_Get_RxDataWidth(CySCB_Type const *base)
2037 {
2038 return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) + 1UL);
2039 }
2040 #endif /* CY_IP_MXSCB_VERSION */
2041
2042 /*******************************************************************************
2043 * Function Name: Cy_SCB_IsTxDataWidthByte
2044 ****************************************************************************//**
2045 *
2046 * Returns true if the TX data width is a byte (8 bits).
2047 *
2048 * \param base
2049 * The pointer to the SCB instance.
2050 *
2051 * \return
2052 * If true, the TX data width is a byte (8 bits). Otherwise, false.
2053 *
2054 *******************************************************************************/
Cy_SCB_IsTxDataWidthByte(CySCB_Type const * base)2055 __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base)
2056 {
2057 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
2058 }
2059
2060 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
2061 /*******************************************************************************
2062 * Function Name: Cy_SCB_Get_TxDataWidth
2063 ****************************************************************************//**
2064 *
2065 * Returns the TX data width.
2066 *
2067 * \param base
2068 * The pointer to the SCB instance.
2069 *
2070 * \return
2071 * The TX data width.
2072 *
2073 *
2074 * \note
2075 * This API is available for CAT1B, CAT1C and CAT1D devices.
2076 *
2077 *******************************************************************************/
Cy_SCB_Get_TxDataWidth(CySCB_Type const * base)2078 __STATIC_INLINE uint32_t Cy_SCB_Get_TxDataWidth(CySCB_Type const *base)
2079 {
2080 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) + 1UL);
2081 }
2082 #endif /* CY_IP_MXSCB_VERSION */
2083
2084 /** \cond INTERNAL */
2085
2086 /*******************************************************************************
2087 * Function Name: Cy_SCB_FwBlockReset
2088 ****************************************************************************//**
2089 *
2090 * Disables and enables the block to return it into the known state (default):
2091 * FIFOs and interrupt statuses are cleared.
2092 *
2093 * \param base
2094 * The pointer to the SCB instance.
2095 *
2096 *******************************************************************************/
Cy_SCB_FwBlockReset(CySCB_Type * base)2097 __STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base)
2098 {
2099 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
2100
2101 /* Clean-up command registers */
2102 SCB_I2C_M_CMD(base) = 0UL;
2103 SCB_I2C_S_CMD(base) = 0UL;
2104
2105 SCB_CTRL(base) |= (uint32_t) SCB_CTRL_ENABLED_Msk;
2106
2107 (void) SCB_CTRL(base);
2108 }
2109
2110
2111 /*******************************************************************************
2112 * Function Name: Cy_SCB_GetRxFifoLevel
2113 ****************************************************************************//**
2114 *
2115 * Returns the RX FIFO level when there are more words in the RX FIFO than the
2116 * level, the RX FIFO level interrupt is triggered.
2117 *
2118 * \param base
2119 * The pointer to the SCB instance.
2120 *
2121 * \return
2122 * RX FIFO level.
2123 *
2124 *******************************************************************************/
Cy_SCB_GetRxFifoLevel(CySCB_Type const * base)2125 __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base)
2126 {
2127 return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, SCB_RX_FIFO_CTRL(base));
2128 }
2129
2130 /** \endcond */
2131 /** \} group_scb_common_functions */
2132
2133 #if defined(__cplusplus)
2134 }
2135 #endif
2136
2137 /** \} group_scb_common */
2138
2139 #endif /* (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB)) */
2140
2141 #endif /* (CY_SCB_COMMON_H) */
2142
2143 /* [] END OF FILE */
2144
