1 /***************************************************************************//**
2 * \file cy_scb_common.h
3 * \version 2.80
4 *
5 * Provides common API declarations of the SCB driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_scb
27 * \{
28 * The Serial Communications Block (SCB) supports three serial communication
29 * protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver
30 * Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of
31 * the protocols is supported by an SCB at any given time.
32 *
33 * The functions and other declarations used in this driver are in cy_scb_spi.h,
34 * cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h
35 * to get access to all functions and declarations in the PDL.
36
37 * \defgroup group_scb_common Common
38 * \defgroup group_scb_ezi2c EZI2C (SCB)
39 * \defgroup group_scb_i2c I2C (SCB)
40 * \defgroup group_scb_spi SPI (SCB)
41 * \defgroup group_scb_uart UART (SCB)
42 * \} */
43
44 /**
45 * \addtogroup group_scb
46 * \{
47 *
48 ********************************************************************************
49 * \section group_scb_more_information More Information
50 ********************************************************************************
51 * For more information on the SCB peripheral, refer to the technical reference
52 * manual (TRM).
53 *
54 *******************************************************************************
55 * \section group_scb_common_changelog Changelog
56 *******************************************************************************
57 * <table class="doxtable">
58 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
59 * <tr>
60 * <td>2.80</td>
61 * <td>Updated the behaviour of \ref Cy_SCB_UART_SetEnableMsbFirst and \ref Cy_SCB_UART_GetEnableMsbFirst functions.
62 * Now the value of enableMsbFirst is being set and fetched correctly.
63 * <td>Defect fixing.</td>
64 * </tr>
65 * <tr>
66 * <td rowspan="2">2.70</td>
67 * <td>Newly added API's for runtime parameter set/get functionality which include
68 * \ref Cy_SCB_UART_SetOverSample to set oversample bits of UART,
69 * \ref Cy_SCB_UART_GetOverSample to add return value of oversample,
70 * \ref Cy_SCB_UART_GetDataWidth to get data width,
71 * \ref Cy_SCB_UART_SetDataWidth to set data width,
72 * \ref Cy_SCB_UART_GetParity to get parity,
73 * \ref Cy_SCB_UART_SetParity to set parity,
74 * \ref Cy_SCB_UART_GetStopBits to get stop bits,
75 * \ref Cy_SCB_UART_SetStopBits to set stop bits,
76 * \ref Cy_SCB_UART_GetDropOnParityError to get drop on parity error,
77 * \ref Cy_SCB_UART_SetDropOnParityError to set drop on parity error,
78 * \ref Cy_SCB_UART_GetEnableMsbFirst to get enable MSB first and
79 * \ref Cy_SCB_UART_SetEnableMsbFirst to set enable MSB first.</td>
80 * <td>Runtime Parameter update.</td>
81 * </tr>
82 * <tr>
83 * <td>Newly added API's which include
84 * \ref Cy_SCB_Get_RxDataWidth to return the RX data width,
85 * \ref Cy_SCB_Get_TxDataWidth to return the TX data width,
86 * \ref Cy_SCB_SetMemWidth to set the RX and TX FIFOs byte mode/halfword/word mode.
87 * Updated Structures \ref cy_stc_scb_uart_config_t, \ref cy_en_scb_spi_parity_t, \ref cy_stc_scb_spi_config_t.</td>
88 * <td>New device support.</td>
89 * </tr>
90 * <tr>
91 * <td rowspan="2">2.60</td>
92 * <td>Fixed the \ref Cy_SCB_UART_GetNumInRingBuffer function to
93 * return correct number of the elements in ring buffer.</td>
94 * <td> \ref Cy_SCB_UART_GetNumInRingBuffer function works incorrectly, when
95 * write pointer of the ring buffer is behind the read pointer.</td>
96 * </tr>
97 * <tr>
98 * <td>Fixed/Documented MISRA 2012 violations.</td>
99 * <td>MISRA 2012 compliance.</td>
100 * </tr>
101 * <tr>
102 * <td>2.50</td>
103 * <td>Fixed the \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function to
104 * properly configure the polarity of the slave select line.</td>
105 * <td> \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function works incorrectly.</td>
106 * </tr>
107 * <tr>
108 * <td>2.40.2</td>
109 * <td>Minor documentation updates.</td>
110 * <td>Documentation enhancement.</td>
111 * </tr>
112 * <tr>
113 * <td rowspan="2">2.40</td>
114 * <td>Update level selection logic of RX FIFO trigger in the Cy_SCB_UART_Receive().</td>
115 * <td>Fix possible stuck if the RTS level is less than the RX FIFO level.</td>
116 * </tr>
117 * <tr>
118 * <td>Exclude self-test assertion macros under release build profile.</td>
119 * <td>Avoid dependency on CY_ASSERT macro implementation.</td>
120 * </tr>
121 * <tr>
122 * <td>2.30.1</td>
123 * <td>Added header guards CY_IP_MXSCB.</td>
124 * <td>To enable the PDL compilation with wounded out IP blocks.</td>
125 * </tr>
126 * <tr>
127 * <td rowspan="5">2.30</td>
128 * <td>Fixed MISRA violation.</td>
129 * <td>MISRA compliance.</td>
130 * </tr>
131 * <tr>
132 * <td>Changed values CY_SCB_SPI_CPHA0_CPOL1 and CY_SCB_SPI_CPHA1_CPOL0 in enum \ref cy_en_scb_spi_sclk_mode_t.</td>
133 * <td>The incorrect values in \ref cy_en_scb_spi_sclk_mode_t caused incorrect initialization of the combination of
134 * phases and polarity: "CHPA = 0, CPOL = 1" and "CHPA = 1, CPOL = 0".
135 * </td>
136 * </tr>
137 * <tr>
138 * <td>Added new CY_SCB_UART_RECEIVE_NOT_EMTPY and CY_SCB_UART_TRANSMIT_EMTPY callback events \ref group_scb_uart_macros_callback_events.</td>
139 * <td>Extended the driver callback events to support the MBED-OS.</td>
140 * </tr>
141 * <tr>
142 * <td>Merged SCB changelogs for each mode into one changelog.</td>
143 * <td>Changelog optimization.</td>
144 * </tr>
145 * <tr>
146 * <td>Merged SCB MISRA-C Compliance sections for each mode into one section.</td>
147 * <td>To optimize the SCB MISRA-C Compliance sections.</td>
148 * </tr>
149 * <tr>
150 * <td> 2.20.1</td>
151 * <td>Documentation of the MISRA rule violation.</td>
152 * <td>MISRA compliance.</td>
153 * </tr>
154 * <tr>
155 * <td rowspan="4">2.20</td>
156 * <td>Flattened the organization of the driver source code into the single
157 * source directory and the single include directory.
158 * </td>
159 * <td>Driver library directory-structure simplification.</td>
160 * </tr>
161 * <tr>
162 * <td>Added register access layer. Use register access macros instead
163 * of direct register access using dereferenced pointers.</td>
164 * <td>Makes register access device-independent, so that the PDL does
165 * not need to be recompiled for each supported part number.</td>
166 * </tr>
167 * <tr>
168 * <td>Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle
169 * fields to the \ref cy_stc_scb_i2c_config_t configuration structure.
170 * </td>
171 * <td>Added the I2C master data rate configuration using the configuration structure.
172 * </td>
173 * </tr>
174 * <tr>
175 * <td>Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates
176 * greater than 400 kbps in Master and Master-Slave modes. \n
177 * Added verification that clk_scb is within the valid range for the desired data rate.
178 * </td>
179 * <td>The analog filter was enabled for all data rates in Master and Master-Slave modes.
180 * This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter.
181 * </td>
182 * </tr>
183 * <tr>
184 * <td rowspan="4"> 2.10</td>
185 * <td>Fixed the ReStart condition generation sequence for a write
186 * transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
187 * <td>The driver can notify about a zero length write transaction completion
188 * before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
189 * function execution was interrupted between setting the restart
190 * generation command and writing the address byte into the TX FIFO.</td>
191 * </tr>
192 * <tr>
193 * <td>Added the slave- and master-specific interrupt functions:
194 * \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt.
195 * </td>
196 * <td>Improved the interrupt configuration options for the I2C slave and
197 * master mode configurations.</td>
198 * </tr>
199 * <tr>
200 * <td>Updated the Start condition generation sequence in the \ref
201 * Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
202 * <td></td>
203 * </tr>
204 * <tr>
205 * <td>Updated the ReStart condition generation sequence for a write
206 * transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.</td>
207 * <td></td>
208 * </tr>
209 * <tr>
210 * <td rowspan="9"> 2.0</td>
211 * <td>Added parameters validation for public API.
212 * <td></td>
213 * </tr>
214 * <tr>
215 * <td>Fixed functions which return interrupt status to return only defined
216 * set of interrupt statuses.</td>
217 * <td></td>
218 * </tr>
219 * <tr>
220 * <td>Added missing "cy_cb_" to the callback function type names.</td>
221 * <td></td>
222 * </tr>
223 * <tr>
224 * <td>Replaced variables that have limited range of values with enumerated
225 * types.</td>
226 * <td></td>
227 * </tr>
228 * <tr>
229 * <td>Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition
230 * generation.</td>
231 * <td></td>
232 * </tr>
233 * <tr>
234 * <td>Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and
235 * \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering
236 * low power mode when RX FIFO is not empty.</td>
237 * <td>The callbacks allowed entering device into low power mode when RX FIFO
238 * had data.</td>
239 * </tr>
240 * <tr>
241 * <td>Fixed SPI callback notification when error event occurred.</td>
242 * <td>The SPI callback passed incorrect event value if error event occurred.</td>
243 * </tr>
244 * <tr>
245 * <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
246 * generate the ReStart condition when the previous transaction was
247 * a write.</td>
248 * <td>The master interpreted the address byte written into the TX FIFO as a
249 * data byte and continued a write transaction. The ReStart condition was
250 * generated after the master completed transferring the data byte.
251 * The SCL line was stretched by the master waiting for the address byte
252 * to be written into the TX FIFO after the ReStart condition generation.
253 * The following timeout detection released the bus from the master
254 * control.</td>
255 * </tr>
256 * <tr>
257 * <td>Fixed the slave operation after the address byte was NACKed by the
258 * firmware.</td>
259 * <td>The observed slave operation failure depends on whether Level 2 assert
260 * is enabled or not. Enabled: the device stuck in the fault handler due
261 * to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
262 * the slave sets the transaction completion status and notifies on the
263 * transaction completion event after the address was NACKed. The failure
264 * is observed only when the slave is configured to accept an address in
265 * the RX FIFO.</td>
266 * </tr>
267 * <tr>
268 * <td>1.0</td>
269 * <td>Initial version.</td>
270 * <td></td>
271 * </tr>
272 * </table>
273 */
274
275 /** \} group_scb */
276 /**
277 * \addtogroup group_scb_common
278 * \{
279 *
280 * Common API for the Serial Communication Block.
281 *
282 * This is the common API that provides an interface to the SCB hardware.
283 * The I2C, SPI, and UART drivers use this common API.
284 * Most users will use individual drivers and do not need to use the common
285 * API for the SCB. However, you can use the common SCB API to implement
286 * a custom driver based on the SCB hardware.
287 *
288 * The functions and other declarations used in this part of the driver are in
289 * cy_scb_common.h. You can include either of cy_scb_spi.h, cy_scb_uart.h,
290 * cy_scb_ezi2c.h, cy_scb_i2c.h depending on the desired functionality.
291 * You can also include cy_pdl.h to get access to all functions and declarations
292 * in the PDL.
293 *
294 *******************************************************************************
295 * \section group_scb_common_configuration Configuration Considerations
296 ********************************************************************************
297 * This is not a driver and it does not require configuration.
298 *
299 * \defgroup group_scb_common_macros Macros
300 * \defgroup group_scb_common_functions Functions
301 * \defgroup group_scb_common_data_structures Data Structures
302 *
303 */
304
305 #if !defined(CY_SCB_COMMON_H)
306 #define CY_SCB_COMMON_H
307
308 #include "cy_device.h"
309
310 #if defined (CY_IP_MXSCB)
311
312 #include <stdint.h>
313 #include <stddef.h>
314 #include <stdbool.h>
315 #include "cy_syslib.h"
316 #include "cy_syspm.h"
317
318 #if defined(__cplusplus)
319 extern "C" {
320 #endif
321
322
323 /*******************************************************************************
324 * Function Prototypes
325 *******************************************************************************/
326
327 /**
328 * \addtogroup group_scb_common_functions
329 * \{
330 */
331 __STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base);
332 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
333 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base);
334 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base);
335 __STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base);
336
337 __STATIC_INLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data);
338 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
339 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base);
340 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base);
341 __STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base);
342 __STATIC_INLINE void Cy_SCB_ClearTxFifo (CySCB_Type *base);
343
344 __STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode);
345
346 __STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base);
347
348 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base);
349 __STATIC_INLINE void Cy_SCB_SetRxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
350 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask (CySCB_Type const *base);
351 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base);
352 __STATIC_INLINE void Cy_SCB_ClearRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
353 __STATIC_INLINE void Cy_SCB_SetRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
354
355 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base);
356 __STATIC_INLINE void Cy_SCB_SetTxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
357 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask (CySCB_Type const *base);
358 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base);
359 __STATIC_INLINE void Cy_SCB_ClearTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
360 __STATIC_INLINE void Cy_SCB_SetTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
361
362 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base);
363 __STATIC_INLINE void Cy_SCB_SetMasterInterruptMask (CySCB_Type *base, uint32_t interruptMask);
364 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask (CySCB_Type const *base);
365 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base);
366 __STATIC_INLINE void Cy_SCB_ClearMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
367 __STATIC_INLINE void Cy_SCB_SetMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
368
369 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base);
370 __STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask (CySCB_Type *base, uint32_t interruptMask);
371 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask (CySCB_Type const *base);
372 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base);
373 __STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
374 __STATIC_INLINE void Cy_SCB_SetSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
375
376 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base);
377 __STATIC_INLINE void Cy_SCB_SetI2CInterruptMask (CySCB_Type *base, uint32_t interruptMask);
378 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask (CySCB_Type const *base);
379 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base);
380 __STATIC_INLINE void Cy_SCB_ClearI2CInterrupt (CySCB_Type *base, uint32_t interruptMask);
381
382 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base);
383 __STATIC_INLINE void Cy_SCB_SetSpiInterruptMask (CySCB_Type *base, uint32_t interruptMask);
384 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask (CySCB_Type const *base);
385 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base);
386 __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt (CySCB_Type *base, uint32_t interruptMask);
387
388
389 /*******************************************************************************
390 * Internal Function Prototypes
391 *******************************************************************************/
392
393 /** \cond INTERNAL */
394 void Cy_SCB_ReadArrayNoCheck (CySCB_Type const *base, void *buffer, uint32_t size);
395 uint32_t Cy_SCB_ReadArray (CySCB_Type const *base, void *buffer, uint32_t size);
396 void Cy_SCB_ReadArrayBlocking (CySCB_Type const *base, void *buffer, uint32_t size);
397 uint32_t Cy_SCB_Write (CySCB_Type *base, uint32_t data);
398 void Cy_SCB_WriteArrayNoCheck (CySCB_Type *base, void *buffer, uint32_t size);
399 uint32_t Cy_SCB_WriteArray (CySCB_Type *base, void *buffer, uint32_t size);
400 void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
401 void Cy_SCB_WriteString (CySCB_Type *base, char_t const string[]);
402 void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size);
403 uint32_t Cy_SCB_WriteDefaultArray (CySCB_Type *base, uint32_t txData, uint32_t size);
404
405 __STATIC_INLINE uint32_t Cy_SCB_GetFifoSize (CySCB_Type const *base);
406 __STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base);
407 __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base);
408 __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base);
409 __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
410 #if(CY_IP_MXSCB_VERSION>=3)
411 __STATIC_INLINE uint32_t Cy_SCB_Get_RxDataWidth(CySCB_Type const *base);
412 __STATIC_INLINE uint32_t Cy_SCB_Get_TxDataWidth(CySCB_Type const *base);
413 #endif /* CY_IP_MXSCB_VERSION */
414 /** \endcond */
415
416 /** \} group_scb_common_functions */
417
418
419 /*******************************************************************************
420 * API Constants
421 *******************************************************************************/
422
423 /**
424 * \addtogroup group_scb_common_macros
425 * \{
426 */
427
428 /** Driver major version */
429 #define CY_SCB_DRV_VERSION_MAJOR (2)
430
431 /** Driver minor version */
432 #define CY_SCB_DRV_VERSION_MINOR (80)
433
434 /** SCB driver identifier */
435 #define CY_SCB_ID CY_PDL_DRV_ID(0x2AU)
436
437 /** Position for SCB driver sub mode */
438 #define CY_SCB_SUB_MODE_Pos (13UL)
439
440 /** EZI2C mode identifier */
441 #define CY_SCB_EZI2C_ID (0x0UL << CY_SCB_SUB_MODE_Pos)
442
443 /** EZI2C mode identifier */
444 #define CY_SCB_I2C_ID (0x1UL << CY_SCB_SUB_MODE_Pos)
445
446 /** EZI2C mode identifier */
447 #define CY_SCB_SPI_ID (0x2UL << CY_SCB_SUB_MODE_Pos)
448
449 /** EZI2C mode identifier */
450 #define CY_SCB_UART_ID (0x3UL << CY_SCB_SUB_MODE_Pos)
451
452 /**
453 * \defgroup group_scb_common_macros_intr_cause SCB Interrupt Causes
454 * \{
455 */
456 /** Interrupt from Master interrupt sources */
457 #define CY_SCB_MASTER_INTR SCB_INTR_CAUSE_M_Msk
458
459 /** Interrupt from Slave interrupt sources */
460 #define CY_SCB_SLAVE_INTR SCB_INTR_CAUSE_S_Msk
461
462 /** Interrupt from TX interrupt sources */
463 #define CY_SCB_TX_INTR SCB_INTR_CAUSE_TX_Msk
464
465 /** Interrupt from RX interrupt sources */
466 #define CY_SCB_RX_INTR SCB_INTR_CAUSE_RX_Msk
467
468 /** Interrupt from I2C externally clocked interrupt sources */
469 #define CY_SCB_I2C_INTR SCB_INTR_CAUSE_I2C_EC_Msk
470
471 /** Interrupt from SPI externally clocked interrupt sources */
472 #define CY_SCB_SPI_INTR SCB_INTR_CAUSE_SPI_EC_Msk
473 /** \} group_scb_common_macros_intr_cause */
474
475 /**
476 * \defgroup group_scb_common_macros_tx_intr TX Interrupt Statuses
477 * \{
478 */
479 /**
480 * The number of data elements in the TX FIFO is less than the value
481 * of the TX FIFO level
482 */
483 #define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk
484
485 /** The TX FIFO is not full */
486 #define CY_SCB_TX_INTR_NOT_FULL SCB_INTR_TX_NOT_FULL_Msk
487
488 /** The TX FIFO is empty */
489 #define CY_SCB_TX_INTR_EMPTY SCB_INTR_TX_EMPTY_Msk
490
491 /** An attempt to write to a full TX FIFO */
492 #define CY_SCB_TX_INTR_OVERFLOW SCB_INTR_TX_OVERFLOW_Msk
493
494 /** An attempt to read from an empty TX FIFO */
495 #define CY_SCB_TX_INTR_UNDERFLOW SCB_INTR_TX_UNDERFLOW_Msk
496
497 /** The UART transfer is complete: all data elements from the TX FIFO are sent
498 */
499 #define CY_SCB_TX_INTR_UART_DONE SCB_INTR_TX_UART_DONE_Msk
500
501 /** SmartCard only: UART received a NACK */
502 #define CY_SCB_TX_INTR_UART_NACK SCB_INTR_TX_UART_NACK_Msk
503
504 /**
505 * SmartCard only: the value on the TX line of the UART does not match the
506 * value on the RX line
507 */
508 #define CY_SCB_TX_INTR_UART_ARB_LOST SCB_INTR_TX_UART_ARB_LOST_Msk
509 /** \} group_scb_common_macros_tx_intr */
510
511 /**
512 * \defgroup group_scb_common_macros_rx_intr RX Interrupt Statuses
513 * \{
514 */
515 /**
516 * The number of data elements in the RX FIFO is greater than the value of the
517 * RX FIFO level
518 */
519 #define CY_SCB_RX_INTR_LEVEL SCB_INTR_RX_TRIGGER_Msk
520
521 /** The RX FIFO is not empty */
522 #define CY_SCB_RX_INTR_NOT_EMPTY SCB_INTR_RX_NOT_EMPTY_Msk
523
524 /** The RX FIFO is full */
525 #define CY_SCB_RX_INTR_FULL SCB_INTR_RX_FULL_Msk
526
527 /** An attempt to write to a full RX FIFO */
528 #define CY_SCB_RX_INTR_OVERFLOW SCB_INTR_RX_OVERFLOW_Msk
529
530 /** An attempt to read from an empty RX FIFO */
531 #define CY_SCB_RX_INTR_UNDERFLOW SCB_INTR_RX_UNDERFLOW_Msk
532
533 /** A UART framing error detected */
534 #define CY_SCB_RX_INTR_UART_FRAME_ERROR SCB_INTR_RX_FRAME_ERROR_Msk
535
536 /** A UART parity error detected */
537 #define CY_SCB_RX_INTR_UART_PARITY_ERROR SCB_INTR_RX_PARITY_ERROR_Msk
538
539 /** A UART break detected */
540 #define CY_SCB_RX_INTR_UART_BREAK_DETECT SCB_INTR_RX_BREAK_DETECT_Msk
541 /** \} group_scb_common_macros_rx_intr */
542
543 /**
544 * \defgroup group_scb_common_macros_slave_intr Slave Interrupt Statuses
545 * \{
546 */
547 /**
548 * I2C slave lost arbitration: the value driven on the SDA line is not the same
549 * as the value observed on the SDA line
550 */
551 #define CY_SCB_SLAVE_INTR_I2C_ARB_LOST SCB_INTR_S_I2C_ARB_LOST_Msk
552
553 /** The I2C slave received a NAK */
554 #define CY_SCB_SLAVE_INTR_I2C_NACK SCB_INTR_S_I2C_NACK_Msk
555
556 /** The I2C slave received an ACK */
557 #define CY_SCB_SLAVE_INTR_I2C_ACK SCB_INTR_S_I2C_ACK_Msk
558
559 /**
560 * A Stop or Repeated Start event for a write transfer intended for this slave
561 * was detected.
562 */
563 #define CY_SCB_SLAVE_INTR_I2C_WRITE_STOP SCB_INTR_S_I2C_WRITE_STOP_Msk
564
565 /** A Stop or Repeated Start event intended for this slave was detected */
566 #define CY_SCB_SLAVE_INTR_I2C_STOP SCB_INTR_S_I2C_STOP_Msk
567
568 /** The I2C slave received a Start condition */
569 #define CY_SCB_SLAVE_INTR_I2C_START SCB_INTR_S_I2C_START_Msk
570
571 /** The I2C slave received the matching address */
572 #define CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH SCB_INTR_S_I2C_ADDR_MATCH_Msk
573
574 /** The I2C Slave received the general call address */
575 #define CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR SCB_INTR_S_I2C_GENERAL_Msk
576
577 /** The I2C slave bus error (detection of unexpected Start or Stop condition) */
578 #define CY_SCB_SLAVE_INTR_I2C_BUS_ERROR SCB_INTR_S_I2C_BUS_ERROR_Msk
579
580 /**
581 * The SPI slave select line is deselected at an expected time during an
582 * SPI transfer.
583 */
584 #define CY_SCB_SLAVE_INTR_SPI_BUS_ERROR SCB_INTR_S_SPI_BUS_ERROR_Msk
585 /** \} group_scb_common_macros_slave_intr */
586
587 /**
588 * \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses
589 * \{
590 */
591 /** The I2C master lost arbitration */
592 #define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk
593
594 /** The I2C master received a NACK */
595 #define CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk
596
597 /** The I2C master received an ACK */
598 #define CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk
599
600 /** The I2C master generated a Stop */
601 #define CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk
602
603 /** The I2C master bus error (detection of unexpected START or STOP condition)
604 */
605 #define CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk
606
607 /**
608 * The SPI master transfer is complete: all data elements transferred from the
609 * TX FIFO and TX shift register.
610 */
611 #define CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk
612 /** \} group_scb_common_macros_master_intr */
613
614 /**
615 * \defgroup group_scb_common_macros_i2c_intr I2C Interrupt Statuses
616 * \{
617 */
618 /**
619 * Wake up request: the I2C slave received the matching address.
620 * Note that this interrupt source triggers in active mode.
621 */
622 #define CY_SCB_I2C_INTR_WAKEUP SCB_INTR_I2C_EC_WAKE_UP_Msk
623 /** \} group_scb_common_macros_i2c_intr */
624
625 /**
626 * \defgroup group_scb_common_macros_SpiIntrStatuses SPI Interrupt Statuses
627 * \{
628 */
629 /**
630 * Wake up request: the SPI slave detects an active edge of the slave select
631 * signal. Note that this interrupt source triggers in active mode.
632 */
633 #define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk
634 /** \} group_scb_common_macros_SpiIntrStatuses */
635
636
637 /*******************************************************************************
638 * Internal Constants
639 *******************************************************************************/
640
641 /** \cond INTERNAL */
642
643 /* Default registers values */
644 #define CY_SCB_CTRL_DEF_VAL (_VAL2FLD(SCB_CTRL_OVS, 15UL) | \
645 _VAL2FLD(SCB_CTRL_MODE, 3UL))
646
647 #define CY_SCB_I2C_CTRL_DEF_VAL (_VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
648 _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
649 _VAL2FLD(SCB_I2C_CTRL_M_READY_DATA_ACK, 1UL) | \
650 _VAL2FLD(SCB_I2C_CTRL_M_NOT_READY_DATA_NACK, 1UL) | \
651 _VAL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, 1UL) | \
652 _VAL2FLD(SCB_I2C_CTRL_S_READY_ADDR_ACK, 1UL) | \
653 _VAL2FLD(SCB_I2C_CTRL_S_READY_DATA_ACK, 1UL) | \
654 _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK, 1UL) | \
655 _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_DATA_NACK, 1UL))
656
657 #define CY_SCB_I2C_CFG_DEF_VAL (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 3UL) | \
658 _VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_SEL, 1UL) | \
659 _VAL2FLD(SCB_I2C_CFG_SCL_IN_FILT_SEL, 1UL) | \
660 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT0_TRIM, 2UL) | \
661 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT1_TRIM, 2UL) | \
662 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT2_TRIM, 2UL))
663
664 #define CY_SCB_SPI_CTRL_DEF_VAL _VAL2FLD(SCB_SPI_CTRL_MODE, 3UL)
665 #define CY_SCB_UART_CTRL_DEF_VAL _VAL2FLD(SCB_UART_CTRL_MODE, 3UL)
666
667 #define CY_SCB_UART_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, 2UL) | \
668 _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, 10UL))
669
670 #define CY_SCB_UART_TX_CTRL_DEF_VAL _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, 2UL)
671
672 #define CY_SCB_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, 7UL) | \
673 _VAL2FLD(SCB_RX_CTRL_MSB_FIRST, 1UL))
674
675 #define CY_SCB_TX_CTRL_DEF_VAL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, 7UL) | \
676 _VAL2FLD(SCB_TX_CTRL_MSB_FIRST, 1UL))
677
678 /* SCB CTRL modes */
679 #define CY_SCB_CTRL_MODE_I2C (0UL)
680 #define CY_SCB_CTRL_MODE_SPI (1UL)
681 #define CY_SCB_CTRL_MODE_UART (2UL)
682
683 /* The position and mask to set the I2C mode */
684 #define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos
685 #define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \
686 SCB_I2C_CTRL_MASTER_MODE_Msk)
687
688 /* Cypress ID #282226:
689 * SCB_I2C_CFG_SDA_IN_FILT_TRIM[1]: SCB clock enable (1), clock disable (0).
690 */
691 #define CY_SCB_I2C_CFG_CLK_ENABLE_Msk (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 2UL))
692
693 /* I2C has fixed data width */
694 #define CY_SCB_I2C_DATA_WIDTH (7UL)
695
696 /* RX and TX control register values */
697 #define CY_SCB_I2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
698 SCB_RX_CTRL_MSB_FIRST_Msk)
699 #define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
700 SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk)
701
702 /* The position and mask to make an address byte */
703 #define CY_SCB_I2C_ADDRESS_Pos (1UL)
704 #define CY_SCB_I2C_ADDRESS_Msk (0xFEUL)
705
706 /* SPI slave select polarity */
707 #define CY_SCB_SPI_CTRL_SSEL_POLARITY_Pos SCB_SPI_CTRL_SSEL_POLARITY0_Pos
708 #define CY_SCB_SPI_CTRL_SSEL_POLARITY_Msk (SCB_SPI_CTRL_SSEL_POLARITY0_Msk | \
709 SCB_SPI_CTRL_SSEL_POLARITY1_Msk | \
710 SCB_SPI_CTRL_SSEL_POLARITY2_Msk | \
711 SCB_SPI_CTRL_SSEL_POLARITY3_Msk)
712
713 #if(CY_IP_MXSCB_VERSION>=3)
714 /* SPI parity and parity enable combination */
715 #define CY_SCB_SPI_RX_CTRL_SET_PARITY_Msk (SCB_SPI_RX_CTRL_PARITY_ENABLED_Msk | \
716 SCB_SPI_RX_CTRL_PARITY_Msk)
717 #define CY_SCB_SPI_RX_CTRL_SET_PARITY_Pos SCB_SPI_RX_CTRL_PARITY_Pos
718
719 #define CY_SCB_SPI_TX_CTRL_SET_PARITY_Msk (SCB_SPI_TX_CTRL_PARITY_ENABLED_Msk | \
720 SCB_SPI_TX_CTRL_PARITY_Msk)
721 #define CY_SCB_SPI_TX_CTRL_SET_PARITY_Pos SCB_SPI_TX_CTRL_PARITY_Pos
722 #endif /* CY_IP_MXSCB_VERSION */
723
724 /* SPI clock modes: CPHA and CPOL */
725 #define CY_SCB_SPI_CTRL_CLK_MODE_Pos SCB_SPI_CTRL_CPHA_Pos
726 #define CY_SCB_SPI_CTRL_CLK_MODE_Msk (SCB_SPI_CTRL_CPHA_Msk | SCB_SPI_CTRL_CPOL_Msk)
727
728 /* UART parity and parity enable combination */
729 #define CY_SCB_UART_RX_CTRL_SET_PARITY_Msk (SCB_UART_RX_CTRL_PARITY_ENABLED_Msk | \
730 SCB_UART_RX_CTRL_PARITY_Msk)
731 #define CY_SCB_UART_RX_CTRL_SET_PARITY_Pos SCB_UART_RX_CTRL_PARITY_Pos
732
733 #define CY_SCB_UART_TX_CTRL_SET_PARITY_Msk (SCB_UART_TX_CTRL_PARITY_ENABLED_Msk | \
734 SCB_UART_TX_CTRL_PARITY_Msk)
735 #define CY_SCB_UART_TX_CTRL_SET_PARITY_Pos SCB_UART_TX_CTRL_PARITY_Pos
736
737 /* Max number of bits for byte mode */
738 #define CY_SCB_BYTE_WIDTH (8UL)
739
740 #if(CY_IP_MXSCB_VERSION>=3)
741 /* Max number of bits for HALF WORD mode */
742 #define CY_SCB_HALF_WORD_WIDTH (16UL)
743
744 /* Max number of bits for WORD mode */
745 #define CY_SCB_WORD_WIDTH (32UL)
746
747 /*SCB Mem width modes */
748 #define CY_SCB_MEM_WIDTH_BYTE (0UL)
749 #define CY_SCB_MEM_WIDTH_HALFWORD (1UL)
750 #define CY_SCB_MEM_WIDTH_WORD (2UL)
751 #endif /* CY_IP_MXSCB_VERSION */
752
753 /* Single unit to wait */
754 #define CY_SCB_WAIT_1_UNIT (1U)
755
756 /* Clear interrupt sources */
757 #define CY_SCB_CLEAR_ALL_INTR_SRC (0UL)
758
759 /* Hardware FIFO size: EZ_DATA_NR / 4 = (512 / 4) = 128 */
760 #define CY_SCB_FIFO_SIZE (128UL)
761
762 /* Provides a list of allowed sources */
763 #define CY_SCB_TX_INTR_MASK (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_NOT_FULL | CY_SCB_TX_INTR_EMPTY | \
764 CY_SCB_TX_INTR_OVERFLOW | CY_SCB_TX_INTR_UNDERFLOW | CY_SCB_TX_INTR_UART_DONE | \
765 CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
766
767 #define CY_SCB_RX_INTR_MASK (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_FULL | \
768 CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UNDERFLOW | \
769 CY_SCB_RX_INTR_UART_FRAME_ERROR | CY_SCB_RX_INTR_UART_PARITY_ERROR | \
770 CY_SCB_RX_INTR_UART_BREAK_DETECT)
771
772
773 #define CY_SCB_SLAVE_INTR_MASK (CY_SCB_SLAVE_INTR_I2C_ARB_LOST | CY_SCB_SLAVE_INTR_I2C_NACK | CY_SCB_SLAVE_INTR_I2C_ACK | \
774 CY_SCB_SLAVE_INTR_I2C_WRITE_STOP | CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_START | \
775 CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
776 CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_SPI_BUS_ERROR)
777
778 #define CY_SCB_MASTER_INTR_MASK (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_NACK | \
779 CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_STOP | \
780 CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_SPI_DONE)
781
782 #define CY_SCB_I2C_INTR_MASK CY_SCB_I2C_INTR_WAKEUP
783
784 #define CY_SCB_SPI_INTR_MASK CY_SCB_SPI_INTR_WAKEUP
785
786 #if(CY_IP_MXSCB_VERSION>=3)
787 #define CY_SCB_IS_MEMWIDTH_VALID(memwidth) ((memwidth) <= CY_SCB_MEM_WIDTH_WORD)
788 #endif /* CY_IP_MXSCB_VERSION */
789
790 #define CY_SCB_IS_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) )
791 #define CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level) ((level) < Cy_SCB_GetFifoSize(base))
792
793 #define CY_SCB_IS_I2C_ADDR_VALID(addr) ( (0U == ((addr) & 0x80U)) )
794 #define CY_SCB_IS_BUFFER_VALID(buffer, size) ( (NULL != (buffer)) && ((size) > 0UL) )
795 #define CY_SCB_IS_I2C_BUFFER_VALID(buffer, size) ( (0UL == (size)) ? true : (NULL != (buffer)) )
796 /** \endcond */
797
798 /** \} group_scb_common_macros */
799
800
801 /*******************************************************************************
802 * In-line Function Implementation
803 *******************************************************************************/
804
805 /**
806 * \addtogroup group_scb_common_functions
807 * \{
808 */
809
810 /*******************************************************************************
811 * Function Name: Cy_SCB_ReadRxFifo
812 ****************************************************************************//**
813 *
814 * Reads a data element directly out of the RX FIFO.
815 * This function does not check whether the RX FIFO has data before reading it.
816 *
817 * \param base
818 * The pointer to the SCB instance.
819 *
820 * \return
821 * Data from RX FIFO.
822 *
823 *******************************************************************************/
Cy_SCB_ReadRxFifo(CySCB_Type const * base)824 __STATIC_INLINE uint32_t Cy_SCB_ReadRxFifo(CySCB_Type const *base)
825 {
826 return (SCB_RX_FIFO_RD(base));
827 }
828
829 /*******************************************************************************
830 * Function Name: Cy_SCB_SetRxFifoLevel
831 ****************************************************************************//**
832 *
833 * Sets the RX FIFO level. When there are more data elements in the RX FIFO than
834 * this level, the RX FIFO level interrupt is triggered.
835 *
836 * \param base
837 * The pointer to the SCB instance.
838 *
839 * \param level
840 * When there are more data elements in the FIFO than this level, the RX level
841 * interrupt is triggered.
842 *
843 *******************************************************************************/
Cy_SCB_SetRxFifoLevel(CySCB_Type * base,uint32_t level)844 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level)
845 {
846 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
847
848 CY_REG32_CLR_SET(SCB_RX_FIFO_CTRL(base), SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level);
849 }
850
851
852 /*******************************************************************************
853 * Function Name: Cy_SCB_GetNumInRxFifo
854 ****************************************************************************//**
855 *
856 * Returns the number of data elements currently in the RX FIFO.
857 *
858 * \param base
859 * The pointer to the SCB instance.
860 *
861 * \return
862 * The number or data elements in RX FIFO.
863 *
864 *******************************************************************************/
Cy_SCB_GetNumInRxFifo(CySCB_Type const * base)865 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base)
866 {
867 return _FLD2VAL(SCB_RX_FIFO_STATUS_USED, SCB_RX_FIFO_STATUS(base));
868 }
869
870
871 /*******************************************************************************
872 * Function Name: Cy_SCB_GetRxSrValid
873 ****************************************************************************//**
874 *
875 * Returns the status of the RX FIFO Shift Register valid bit.
876 *
877 * \param base
878 * The pointer to the SCB instance.
879 *
880 * \return
881 * 1 - RX shift register valid; 0 - RX shift register not valid.
882 *
883 *******************************************************************************/
Cy_SCB_GetRxSrValid(CySCB_Type const * base)884 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
885 {
886 return _FLD2VAL(SCB_RX_FIFO_STATUS_SR_VALID, SCB_RX_FIFO_STATUS(base));
887 }
888
889
890 /*******************************************************************************
891 * Function Name: Cy_SCB_ClearRxFifo
892 ****************************************************************************//**
893 *
894 * Clears the RX FIFO and shifter.
895 *
896 * \param base
897 * The pointer to the SCB instance.
898 *
899 * \note
900 * If there is partial data in the shifter, it is cleared and lost.
901 *
902 *******************************************************************************/
Cy_SCB_ClearRxFifo(CySCB_Type * base)903 __STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
904 {
905 SCB_RX_FIFO_CTRL(base) |= (uint32_t) SCB_RX_FIFO_CTRL_CLEAR_Msk;
906 SCB_RX_FIFO_CTRL(base) &= (uint32_t) ~SCB_RX_FIFO_CTRL_CLEAR_Msk;
907
908 (void) SCB_RX_FIFO_CTRL(base);
909 }
910
911
912 /*******************************************************************************
913 * Function Name: Cy_SCB_WriteTxFifo
914 ****************************************************************************//**
915 *
916 * Writes data directly into the TX FIFO.
917 * This function does not check whether the TX FIFO is not full before writing
918 * into it.
919 *
920 * \param base
921 * The pointer to the SCB instance.
922 *
923 * \param data
924 * Data to write to the TX FIFO.
925 *
926 *******************************************************************************/
Cy_SCB_WriteTxFifo(CySCB_Type * base,uint32_t data)927 __STATIC_INLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data)
928 {
929 SCB_TX_FIFO_WR(base) = data;
930 }
931
932
933 /*******************************************************************************
934 * Function Name: Cy_SCB_SetTxFifoLevel
935 ****************************************************************************//**
936 *
937 * Sets the TX FIFO level. When there are fewer data elements in the TX FIFO than
938 * this level, the TX FIFO level interrupt is triggered.
939 *
940 * \param base
941 * The pointer to the SCB instance.
942 *
943 * \param level
944 * When there are fewer data elements in the FIFO than this level, the TX level
945 * interrupt is triggered.
946 *
947 *******************************************************************************/
Cy_SCB_SetTxFifoLevel(CySCB_Type * base,uint32_t level)948 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level)
949 {
950 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
951
952 CY_REG32_CLR_SET(SCB_TX_FIFO_CTRL(base), SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level);
953 }
954
955
956 /*******************************************************************************
957 * Function Name: Cy_SCB_GetNumInTxFifo
958 ****************************************************************************//**
959 *
960 * Returns the number of data elements currently in the TX FIFO.
961 *
962 * \param base
963 * The pointer to the SCB instance.
964 *
965 * \return
966 * The number or data elements in the TX FIFO.
967 *
968 *******************************************************************************/
Cy_SCB_GetNumInTxFifo(CySCB_Type const * base)969 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base)
970 {
971 return _FLD2VAL(SCB_TX_FIFO_STATUS_USED, SCB_TX_FIFO_STATUS(base));
972 }
973
974
975 /*******************************************************************************
976 * Function Name: Cy_SCB_GetTxSrValid
977 ****************************************************************************//**
978 *
979 * Returns the status of the TX FIFO Shift Register valid bit.
980 *
981 * \param base
982 * The pointer to the SCB instance.
983 *
984 * \return
985 * 1 - TX shift register valid; 0 - TX shift register not valid.
986 *
987 *******************************************************************************/
Cy_SCB_GetTxSrValid(CySCB_Type const * base)988 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
989 {
990 return _FLD2VAL(SCB_TX_FIFO_STATUS_SR_VALID, SCB_TX_FIFO_STATUS(base));
991 }
992
993
994 /*******************************************************************************
995 * Function Name: Cy_SCB_IsTxComplete
996 ****************************************************************************//**
997 *
998 * Checks whether the TX FIFO and Shifter are empty and there is no more data to send.
999 *
1000 * \param base
1001 * Pointer to SPI the SCB instance.
1002 *
1003 * \return
1004 * If true, transmission complete. If false, transmission is not complete.
1005 *
1006 *******************************************************************************/
Cy_SCB_IsTxComplete(CySCB_Type const * base)1007 __STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base)
1008 {
1009 return (0UL == (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base)));
1010 }
1011
1012
1013 /*******************************************************************************
1014 * Function Name: Cy_SCB_ClearTxFifo
1015 ****************************************************************************//**
1016 *
1017 * Clears the TX FIFO.
1018 *
1019 * \param base
1020 * The pointer to the SCB instance.
1021 *
1022 * \note
1023 * The TX FIFO clear operation also clears the shift register. Thus the shifter
1024 * could be cleared in the middle of a data element transfer. Thia results in
1025 * "ones" being sent on the bus for the remainder of the transfer.
1026 *
1027 *******************************************************************************/
Cy_SCB_ClearTxFifo(CySCB_Type * base)1028 __STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base)
1029 {
1030 SCB_TX_FIFO_CTRL(base) |= (uint32_t) SCB_TX_FIFO_CTRL_CLEAR_Msk;
1031 SCB_TX_FIFO_CTRL(base) &= (uint32_t) ~SCB_TX_FIFO_CTRL_CLEAR_Msk;
1032
1033 (void) SCB_TX_FIFO_CTRL(base);
1034 }
1035
1036
1037 /*******************************************************************************
1038 * Function Name: Cy_SCB_SetByteMode
1039 ****************************************************************************//**
1040 *
1041 * Sets whether the RX and TX FIFOs are in byte mode.
1042 * The FIFOs are either 16-bit wide or 8-bit wide (byte mode).
1043 * When the FIFO is in byte mode it is twice as deep. See the device datasheet
1044 * for FIFO depths.
1045 *
1046 * \param base
1047 * The pointer to the SCB instance.
1048 *
1049 * \param byteMode
1050 * If true, TX and RX FIFOs are 8-bit wide. If false, the FIFOs are 16-bit wide.
1051 *
1052 *******************************************************************************/
Cy_SCB_SetByteMode(CySCB_Type * base,bool byteMode)1053 __STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode)
1054 {
1055 #if(CY_IP_MXSCB_VERSION>=3)
1056 SCB_CTRL(base) &= ~SCB_CTRL_MEM_WIDTH_Msk;
1057 if (byteMode)
1058 {
1059 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, CY_SCB_MEM_WIDTH_BYTE);
1060 }
1061 else
1062 {
1063 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, CY_SCB_MEM_WIDTH_HALFWORD);
1064 }
1065 #elif(CY_IP_MXSCB_VERSION==1)
1066 if (byteMode)
1067 {
1068 SCB_CTRL(base) |= SCB_CTRL_BYTE_MODE_Msk;
1069 }
1070 else
1071 {
1072 SCB_CTRL(base) &= ~SCB_CTRL_BYTE_MODE_Msk;
1073 }
1074 #endif /* CY_IP_MXSCB_VERSION */
1075 }
1076
1077 #if(CY_IP_MXSCB_VERSION>=3) || defined (CY_DOXYGEN)
1078 /*******************************************************************************
1079 * Function Name: Cy_SCB_SetMemWidth
1080 ****************************************************************************//**
1081 *
1082 * Sets the RX and TX FIFOs byte mode/halfword/word mode.
1083 * The FIFOs are either 8-bit(byte),16-bit(halfword) or 32-bit (word) wide.
1084 * See the device datasheet for FIFO depths.
1085 *
1086 * \param base
1087 * The pointer to the SCB instance.
1088 *
1089 * \param MemWidthMode
1090 * If 0x0, TX and RX FIFOs are 8-bit wide.
1091 * If 0x1, the FIFOs are 16-bit wide.
1092 * If 0x2, the FIFOs are 32-bit wide.
1093 *
1094 * \note
1095 * This API is available for CAT1B devices.
1096 *
1097 *******************************************************************************/
Cy_SCB_SetMemWidth(CySCB_Type * base,uint32_t MemWidthMode)1098 __STATIC_INLINE void Cy_SCB_SetMemWidth(CySCB_Type *base, uint32_t MemWidthMode)
1099 {
1100 CY_ASSERT_L2(CY_SCB_IS_MEMWIDTH_VALID(MemWidthMode));
1101
1102 SCB_CTRL(base) &= ~SCB_CTRL_MEM_WIDTH_Msk;
1103
1104 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, MemWidthMode);
1105 }
1106 #endif /* CY_IP_MXSCB_VERSION */
1107
1108 /*******************************************************************************
1109 * Function Name: Cy_SCB_GetInterruptCause
1110 ****************************************************************************//**
1111 *
1112 * Returns the mask of bits showing the source of the current triggered
1113 * interrupt. This is useful for modes of operation where an interrupt can
1114 * be generated by conditions in multiple interrupt source registers.
1115 *
1116 * \param base
1117 * The pointer to the SCB instance.
1118 *
1119 * \return
1120 * The mask with the OR of the following conditions that have been triggered.
1121 * See \ref group_scb_common_macros_intr_cause for the set of constants.
1122 *
1123 *******************************************************************************/
Cy_SCB_GetInterruptCause(CySCB_Type const * base)1124 __STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base)
1125 {
1126 return (SCB_INTR_CAUSE(base));
1127 }
1128
1129
1130 /*******************************************************************************
1131 * Function Name: Cy_SCB_GetRxInterruptStatus
1132 ****************************************************************************//**
1133 *
1134 * Returns the RX interrupt request register. This register contains the current
1135 * status of the RX interrupt sources.
1136 *
1137 * \param base
1138 * The pointer to the SCB instance.
1139 *
1140 * \return
1141 * The current status of the RX interrupt sources. Each constant is a bit field
1142 * value. The value returned may have multiple bits set to indicate the
1143 * current status.
1144 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1145 *
1146 *******************************************************************************/
Cy_SCB_GetRxInterruptStatus(CySCB_Type const * base)1147 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base)
1148 {
1149 return (SCB_INTR_RX(base) & CY_SCB_RX_INTR_MASK);
1150 }
1151
1152
1153 /*******************************************************************************
1154 * Function Name: Cy_SCB_SetRxInterruptMask
1155 ****************************************************************************//**
1156 *
1157 * Writes the RX interrupt mask register. This register configures which bits
1158 * from the RX interrupt request register can trigger an interrupt event.
1159 *
1160 * \param base
1161 * The pointer to the SCB instance.
1162 *
1163 * \param interruptMask
1164 * Enabled RX interrupt sources.
1165 * See \ref group_scb_common_macros_rx_intr.
1166 *
1167 *******************************************************************************/
Cy_SCB_SetRxInterruptMask(CySCB_Type * base,uint32_t interruptMask)1168 __STATIC_INLINE void Cy_SCB_SetRxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1169 {
1170 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1171
1172 SCB_INTR_RX_MASK(base) = interruptMask;
1173 }
1174
1175
1176 /*******************************************************************************
1177 * Function Name: Cy_SCB_GetRxInterruptMask
1178 ****************************************************************************//**
1179 *
1180 * Returns the RX interrupt mask register. This register specifies which bits
1181 * from the RX interrupt request register trigger can an interrupt event.
1182 *
1183 * \param base
1184 * The pointer to the SCB instance.
1185 *
1186 * \return
1187 * Enabled RX interrupt sources.
1188 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1189 *
1190 *******************************************************************************/
Cy_SCB_GetRxInterruptMask(CySCB_Type const * base)1191 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask(CySCB_Type const *base)
1192 {
1193 return (SCB_INTR_RX_MASK(base));
1194 }
1195
1196
1197 /*******************************************************************************
1198 * Function Name: Cy_SCB_GetRxInterruptStatusMasked
1199 ****************************************************************************//**
1200 *
1201 * Returns the RX interrupt masked request register. This register contains
1202 * a logical AND of corresponding bits from the RX interrupt request and
1203 * mask registers.
1204 * This function is intended to be used in the interrupt service routine to
1205 * identify which of the enabled RX interrupt sources caused the interrupt event.
1206 *
1207 * \param base
1208 * The pointer to the SCB instance.
1209 *
1210 * \return
1211 * The current status of enabled RX interrupt sources.
1212 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1213 *
1214 *******************************************************************************/
Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const * base)1215 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base)
1216 {
1217 return (SCB_INTR_RX_MASKED(base));
1218 }
1219
1220
1221 /*******************************************************************************
1222 * Function Name: Cy_SCB_ClearRxInterrupt
1223 ****************************************************************************//**
1224 *
1225 * Clears the RX interrupt sources in the interrupt request register.
1226 *
1227 * \param base
1228 * The pointer to the SCB instance.
1229 *
1230 * \param interruptMask
1231 * The RX interrupt sources to be cleared.
1232 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1233 *
1234 * \note
1235 * - CY_SCB_INTR_RX_FIFO_LEVEL interrupt source is not cleared when
1236 * the RX FIFO has more entries than the level.
1237 * - CY_SCB_INTR_RX_NOT_EMPTY interrupt source is not cleared when the
1238 * RX FIFO is not empty.
1239 * - CY_SCB_INTR_RX_FULL interrupt source is not cleared when the
1240 * RX FIFO is full.
1241 *
1242 *******************************************************************************/
Cy_SCB_ClearRxInterrupt(CySCB_Type * base,uint32_t interruptMask)1243 __STATIC_INLINE void Cy_SCB_ClearRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1244 {
1245 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1246
1247 SCB_INTR_RX(base) = interruptMask;
1248 (void) SCB_INTR_RX(base);
1249 }
1250
1251
1252 /*******************************************************************************
1253 * Function Name: Cy_SCB_SetRxInterrupt
1254 ****************************************************************************//**
1255 *
1256 * Sets the RX interrupt sources in the interrupt request register.
1257 *
1258 * \param base
1259 * The pointer to the SCB instance.
1260 *
1261 * \param interruptMask
1262 * The RX interrupt sources to set in the RX interrupt request register.
1263 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1264 *
1265 *******************************************************************************/
Cy_SCB_SetRxInterrupt(CySCB_Type * base,uint32_t interruptMask)1266 __STATIC_INLINE void Cy_SCB_SetRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1267 {
1268 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1269
1270 SCB_INTR_RX_SET(base) = interruptMask;
1271 }
1272
1273
1274 /*******************************************************************************
1275 * Function Name: Cy_SCB_GetTxInterruptStatus
1276 ****************************************************************************//**
1277 *
1278 * Returns the TX interrupt request register. This register contains the current
1279 * status of the TX interrupt sources.
1280 *
1281 * \param base
1282 * The pointer to the SCB instance.
1283 *
1284 * \return
1285 * The current status of TX interrupt sources.
1286 * Each constant is a bit field value. The value returned may have multiple
1287 * bits set to indicate the current status.
1288 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1289 *
1290 *******************************************************************************/
Cy_SCB_GetTxInterruptStatus(CySCB_Type const * base)1291 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base)
1292 {
1293 return (SCB_INTR_TX(base) & CY_SCB_TX_INTR_MASK);
1294 }
1295
1296
1297 /*******************************************************************************
1298 * Function Name: Cy_SCB_SetTxInterruptMask
1299 ****************************************************************************//**
1300 *
1301 * Writes the TX interrupt mask register. This register configures which bits
1302 * from the TX interrupt request register can trigger an interrupt event.
1303 *
1304 * \param base
1305 * The pointer to the SCB instance.
1306 *
1307 * \param interruptMask
1308 * Enabled TX interrupt sources.
1309 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1310 *
1311 *******************************************************************************/
Cy_SCB_SetTxInterruptMask(CySCB_Type * base,uint32_t interruptMask)1312 __STATIC_INLINE void Cy_SCB_SetTxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1313 {
1314 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1315
1316 SCB_INTR_TX_MASK(base) = interruptMask;
1317 }
1318
1319
1320 /*******************************************************************************
1321 * Function Name: Cy_SCB_GetTxInterruptMask
1322 ****************************************************************************//**
1323 *
1324 * Returns the TX interrupt mask register. This register specifies which
1325 * bits from the TX interrupt request register can trigger an interrupt event.
1326 *
1327 * \param base
1328 * The pointer to the SCB instance.
1329 *
1330 * \return
1331 * Enabled TX interrupt sources.
1332 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1333 *
1334 *******************************************************************************/
Cy_SCB_GetTxInterruptMask(CySCB_Type const * base)1335 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask(CySCB_Type const *base)
1336 {
1337 return (SCB_INTR_TX_MASK(base));
1338 }
1339
1340
1341 /*******************************************************************************
1342 * Function Name: Cy_SCB_GetTxInterruptStatusMasked
1343 ****************************************************************************//**
1344 *
1345 * Returns the TX interrupt masked request register. This register contains
1346 * a logical AND of corresponding bits from the TX interrupt request and
1347 * mask registers.
1348 * This function is intended to be used in the interrupt service routine to
1349 * identify which of enabled TX interrupt sources caused the interrupt event.
1350 *
1351 * \param base
1352 * The pointer to the SCB instance.
1353 *
1354 * \return
1355 * The current status of enabled TX interrupt sources.
1356 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1357 *
1358 *******************************************************************************/
Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const * base)1359 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base)
1360 {
1361 return (SCB_INTR_TX_MASKED(base));
1362 }
1363
1364
1365 /*******************************************************************************
1366 * Function Name: Cy_SCB_ClearTxInterrupt
1367 ****************************************************************************//**
1368 *
1369 * Clears the TX interrupt sources in the interrupt request register.
1370 *
1371 * \param base
1372 * The pointer to the SCB instance.
1373 *
1374 * \param interruptMask
1375 * The TX interrupt sources to be cleared.
1376 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1377 *
1378 * \note
1379 * - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the
1380 * TX FIFO has fewer entries than the TX level.
1381 * - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the
1382 * TX FIFO has empty entries in the TX FIFO.
1383 * - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the
1384 * TX FIFO is empty.
1385 * - CY_SCB_INTR_TX_UNDERFLOW interrupt source is not cleared when the
1386 * TX FIFO is empty. Put data into the TX FIFO before clearing it.
1387 *
1388 *******************************************************************************/
Cy_SCB_ClearTxInterrupt(CySCB_Type * base,uint32_t interruptMask)1389 __STATIC_INLINE void Cy_SCB_ClearTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1390 {
1391 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1392
1393 SCB_INTR_TX(base) = interruptMask;
1394 (void) SCB_INTR_TX(base);
1395 }
1396
1397
1398 /*******************************************************************************
1399 * Function Name: Cy_SCB_SetTxInterrupt
1400 ****************************************************************************//**
1401 *
1402 * Sets TX interrupt sources in the interrupt request register.
1403 *
1404 * \param base
1405 * The pointer to the SCB instance.
1406 *
1407 * \param interruptMask
1408 * The TX interrupt sources to set in the TX interrupt request register.
1409 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1410 *
1411 *******************************************************************************/
Cy_SCB_SetTxInterrupt(CySCB_Type * base,uint32_t interruptMask)1412 __STATIC_INLINE void Cy_SCB_SetTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1413 {
1414 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1415
1416 SCB_INTR_TX_SET(base) = interruptMask;
1417 }
1418
1419
1420 /*******************************************************************************
1421 * Function Name: Cy_SCB_GetMasterInterruptStatus
1422 ****************************************************************************//**
1423 *
1424 * Returns the master interrupt request register. This register contains the current
1425 * status of the master interrupt sources.
1426 *
1427 * \param base
1428 * The pointer to the SCB instance.
1429 *
1430 * \return
1431 * The current status of the master interrupt sources.
1432 * Each constant is a bit field value. The value returned may have multiple
1433 * bits set to indicate the current status.
1434 * See \ref group_scb_common_macros_master_intr for the set of constants.
1435 *
1436 *******************************************************************************/
Cy_SCB_GetMasterInterruptStatus(CySCB_Type const * base)1437 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base)
1438 {
1439 return (SCB_INTR_M(base) & CY_SCB_MASTER_INTR_MASK);
1440 }
1441
1442
1443 /*******************************************************************************
1444 * Function Name: Cy_SCB_SetMasterInterruptMask
1445 ****************************************************************************//**
1446 *
1447 * Writes the master interrupt mask register. This register specifies which bits
1448 * from the master interrupt request register can trigger an interrupt event.
1449 *
1450 * \param base
1451 * The pointer to the SCB instance.
1452 *
1453 * \param interruptMask
1454 * The master interrupt sources to be enable.
1455 * See \ref group_scb_common_macros_master_intr for the set of constants.
1456 *
1457 *******************************************************************************/
Cy_SCB_SetMasterInterruptMask(CySCB_Type * base,uint32_t interruptMask)1458 __STATIC_INLINE void Cy_SCB_SetMasterInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1459 {
1460 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1461
1462 SCB_INTR_M_MASK(base) = interruptMask;
1463 }
1464
1465
1466 /*******************************************************************************
1467 * Function Name: Cy_SCB_GetMasterInterruptMask
1468 ****************************************************************************//**
1469 *
1470 * Returns the master interrupt mask register. This register specifies which bits
1471 * from the master interrupt request register can trigger an interrupt event.
1472 *
1473 * \param base
1474 * The pointer to the SCB instance.
1475 *
1476 * \return
1477 * Enabled master interrupt sources.
1478 * See \ref group_scb_common_macros_master_intr for the set of constants.
1479 *
1480 *******************************************************************************/
Cy_SCB_GetMasterInterruptMask(CySCB_Type const * base)1481 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask(CySCB_Type const *base)
1482 {
1483 return (SCB_INTR_M_MASK(base));
1484 }
1485
1486
1487 /*******************************************************************************
1488 * Function Name: Cy_SCB_GetMasterInterruptStatusMasked
1489 ****************************************************************************//**
1490 *
1491 * Returns the master interrupt masked request register. This register contains a
1492 * logical AND of corresponding bits from the master interrupt request and mask
1493 * registers.
1494 * This function is intended to be used in the interrupt service routine to
1495 * identify which of the enabled master interrupt sources caused the interrupt
1496 * event.
1497 *
1498 * \param base
1499 * The pointer to the SCB instance.
1500 *
1501 * \return
1502 * The current status of enabled master interrupt sources.
1503 * See \ref group_scb_common_macros_master_intr for the set of constants.
1504 *
1505 *******************************************************************************/
Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const * base)1506 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base)
1507 {
1508 return (SCB_INTR_M_MASKED(base));
1509 }
1510
1511
1512 /*******************************************************************************
1513 * Function Name: Cy_SCB_ClearMasterInterrupt
1514 ****************************************************************************//**
1515 *
1516 * Clears master interrupt sources in the interrupt request register.
1517 *
1518 * \param base
1519 * The pointer to the SCB instance.
1520 *
1521 * \param interruptMask
1522 * The master interrupt sources to be cleared.
1523 * See \ref group_scb_common_macros_master_intr for the set of constants.
1524 *
1525 *******************************************************************************/
Cy_SCB_ClearMasterInterrupt(CySCB_Type * base,uint32_t interruptMask)1526 __STATIC_INLINE void Cy_SCB_ClearMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
1527 {
1528 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1529
1530 SCB_INTR_M(base) = interruptMask;
1531 (void) SCB_INTR_M(base);
1532 }
1533
1534
1535 /*******************************************************************************
1536 * Function Name: Cy_SCB_SetMasterInterrupt
1537 ****************************************************************************//**
1538 *
1539 * Sets master interrupt sources in the interrupt request register.
1540 *
1541 * \param base
1542 * The pointer to the SCB instance.
1543 *
1544 * \param interruptMask
1545 * The master interrupt sources to set in the master interrupt request register.
1546 * See \ref group_scb_common_macros_master_intr for the set of constants.
1547 *
1548 *******************************************************************************/
Cy_SCB_SetMasterInterrupt(CySCB_Type * base,uint32_t interruptMask)1549 __STATIC_INLINE void Cy_SCB_SetMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
1550 {
1551 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1552
1553 SCB_INTR_M_SET(base) = interruptMask;
1554 }
1555
1556
1557 /*******************************************************************************
1558 * Function Name: Cy_SCB_GetSlaveInterruptStatus
1559 ****************************************************************************//**
1560 *
1561 * Returns the slave interrupt request register. This register contains the current
1562 * status of the slave interrupt sources.
1563 *
1564 * \param base
1565 * The pointer to the SCB instance.
1566 *
1567 * \return
1568 * The current status of the slave interrupt sources.
1569 * Each constant is a bit field value. The value returned may have multiple
1570 * bits set to indicate the current status.
1571 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1572 *
1573 *******************************************************************************/
Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const * base)1574 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base)
1575 {
1576 return (SCB_INTR_S(base) & CY_SCB_SLAVE_INTR_MASK);
1577 }
1578
1579
1580 /*******************************************************************************
1581 * Function Name: Cy_SCB_SetSlaveInterruptMask
1582 ****************************************************************************//**
1583 *
1584 * Writes slave interrupt mask register.
1585 * This register specifies which bits from the slave interrupt request register
1586 * can trigger an interrupt event.
1587 *
1588 * \param base
1589 * The pointer to the SCB instance.
1590 *
1591 * \param interruptMask
1592 * Enabled slave interrupt sources.
1593 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1594 *
1595 *******************************************************************************/
Cy_SCB_SetSlaveInterruptMask(CySCB_Type * base,uint32_t interruptMask)1596 __STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1597 {
1598 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1599
1600 SCB_INTR_S_MASK(base) = interruptMask;
1601 }
1602
1603
1604 /*******************************************************************************
1605 * Function Name: Cy_SCB_GetSlaveInterruptMask
1606 ****************************************************************************//**
1607 *
1608 * Returns the slave interrupt mask register.
1609 * This register specifies which bits from the slave interrupt request register
1610 * can trigger an interrupt event.
1611 *
1612 * \param base
1613 * The pointer to the SCB instance.
1614 *
1615 * \return
1616 * Enabled slave interrupt sources.
1617 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1618 *
1619 *******************************************************************************/
Cy_SCB_GetSlaveInterruptMask(CySCB_Type const * base)1620 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask(CySCB_Type const *base)
1621 {
1622 return (SCB_INTR_S_MASK(base));
1623 }
1624
1625
1626 /*******************************************************************************
1627 * Function Name: Cy_SCB_GetSlaveInterruptStatusMasked
1628 ****************************************************************************//**
1629 *
1630 * Returns the slave interrupt masked request register. This register contains a
1631 * logical AND of corresponding bits from the slave interrupt request and mask
1632 * registers.
1633 * This function is intended to be used in the interrupt service routine to
1634 * identify which of enabled slave interrupt sources caused the interrupt
1635 * event.
1636 *
1637 * \param base
1638 * The pointer to the SCB instance.
1639 *
1640 * \return
1641 * The current status of enabled slave interrupt sources.
1642 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1643 *
1644 *******************************************************************************/
Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const * base)1645 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base)
1646 {
1647 return (SCB_INTR_S_MASKED(base));
1648 }
1649
1650
1651 /*******************************************************************************
1652 * Function Name: Cy_SCB_ClearSlaveInterrupt
1653 ****************************************************************************//**
1654 *
1655 * Clears the slave interrupt sources in the interrupt request register.
1656 *
1657 * \param base
1658 * The pointer to the SCB instance.
1659 *
1660 * \param interruptMask
1661 * Slave interrupt sources to be cleared.
1662 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1663 *
1664 *******************************************************************************/
Cy_SCB_ClearSlaveInterrupt(CySCB_Type * base,uint32_t interruptMask)1665 __STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
1666 {
1667 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1668
1669 SCB_INTR_S(base) = interruptMask;
1670 (void) SCB_INTR_S(base);
1671 }
1672
1673
1674 /*******************************************************************************
1675 * Function Name: Cy_SCB_SetSlaveInterrupt
1676 ****************************************************************************//**
1677 *
1678 * Sets slave interrupt sources in the interrupt request register.
1679 *
1680 * \param base
1681 * The pointer to the SCB instance.
1682 *
1683 * \param interruptMask
1684 * The slave interrupt sources to set in the slave interrupt request register
1685 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1686 *
1687 *******************************************************************************/
Cy_SCB_SetSlaveInterrupt(CySCB_Type * base,uint32_t interruptMask)1688 __STATIC_INLINE void Cy_SCB_SetSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
1689 {
1690 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1691
1692 SCB_INTR_S_SET(base) = interruptMask;
1693 }
1694
1695
1696 /*******************************************************************************
1697 * Function Name: Cy_SCB_GetI2CInterruptStatus
1698 ****************************************************************************//**
1699 *
1700 * Returns the I2C interrupt request register. This register contains the
1701 * current status of the I2C interrupt sources.
1702 *
1703 * \param base
1704 * The pointer to the SCB instance.
1705 *
1706 * \return
1707 * The current status of the I2C interrupt sources. Each constant is a bit
1708 * field value.
1709 * The value returned may have multiple bits set to indicate the current status.
1710 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1711 *
1712 *******************************************************************************/
Cy_SCB_GetI2CInterruptStatus(CySCB_Type const * base)1713 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base)
1714 {
1715 return (SCB_INTR_I2C_EC(base) & CY_SCB_I2C_INTR_MASK);
1716 }
1717
1718
1719 /*******************************************************************************
1720 * Function Name: Cy_SCB_SetI2CInterruptMask
1721 ****************************************************************************//**
1722 *
1723 * Writes the I2C interrupt mask register. This register specifies which bits
1724 * from the I2C interrupt request register can trigger an interrupt event.
1725 *
1726 * \param base
1727 * The pointer to the SCB instance.
1728 *
1729 * \param interruptMask
1730 * Enabled I2C interrupt sources.
1731 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1732 *
1733 *******************************************************************************/
Cy_SCB_SetI2CInterruptMask(CySCB_Type * base,uint32_t interruptMask)1734 __STATIC_INLINE void Cy_SCB_SetI2CInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1735 {
1736 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
1737
1738 SCB_INTR_I2C_EC_MASK(base) = interruptMask;
1739 }
1740
1741
1742 /*******************************************************************************
1743 * Function Name: Cy_SCB_GetI2CInterruptMask
1744 ****************************************************************************//**
1745 *
1746 * Returns the I2C interrupt mask register. This register specifies which bits
1747 * from the I2C interrupt request register can trigger an interrupt event.
1748 *
1749 * \param base
1750 * The pointer to the SCB instance.
1751 *
1752 * \return
1753 * Enabled I2C interrupt sources.
1754 * See \ref group_scb_common_macros_i2c_intr.
1755 *
1756 *******************************************************************************/
Cy_SCB_GetI2CInterruptMask(CySCB_Type const * base)1757 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask(CySCB_Type const *base)
1758 {
1759 return (SCB_INTR_I2C_EC_MASK(base));
1760 }
1761
1762
1763 /*******************************************************************************
1764 * Function Name: Cy_SCB_GetI2CInterruptStatusMasked
1765 ****************************************************************************//**
1766 *
1767 * Returns the I2C interrupt masked request register. This register contains
1768 * a logical AND of corresponding bits from I2C interrupt request and mask
1769 * registers.
1770 * This function is intended to be used in the interrupt service routine to
1771 * identify which of enabled I2C interrupt sources caused the interrupt event.
1772 *
1773 * \param base
1774 * The pointer to the SCB instance.
1775 *
1776 * \return
1777 * The current status of enabled I2C interrupt sources.
1778 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1779 *
1780 *******************************************************************************/
Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const * base)1781 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base)
1782 {
1783 return (SCB_INTR_I2C_EC_MASKED(base));
1784 }
1785
1786
1787 /*******************************************************************************
1788 * Function Name: Cy_SCB_ClearI2CInterrupt
1789 ****************************************************************************//**
1790 *
1791 * Clears I2C interrupt sources in the interrupt request register.
1792 *
1793 * \param base
1794 * The pointer to the SCB instance.
1795 *
1796 * \param interruptMask
1797 * The I2C interrupt sources to be cleared.
1798 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1799 *
1800 *******************************************************************************/
Cy_SCB_ClearI2CInterrupt(CySCB_Type * base,uint32_t interruptMask)1801 __STATIC_INLINE void Cy_SCB_ClearI2CInterrupt(CySCB_Type *base, uint32_t interruptMask)
1802 {
1803 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
1804
1805 SCB_INTR_I2C_EC(base) = interruptMask;
1806 (void) SCB_INTR_I2C_EC(base);
1807 }
1808
1809
1810 /*******************************************************************************
1811 * Function Name: Cy_SCB_GetSpiInterruptStatus
1812 ****************************************************************************//**
1813 *
1814 * Returns the SPI interrupt request register. This register contains the current
1815 * status of the SPI interrupt sources.
1816 *
1817 * \param base
1818 * The pointer to the SCB instance.
1819 *
1820 * \return
1821 * The current status of SPI interrupt sources. Each constant is a bit field value.
1822 * The value returned may have multiple bits set to indicate the current status
1823 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1824 *
1825 *******************************************************************************/
Cy_SCB_GetSpiInterruptStatus(CySCB_Type const * base)1826 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base)
1827 {
1828 return (SCB_INTR_SPI_EC(base) & CY_SCB_SPI_INTR_MASK);
1829 }
1830
1831
1832 /*******************************************************************************
1833 * Function Name: Cy_SCB_SetSpiInterruptMask
1834 ****************************************************************************//**
1835 *
1836 * Writes the SPI interrupt mask register. This register specifies which
1837 * bits from the SPI interrupt request register can trigger an interrupt event.
1838 *
1839 * \param base
1840 * The pointer to the SCB instance.
1841 *
1842 * \param interruptMask
1843 * Enabled SPI interrupt sources.
1844 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1845 *
1846 *******************************************************************************/
Cy_SCB_SetSpiInterruptMask(CySCB_Type * base,uint32_t interruptMask)1847 __STATIC_INLINE void Cy_SCB_SetSpiInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1848 {
1849 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
1850
1851 SCB_INTR_SPI_EC_MASK(base) = interruptMask;
1852 }
1853
1854
1855 /*******************************************************************************
1856 * Function Name: Cy_SCB_GetSpiInterruptMask
1857 ****************************************************************************//**
1858 *
1859 * Returns the SPI interrupt mask register. This register specifies which bits
1860 * from the SPI interrupt request register can trigger an interrupt event.
1861 *
1862 * \param base
1863 * The pointer to the SCB instance.
1864 *
1865 * \return
1866 * Enabled SPI interrupt sources.
1867 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1868 *
1869 *******************************************************************************/
Cy_SCB_GetSpiInterruptMask(CySCB_Type const * base)1870 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask(CySCB_Type const *base)
1871 {
1872 return (SCB_INTR_SPI_EC_MASK(base));
1873 }
1874
1875
1876 /*******************************************************************************
1877 * Function Name: Cy_SCB_GetSpiInterruptStatusMasked
1878 ****************************************************************************//**
1879 *
1880 * Returns the SPI interrupt masked request register. This register contains
1881 * a logical AND of corresponding bits from the SPI interrupt request and
1882 * mask registers.
1883 * This function is intended to be used in the interrupt service routine to
1884 * identify which of enabled SPI interrupt sources caused the interrupt event.
1885 *
1886 * \param base
1887 * The pointer to the SCB instance.
1888 *
1889 * \return
1890 * The current status of enabled SPI interrupt sources.
1891 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1892 *
1893 *******************************************************************************/
Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const * base)1894 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base)
1895 {
1896 return (SCB_INTR_SPI_EC_MASKED(base));
1897 }
1898
1899
1900 /*******************************************************************************
1901 * Function Name: Cy_SCB_ClearSpiInterrupt
1902 ****************************************************************************//**
1903 *
1904 * Clears SPI interrupt sources in the interrupt request register.
1905 *
1906 * \param base
1907 * The pointer to the SCB instance.
1908 *
1909 * \param interruptMask
1910 * The SPI interrupt sources to be cleared.
1911 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1912 *
1913 *******************************************************************************/
Cy_SCB_ClearSpiInterrupt(CySCB_Type * base,uint32_t interruptMask)1914 __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interruptMask)
1915 {
1916 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
1917
1918 SCB_INTR_SPI_EC(base) = interruptMask;
1919 (void) SCB_INTR_SPI_EC(base);
1920 }
1921
1922 /** \cond INTERNAL */
1923 /*******************************************************************************
1924 * Function Name: Cy_SCB_GetFifoSize
1925 ****************************************************************************//**
1926 *
1927 * Returns the RX and TX FIFO depth.
1928 *
1929 * \param base
1930 * The pointer to the SCB instance.
1931 *
1932 * \return
1933 * FIFO depth.
1934 *
1935 *******************************************************************************/
Cy_SCB_GetFifoSize(CySCB_Type const * base)1936 __STATIC_INLINE uint32_t Cy_SCB_GetFifoSize(CySCB_Type const *base)
1937 {
1938 #if(CY_IP_MXSCB_VERSION>=3)
1939 {return (((uint32_t)(CY_SCB_FIFO_SIZE)) >> _FLD2VAL(SCB_CTRL_MEM_WIDTH, SCB_CTRL(base)));}
1940 #elif(CY_IP_MXSCB_VERSION==1)
1941 {return (_FLD2BOOL(SCB_CTRL_BYTE_MODE, SCB_CTRL(base)) ? (CY_SCB_FIFO_SIZE) : (CY_SCB_FIFO_SIZE / 2UL));}
1942 #endif /* CY_IP_MXSCB_VERSION */
1943 }
1944
1945
1946 /*******************************************************************************
1947 * Function Name: Cy_SCB_IsRxDataWidthByte
1948 ****************************************************************************//**
1949 *
1950 * Returns true if the RX data width is a byte (8 bits).
1951 *
1952 * \param base
1953 * The pointer to the SCB instance.
1954 *
1955 * \return
1956 * True if the RX data width is a byte (8 bits).
1957 *
1958 *******************************************************************************/
Cy_SCB_IsRxDataWidthByte(CySCB_Type const * base)1959 __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base)
1960 {
1961 return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
1962 }
1963
1964 /** \endcond */
1965
1966 #if(CY_IP_MXSCB_VERSION>=3) || defined (CY_DOXYGEN)
1967 /*******************************************************************************
1968 * Function Name: Cy_SCB_Get_RxDataWidth
1969 ****************************************************************************//**
1970 *
1971 * Returns the RX data width.
1972 *
1973 * \param base
1974 * The pointer to the SCB instance.
1975 *
1976 * \return
1977 * RX data width.
1978 *
1979 *
1980 * \note
1981 * This API is available for CAT1B devices.
1982 *
1983 *******************************************************************************/
Cy_SCB_Get_RxDataWidth(CySCB_Type const * base)1984 __STATIC_INLINE uint32_t Cy_SCB_Get_RxDataWidth(CySCB_Type const *base)
1985 {
1986 return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) + 1UL);
1987 }
1988 #endif /* CY_IP_MXSCB_VERSION */
1989
1990 /*******************************************************************************
1991 * Function Name: Cy_SCB_IsTxDataWidthByte
1992 ****************************************************************************//**
1993 *
1994 * Returns true if the TX data width is a byte (8 bits).
1995 *
1996 * \param base
1997 * The pointer to the SCB instance.
1998 *
1999 * \return
2000 * If true, the TX data width is a byte (8 bits). Otherwise, false.
2001 *
2002 *******************************************************************************/
Cy_SCB_IsTxDataWidthByte(CySCB_Type const * base)2003 __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base)
2004 {
2005 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
2006 }
2007
2008 #if(CY_IP_MXSCB_VERSION>=3) || defined (CY_DOXYGEN)
2009 /*******************************************************************************
2010 * Function Name: Cy_SCB_Get_TxDataWidth
2011 ****************************************************************************//**
2012 *
2013 * Returns the TX data width.
2014 *
2015 * \param base
2016 * The pointer to the SCB instance.
2017 *
2018 * \return
2019 * The TX data width.
2020 *
2021 *
2022 * \note
2023 * This API is available for CAT1B devices.
2024 *
2025 *******************************************************************************/
Cy_SCB_Get_TxDataWidth(CySCB_Type const * base)2026 __STATIC_INLINE uint32_t Cy_SCB_Get_TxDataWidth(CySCB_Type const *base)
2027 {
2028 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) + 1UL);
2029 }
2030 #endif /* CY_IP_MXSCB_VERSION */
2031
2032 /** \cond INTERNAL */
2033
2034 /*******************************************************************************
2035 * Function Name: Cy_SCB_FwBlockReset
2036 ****************************************************************************//**
2037 *
2038 * Disables and enables the block to return it into the known state (default):
2039 * FIFOs and interrupt statuses are cleared.
2040 *
2041 * \param base
2042 * The pointer to the SCB instance.
2043 *
2044 *******************************************************************************/
Cy_SCB_FwBlockReset(CySCB_Type * base)2045 __STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base)
2046 {
2047 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
2048
2049 /* Clean-up command registers */
2050 SCB_I2C_M_CMD(base) = 0UL;
2051 SCB_I2C_S_CMD(base) = 0UL;
2052
2053 SCB_CTRL(base) |= (uint32_t) SCB_CTRL_ENABLED_Msk;
2054
2055 (void) SCB_CTRL(base);
2056 }
2057
2058
2059 /*******************************************************************************
2060 * Function Name: Cy_SCB_GetRxFifoLevel
2061 ****************************************************************************//**
2062 *
2063 * Returns the RX FIFO level when there are more words in the RX FIFO than the
2064 * level, the RX FIFO level interrupt is triggered.
2065 *
2066 * \param base
2067 * The pointer to the SCB instance.
2068 *
2069 * \return
2070 * RX FIFO level.
2071 *
2072 *******************************************************************************/
Cy_SCB_GetRxFifoLevel(CySCB_Type const * base)2073 __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base)
2074 {
2075 return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, SCB_RX_FIFO_CTRL(base));
2076 }
2077
2078 /** \endcond */
2079 /** \} group_scb_common_functions */
2080
2081 #if defined(__cplusplus)
2082 }
2083 #endif
2084
2085 /** \} group_scb_common */
2086
2087 #endif /* CY_IP_MXSCB */
2088
2089 #endif /* (CY_SCB_COMMON_H) */
2090
2091 /* [] END OF FILE */
2092
