1 /***************************************************************************//**
2 * \file cy_scb_common.h
3 * \version 3.10
4 *
5 * Provides common API declarations of the SCB driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2016-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_scb
27 * \{
28 * The Serial Communications Block (SCB) supports three serial communication
29 * protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver
30 * Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of
31 * the protocols is supported by an SCB at any given time.
32 *
33 * The functions and other declarations used in this driver are in cy_scb_spi.h,
34 * cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h
35 * to get access to all functions and declarations in the PDL.
36
37 * \defgroup group_scb_common Common
38 * \defgroup group_scb_ezi2c EZI2C (SCB)
39 * \defgroup group_scb_i2c I2C (SCB)
40 * \defgroup group_scb_spi SPI (SCB)
41 * \defgroup group_scb_uart UART (SCB)
42 * \} */
43
44 /**
45 * \addtogroup group_scb
46 * \{
47 *
48 ********************************************************************************
49 * \section group_scb_more_information More Information
50 ********************************************************************************
51 * For more information on the SCB peripheral, refer to the technical reference
52 * manual (TRM).
53 *
54 *******************************************************************************
55 * \section group_scb_common_changelog Changelog
56 *******************************************************************************
57 * <table class="doxtable">
58 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
59 * <tr>
60 * <td>3.10</td>
61 * <td>Fixed MISRA 2012 violations.</td>
62 * <td>MISRA 2012 compliance.</td>
63 * </tr>
64 * <tr>
65 * <td rowspan="2">3.0</td>
66 * <td>Updated \ref Cy_SCB_SPI_Init and other internal data handling functions to handle wide range of data widths.</td>
67 * <td>Defect fixing.</td>
68 * </tr>
69 * <tr>
70 * <td>Minor documentation updates.</td>
71 * <td>Documentation enhancement.</td>
72 * </tr>
73 * <tr>
74 * <td rowspan="2">2.90</td>
75 * <td>A new API, \ref Cy_SCB_SetEzI2CMode, has been added to help set the hardware EZ mode for the I2C protocol.</td>
76 * <td>The HW EZ Mode for the I2C protocol can be enabled or disabled.</td>
77 * </tr>
78 * <tr>
79 * <td>Newly added APIs \ref Cy_SCB_I2C_SetStretchThreshold to set the stretch threshold value,
80 * \ref Cy_SCB_I2C_GetStretchCount to get the stretch count,
81 * \ref Cy_SCB_I2C_IsStretchDetected to detect if I2C SCL is stretched,
82 * \ref Cy_SCB_I2C_IsSyncDetected to check if synchronization is detected on I2C SCL.
83 * \ref Cy_SCB_I2C_IsStretching to check if DUT is stretching the I2C SCL.</td>
84 * <td>New device support.</td>
85 * </tr>
86 * <tr>
87 * <td>2.80</td>
88 * <td>Updated the behaviour of \ref Cy_SCB_UART_SetEnableMsbFirst and \ref Cy_SCB_UART_GetEnableMsbFirst functions.
89 * Now the value of enableMsbFirst is being set and fetched correctly.
90 * <td>Defect fixing.</td>
91 * </tr>
92 * <tr>
93 * <td rowspan="2">2.70</td>
94 * <td>Newly added API's for runtime parameter set/get functionality which include
95 * \ref Cy_SCB_UART_SetOverSample to set oversample bits of UART,
96 * \ref Cy_SCB_UART_GetOverSample to add return value of oversample,
97 * \ref Cy_SCB_UART_GetDataWidth to get data width,
98 * \ref Cy_SCB_UART_SetDataWidth to set data width,
99 * \ref Cy_SCB_UART_GetParity to get parity,
100 * \ref Cy_SCB_UART_SetParity to set parity,
101 * \ref Cy_SCB_UART_GetStopBits to get stop bits,
102 * \ref Cy_SCB_UART_SetStopBits to set stop bits,
103 * \ref Cy_SCB_UART_GetDropOnParityError to get drop on parity error,
104 * \ref Cy_SCB_UART_SetDropOnParityError to set drop on parity error,
105 * \ref Cy_SCB_UART_GetEnableMsbFirst to get enable MSB first and
106 * \ref Cy_SCB_UART_SetEnableMsbFirst to set enable MSB first.</td>
107 * <td>Runtime Parameter update.</td>
108 * </tr>
109 * <tr>
110 * <td>Newly added API's which include
111 * \ref Cy_SCB_Get_RxDataWidth to return the RX data width,
112 * \ref Cy_SCB_Get_TxDataWidth to return the TX data width,
113 * \ref Cy_SCB_SetMemWidth to set the RX and TX FIFOs byte mode/halfword/word mode.
114 * Updated Structures \ref cy_stc_scb_uart_config_t, \ref cy_en_scb_spi_parity_t, \ref cy_stc_scb_spi_config_t.</td>
115 * <td>New device support.</td>
116 * </tr>
117 * <tr>
118 * <td rowspan="2">2.60</td>
119 * <td>Fixed the \ref Cy_SCB_UART_GetNumInRingBuffer function to
120 * return correct number of the elements in ring buffer.</td>
121 * <td> \ref Cy_SCB_UART_GetNumInRingBuffer function works incorrectly, when
122 * write pointer of the ring buffer is behind the read pointer.</td>
123 * </tr>
124 * <tr>
125 * <td>Fixed/Documented MISRA 2012 violations.</td>
126 * <td>MISRA 2012 compliance.</td>
127 * </tr>
128 * <tr>
129 * <td>2.50</td>
130 * <td>Fixed the \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function to
131 * properly configure the polarity of the slave select line.</td>
132 * <td> \ref Cy_SCB_SPI_SetActiveSlaveSelectPolarity function works incorrectly.</td>
133 * </tr>
134 * <tr>
135 * <td>2.40.2</td>
136 * <td>Minor documentation updates.</td>
137 * <td>Documentation enhancement.</td>
138 * </tr>
139 * <tr>
140 * <td rowspan="2">2.40</td>
141 * <td>Update level selection logic of RX FIFO trigger in the Cy_SCB_UART_Receive().</td>
142 * <td>Fix possible stuck if the RTS level is less than the RX FIFO level.</td>
143 * </tr>
144 * <tr>
145 * <td>Exclude self-test assertion macros under release build profile.</td>
146 * <td>Avoid dependency on CY_ASSERT macro implementation.</td>
147 * </tr>
148 * <tr>
149 * <td>2.30.1</td>
150 * <td>Added header guards CY_IP_MXSCB.</td>
151 * <td>To enable the PDL compilation with wounded out IP blocks.</td>
152 * </tr>
153 * <tr>
154 * <td rowspan="5">2.30</td>
155 * <td>Fixed MISRA violation.</td>
156 * <td>MISRA compliance.</td>
157 * </tr>
158 * <tr>
159 * <td>Changed values CY_SCB_SPI_CPHA0_CPOL1 and CY_SCB_SPI_CPHA1_CPOL0 in enum \ref cy_en_scb_spi_sclk_mode_t.</td>
160 * <td>The incorrect values in \ref cy_en_scb_spi_sclk_mode_t caused incorrect initialization of the combination of
161 * phases and polarity: "CHPA = 0, CPOL = 1" and "CHPA = 1, CPOL = 0".
162 * </td>
163 * </tr>
164 * <tr>
165 * <td>Added new CY_SCB_UART_RECEIVE_NOT_EMTPY and CY_SCB_UART_TRANSMIT_EMTPY callback events \ref group_scb_uart_macros_callback_events.</td>
166 * <td>Extended the driver callback events to support the MBED-OS.</td>
167 * </tr>
168 * <tr>
169 * <td>Merged SCB changelogs for each mode into one changelog.</td>
170 * <td>Changelog optimization.</td>
171 * </tr>
172 * <tr>
173 * <td>Merged SCB MISRA-C Compliance sections for each mode into one section.</td>
174 * <td>To optimize the SCB MISRA-C Compliance sections.</td>
175 * </tr>
176 * <tr>
177 * <td> 2.20.1</td>
178 * <td>Documentation of the MISRA rule violation.</td>
179 * <td>MISRA compliance.</td>
180 * </tr>
181 * <tr>
182 * <td rowspan="4">2.20</td>
183 * <td>Flattened the organization of the driver source code into the single
184 * source directory and the single include directory.
185 * </td>
186 * <td>Driver library directory-structure simplification.</td>
187 * </tr>
188 * <tr>
189 * <td>Added register access layer. Use register access macros instead
190 * of direct register access using dereferenced pointers.</td>
191 * <td>Makes register access device-independent, so that the PDL does
192 * not need to be recompiled for each supported part number.</td>
193 * </tr>
194 * <tr>
195 * <td>Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle
196 * fields to the \ref cy_stc_scb_i2c_config_t configuration structure.
197 * </td>
198 * <td>Added the I2C master data rate configuration using the configuration structure.
199 * </td>
200 * </tr>
201 * <tr>
202 * <td>Fixed the \ref Cy_SCB_I2C_SetDataRate function to properly configure data rates
203 * greater than 400 kbps in Master and Master-Slave modes. \n
204 * Added verification that clk_scb is within the valid range for the desired data rate.
205 * </td>
206 * <td>The analog filter was enabled for all data rates in Master and Master-Slave modes.
207 * This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter.
208 * </td>
209 * </tr>
210 * <tr>
211 * <td rowspan="4"> 2.10</td>
212 * <td>Fixed the ReStart condition generation sequence for a write
213 * transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
214 * <td>The driver can notify about a zero length write transaction completion
215 * before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
216 * function execution was interrupted between setting the restart
217 * generation command and writing the address byte into the TX FIFO.</td>
218 * </tr>
219 * <tr>
220 * <td>Added the slave- and master-specific interrupt functions:
221 * \ref Cy_SCB_I2C_SlaveInterrupt and \ref Cy_SCB_I2C_MasterInterrupt.
222 * </td>
223 * <td>Improved the interrupt configuration options for the I2C slave and
224 * master mode configurations.</td>
225 * </tr>
226 * <tr>
227 * <td>Updated the Start condition generation sequence in the \ref
228 * Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
229 * <td></td>
230 * </tr>
231 * <tr>
232 * <td>Updated the ReStart condition generation sequence for a write
233 * transaction in the \ref Cy_SCB_I2C_MasterSendReStart function.</td>
234 * <td></td>
235 * </tr>
236 * <tr>
237 * <td rowspan="9"> 2.0</td>
238 * <td>Added parameters validation for public API.
239 * <td></td>
240 * </tr>
241 * <tr>
242 * <td>Fixed functions which return interrupt status to return only defined
243 * set of interrupt statuses.</td>
244 * <td></td>
245 * </tr>
246 * <tr>
247 * <td>Added missing "cy_cb_" to the callback function type names.</td>
248 * <td></td>
249 * </tr>
250 * <tr>
251 * <td>Replaced variables that have limited range of values with enumerated
252 * types.</td>
253 * <td></td>
254 * </tr>
255 * <tr>
256 * <td>Added function \ref Cy_SCB_UART_SendBreakBlocking for break condition
257 * generation.</td>
258 * <td></td>
259 * </tr>
260 * <tr>
261 * <td>Fixed low power callbacks \ref Cy_SCB_UART_DeepSleepCallback and
262 * \ref Cy_SCB_UART_HibernateCallback to prevent the device from entering
263 * low power mode when RX FIFO is not empty.</td>
264 * <td>The callbacks allowed entering device into low power mode when RX FIFO
265 * had data.</td>
266 * </tr>
267 * <tr>
268 * <td>Fixed SPI callback notification when error event occurred.</td>
269 * <td>The SPI callback passed incorrect event value if error event occurred.</td>
270 * </tr>
271 * <tr>
272 * <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
273 * generate the ReStart condition when the previous transaction was
274 * a write.</td>
275 * <td>The master interpreted the address byte written into the TX FIFO as a
276 * data byte and continued a write transaction. The ReStart condition was
277 * generated after the master completed transferring the data byte.
278 * The SCL line was stretched by the master waiting for the address byte
279 * to be written into the TX FIFO after the ReStart condition generation.
280 * The following timeout detection released the bus from the master
281 * control.</td>
282 * </tr>
283 * <tr>
284 * <td>Fixed the slave operation after the address byte was NACKed by the
285 * firmware.</td>
286 * <td>The observed slave operation failure depends on whether Level 2 assert
287 * is enabled or not. Enabled: the device stuck in the fault handler due
288 * to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
289 * the slave sets the transaction completion status and notifies on the
290 * transaction completion event after the address was NACKed. The failure
291 * is observed only when the slave is configured to accept an address in
292 * the RX FIFO.</td>
293 * </tr>
294 * <tr>
295 * <td>1.0</td>
296 * <td>Initial version.</td>
297 * <td></td>
298 * </tr>
299 * </table>
300 */
301
302 /** \} group_scb */
303 /**
304 * \addtogroup group_scb_common
305 * \{
306 *
307 * Common API for the Serial Communication Block.
308 *
309 * This is the common API that provides an interface to the SCB hardware.
310 * The I2C, SPI, and UART drivers use this common API.
311 * Most users will use individual drivers and do not need to use the common
312 * API for the SCB. However, you can use the common SCB API to implement
313 * a custom driver based on the SCB hardware.
314 *
315 * The functions and other declarations used in this part of the driver are in
316 * cy_scb_common.h. You can include either of cy_scb_spi.h, cy_scb_uart.h,
317 * cy_scb_ezi2c.h, cy_scb_i2c.h depending on the desired functionality.
318 * You can also include cy_pdl.h to get access to all functions and declarations
319 * in the PDL.
320 *
321 *******************************************************************************
322 * \section group_scb_common_configuration Configuration Considerations
323 ********************************************************************************
324 * This is not a driver and it does not require configuration.
325 *
326 * \defgroup group_scb_common_macros Macros
327 * \defgroup group_scb_common_functions Functions
328 * \defgroup group_scb_common_data_structures Data Structures
329 *
330 */
331
332 #if !defined(CY_SCB_COMMON_H)
333 #define CY_SCB_COMMON_H
334
335 #include "cy_device.h"
336
337 #if (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB))
338
339 #include <stdint.h>
340 #include <stddef.h>
341 #include <stdbool.h>
342 #include "cy_syslib.h"
343 #include "cy_syspm.h"
344
345 #if defined(__cplusplus)
346 extern "C" {
347 #endif
348
349
350 /*******************************************************************************
351 * Function Prototypes
352 *******************************************************************************/
353
354 /**
355 * \addtogroup group_scb_common_functions
356 * \{
357 */
358 __STATIC_FORCEINLINE uint32_t Cy_SCB_ReadRxFifo (CySCB_Type const *base);
359 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level);
360 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base);
361 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid (CySCB_Type const *base);
362 __STATIC_INLINE void Cy_SCB_ClearRxFifo (CySCB_Type *base);
363
364 __STATIC_FORCEINLINE void Cy_SCB_WriteTxFifo (CySCB_Type *base, uint32_t data);
365 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level);
366 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base);
367 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid (CySCB_Type const *base);
368 __STATIC_INLINE bool Cy_SCB_IsTxComplete (CySCB_Type const *base);
369 __STATIC_INLINE void Cy_SCB_ClearTxFifo (CySCB_Type *base);
370
371 __STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode);
372
373 __STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base);
374
375 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base);
376 __STATIC_INLINE void Cy_SCB_SetRxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
377 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask (CySCB_Type const *base);
378 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base);
379 __STATIC_INLINE void Cy_SCB_ClearRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
380 __STATIC_INLINE void Cy_SCB_SetRxInterrupt (CySCB_Type *base, uint32_t interruptMask);
381
382 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base);
383 __STATIC_INLINE void Cy_SCB_SetTxInterruptMask (CySCB_Type *base, uint32_t interruptMask);
384 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask (CySCB_Type const *base);
385 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base);
386 __STATIC_INLINE void Cy_SCB_ClearTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
387 __STATIC_INLINE void Cy_SCB_SetTxInterrupt (CySCB_Type *base, uint32_t interruptMask);
388
389 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base);
390 __STATIC_INLINE void Cy_SCB_SetMasterInterruptMask (CySCB_Type *base, uint32_t interruptMask);
391 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask (CySCB_Type const *base);
392 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base);
393 __STATIC_INLINE void Cy_SCB_ClearMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
394 __STATIC_INLINE void Cy_SCB_SetMasterInterrupt (CySCB_Type *base, uint32_t interruptMask);
395
396 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base);
397 __STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask (CySCB_Type *base, uint32_t interruptMask);
398 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask (CySCB_Type const *base);
399 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base);
400 __STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
401 __STATIC_INLINE void Cy_SCB_SetSlaveInterrupt (CySCB_Type *base, uint32_t interruptMask);
402
403 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base);
404 __STATIC_INLINE void Cy_SCB_SetI2CInterruptMask (CySCB_Type *base, uint32_t interruptMask);
405 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask (CySCB_Type const *base);
406 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base);
407 __STATIC_INLINE void Cy_SCB_ClearI2CInterrupt (CySCB_Type *base, uint32_t interruptMask);
408
409 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base);
410 __STATIC_INLINE void Cy_SCB_SetSpiInterruptMask (CySCB_Type *base, uint32_t interruptMask);
411 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask (CySCB_Type const *base);
412 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base);
413 __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt (CySCB_Type *base, uint32_t interruptMask);
414
415
416 /*******************************************************************************
417 * Internal Function Prototypes
418 *******************************************************************************/
419
420 /** \cond INTERNAL */
421 void Cy_SCB_ReadArrayNoCheck (CySCB_Type const *base, void *buffer, uint32_t size);
422 uint32_t Cy_SCB_ReadArray (CySCB_Type const *base, void *buffer, uint32_t size);
423 void Cy_SCB_ReadArrayBlocking (CySCB_Type const *base, void *buffer, uint32_t size);
424 uint32_t Cy_SCB_Write (CySCB_Type *base, uint32_t data);
425 void Cy_SCB_WriteArrayNoCheck (CySCB_Type *base, void *buffer, uint32_t size);
426 uint32_t Cy_SCB_WriteArray (CySCB_Type *base, void *buffer, uint32_t size);
427 void Cy_SCB_WriteArrayBlocking(CySCB_Type *base, void *buffer, uint32_t size);
428 void Cy_SCB_WriteString (CySCB_Type *base, char_t const string[]);
429 void Cy_SCB_WriteDefaultArrayNoCheck(CySCB_Type *base, uint32_t txData, uint32_t size);
430 uint32_t Cy_SCB_WriteDefaultArray (CySCB_Type *base, uint32_t txData, uint32_t size);
431
432 __STATIC_INLINE uint32_t Cy_SCB_GetFifoSize (CySCB_Type const *base);
433 __STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base);
434 __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base);
435 __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base);
436 __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel (CySCB_Type const *base);
437 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
438 __STATIC_INLINE uint32_t Cy_SCB_Get_RxDataWidth(CySCB_Type const *base);
439 __STATIC_INLINE uint32_t Cy_SCB_Get_TxDataWidth(CySCB_Type const *base);
440 #endif /* CY_IP_MXSCB_VERSION */
441 /** \endcond */
442
443 /** \} group_scb_common_functions */
444
445
446 /*******************************************************************************
447 * API Constants
448 *******************************************************************************/
449
450 /**
451 * \addtogroup group_scb_common_macros
452 * \{
453 */
454
455 /** Driver major version */
456 #define CY_SCB_DRV_VERSION_MAJOR (3)
457
458 /** Driver minor version */
459 #define CY_SCB_DRV_VERSION_MINOR (10)
460
461 /** SCB driver identifier */
462 #define CY_SCB_ID CY_PDL_DRV_ID(0x2AU)
463
464 /** Position for SCB driver sub mode */
465 #define CY_SCB_SUB_MODE_Pos (13UL)
466
467 /** EZI2C mode identifier */
468 #define CY_SCB_EZI2C_ID (0x0UL << CY_SCB_SUB_MODE_Pos)
469
470 /** I2C mode identifier */
471 #define CY_SCB_I2C_ID (0x1UL << CY_SCB_SUB_MODE_Pos)
472
473 /** SPI mode identifier */
474 #define CY_SCB_SPI_ID (0x2UL << CY_SCB_SUB_MODE_Pos)
475
476 /** UART mode identifier */
477 #define CY_SCB_UART_ID (0x3UL << CY_SCB_SUB_MODE_Pos)
478
479 /**
480 * \defgroup group_scb_common_macros_intr_cause SCB Interrupt Causes
481 * \{
482 */
483 /** Interrupt from Master interrupt sources */
484 #define CY_SCB_MASTER_INTR SCB_INTR_CAUSE_M_Msk
485
486 /** Interrupt from Slave interrupt sources */
487 #define CY_SCB_SLAVE_INTR SCB_INTR_CAUSE_S_Msk
488
489 /** Interrupt from TX interrupt sources */
490 #define CY_SCB_TX_INTR SCB_INTR_CAUSE_TX_Msk
491
492 /** Interrupt from RX interrupt sources */
493 #define CY_SCB_RX_INTR SCB_INTR_CAUSE_RX_Msk
494
495 /** Interrupt from I2C externally clocked interrupt sources */
496 #define CY_SCB_I2C_INTR SCB_INTR_CAUSE_I2C_EC_Msk
497
498 /** Interrupt from SPI externally clocked interrupt sources */
499 #define CY_SCB_SPI_INTR SCB_INTR_CAUSE_SPI_EC_Msk
500 /** \} group_scb_common_macros_intr_cause */
501
502 /**
503 * \defgroup group_scb_common_macros_tx_intr TX Interrupt Statuses
504 * \{
505 */
506 /**
507 * The number of data elements in the TX FIFO is less than the value
508 * of the TX FIFO level
509 */
510 #define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk
511
512 /** The TX FIFO is not full */
513 #define CY_SCB_TX_INTR_NOT_FULL SCB_INTR_TX_NOT_FULL_Msk
514
515 /** The TX FIFO is empty */
516 #define CY_SCB_TX_INTR_EMPTY SCB_INTR_TX_EMPTY_Msk
517
518 /** An attempt to write to a full TX FIFO */
519 #define CY_SCB_TX_INTR_OVERFLOW SCB_INTR_TX_OVERFLOW_Msk
520
521 /** An attempt to read from an empty TX FIFO */
522 #define CY_SCB_TX_INTR_UNDERFLOW SCB_INTR_TX_UNDERFLOW_Msk
523
524 /** The UART transfer is complete: all data elements from the TX FIFO are sent
525 */
526 #define CY_SCB_TX_INTR_UART_DONE SCB_INTR_TX_UART_DONE_Msk
527
528 /** SmartCard only: UART received a NACK */
529 #define CY_SCB_TX_INTR_UART_NACK SCB_INTR_TX_UART_NACK_Msk
530
531 /**
532 * SmartCard only: the value on the TX line of the UART does not match the
533 * value on the RX line
534 */
535 #define CY_SCB_TX_INTR_UART_ARB_LOST SCB_INTR_TX_UART_ARB_LOST_Msk
536 /** \} group_scb_common_macros_tx_intr */
537
538 /**
539 * \defgroup group_scb_common_macros_rx_intr RX Interrupt Statuses
540 * \{
541 */
542 /**
543 * The number of data elements in the RX FIFO is greater than the value of the
544 * RX FIFO level
545 */
546 #define CY_SCB_RX_INTR_LEVEL SCB_INTR_RX_TRIGGER_Msk
547
548 /** The RX FIFO is not empty */
549 #define CY_SCB_RX_INTR_NOT_EMPTY SCB_INTR_RX_NOT_EMPTY_Msk
550
551 /** The RX FIFO is full */
552 #define CY_SCB_RX_INTR_FULL SCB_INTR_RX_FULL_Msk
553
554 /** An attempt to write to a full RX FIFO */
555 #define CY_SCB_RX_INTR_OVERFLOW SCB_INTR_RX_OVERFLOW_Msk
556
557 /** An attempt to read from an empty RX FIFO */
558 #define CY_SCB_RX_INTR_UNDERFLOW SCB_INTR_RX_UNDERFLOW_Msk
559
560 /** A UART framing error detected */
561 #define CY_SCB_RX_INTR_UART_FRAME_ERROR SCB_INTR_RX_FRAME_ERROR_Msk
562
563 /** A UART parity error detected */
564 #define CY_SCB_RX_INTR_UART_PARITY_ERROR SCB_INTR_RX_PARITY_ERROR_Msk
565
566 /** A UART break detected */
567 #define CY_SCB_RX_INTR_UART_BREAK_DETECT SCB_INTR_RX_BREAK_DETECT_Msk
568 /** \} group_scb_common_macros_rx_intr */
569
570 /**
571 * \defgroup group_scb_common_macros_slave_intr Slave Interrupt Statuses
572 * \{
573 */
574 /**
575 * I2C slave lost arbitration: the value driven on the SDA line is not the same
576 * as the value observed on the SDA line
577 */
578 #define CY_SCB_SLAVE_INTR_I2C_ARB_LOST SCB_INTR_S_I2C_ARB_LOST_Msk
579
580 /** The I2C slave received a NAK */
581 #define CY_SCB_SLAVE_INTR_I2C_NACK SCB_INTR_S_I2C_NACK_Msk
582
583 /** The I2C slave received an ACK */
584 #define CY_SCB_SLAVE_INTR_I2C_ACK SCB_INTR_S_I2C_ACK_Msk
585
586 /**
587 * A Stop or Repeated Start event for a write transfer intended for this slave
588 * was detected.
589 */
590 #define CY_SCB_SLAVE_INTR_I2C_WRITE_STOP SCB_INTR_S_I2C_WRITE_STOP_Msk
591
592 /** A Stop or Repeated Start event intended for this slave was detected */
593 #define CY_SCB_SLAVE_INTR_I2C_STOP SCB_INTR_S_I2C_STOP_Msk
594
595 /** The I2C slave received a Start condition */
596 #define CY_SCB_SLAVE_INTR_I2C_START SCB_INTR_S_I2C_START_Msk
597
598 /** The I2C slave received the matching address */
599 #define CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH SCB_INTR_S_I2C_ADDR_MATCH_Msk
600
601 /** The I2C Slave received the general call address */
602 #define CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR SCB_INTR_S_I2C_GENERAL_Msk
603
604 /** The I2C slave bus error (detection of unexpected Start or Stop condition) */
605 #define CY_SCB_SLAVE_INTR_I2C_BUS_ERROR SCB_INTR_S_I2C_BUS_ERROR_Msk
606
607 /**
608 * The SPI slave select line is deselected at an expected time during an
609 * SPI transfer.
610 */
611 #define CY_SCB_SLAVE_INTR_SPI_BUS_ERROR SCB_INTR_S_SPI_BUS_ERROR_Msk
612 /** \} group_scb_common_macros_slave_intr */
613
614 /**
615 * \defgroup group_scb_common_macros_master_intr Master Interrupt Statuses
616 * \{
617 */
618 /** The I2C master lost arbitration */
619 #define CY_SCB_MASTER_INTR_I2C_ARB_LOST SCB_INTR_M_I2C_ARB_LOST_Msk
620
621 /** The I2C master received a NACK */
622 #define CY_SCB_MASTER_INTR_I2C_NACK SCB_INTR_M_I2C_NACK_Msk
623
624 /** The I2C master received an ACK */
625 #define CY_SCB_MASTER_INTR_I2C_ACK SCB_INTR_M_I2C_ACK_Msk
626
627 /** The I2C master generated a Stop */
628 #define CY_SCB_MASTER_INTR_I2C_STOP SCB_INTR_M_I2C_STOP_Msk
629
630 /** The I2C master bus error (detection of unexpected START or STOP condition)
631 */
632 #define CY_SCB_MASTER_INTR_I2C_BUS_ERROR SCB_INTR_M_I2C_BUS_ERROR_Msk
633
634 /**
635 * The SPI master transfer is complete: all data elements transferred from the
636 * TX FIFO and TX shift register.
637 */
638 #define CY_SCB_MASTER_INTR_SPI_DONE SCB_INTR_M_SPI_DONE_Msk
639 /** \} group_scb_common_macros_master_intr */
640
641 /**
642 * \defgroup group_scb_common_macros_i2c_intr I2C Interrupt Statuses
643 * \{
644 */
645 /**
646 * Wake up request: the I2C slave received the matching address.
647 * Note that this interrupt source triggers in active mode.
648 */
649 #define CY_SCB_I2C_INTR_WAKEUP SCB_INTR_I2C_EC_WAKE_UP_Msk
650 /** \} group_scb_common_macros_i2c_intr */
651
652 /**
653 * \defgroup group_scb_common_macros_SpiIntrStatuses SPI Interrupt Statuses
654 * \{
655 */
656 /**
657 * Wake up request: the SPI slave detects an active edge of the slave select
658 * signal. Note that this interrupt source triggers in active mode.
659 */
660 #define CY_SCB_SPI_INTR_WAKEUP SCB_INTR_SPI_EC_WAKE_UP_Msk
661 /** \} group_scb_common_macros_SpiIntrStatuses */
662
663
664 /*******************************************************************************
665 * Internal Constants
666 *******************************************************************************/
667
668 /** \cond INTERNAL */
669
670 /* Default registers values */
671 #define CY_SCB_CTRL_DEF_VAL (_VAL2FLD(SCB_CTRL_OVS, 15UL) | \
672 _VAL2FLD(SCB_CTRL_MODE, 3UL))
673
674 #define CY_SCB_I2C_CTRL_DEF_VAL (_VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
675 _VAL2FLD(SCB_I2C_CTRL_HIGH_PHASE_OVS, 8UL) | \
676 _VAL2FLD(SCB_I2C_CTRL_M_READY_DATA_ACK, 1UL) | \
677 _VAL2FLD(SCB_I2C_CTRL_M_NOT_READY_DATA_NACK, 1UL) | \
678 _VAL2FLD(SCB_I2C_CTRL_S_GENERAL_IGNORE, 1UL) | \
679 _VAL2FLD(SCB_I2C_CTRL_S_READY_ADDR_ACK, 1UL) | \
680 _VAL2FLD(SCB_I2C_CTRL_S_READY_DATA_ACK, 1UL) | \
681 _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK, 1UL) | \
682 _VAL2FLD(SCB_I2C_CTRL_S_NOT_READY_DATA_NACK, 1UL))
683
684 #define CY_SCB_I2C_CFG_DEF_VAL (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 3UL) | \
685 _VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_SEL, 1UL) | \
686 _VAL2FLD(SCB_I2C_CFG_SCL_IN_FILT_SEL, 1UL) | \
687 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT0_TRIM, 2UL) | \
688 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT1_TRIM, 2UL) | \
689 _VAL2FLD(SCB_I2C_CFG_SDA_OUT_FILT2_TRIM, 2UL))
690
691 #define CY_SCB_SPI_CTRL_DEF_VAL _VAL2FLD(SCB_SPI_CTRL_MODE, 3UL)
692 #define CY_SCB_UART_CTRL_DEF_VAL _VAL2FLD(SCB_UART_CTRL_MODE, 3UL)
693
694 #define CY_SCB_UART_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_UART_RX_CTRL_STOP_BITS, 2UL) | \
695 _VAL2FLD(SCB_UART_RX_CTRL_BREAK_WIDTH, 10UL))
696
697 #define CY_SCB_UART_TX_CTRL_DEF_VAL _VAL2FLD(SCB_UART_TX_CTRL_STOP_BITS, 2UL)
698
699 #define CY_SCB_RX_CTRL_DEF_VAL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, 7UL) | \
700 _VAL2FLD(SCB_RX_CTRL_MSB_FIRST, 1UL))
701
702 #define CY_SCB_TX_CTRL_DEF_VAL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, 7UL) | \
703 _VAL2FLD(SCB_TX_CTRL_MSB_FIRST, 1UL))
704
705 /* SCB CTRL modes */
706 #define CY_SCB_CTRL_MODE_I2C (0UL)
707 #define CY_SCB_CTRL_MODE_SPI (1UL)
708 #define CY_SCB_CTRL_MODE_UART (2UL)
709
710 /* The position and mask to set the I2C mode */
711 #define CY_SCB_I2C_CTRL_MODE_Pos SCB_I2C_CTRL_SLAVE_MODE_Pos
712 #define CY_SCB_I2C_CTRL_MODE_Msk (SCB_I2C_CTRL_SLAVE_MODE_Msk | \
713 SCB_I2C_CTRL_MASTER_MODE_Msk)
714
715 /* Cypress ID #282226:
716 * SCB_I2C_CFG_SDA_IN_FILT_TRIM[1]: SCB clock enable (1), clock disable (0).
717 */
718 #define CY_SCB_I2C_CFG_CLK_ENABLE_Msk (_VAL2FLD(SCB_I2C_CFG_SDA_IN_FILT_TRIM, 2UL))
719
720 /* I2C has fixed data width */
721 #define CY_SCB_I2C_DATA_WIDTH (7UL)
722
723 /* RX and TX control register values */
724 #define CY_SCB_I2C_RX_CTRL (_VAL2FLD(SCB_RX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
725 SCB_RX_CTRL_MSB_FIRST_Msk)
726 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION<=2)) && (!defined (CY_IP_MXS22SCB)))
727 #define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
728 SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk)
729 #else
730 #define CY_SCB_I2C_TX_CTRL (_VAL2FLD(SCB_TX_CTRL_DATA_WIDTH, CY_SCB_I2C_DATA_WIDTH) | \
731 SCB_TX_CTRL_MSB_FIRST_Msk | SCB_TX_CTRL_OPEN_DRAIN_Msk | \
732 SCB_TX_CTRL_OPEN_DRAIN_SCL_Msk)
733 #endif
734 /* The position and mask to make an address byte */
735 #define CY_SCB_I2C_ADDRESS_Pos (1UL)
736 #define CY_SCB_I2C_ADDRESS_Msk (0xFEUL)
737
738 /* SPI slave select polarity */
739 #define CY_SCB_SPI_CTRL_SSEL_POLARITY_Pos SCB_SPI_CTRL_SSEL_POLARITY0_Pos
740 #define CY_SCB_SPI_CTRL_SSEL_POLARITY_Msk (SCB_SPI_CTRL_SSEL_POLARITY0_Msk | \
741 SCB_SPI_CTRL_SSEL_POLARITY1_Msk | \
742 SCB_SPI_CTRL_SSEL_POLARITY2_Msk | \
743 SCB_SPI_CTRL_SSEL_POLARITY3_Msk)
744
745 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
746 /* SPI parity and parity enable combination */
747 #define CY_SCB_SPI_RX_CTRL_SET_PARITY_Msk (SCB_SPI_RX_CTRL_PARITY_ENABLED_Msk | \
748 SCB_SPI_RX_CTRL_PARITY_Msk)
749 #define CY_SCB_SPI_RX_CTRL_SET_PARITY_Pos SCB_SPI_RX_CTRL_PARITY_Pos
750
751 #define CY_SCB_SPI_TX_CTRL_SET_PARITY_Msk (SCB_SPI_TX_CTRL_PARITY_ENABLED_Msk | \
752 SCB_SPI_TX_CTRL_PARITY_Msk)
753 #define CY_SCB_SPI_TX_CTRL_SET_PARITY_Pos SCB_SPI_TX_CTRL_PARITY_Pos
754 #endif /* CY_IP_MXSCB_VERSION */
755
756 /* SPI clock modes: CPHA and CPOL */
757 #define CY_SCB_SPI_CTRL_CLK_MODE_Pos SCB_SPI_CTRL_CPHA_Pos
758 #define CY_SCB_SPI_CTRL_CLK_MODE_Msk (SCB_SPI_CTRL_CPHA_Msk | SCB_SPI_CTRL_CPOL_Msk)
759
760 /* UART parity and parity enable combination */
761 #define CY_SCB_UART_RX_CTRL_SET_PARITY_Msk (SCB_UART_RX_CTRL_PARITY_ENABLED_Msk | \
762 SCB_UART_RX_CTRL_PARITY_Msk)
763 #define CY_SCB_UART_RX_CTRL_SET_PARITY_Pos SCB_UART_RX_CTRL_PARITY_Pos
764
765 #define CY_SCB_UART_TX_CTRL_SET_PARITY_Msk (SCB_UART_TX_CTRL_PARITY_ENABLED_Msk | \
766 SCB_UART_TX_CTRL_PARITY_Msk)
767 #define CY_SCB_UART_TX_CTRL_SET_PARITY_Pos SCB_UART_TX_CTRL_PARITY_Pos
768
769 /* Max number of bits for byte mode */
770 #define CY_SCB_BYTE_WIDTH (8UL)
771
772 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
773 /* Max number of bits for HALF WORD mode */
774 #define CY_SCB_HALF_WORD_WIDTH (16UL)
775
776 /* Max number of bits for WORD mode */
777 #define CY_SCB_WORD_WIDTH (32UL)
778
779 /*SCB Mem width modes */
780 #define CY_SCB_MEM_WIDTH_BYTE (0UL)
781 #define CY_SCB_MEM_WIDTH_HALFWORD (1UL)
782 #define CY_SCB_MEM_WIDTH_WORD (2UL)
783 #endif /* ((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) */
784
785 /* Single unit to wait */
786 #define CY_SCB_WAIT_1_UNIT (1U)
787
788 /* Clear interrupt sources */
789 #define CY_SCB_CLEAR_ALL_INTR_SRC (0UL)
790
791 /* Hardware FIFO size: EZ_DATA_NR / 4 = (512 / 4) = 128 */
792 #define CY_SCB_FIFO_SIZE (128UL)
793
794 /* Provides a list of allowed sources */
795 #define CY_SCB_TX_INTR_MASK (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_NOT_FULL | CY_SCB_TX_INTR_EMPTY | \
796 CY_SCB_TX_INTR_OVERFLOW | CY_SCB_TX_INTR_UNDERFLOW | CY_SCB_TX_INTR_UART_DONE | \
797 CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INTR_UART_ARB_LOST)
798
799 #define CY_SCB_RX_INTR_MASK (CY_SCB_RX_INTR_LEVEL | CY_SCB_RX_INTR_NOT_EMPTY | CY_SCB_RX_INTR_FULL | \
800 CY_SCB_RX_INTR_OVERFLOW | CY_SCB_RX_INTR_UNDERFLOW | \
801 CY_SCB_RX_INTR_UART_FRAME_ERROR | CY_SCB_RX_INTR_UART_PARITY_ERROR | \
802 CY_SCB_RX_INTR_UART_BREAK_DETECT)
803
804
805 #define CY_SCB_SLAVE_INTR_MASK (CY_SCB_SLAVE_INTR_I2C_ARB_LOST | CY_SCB_SLAVE_INTR_I2C_NACK | CY_SCB_SLAVE_INTR_I2C_ACK | \
806 CY_SCB_SLAVE_INTR_I2C_WRITE_STOP | CY_SCB_SLAVE_INTR_I2C_STOP | CY_SCB_SLAVE_INTR_I2C_START | \
807 CY_SCB_SLAVE_INTR_I2C_ADDR_MATCH | CY_SCB_SLAVE_INTR_I2C_GENERAL_ADDR | \
808 CY_SCB_SLAVE_INTR_I2C_BUS_ERROR | CY_SCB_SLAVE_INTR_SPI_BUS_ERROR)
809
810 #define CY_SCB_MASTER_INTR_MASK (CY_SCB_MASTER_INTR_I2C_ARB_LOST | CY_SCB_MASTER_INTR_I2C_NACK | \
811 CY_SCB_MASTER_INTR_I2C_ACK | CY_SCB_MASTER_INTR_I2C_STOP | \
812 CY_SCB_MASTER_INTR_I2C_BUS_ERROR | CY_SCB_MASTER_INTR_SPI_DONE)
813
814 #define CY_SCB_I2C_INTR_MASK CY_SCB_I2C_INTR_WAKEUP
815
816 #define CY_SCB_SPI_INTR_MASK CY_SCB_SPI_INTR_WAKEUP
817
818 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
819 #define CY_SCB_IS_MEMWIDTH_VALID(memwidth) ((memwidth) <= CY_SCB_MEM_WIDTH_WORD)
820 #endif /* CY_IP_MXSCB_VERSION */
821
822 #define CY_SCB_IS_INTR_VALID(intr, mask) ( 0UL == ((intr) & ((uint32_t) ~(mask))) )
823 #define CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level) ((level) < Cy_SCB_GetFifoSize(base))
824
825 #define CY_SCB_IS_I2C_ADDR_VALID(addr) ( (0U == ((addr) & 0x80U)) )
826 #define CY_SCB_IS_BUFFER_VALID(buffer, size) ( (NULL != (buffer)) && ((size) > 0UL) )
827 #define CY_SCB_IS_I2C_BUFFER_VALID(buffer, size) ( (0UL == (size)) ? true : (NULL != (buffer)) )
828 /** \endcond */
829
830 /** \} group_scb_common_macros */
831
832
833 /*******************************************************************************
834 * In-line Function Implementation
835 *******************************************************************************/
836
837 /**
838 * \addtogroup group_scb_common_functions
839 * \{
840 */
841
842 /*******************************************************************************
843 * Function Name: Cy_SCB_ReadRxFifo
844 ****************************************************************************//**
845 *
846 * Reads a data element directly out of the RX FIFO.
847 * This function does not check whether the RX FIFO has data before reading it.
848 *
849 * \param base
850 * The pointer to the SCB instance.
851 *
852 * \return
853 * Data from RX FIFO.
854 *
855 *******************************************************************************/
Cy_SCB_ReadRxFifo(CySCB_Type const * base)856 __STATIC_FORCEINLINE uint32_t Cy_SCB_ReadRxFifo(CySCB_Type const *base)
857 {
858 return (SCB_RX_FIFO_RD(base));
859 }
860
861 /*******************************************************************************
862 * Function Name: Cy_SCB_SetRxFifoLevel
863 ****************************************************************************//**
864 *
865 * Sets the RX FIFO level. When there are more data elements in the RX FIFO than
866 * this level, the RX FIFO level interrupt is triggered.
867 *
868 * \param base
869 * The pointer to the SCB instance.
870 *
871 * \param level
872 * When there are more data elements in the FIFO than this level, the RX level
873 * interrupt is triggered.
874 *
875 *******************************************************************************/
Cy_SCB_SetRxFifoLevel(CySCB_Type * base,uint32_t level)876 __STATIC_INLINE void Cy_SCB_SetRxFifoLevel(CySCB_Type *base, uint32_t level)
877 {
878 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
879
880 CY_REG32_CLR_SET(SCB_RX_FIFO_CTRL(base), SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, level);
881 }
882
883
884 /*******************************************************************************
885 * Function Name: Cy_SCB_GetNumInRxFifo
886 ****************************************************************************//**
887 *
888 * Returns the number of data elements currently in the RX FIFO.
889 *
890 * \param base
891 * The pointer to the SCB instance.
892 *
893 * \return
894 * The number or data elements in RX FIFO.
895 *
896 *******************************************************************************/
Cy_SCB_GetNumInRxFifo(CySCB_Type const * base)897 __STATIC_INLINE uint32_t Cy_SCB_GetNumInRxFifo(CySCB_Type const *base)
898 {
899 return _FLD2VAL(SCB_RX_FIFO_STATUS_USED, SCB_RX_FIFO_STATUS(base));
900 }
901
902
903 /*******************************************************************************
904 * Function Name: Cy_SCB_GetRxSrValid
905 ****************************************************************************//**
906 *
907 * Returns the status of the RX FIFO Shift Register valid bit.
908 *
909 * \param base
910 * The pointer to the SCB instance.
911 *
912 * \return
913 * 1 - RX shift register valid; 0 - RX shift register not valid.
914 *
915 *******************************************************************************/
Cy_SCB_GetRxSrValid(CySCB_Type const * base)916 __STATIC_INLINE uint32_t Cy_SCB_GetRxSrValid(CySCB_Type const *base)
917 {
918 return _FLD2VAL(SCB_RX_FIFO_STATUS_SR_VALID, SCB_RX_FIFO_STATUS(base));
919 }
920
921
922 /*******************************************************************************
923 * Function Name: Cy_SCB_ClearRxFifo
924 ****************************************************************************//**
925 *
926 * Clears the RX FIFO and shifter.
927 *
928 * \param base
929 * The pointer to the SCB instance.
930 *
931 * \note
932 * If there is partial data in the shifter, it is cleared and lost.
933 *
934 *******************************************************************************/
Cy_SCB_ClearRxFifo(CySCB_Type * base)935 __STATIC_INLINE void Cy_SCB_ClearRxFifo(CySCB_Type* base)
936 {
937 SCB_RX_FIFO_CTRL(base) |= (uint32_t) SCB_RX_FIFO_CTRL_CLEAR_Msk;
938 SCB_RX_FIFO_CTRL(base) &= (uint32_t) ~SCB_RX_FIFO_CTRL_CLEAR_Msk;
939
940 (void) SCB_RX_FIFO_CTRL(base);
941 }
942
943
944 /*******************************************************************************
945 * Function Name: Cy_SCB_WriteTxFifo
946 ****************************************************************************//**
947 *
948 * Writes data directly into the TX FIFO.
949 * This function does not check whether the TX FIFO is not full before writing
950 * into it.
951 *
952 * \param base
953 * The pointer to the SCB instance.
954 *
955 * \param data
956 * Data to write to the TX FIFO.
957 *
958 *******************************************************************************/
Cy_SCB_WriteTxFifo(CySCB_Type * base,uint32_t data)959 __STATIC_FORCEINLINE void Cy_SCB_WriteTxFifo(CySCB_Type* base, uint32_t data)
960 {
961 SCB_TX_FIFO_WR(base) = data;
962 }
963
964
965 /*******************************************************************************
966 * Function Name: Cy_SCB_SetTxFifoLevel
967 ****************************************************************************//**
968 *
969 * Sets the TX FIFO level. When there are fewer data elements in the TX FIFO than
970 * this level, the TX FIFO level interrupt is triggered.
971 *
972 * \param base
973 * The pointer to the SCB instance.
974 *
975 * \param level
976 * When there are fewer data elements in the FIFO than this level, the TX level
977 * interrupt is triggered.
978 *
979 *******************************************************************************/
Cy_SCB_SetTxFifoLevel(CySCB_Type * base,uint32_t level)980 __STATIC_INLINE void Cy_SCB_SetTxFifoLevel(CySCB_Type *base, uint32_t level)
981 {
982 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level));
983
984 CY_REG32_CLR_SET(SCB_TX_FIFO_CTRL(base), SCB_TX_FIFO_CTRL_TRIGGER_LEVEL, level);
985 }
986
987
988 /*******************************************************************************
989 * Function Name: Cy_SCB_GetNumInTxFifo
990 ****************************************************************************//**
991 *
992 * Returns the number of data elements currently in the TX FIFO.
993 *
994 * \param base
995 * The pointer to the SCB instance.
996 *
997 * \return
998 * The number or data elements in the TX FIFO.
999 *
1000 *******************************************************************************/
Cy_SCB_GetNumInTxFifo(CySCB_Type const * base)1001 __STATIC_INLINE uint32_t Cy_SCB_GetNumInTxFifo(CySCB_Type const *base)
1002 {
1003 return _FLD2VAL(SCB_TX_FIFO_STATUS_USED, SCB_TX_FIFO_STATUS(base));
1004 }
1005
1006
1007 /*******************************************************************************
1008 * Function Name: Cy_SCB_GetTxSrValid
1009 ****************************************************************************//**
1010 *
1011 * Returns the status of the TX FIFO Shift Register valid bit.
1012 *
1013 * \param base
1014 * The pointer to the SCB instance.
1015 *
1016 * \return
1017 * 1 - TX shift register valid; 0 - TX shift register not valid.
1018 *
1019 *******************************************************************************/
Cy_SCB_GetTxSrValid(CySCB_Type const * base)1020 __STATIC_INLINE uint32_t Cy_SCB_GetTxSrValid(CySCB_Type const *base)
1021 {
1022 return _FLD2VAL(SCB_TX_FIFO_STATUS_SR_VALID, SCB_TX_FIFO_STATUS(base));
1023 }
1024
1025
1026 /*******************************************************************************
1027 * Function Name: Cy_SCB_IsTxComplete
1028 ****************************************************************************//**
1029 *
1030 * Checks whether the TX FIFO and Shifter are empty and there is no more data to send.
1031 *
1032 * \param base
1033 * Pointer to SPI the SCB instance.
1034 *
1035 * \return
1036 * If true, transmission complete. If false, transmission is not complete.
1037 *
1038 *******************************************************************************/
Cy_SCB_IsTxComplete(CySCB_Type const * base)1039 __STATIC_INLINE bool Cy_SCB_IsTxComplete(CySCB_Type const *base)
1040 {
1041 return (0UL == (Cy_SCB_GetNumInTxFifo(base) + Cy_SCB_GetTxSrValid(base)));
1042 }
1043
1044
1045 /*******************************************************************************
1046 * Function Name: Cy_SCB_ClearTxFifo
1047 ****************************************************************************//**
1048 *
1049 * Clears the TX FIFO.
1050 *
1051 * \param base
1052 * The pointer to the SCB instance.
1053 *
1054 * \note
1055 * The TX FIFO clear operation also clears the shift register. Thus the shifter
1056 * could be cleared in the middle of a data element transfer. Thia results in
1057 * "ones" being sent on the bus for the remainder of the transfer.
1058 *
1059 *******************************************************************************/
Cy_SCB_ClearTxFifo(CySCB_Type * base)1060 __STATIC_INLINE void Cy_SCB_ClearTxFifo(CySCB_Type *base)
1061 {
1062 SCB_TX_FIFO_CTRL(base) |= (uint32_t) SCB_TX_FIFO_CTRL_CLEAR_Msk;
1063 SCB_TX_FIFO_CTRL(base) &= (uint32_t) ~SCB_TX_FIFO_CTRL_CLEAR_Msk;
1064
1065 (void) SCB_TX_FIFO_CTRL(base);
1066 }
1067
1068
1069 /*******************************************************************************
1070 * Function Name: Cy_SCB_SetByteMode
1071 ****************************************************************************//**
1072 *
1073 * Sets whether the RX and TX FIFOs are in byte mode.
1074 * The FIFOs are either 16-bit wide or 8-bit wide (byte mode).
1075 * When the FIFO is in byte mode it is twice as deep. See the device datasheet
1076 * for FIFO depths.
1077 *
1078 * \param base
1079 * The pointer to the SCB instance.
1080 *
1081 * \param byteMode
1082 * If true, TX and RX FIFOs are 8-bit wide. If false, the FIFOs are 16-bit wide.
1083 *
1084 *******************************************************************************/
Cy_SCB_SetByteMode(CySCB_Type * base,bool byteMode)1085 __STATIC_INLINE void Cy_SCB_SetByteMode(CySCB_Type *base, bool byteMode)
1086 {
1087 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
1088 SCB_CTRL(base) &= ~SCB_CTRL_MEM_WIDTH_Msk;
1089 if (byteMode)
1090 {
1091 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, CY_SCB_MEM_WIDTH_BYTE);
1092 }
1093 else
1094 {
1095 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, CY_SCB_MEM_WIDTH_HALFWORD);
1096 }
1097 #elif(defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION==1))
1098 if (byteMode)
1099 {
1100 SCB_CTRL(base) |= SCB_CTRL_BYTE_MODE_Msk;
1101 }
1102 else
1103 {
1104 SCB_CTRL(base) &= ~SCB_CTRL_BYTE_MODE_Msk;
1105 }
1106 #endif /* ((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) */
1107 }
1108
1109 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
1110 /*******************************************************************************
1111 * Function Name: Cy_SCB_SetMemWidth
1112 ****************************************************************************//**
1113 *
1114 * Sets the RX and TX FIFOs byte mode/halfword/word mode.
1115 * The FIFOs are either 8-bit(byte),16-bit(halfword) or 32-bit (word) wide.
1116 * See the device datasheet for FIFO depths.
1117 *
1118 * \param base
1119 * The pointer to the SCB instance.
1120 *
1121 * \param MemWidthMode
1122 * If 0x0, TX and RX FIFOs are 8-bit wide.
1123 * If 0x1, the FIFOs are 16-bit wide.
1124 * If 0x2, the FIFOs are 32-bit wide.
1125 *
1126 * \note
1127 * This API is available for CAT1B and CAT1C devices.
1128 *
1129 *******************************************************************************/
Cy_SCB_SetMemWidth(CySCB_Type * base,uint32_t MemWidthMode)1130 __STATIC_INLINE void Cy_SCB_SetMemWidth(CySCB_Type *base, uint32_t MemWidthMode)
1131 {
1132 CY_ASSERT_L2(CY_SCB_IS_MEMWIDTH_VALID(MemWidthMode));
1133
1134 SCB_CTRL(base) &= ~SCB_CTRL_MEM_WIDTH_Msk;
1135
1136 SCB_CTRL(base) |= _VAL2FLD(SCB_CTRL_MEM_WIDTH, MemWidthMode);
1137 }
1138 #endif /* CY_IP_MXSCB_VERSION */
1139
1140 /*******************************************************************************
1141 * Function Name: Cy_SCB_GetInterruptCause
1142 ****************************************************************************//**
1143 *
1144 * Returns the mask of bits showing the source of the current triggered
1145 * interrupt. This is useful for modes of operation where an interrupt can
1146 * be generated by conditions in multiple interrupt source registers.
1147 *
1148 * \param base
1149 * The pointer to the SCB instance.
1150 *
1151 * \return
1152 * The mask with the OR of the following conditions that have been triggered.
1153 * See \ref group_scb_common_macros_intr_cause for the set of constants.
1154 *
1155 *******************************************************************************/
Cy_SCB_GetInterruptCause(CySCB_Type const * base)1156 __STATIC_INLINE uint32_t Cy_SCB_GetInterruptCause(CySCB_Type const *base)
1157 {
1158 return (SCB_INTR_CAUSE(base));
1159 }
1160
1161
1162 /*******************************************************************************
1163 * Function Name: Cy_SCB_GetRxInterruptStatus
1164 ****************************************************************************//**
1165 *
1166 * Returns the RX interrupt request register. This register contains the current
1167 * status of the RX interrupt sources.
1168 *
1169 * \param base
1170 * The pointer to the SCB instance.
1171 *
1172 * \return
1173 * The current status of the RX interrupt sources. Each constant is a bit field
1174 * value. The value returned may have multiple bits set to indicate the
1175 * current status.
1176 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1177 *
1178 *******************************************************************************/
Cy_SCB_GetRxInterruptStatus(CySCB_Type const * base)1179 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatus(CySCB_Type const *base)
1180 {
1181 return (SCB_INTR_RX(base) & CY_SCB_RX_INTR_MASK);
1182 }
1183
1184
1185 /*******************************************************************************
1186 * Function Name: Cy_SCB_SetRxInterruptMask
1187 ****************************************************************************//**
1188 *
1189 * Writes the RX interrupt mask register. This register configures which bits
1190 * from the RX interrupt request register can trigger an interrupt event.
1191 *
1192 * \param base
1193 * The pointer to the SCB instance.
1194 *
1195 * \param interruptMask
1196 * Enabled RX interrupt sources.
1197 * See \ref group_scb_common_macros_rx_intr.
1198 *
1199 *******************************************************************************/
Cy_SCB_SetRxInterruptMask(CySCB_Type * base,uint32_t interruptMask)1200 __STATIC_INLINE void Cy_SCB_SetRxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1201 {
1202 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1203
1204 SCB_INTR_RX_MASK(base) = interruptMask;
1205 }
1206
1207
1208 /*******************************************************************************
1209 * Function Name: Cy_SCB_GetRxInterruptMask
1210 ****************************************************************************//**
1211 *
1212 * Returns the RX interrupt mask register. This register specifies which bits
1213 * from the RX interrupt request register trigger can an interrupt event.
1214 *
1215 * \param base
1216 * The pointer to the SCB instance.
1217 *
1218 * \return
1219 * Enabled RX interrupt sources.
1220 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1221 *
1222 *******************************************************************************/
Cy_SCB_GetRxInterruptMask(CySCB_Type const * base)1223 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptMask(CySCB_Type const *base)
1224 {
1225 return (SCB_INTR_RX_MASK(base));
1226 }
1227
1228
1229 /*******************************************************************************
1230 * Function Name: Cy_SCB_GetRxInterruptStatusMasked
1231 ****************************************************************************//**
1232 *
1233 * Returns the RX interrupt masked request register. This register contains
1234 * a logical AND of corresponding bits from the RX interrupt request and
1235 * mask registers.
1236 * This function is intended to be used in the interrupt service routine to
1237 * identify which of the enabled RX interrupt sources caused the interrupt event.
1238 *
1239 * \param base
1240 * The pointer to the SCB instance.
1241 *
1242 * \return
1243 * The current status of enabled RX interrupt sources.
1244 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1245 *
1246 *******************************************************************************/
Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const * base)1247 __STATIC_INLINE uint32_t Cy_SCB_GetRxInterruptStatusMasked(CySCB_Type const *base)
1248 {
1249 return (SCB_INTR_RX_MASKED(base));
1250 }
1251
1252
1253 /*******************************************************************************
1254 * Function Name: Cy_SCB_ClearRxInterrupt
1255 ****************************************************************************//**
1256 *
1257 * Clears the RX interrupt sources in the interrupt request register.
1258 *
1259 * \param base
1260 * The pointer to the SCB instance.
1261 *
1262 * \param interruptMask
1263 * The RX interrupt sources to be cleared.
1264 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1265 *
1266 * \note
1267 * - CY_SCB_INTR_RX_FIFO_LEVEL interrupt source is not cleared when
1268 * the RX FIFO has more entries than the level.
1269 * - CY_SCB_INTR_RX_NOT_EMPTY interrupt source is not cleared when the
1270 * RX FIFO is not empty.
1271 * - CY_SCB_INTR_RX_FULL interrupt source is not cleared when the
1272 * RX FIFO is full.
1273 *
1274 *******************************************************************************/
Cy_SCB_ClearRxInterrupt(CySCB_Type * base,uint32_t interruptMask)1275 __STATIC_INLINE void Cy_SCB_ClearRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1276 {
1277 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1278
1279 SCB_INTR_RX(base) = interruptMask;
1280 (void) SCB_INTR_RX(base);
1281 }
1282
1283
1284 /*******************************************************************************
1285 * Function Name: Cy_SCB_SetRxInterrupt
1286 ****************************************************************************//**
1287 *
1288 * Sets the RX interrupt sources in the interrupt request register.
1289 *
1290 * \param base
1291 * The pointer to the SCB instance.
1292 *
1293 * \param interruptMask
1294 * The RX interrupt sources to set in the RX interrupt request register.
1295 * See \ref group_scb_common_macros_rx_intr for the set of constants.
1296 *
1297 *******************************************************************************/
Cy_SCB_SetRxInterrupt(CySCB_Type * base,uint32_t interruptMask)1298 __STATIC_INLINE void Cy_SCB_SetRxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1299 {
1300 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK));
1301
1302 SCB_INTR_RX_SET(base) = interruptMask;
1303 }
1304
1305
1306 /*******************************************************************************
1307 * Function Name: Cy_SCB_GetTxInterruptStatus
1308 ****************************************************************************//**
1309 *
1310 * Returns the TX interrupt request register. This register contains the current
1311 * status of the TX interrupt sources.
1312 *
1313 * \param base
1314 * The pointer to the SCB instance.
1315 *
1316 * \return
1317 * The current status of TX interrupt sources.
1318 * Each constant is a bit field value. The value returned may have multiple
1319 * bits set to indicate the current status.
1320 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1321 *
1322 *******************************************************************************/
Cy_SCB_GetTxInterruptStatus(CySCB_Type const * base)1323 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatus(CySCB_Type const *base)
1324 {
1325 return (SCB_INTR_TX(base) & CY_SCB_TX_INTR_MASK);
1326 }
1327
1328
1329 /*******************************************************************************
1330 * Function Name: Cy_SCB_SetTxInterruptMask
1331 ****************************************************************************//**
1332 *
1333 * Writes the TX interrupt mask register. This register configures which bits
1334 * from the TX interrupt request register can trigger an interrupt event.
1335 *
1336 * \param base
1337 * The pointer to the SCB instance.
1338 *
1339 * \param interruptMask
1340 * Enabled TX interrupt sources.
1341 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1342 *
1343 *******************************************************************************/
Cy_SCB_SetTxInterruptMask(CySCB_Type * base,uint32_t interruptMask)1344 __STATIC_INLINE void Cy_SCB_SetTxInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1345 {
1346 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1347
1348 SCB_INTR_TX_MASK(base) = interruptMask;
1349 }
1350
1351
1352 /*******************************************************************************
1353 * Function Name: Cy_SCB_GetTxInterruptMask
1354 ****************************************************************************//**
1355 *
1356 * Returns the TX interrupt mask register. This register specifies which
1357 * bits from the TX interrupt request register can trigger an interrupt event.
1358 *
1359 * \param base
1360 * The pointer to the SCB instance.
1361 *
1362 * \return
1363 * Enabled TX interrupt sources.
1364 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1365 *
1366 *******************************************************************************/
Cy_SCB_GetTxInterruptMask(CySCB_Type const * base)1367 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptMask(CySCB_Type const *base)
1368 {
1369 return (SCB_INTR_TX_MASK(base));
1370 }
1371
1372
1373 /*******************************************************************************
1374 * Function Name: Cy_SCB_GetTxInterruptStatusMasked
1375 ****************************************************************************//**
1376 *
1377 * Returns the TX interrupt masked request register. This register contains
1378 * a logical AND of corresponding bits from the TX interrupt request and
1379 * mask registers.
1380 * This function is intended to be used in the interrupt service routine to
1381 * identify which of enabled TX interrupt sources caused the interrupt event.
1382 *
1383 * \param base
1384 * The pointer to the SCB instance.
1385 *
1386 * \return
1387 * The current status of enabled TX interrupt sources.
1388 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1389 *
1390 *******************************************************************************/
Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const * base)1391 __STATIC_INLINE uint32_t Cy_SCB_GetTxInterruptStatusMasked(CySCB_Type const *base)
1392 {
1393 return (SCB_INTR_TX_MASKED(base));
1394 }
1395
1396
1397 /*******************************************************************************
1398 * Function Name: Cy_SCB_ClearTxInterrupt
1399 ****************************************************************************//**
1400 *
1401 * Clears the TX interrupt sources in the interrupt request register.
1402 *
1403 * \param base
1404 * The pointer to the SCB instance.
1405 *
1406 * \param interruptMask
1407 * The TX interrupt sources to be cleared.
1408 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1409 *
1410 * \note
1411 * - CY_SCB_INTR_TX_FIFO_LEVEL interrupt source is not cleared when the
1412 * TX FIFO has fewer entries than the TX level.
1413 * - CY_SCB_INTR_TX_NOT_FULL interrupt source is not cleared when the
1414 * TX FIFO has empty entries in the TX FIFO.
1415 * - CY_SCB_INTR_TX_EMPTY interrupt source is not cleared when the
1416 * TX FIFO is empty.
1417 * - CY_SCB_INTR_TX_UNDERFLOW interrupt source is not cleared when the
1418 * TX FIFO is empty. Put data into the TX FIFO before clearing it.
1419 *
1420 *******************************************************************************/
Cy_SCB_ClearTxInterrupt(CySCB_Type * base,uint32_t interruptMask)1421 __STATIC_INLINE void Cy_SCB_ClearTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1422 {
1423 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1424
1425 SCB_INTR_TX(base) = interruptMask;
1426 (void) SCB_INTR_TX(base);
1427 }
1428
1429
1430 /*******************************************************************************
1431 * Function Name: Cy_SCB_SetTxInterrupt
1432 ****************************************************************************//**
1433 *
1434 * Sets TX interrupt sources in the interrupt request register.
1435 *
1436 * \param base
1437 * The pointer to the SCB instance.
1438 *
1439 * \param interruptMask
1440 * The TX interrupt sources to set in the TX interrupt request register.
1441 * See \ref group_scb_common_macros_tx_intr for the set of constants.
1442 *
1443 *******************************************************************************/
Cy_SCB_SetTxInterrupt(CySCB_Type * base,uint32_t interruptMask)1444 __STATIC_INLINE void Cy_SCB_SetTxInterrupt(CySCB_Type *base, uint32_t interruptMask)
1445 {
1446 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK));
1447
1448 SCB_INTR_TX_SET(base) = interruptMask;
1449 }
1450
1451
1452 /*******************************************************************************
1453 * Function Name: Cy_SCB_GetMasterInterruptStatus
1454 ****************************************************************************//**
1455 *
1456 * Returns the master interrupt request register. This register contains the current
1457 * status of the master interrupt sources.
1458 *
1459 * \param base
1460 * The pointer to the SCB instance.
1461 *
1462 * \return
1463 * The current status of the master interrupt sources.
1464 * Each constant is a bit field value. The value returned may have multiple
1465 * bits set to indicate the current status.
1466 * See \ref group_scb_common_macros_master_intr for the set of constants.
1467 *
1468 *******************************************************************************/
Cy_SCB_GetMasterInterruptStatus(CySCB_Type const * base)1469 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatus(CySCB_Type const *base)
1470 {
1471 return (SCB_INTR_M(base) & CY_SCB_MASTER_INTR_MASK);
1472 }
1473
1474
1475 /*******************************************************************************
1476 * Function Name: Cy_SCB_SetMasterInterruptMask
1477 ****************************************************************************//**
1478 *
1479 * Writes the master interrupt mask register. This register specifies which bits
1480 * from the master interrupt request register can trigger an interrupt event.
1481 *
1482 * \param base
1483 * The pointer to the SCB instance.
1484 *
1485 * \param interruptMask
1486 * The master interrupt sources to be enable.
1487 * See \ref group_scb_common_macros_master_intr for the set of constants.
1488 *
1489 *******************************************************************************/
Cy_SCB_SetMasterInterruptMask(CySCB_Type * base,uint32_t interruptMask)1490 __STATIC_INLINE void Cy_SCB_SetMasterInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1491 {
1492 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1493
1494 SCB_INTR_M_MASK(base) = interruptMask;
1495 }
1496
1497
1498 /*******************************************************************************
1499 * Function Name: Cy_SCB_GetMasterInterruptMask
1500 ****************************************************************************//**
1501 *
1502 * Returns the master interrupt mask register. This register specifies which bits
1503 * from the master interrupt request register can trigger an interrupt event.
1504 *
1505 * \param base
1506 * The pointer to the SCB instance.
1507 *
1508 * \return
1509 * Enabled master interrupt sources.
1510 * See \ref group_scb_common_macros_master_intr for the set of constants.
1511 *
1512 *******************************************************************************/
Cy_SCB_GetMasterInterruptMask(CySCB_Type const * base)1513 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptMask(CySCB_Type const *base)
1514 {
1515 return (SCB_INTR_M_MASK(base));
1516 }
1517
1518
1519 /*******************************************************************************
1520 * Function Name: Cy_SCB_GetMasterInterruptStatusMasked
1521 ****************************************************************************//**
1522 *
1523 * Returns the master interrupt masked request register. This register contains a
1524 * logical AND of corresponding bits from the master interrupt request and mask
1525 * registers.
1526 * This function is intended to be used in the interrupt service routine to
1527 * identify which of the enabled master interrupt sources caused the interrupt
1528 * event.
1529 *
1530 * \param base
1531 * The pointer to the SCB instance.
1532 *
1533 * \return
1534 * The current status of enabled master interrupt sources.
1535 * See \ref group_scb_common_macros_master_intr for the set of constants.
1536 *
1537 *******************************************************************************/
Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const * base)1538 __STATIC_INLINE uint32_t Cy_SCB_GetMasterInterruptStatusMasked(CySCB_Type const *base)
1539 {
1540 return (SCB_INTR_M_MASKED(base));
1541 }
1542
1543
1544 /*******************************************************************************
1545 * Function Name: Cy_SCB_ClearMasterInterrupt
1546 ****************************************************************************//**
1547 *
1548 * Clears master interrupt sources in the interrupt request register.
1549 *
1550 * \param base
1551 * The pointer to the SCB instance.
1552 *
1553 * \param interruptMask
1554 * The master interrupt sources to be cleared.
1555 * See \ref group_scb_common_macros_master_intr for the set of constants.
1556 *
1557 *******************************************************************************/
Cy_SCB_ClearMasterInterrupt(CySCB_Type * base,uint32_t interruptMask)1558 __STATIC_INLINE void Cy_SCB_ClearMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
1559 {
1560 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1561
1562 SCB_INTR_M(base) = interruptMask;
1563 (void) SCB_INTR_M(base);
1564 }
1565
1566
1567 /*******************************************************************************
1568 * Function Name: Cy_SCB_SetMasterInterrupt
1569 ****************************************************************************//**
1570 *
1571 * Sets master interrupt sources in the interrupt request register.
1572 *
1573 * \param base
1574 * The pointer to the SCB instance.
1575 *
1576 * \param interruptMask
1577 * The master interrupt sources to set in the master interrupt request register.
1578 * See \ref group_scb_common_macros_master_intr for the set of constants.
1579 *
1580 *******************************************************************************/
Cy_SCB_SetMasterInterrupt(CySCB_Type * base,uint32_t interruptMask)1581 __STATIC_INLINE void Cy_SCB_SetMasterInterrupt(CySCB_Type *base, uint32_t interruptMask)
1582 {
1583 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK));
1584
1585 SCB_INTR_M_SET(base) = interruptMask;
1586 }
1587
1588
1589 /*******************************************************************************
1590 * Function Name: Cy_SCB_GetSlaveInterruptStatus
1591 ****************************************************************************//**
1592 *
1593 * Returns the slave interrupt request register. This register contains the current
1594 * status of the slave interrupt sources.
1595 *
1596 * \param base
1597 * The pointer to the SCB instance.
1598 *
1599 * \return
1600 * The current status of the slave interrupt sources.
1601 * Each constant is a bit field value. The value returned may have multiple
1602 * bits set to indicate the current status.
1603 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1604 *
1605 *******************************************************************************/
Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const * base)1606 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatus(CySCB_Type const *base)
1607 {
1608 return (SCB_INTR_S(base) & CY_SCB_SLAVE_INTR_MASK);
1609 }
1610
1611
1612 /*******************************************************************************
1613 * Function Name: Cy_SCB_SetSlaveInterruptMask
1614 ****************************************************************************//**
1615 *
1616 * Writes slave interrupt mask register.
1617 * This register specifies which bits from the slave interrupt request register
1618 * can trigger an interrupt event.
1619 *
1620 * \param base
1621 * The pointer to the SCB instance.
1622 *
1623 * \param interruptMask
1624 * Enabled slave interrupt sources.
1625 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1626 *
1627 *******************************************************************************/
Cy_SCB_SetSlaveInterruptMask(CySCB_Type * base,uint32_t interruptMask)1628 __STATIC_INLINE void Cy_SCB_SetSlaveInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1629 {
1630 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1631
1632 SCB_INTR_S_MASK(base) = interruptMask;
1633 }
1634
1635
1636 /*******************************************************************************
1637 * Function Name: Cy_SCB_GetSlaveInterruptMask
1638 ****************************************************************************//**
1639 *
1640 * Returns the slave interrupt mask register.
1641 * This register specifies which bits from the slave interrupt request register
1642 * can trigger an interrupt event.
1643 *
1644 * \param base
1645 * The pointer to the SCB instance.
1646 *
1647 * \return
1648 * Enabled slave interrupt sources.
1649 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1650 *
1651 *******************************************************************************/
Cy_SCB_GetSlaveInterruptMask(CySCB_Type const * base)1652 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptMask(CySCB_Type const *base)
1653 {
1654 return (SCB_INTR_S_MASK(base));
1655 }
1656
1657
1658 /*******************************************************************************
1659 * Function Name: Cy_SCB_GetSlaveInterruptStatusMasked
1660 ****************************************************************************//**
1661 *
1662 * Returns the slave interrupt masked request register. This register contains a
1663 * logical AND of corresponding bits from the slave interrupt request and mask
1664 * registers.
1665 * This function is intended to be used in the interrupt service routine to
1666 * identify which of enabled slave interrupt sources caused the interrupt
1667 * event.
1668 *
1669 * \param base
1670 * The pointer to the SCB instance.
1671 *
1672 * \return
1673 * The current status of enabled slave interrupt sources.
1674 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1675 *
1676 *******************************************************************************/
Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const * base)1677 __STATIC_INLINE uint32_t Cy_SCB_GetSlaveInterruptStatusMasked(CySCB_Type const *base)
1678 {
1679 return (SCB_INTR_S_MASKED(base));
1680 }
1681
1682
1683 /*******************************************************************************
1684 * Function Name: Cy_SCB_ClearSlaveInterrupt
1685 ****************************************************************************//**
1686 *
1687 * Clears the slave interrupt sources in the interrupt request register.
1688 *
1689 * \param base
1690 * The pointer to the SCB instance.
1691 *
1692 * \param interruptMask
1693 * Slave interrupt sources to be cleared.
1694 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1695 *
1696 *******************************************************************************/
Cy_SCB_ClearSlaveInterrupt(CySCB_Type * base,uint32_t interruptMask)1697 __STATIC_INLINE void Cy_SCB_ClearSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
1698 {
1699 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1700
1701 SCB_INTR_S(base) = interruptMask;
1702 (void) SCB_INTR_S(base);
1703 }
1704
1705
1706 /*******************************************************************************
1707 * Function Name: Cy_SCB_SetSlaveInterrupt
1708 ****************************************************************************//**
1709 *
1710 * Sets slave interrupt sources in the interrupt request register.
1711 *
1712 * \param base
1713 * The pointer to the SCB instance.
1714 *
1715 * \param interruptMask
1716 * The slave interrupt sources to set in the slave interrupt request register
1717 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1718 *
1719 *******************************************************************************/
Cy_SCB_SetSlaveInterrupt(CySCB_Type * base,uint32_t interruptMask)1720 __STATIC_INLINE void Cy_SCB_SetSlaveInterrupt(CySCB_Type *base, uint32_t interruptMask)
1721 {
1722 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SLAVE_INTR_MASK));
1723
1724 SCB_INTR_S_SET(base) = interruptMask;
1725 }
1726
1727
1728 /*******************************************************************************
1729 * Function Name: Cy_SCB_GetI2CInterruptStatus
1730 ****************************************************************************//**
1731 *
1732 * Returns the I2C interrupt request register. This register contains the
1733 * current status of the I2C interrupt sources.
1734 *
1735 * \param base
1736 * The pointer to the SCB instance.
1737 *
1738 * \return
1739 * The current status of the I2C interrupt sources. Each constant is a bit
1740 * field value.
1741 * The value returned may have multiple bits set to indicate the current status.
1742 * See \ref group_scb_common_macros_slave_intr for the set of constants.
1743 *
1744 *******************************************************************************/
Cy_SCB_GetI2CInterruptStatus(CySCB_Type const * base)1745 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatus(CySCB_Type const *base)
1746 {
1747 return (SCB_INTR_I2C_EC(base) & CY_SCB_I2C_INTR_MASK);
1748 }
1749
1750
1751 /*******************************************************************************
1752 * Function Name: Cy_SCB_SetI2CInterruptMask
1753 ****************************************************************************//**
1754 *
1755 * Writes the I2C interrupt mask register. This register specifies which bits
1756 * from the I2C interrupt request register can trigger an interrupt event.
1757 *
1758 * \param base
1759 * The pointer to the SCB instance.
1760 *
1761 * \param interruptMask
1762 * Enabled I2C interrupt sources.
1763 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1764 *
1765 *******************************************************************************/
Cy_SCB_SetI2CInterruptMask(CySCB_Type * base,uint32_t interruptMask)1766 __STATIC_INLINE void Cy_SCB_SetI2CInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1767 {
1768 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
1769
1770 SCB_INTR_I2C_EC_MASK(base) = interruptMask;
1771 }
1772
1773
1774 /*******************************************************************************
1775 * Function Name: Cy_SCB_GetI2CInterruptMask
1776 ****************************************************************************//**
1777 *
1778 * Returns the I2C interrupt mask register. This register specifies which bits
1779 * from the I2C interrupt request register can trigger an interrupt event.
1780 *
1781 * \param base
1782 * The pointer to the SCB instance.
1783 *
1784 * \return
1785 * Enabled I2C interrupt sources.
1786 * See \ref group_scb_common_macros_i2c_intr.
1787 *
1788 *******************************************************************************/
Cy_SCB_GetI2CInterruptMask(CySCB_Type const * base)1789 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptMask(CySCB_Type const *base)
1790 {
1791 return (SCB_INTR_I2C_EC_MASK(base));
1792 }
1793
1794
1795 /*******************************************************************************
1796 * Function Name: Cy_SCB_GetI2CInterruptStatusMasked
1797 ****************************************************************************//**
1798 *
1799 * Returns the I2C interrupt masked request register. This register contains
1800 * a logical AND of corresponding bits from I2C interrupt request and mask
1801 * registers.
1802 * This function is intended to be used in the interrupt service routine to
1803 * identify which of enabled I2C interrupt sources caused the interrupt event.
1804 *
1805 * \param base
1806 * The pointer to the SCB instance.
1807 *
1808 * \return
1809 * The current status of enabled I2C interrupt sources.
1810 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1811 *
1812 *******************************************************************************/
Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const * base)1813 __STATIC_INLINE uint32_t Cy_SCB_GetI2CInterruptStatusMasked(CySCB_Type const *base)
1814 {
1815 return (SCB_INTR_I2C_EC_MASKED(base));
1816 }
1817
1818
1819 /*******************************************************************************
1820 * Function Name: Cy_SCB_ClearI2CInterrupt
1821 ****************************************************************************//**
1822 *
1823 * Clears I2C interrupt sources in the interrupt request register.
1824 *
1825 * \param base
1826 * The pointer to the SCB instance.
1827 *
1828 * \param interruptMask
1829 * The I2C interrupt sources to be cleared.
1830 * See \ref group_scb_common_macros_i2c_intr for the set of constants.
1831 *
1832 *******************************************************************************/
Cy_SCB_ClearI2CInterrupt(CySCB_Type * base,uint32_t interruptMask)1833 __STATIC_INLINE void Cy_SCB_ClearI2CInterrupt(CySCB_Type *base, uint32_t interruptMask)
1834 {
1835 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_I2C_INTR_MASK));
1836
1837 SCB_INTR_I2C_EC(base) = interruptMask;
1838 (void) SCB_INTR_I2C_EC(base);
1839 }
1840
1841
1842 /*******************************************************************************
1843 * Function Name: Cy_SCB_GetSpiInterruptStatus
1844 ****************************************************************************//**
1845 *
1846 * Returns the SPI interrupt request register. This register contains the current
1847 * status of the SPI interrupt sources.
1848 *
1849 * \param base
1850 * The pointer to the SCB instance.
1851 *
1852 * \return
1853 * The current status of SPI interrupt sources. Each constant is a bit field value.
1854 * The value returned may have multiple bits set to indicate the current status
1855 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1856 *
1857 *******************************************************************************/
Cy_SCB_GetSpiInterruptStatus(CySCB_Type const * base)1858 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatus(CySCB_Type const *base)
1859 {
1860 return (SCB_INTR_SPI_EC(base) & CY_SCB_SPI_INTR_MASK);
1861 }
1862
1863
1864 /*******************************************************************************
1865 * Function Name: Cy_SCB_SetSpiInterruptMask
1866 ****************************************************************************//**
1867 *
1868 * Writes the SPI interrupt mask register. This register specifies which
1869 * bits from the SPI interrupt request register can trigger an interrupt event.
1870 *
1871 * \param base
1872 * The pointer to the SCB instance.
1873 *
1874 * \param interruptMask
1875 * Enabled SPI interrupt sources.
1876 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1877 *
1878 *******************************************************************************/
Cy_SCB_SetSpiInterruptMask(CySCB_Type * base,uint32_t interruptMask)1879 __STATIC_INLINE void Cy_SCB_SetSpiInterruptMask(CySCB_Type *base, uint32_t interruptMask)
1880 {
1881 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
1882
1883 SCB_INTR_SPI_EC_MASK(base) = interruptMask;
1884 }
1885
1886
1887 /*******************************************************************************
1888 * Function Name: Cy_SCB_GetSpiInterruptMask
1889 ****************************************************************************//**
1890 *
1891 * Returns the SPI interrupt mask register. This register specifies which bits
1892 * from the SPI interrupt request register can trigger an interrupt event.
1893 *
1894 * \param base
1895 * The pointer to the SCB instance.
1896 *
1897 * \return
1898 * Enabled SPI interrupt sources.
1899 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1900 *
1901 *******************************************************************************/
Cy_SCB_GetSpiInterruptMask(CySCB_Type const * base)1902 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptMask(CySCB_Type const *base)
1903 {
1904 return (SCB_INTR_SPI_EC_MASK(base));
1905 }
1906
1907
1908 /*******************************************************************************
1909 * Function Name: Cy_SCB_GetSpiInterruptStatusMasked
1910 ****************************************************************************//**
1911 *
1912 * Returns the SPI interrupt masked request register. This register contains
1913 * a logical AND of corresponding bits from the SPI interrupt request and
1914 * mask registers.
1915 * This function is intended to be used in the interrupt service routine to
1916 * identify which of enabled SPI interrupt sources caused the interrupt event.
1917 *
1918 * \param base
1919 * The pointer to the SCB instance.
1920 *
1921 * \return
1922 * The current status of enabled SPI interrupt sources.
1923 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1924 *
1925 *******************************************************************************/
Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const * base)1926 __STATIC_INLINE uint32_t Cy_SCB_GetSpiInterruptStatusMasked(CySCB_Type const *base)
1927 {
1928 return (SCB_INTR_SPI_EC_MASKED(base));
1929 }
1930
1931
1932 /*******************************************************************************
1933 * Function Name: Cy_SCB_ClearSpiInterrupt
1934 ****************************************************************************//**
1935 *
1936 * Clears SPI interrupt sources in the interrupt request register.
1937 *
1938 * \param base
1939 * The pointer to the SCB instance.
1940 *
1941 * \param interruptMask
1942 * The SPI interrupt sources to be cleared.
1943 * See \ref group_scb_common_macros_SpiIntrStatuses for the set of constants.
1944 *
1945 *******************************************************************************/
Cy_SCB_ClearSpiInterrupt(CySCB_Type * base,uint32_t interruptMask)1946 __STATIC_INLINE void Cy_SCB_ClearSpiInterrupt(CySCB_Type *base, uint32_t interruptMask)
1947 {
1948 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_SPI_INTR_MASK));
1949
1950 SCB_INTR_SPI_EC(base) = interruptMask;
1951 (void) SCB_INTR_SPI_EC(base);
1952 }
1953
1954 /** \cond INTERNAL */
1955 /*******************************************************************************
1956 * Function Name: Cy_SCB_GetFifoSize
1957 ****************************************************************************//**
1958 *
1959 * Returns the RX and TX FIFO depth.
1960 *
1961 * \param base
1962 * The pointer to the SCB instance.
1963 *
1964 * \return
1965 * FIFO depth.
1966 *
1967 *******************************************************************************/
Cy_SCB_GetFifoSize(CySCB_Type const * base)1968 __STATIC_INLINE uint32_t Cy_SCB_GetFifoSize(CySCB_Type const *base)
1969 {
1970 #if((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB))
1971 {return (((uint32_t)(CY_SCB_FIFO_SIZE)) >> _FLD2VAL(SCB_CTRL_MEM_WIDTH, SCB_CTRL(base)));}
1972 #elif(defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION==1))
1973 {return (_FLD2BOOL(SCB_CTRL_BYTE_MODE, SCB_CTRL(base)) ? (CY_SCB_FIFO_SIZE) : (CY_SCB_FIFO_SIZE / 2UL));}
1974 #else
1975 return 0;
1976 #endif /* ((CY_IP_MXSCB_VERSION>=2) || defined (CY_IP_MXS22SCB)) */
1977
1978 }
1979
1980
1981 /*******************************************************************************
1982 * Function Name: Cy_SCB_IsRxDataWidthByte
1983 ****************************************************************************//**
1984 *
1985 * Returns true if the RX data width is a byte (8 bits).
1986 *
1987 * \param base
1988 * The pointer to the SCB instance.
1989 *
1990 * \return
1991 * True if the RX data width is a byte (8 bits).
1992 *
1993 *******************************************************************************/
Cy_SCB_IsRxDataWidthByte(CySCB_Type const * base)1994 __STATIC_INLINE bool Cy_SCB_IsRxDataWidthByte(CySCB_Type const *base)
1995 {
1996 return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
1997 }
1998
1999 /** \endcond */
2000
2001 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
2002 /*******************************************************************************
2003 * Function Name: Cy_SCB_Get_RxDataWidth
2004 ****************************************************************************//**
2005 *
2006 * Returns the RX data width.
2007 *
2008 * \param base
2009 * The pointer to the SCB instance.
2010 *
2011 * \return
2012 * RX data width.
2013 *
2014 *
2015 * \note
2016 * This API is available for CAT1B devices.
2017 *
2018 *******************************************************************************/
Cy_SCB_Get_RxDataWidth(CySCB_Type const * base)2019 __STATIC_INLINE uint32_t Cy_SCB_Get_RxDataWidth(CySCB_Type const *base)
2020 {
2021 return (_FLD2VAL(SCB_RX_CTRL_DATA_WIDTH, SCB_RX_CTRL(base)) + 1UL);
2022 }
2023 #endif /* CY_IP_MXSCB_VERSION */
2024
2025 /*******************************************************************************
2026 * Function Name: Cy_SCB_IsTxDataWidthByte
2027 ****************************************************************************//**
2028 *
2029 * Returns true if the TX data width is a byte (8 bits).
2030 *
2031 * \param base
2032 * The pointer to the SCB instance.
2033 *
2034 * \return
2035 * If true, the TX data width is a byte (8 bits). Otherwise, false.
2036 *
2037 *******************************************************************************/
Cy_SCB_IsTxDataWidthByte(CySCB_Type const * base)2038 __STATIC_INLINE bool Cy_SCB_IsTxDataWidthByte(CySCB_Type const *base)
2039 {
2040 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) < CY_SCB_BYTE_WIDTH);
2041 }
2042
2043 #if(((defined (CY_IP_MXSCB_VERSION) && (CY_IP_MXSCB_VERSION>=2)) || defined (CY_IP_MXS22SCB)) || defined (CY_DOXYGEN))
2044 /*******************************************************************************
2045 * Function Name: Cy_SCB_Get_TxDataWidth
2046 ****************************************************************************//**
2047 *
2048 * Returns the TX data width.
2049 *
2050 * \param base
2051 * The pointer to the SCB instance.
2052 *
2053 * \return
2054 * The TX data width.
2055 *
2056 *
2057 * \note
2058 * This API is available for CAT1B devices.
2059 *
2060 *******************************************************************************/
Cy_SCB_Get_TxDataWidth(CySCB_Type const * base)2061 __STATIC_INLINE uint32_t Cy_SCB_Get_TxDataWidth(CySCB_Type const *base)
2062 {
2063 return (_FLD2VAL(SCB_TX_CTRL_DATA_WIDTH, SCB_TX_CTRL(base)) + 1UL);
2064 }
2065 #endif /* CY_IP_MXSCB_VERSION */
2066
2067 /** \cond INTERNAL */
2068
2069 /*******************************************************************************
2070 * Function Name: Cy_SCB_FwBlockReset
2071 ****************************************************************************//**
2072 *
2073 * Disables and enables the block to return it into the known state (default):
2074 * FIFOs and interrupt statuses are cleared.
2075 *
2076 * \param base
2077 * The pointer to the SCB instance.
2078 *
2079 *******************************************************************************/
Cy_SCB_FwBlockReset(CySCB_Type * base)2080 __STATIC_INLINE void Cy_SCB_FwBlockReset(CySCB_Type *base)
2081 {
2082 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk;
2083
2084 /* Clean-up command registers */
2085 SCB_I2C_M_CMD(base) = 0UL;
2086 SCB_I2C_S_CMD(base) = 0UL;
2087
2088 SCB_CTRL(base) |= (uint32_t) SCB_CTRL_ENABLED_Msk;
2089
2090 (void) SCB_CTRL(base);
2091 }
2092
2093
2094 /*******************************************************************************
2095 * Function Name: Cy_SCB_GetRxFifoLevel
2096 ****************************************************************************//**
2097 *
2098 * Returns the RX FIFO level when there are more words in the RX FIFO than the
2099 * level, the RX FIFO level interrupt is triggered.
2100 *
2101 * \param base
2102 * The pointer to the SCB instance.
2103 *
2104 * \return
2105 * RX FIFO level.
2106 *
2107 *******************************************************************************/
Cy_SCB_GetRxFifoLevel(CySCB_Type const * base)2108 __STATIC_INLINE uint32_t Cy_SCB_GetRxFifoLevel(CySCB_Type const *base)
2109 {
2110 return _FLD2VAL(SCB_RX_FIFO_CTRL_TRIGGER_LEVEL, SCB_RX_FIFO_CTRL(base));
2111 }
2112
2113 /** \endcond */
2114 /** \} group_scb_common_functions */
2115
2116 #if defined(__cplusplus)
2117 }
2118 #endif
2119
2120 /** \} group_scb_common */
2121
2122 #endif /* (defined (CY_IP_MXSCB) || defined (CY_IP_MXS22SCB)) */
2123
2124 #endif /* (CY_SCB_COMMON_H) */
2125
2126 /* [] END OF FILE */
2127
