1 /***************************************************************************//**
2 * \file cy_sar.h
3 * \version 2.10
4 *
5 * Header file for the SAR driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2017-2021 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24
25 /**
26 * \addtogroup group_sar
27 * \{
28 * This driver configures and controls the SAR ADC subsystem block, which is a
29 * part of \ref group_pass_structure "PASS" hardware block.
30 *
31 * The functions and other declarations used in this driver are in cy_sar.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * This SAR ADC block is comprised of:
36 * - a 12-bit SAR converter (SARADC)
37 * - an embedded reference block (SARREF)
38 * - a mux (\ref group_sar_sarmux "SARMUX") at the inputs of the converter
39 * - a sequence controller (\ref group_sar_sarmux "SARSEQ") that enables multi-channel acquisition
40 * in a round robin fashion, without CPU intervention, to maximize scan rates.
41 *
42 * Devices with PASS_v2 hardware block may contain multiple SAR ADC blocks.
43 *
44 * \image html sar_block_diagram.png
45 *
46 * The high level features of the subsystem are:
47 * - maximum sample rate of 1 Msps (2 Msps for devices with PASS_v2 hardware block)
48 * - sixteen individually configurable channels (depends on device routing capabilities)
49 * - per channel selectable
50 * - single-ended or differential input mode
51 * - input from external pin (8 channels in single-ended mode or 4 channels in differential mode)
52 * or from internal signals (AMUXBUS, CTB, Die Temperature Sensor)
53 * - choose one of four programmable acquisition times
54 * - averaging and accumulation
55 * - scan can be triggered by firmware or hardware in single shot or continuous mode
56 * - hardware averaging from 2 to 256 samples
57 * - selectable voltage references
58 * - internal VDDA and VDDA/2 references
59 * - buffered 1.2 V bandgap reference from \ref group_sysanalog_aref "AREF"
60 * - external reference from dedicated pin
61 * - interrupt generation
62 * - built-in FIFO buffer (PASS_v2 only)
63 * - ability to perform scans in Deep Sleep power mode (PASS_v2 only).
64 *
65 * \section group_sar_usage Usage
66 *
67 * The high level steps to use this driver are:
68 *
69 * -# \ref group_sar_initialization
70 * -# \ref group_sar_trigger_conversions
71 * -# \ref group_sar_handle_interrupts
72 * -# \ref group_sar_retrieve_result
73 * -# \ref group_sar_fifo_usage
74 *
75 * \section group_sar_initialization Initialization and Enable
76 *
77 * To configure the SAR subsystem, call \ref Cy_SAR_Init. Pass in a pointer to the \ref SAR_Type
78 * structure for the base hardware register address and pass in the configuration structure,
79 * \ref cy_stc_sar_config_t.
80 *
81 * \note Make sure to choose correct hardware identifiers, taking into account the indexing in the used device:
82 * \snippet sar/snippet/main.c SNIPPET_SAR_HW_COMPATIBILITY
83 *
84 *
85 * After initialization, call \ref Cy_SAR_Enable to enable the hardware.
86 *
87 * Here is guidance on how to set the data fields of the configuration structure:
88 *
89 * \subsection group_sar_init_struct_ctrl uint32_t ctrl
90 *
91 * This field specifies configurations that apply to all channels such as the Vref
92 * source or the negative terminal selection for all single-ended channels.
93 * Select a value from each of the following enums that begin with "cy_en_sar_ctrl_" and "OR" them together.
94 * - \ref cy_en_sar_ctrl_pwr_ctrl_vref_t
95 * - \ref cy_en_sar_ctrl_vref_sel_t
96 * - \ref cy_en_sar_ctrl_bypass_cap_t
97 * - \ref cy_en_sar_ctrl_neg_sel_t
98 * - \ref cy_en_sar_ctrl_hw_ctrl_negvref_t
99 * - \ref cy_en_sar_ctrl_comp_delay_t
100 * - \ref cy_en_sar_ctrl_comp_pwr_t
101 * - \ref cy_en_sar_ctrl_sarmux_deep_sleep_t
102 * - \ref cy_en_sar_ctrl_sarseq_routing_switches_t
103 *
104 * \snippet sar/snippet/main.c SNIPPET_CTRL
105 *
106 * \subsection group_sar_init_struct_sampleCtrl uint32_t sampleCtrl
107 *
108 * This field configures sampling details that apply to all channels.
109 * Select a value from each of the following enums that begin with "cy_en_sar_sample_" and "OR" them together.
110 * - \ref cy_en_sar_sample_ctrl_result_align_t
111 * - \ref cy_en_sar_sample_ctrl_single_ended_format_t
112 * - \ref cy_en_sar_sample_ctrl_differential_format_t
113 * - \ref cy_en_sar_sample_ctrl_avg_cnt_t
114 * - \ref cy_en_sar_sample_ctrl_avg_mode_t
115 * - \ref cy_en_sar_sample_ctrl_trigger_mode_t
116 *
117 * \snippet sar/snippet/main.c SNIPPET_SAR_SAMPLE_CTRL
118 *
119 * \subsection group_sar_init_struct_sampleTime01 uint32_t sampleTime01
120 *
121 * This field configures the value for sample times 0 and 1 in ADC clock cycles.
122 *
123 * The SAR has four programmable 10-bit aperture times that are configured using two data fields,
124 * \ref group_sar_init_struct_sampleTime01 and
125 * \ref group_sar_init_struct_sampleTime23.
126 * Ten bits allow for a range of 0 to 1023 cycles, however 0 and 1 are invalid.
127 * The minimum aperture time is 167 ns. With an 18 MHz ADC clock, this is
128 * equal to 3 cycles or a value of 4 in this field. The actual aperture time is one cycle less than
129 * the value stored in this field.
130 *
131 * Use the shifts defined in \ref cy_en_sar_sample_time_shift_t.
132 *
133 * \snippet sar/snippet/main.c SNIPPET_SAR_SAMPLE_TIME01
134 *
135 * \subsection group_sar_init_struct_sampleTime23 uint32_t sampleTime23
136 *
137 * This field configures the value for sample times 2 and 3 in ADC clock cycles.
138 * Use the shifts defined in \ref cy_en_sar_sample_time_shift_t.
139 *
140 * \snippet sar/snippet/main.c SNIPPET_SAR_SAMPLE_TIME23
141 *
142 * \subsection group_sar_init_struct_rangeThres uint32_t rangeThres
143 *
144 * This field configures the upper and lower thresholds for the range interrupt.
145 * These thresholds apply on a global level for all channels with range detection enabled.
146 *
147 * The SARSEQ supports range detection to allow for automatic detection of sample values
148 * compared to two programmable thresholds without CPU involvement.
149 * Range detection is done after averaging, alignment, and sign extension (if applicable). In other words the
150 * threshold values need to have the same data format as the result data.
151 * The values are interpreted as signed or unsigned according to each channel's configuration.
152 *
153 * Use the shifts defined in \ref cy_en_sar_range_thres_shift_t.
154 *
155 * The \ref Cy_SAR_SetLowLimit and \ref Cy_SAR_SetHighLimit provide run-time configurability of these thresholds.
156 *
157 * \snippet sar/snippet/main.c SNIPPET_SAR_RANGE_THRES
158 *
159 * \subsection group_sar_init_struct_rangeCond cy_en_sar_range_detect_condition_t rangeCond
160 *
161 * This field configures the condition (below, inside, outside, or above) that will trigger
162 * the range interrupt. Select a value from the \ref cy_en_sar_range_detect_condition_t enum.
163 *
164 * \subsection group_sar_init_struct_chanEn uint32_t chanEn
165 *
166 * This field configures which channels will be scanned.
167 * Each bit corresponds to a channel. Bit 0 enables channel 0, bit 1 enables channel 1,
168 * bit 2 enables channel 2, and so on.
169 *
170 * \subsection group_sar_init_struct_chanConfig uint32_t chanConfig[16]
171 *
172 * Each channel has its own channel configuration register.
173 * The channel configuration specifies which pin/signal is connected to that channel
174 * and how the channel is sampled.
175 *
176 * Select a value from each of the following enums that begin with "cy_en_sar_chan_config_" and "OR" them together.
177 *
178 * - \ref cy_en_sar_chan_config_input_mode_t
179 * - \ref cy_en_sar_chan_config_pos_pin_addr_t
180 * - \ref cy_en_sar_chan_config_pos_port_addr_t
181 * - \ref cy_en_sar_chan_config_avg_en_t
182 * - \ref cy_en_sar_chan_config_sample_time_t
183 * - \ref cy_en_sar_chan_config_neg_pin_addr_t
184 * - \ref cy_en_sar_chan_config_neg_port_addr_t
185 *
186 * Some important considerations are:
187 * - The POS_PORT_ADDR and POS_PIN_ADDR bit fields are used by the SARSEQ to select
188 * the connection to the positive terminal (Vplus) of the ADC for each channel.
189 * - When the channel is an unpaired differential input (\ref CY_SAR_CHAN_DIFFERENTIAL_UNPAIRED), the
190 * NEG_PORT_ADDR and NEG_PIN_ADDR are used by the SARSEQ to select the connection
191 * to the negative terminal (Vminus) of the ADC.
192 * - When the channel is a differential input pair (\ref CY_SAR_CHAN_DIFFERENTIAL_PAIRED), the NEG_PORT_ADDR and NEG_PIN_ADDR are ignored.
193 * For differential input pairs, only the pin for the positive terminal needs to be
194 * specified and this pin must be even. For example, Pin 0 (positive terminal) and Pin 1 (negative terminal)
195 * are a pair. Pin 2 (positive terminal) and Pin 3 (negative terminal) are a pair.
196 *
197 * If the SARSEQ is disabled (\ref cy_en_sar_ctrl_sarseq_routing_switches_t) or
198 * it is not controlling any switches (\ref group_sar_init_struct_muxSwitchSqCtrl = 0), the port and pin addresses
199 * are ignored. This is possible when there is only one channel to scan.
200 *
201 * \snippet sar/snippet/main.c SNIPPET_SAR_CHAN_CONFIG
202 *
203 * \subsection group_sar_init_struct_intrMask uint32_t intrMask
204 *
205 * This field configures which interrupt events (end of scan, overflow, or firmware collision) will be serviced by the firmware.
206 *
207 * Select one or more values from the \ref group_sar_macros_interrupt enum and "OR" them
208 * together.
209 *
210 * \snippet sar/snippet/main.c SNIPPET_SAR_INTR_MASK
211 *
212 * \subsection group_sar_init_struct_satIntrMask uint32_t satIntrMask
213 *
214 * This field configures which channels will cause a saturation interrupt.
215 *
216 * The SARSEQ has a saturation detect that is always applied to every conversion.
217 * This feature detects whether a channel's sample value is equal to the minimum or maximum values.
218 * This allows the firmware to take action, for example, discard the result, when the SARADC saturates.
219 * The sample value is tested right after conversion, that is, before averaging. This means that it
220 * can happen that the interrupt is set while the averaged result in the data register is not
221 * equal to the minimum or maximum.
222 *
223 * Each bit corresponds to a channel. A value of 0 disables saturation detection for all channels.
224 *
225 * \subsection group_sar_init_struct_rangeIntrMask uint32_t rangeIntrMask
226 *
227 * This field configures which channels will cause a range detection interrupt.
228 * Each bit corresponds to a channel. A value of 0 disables range detection for all channels.
229 *
230 * \subsection group_sar_init_struct_muxSwitch uint32_t muxSwitch
231 *
232 * This field is the firmware control of the SARMUX switches.
233 *
234 * Use one or more values from the \ref cy_en_sar_mux_switch_fw_ctrl_t enum and "OR" them together.
235 * If the SARSEQ is enabled, the SARMUX switches that will be used must
236 * also be closed using this firmware control.
237 *
238 * \snippet sar/snippet/main.c SNIPPET_SAR_MUX_SWITCH
239 *
240 * Firmware control can be changed at run-time by calling \ref Cy_SAR_SetAnalogSwitch with \ref CY_SAR_MUX_SWITCH0
241 * and the desired switch states.
242 *
243 * \subsection group_sar_init_struct_muxSwitchSqCtrl uint32_t muxSwitchSqCtrl
244 *
245 * This field enables or disables SARSEQ control of the SARMUX switches.
246 * To disable control of all switches, set this field to 0. To disable the SARSEQ all together,
247 * use \ref CY_SAR_SARSEQ_SWITCH_DISABLE when configuring the \ref group_sar_init_struct_ctrl register.
248 *
249 * Use one or more values from the \ref cy_en_sar_mux_switch_sq_ctrl_t enum and "OR" them together.
250 *
251 * \snippet sar/snippet/main.c SNIPPET_SAR_MUX_SQ_CTRL
252 *
253 * SARSEQ control can be changed at run-time by calling \ref Cy_SAR_SetSwitchSarSeqCtrl.
254 *
255 * \subsection group_sar_init_struct_configRouting bool configRouting
256 *
257 * If true, the \ref group_sar_init_struct_muxSwitch and \ref group_sar_init_struct_muxSwitchSqCtrl fields
258 * will be used. If false, the fields will be ignored.
259 *
260 * \subsection group_sar_init_struct_vrefMvValue uint32_t vrefMvValue
261 *
262 * This field sets the value of the reference voltage in millivolts used. This value
263 * is used for converting counts to volts in the \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts, and
264 * \ref Cy_SAR_CountsTo_uVolts functions.
265 *
266 * The rest of the \ref cy_stc_sar_config_t fields starting from \ref cy_stc_sar_config_t::clock affects
267 * SAR ADC configuration only for PASS_ver2. Refer to \ref cy_stc_sar_config_t for details.
268 *
269 * \section group_sar_trigger_conversions Triggering Conversions
270 *
271 * The SAR subsystem has the following modes for triggering a conversion:
272 * <table class="doxtable">
273 * <tr>
274 * <th>Mode</th>
275 * <th>Description</th>
276 * <th>Usage</th>
277 * </tr>
278 * <tr>
279 * <td>Continuous</td>
280 * <td>After completing a scan, the
281 * SARSEQ will immediately start the next scan. That is, the SARSEQ will always be BUSY.
282 * As a result all other triggers, firmware or hardware, are essentially ignored.
283 * </td>
284 * <td>To enter this mode, call \ref Cy_SAR_StartConvert with \ref CY_SAR_START_CONVERT_CONTINUOUS.
285 * To stop continuous conversions, call \ref Cy_SAR_StopConvert.
286 * </td>
287 * </tr>
288 * <tr>
289 * <td>Firmware single shot</td>
290 * <td>A single conversion of all enabled channels is triggered with a function call to \ref Cy_SAR_StartConvert with
291 * \ref CY_SAR_START_CONVERT_SINGLE_SHOT.
292 * </td>
293 * <td>
294 * Firmware triggering is always available by calling \ref Cy_SAR_StartConvert with \ref CY_SAR_START_CONVERT_SINGLE_SHOT.
295 * To allow only firmware triggering, or disable
296 * hardware triggering, set up the \ref cy_stc_sar_config_t config structure with \ref CY_SAR_TRIGGER_MODE_FW_ONLY.
297 * </td>
298 * </tr>
299 * <tr>
300 * <td>Hardware edge sensitive</td>
301 * <td>A single conversion of all enabled channels is triggered on the rising edge of the hardware
302 * trigger signal.</td>
303 * <td>To enable this mode, set up the \ref cy_stc_sar_config_t config structure with
304 * \ref CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE.</td>
305 * </tr>
306 * <tr>
307 * <td>Hardware level sensitive</td>
308 * <td>Conversions are triggered continuously when the hardware trigger signal is high.</td>
309 * <td>To enable this mode, set up the \ref cy_stc_sar_config_t config structure with
310 * \ref CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL.</td>
311 * </tr>
312 * </table>
313 *
314 * If trigger occurs during a scan, a \ref CY_SAR_INTR_FW_COLLISION interrupt occurs and the trigger is delayed until after end of scan.
315 *
316 * The trigger mode can be changed during run time with \ref Cy_SAR_SetConvertMode.
317 *
318 * For the hardware trigger modes, use the \ref group_trigmux driver to route an internal or external
319 * signal to the SAR trigger input.
320 * When making the required \ref Cy_TrigMux_Connect calls, use the pre-defined enum, TRIG6_OUT_PASS_TR_SAR_IN,
321 * for the SAR trigger input.
322 *
323 * \snippet sar/snippet/main.c SNIPPET_SAR_CONFIG_TRIGGER
324 *
325 * \section group_sar_handle_interrupts Handling Interrupts
326 *
327 * The SAR can generate interrupts on these events:
328 *
329 * - End of scan (EOS): when scanning of all enabled channels complete.
330 * - Overflow: when the result register is updated before the previous result is read.
331 * - FW collision: when a new trigger is received while the SAR is still processing the previous trigger.
332 * - Saturation detection: when the channel result is equal to the minimum or maximum value.
333 * - Range detection: when the channel result meets the programmed upper or lower threshold values.
334 *
335 * The SAR interrupt to the NVIC is raised any time the intersection (logic and) of the interrupt
336 * flags and the corresponding interrupt masks are non-zero.
337 *
338 * Implement an interrupt routine and assign it to the SAR interrupt.
339 * Use the pre-defined enum, pass_interrupt_sar_IRQn, as the interrupt source for the SAR.
340 *
341 * The following code snippet demonstrates how to implement a routine to handle the interrupt.
342 * The routine gets called when any one of the SAR interrupts are triggered.
343 * When servicing an interrupt, the user must clear the interrupt so that subsequent
344 * interrupts can be handled.
345 *
346 * \snippet sar/snippet/main.c SNIPPET_SAR_ISR
347 *
348 * The following code snippet demonstrates how to configure and enable the interrupt.
349 *
350 * \snippet sar/snippet/main.c SNIPPET_SAR_CONFIG_INTR
351 *
352 * Alternately, instead of handling the interrupts, the \ref Cy_SAR_IsEndConversion function
353 * allows for firmware polling of the end of conversion status.
354 *
355 * \section group_sar_retrieve_result Retrieve Channel Results
356 *
357 * Retrieve the ADC result by calling \ref Cy_SAR_GetResult16 with the desired channel.
358 * To convert the result to a voltage, pass the ADC result to \ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts, or
359 * \ref Cy_SAR_CountsTo_uVolts.
360 *
361 * \section group_sar_fifo_usage FIFO Usage
362 *
363 * The PASS_ver2 SAR can operate in the system Deep Sleep power mode.
364 * To do so the SAR should be clocked by the \ref group_sysanalog_dpslp,
365 * triggered by the \ref group_sysanalog_timer, and use the FIFO:
366 * \snippet sar/snippet/main.c SNIPPET_FIFO_ISR
367 * \snippet sar/snippet/main.c SNIPPET_FIFO_OPERATE
368 *
369 * \section group_sar_clock SAR Clock Configuration
370 *
371 * The SAR requires a clock. Assign a clock to the SAR using the
372 * pre-defined enum, PCLK_PASS_CLOCK_SAR, to identify the SAR subsystem.
373 * Set the clock divider value to achieve the desired clock rate. The SAR can support
374 * a maximum frequency of 18 MHz.
375 *
376 * For PASS_ver2 the maximum clock frequency is 36 MHz.
377 * Also, the SAR clock could be switched to the \ref group_sysanalog_dpslp to operate in
378 * the system Deep Sleed power mode using \ref cy_stc_sar_config_t::clock.
379 *
380 * \snippet sar/snippet/main.c SAR_SNIPPET_CONFIGURE_CLOCK
381 *
382 * \section group_sar_scan_time Scan Rate
383 *
384 * The scan rate is dependent on the following:
385 *
386 * - ADC clock rate
387 * - Number of channels
388 * - Averaging
389 * - Resolution
390 * - Acquisition times
391 *
392 * \subsection group_sar_acquisition_time Acquisition Time
393 *
394 * The acquisition time of a channel is based on which of the four global aperture times are selected for that
395 * channel. The selection is done during initialization per channel with \ref group_sar_init_struct_chanConfig.
396 * The four global aperture times are also set during initialization with \ref group_sar_init_struct_sampleTime01 and
397 * \ref group_sar_init_struct_sampleTime23. Note that these global aperture times are in SAR clock cycles and the
398 * acquisition time is 1 less than that value in the register.
399 *
400 * \image html sar_acquisition_time_eqn.png
401 *
402 * \subsection group_sar_channel_sample_time Channel Sample Time
403 *
404 * The sample time for a channel is the time required to acquire the analog signal
405 * and convert it to a digital code.
406 *
407 * \image html sar_channel_sample_time_eqn.png
408 *
409 * The SAR ADC is a 12-bit converter so Resolution = 12.
410 *
411 * \subsection group_sar_total_scan_time Total Scan Time
412 *
413 * Channels using one of the sequential averaging modes (\ref CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM or \ref CY_SAR_AVG_MODE_SEQUENTIAL_FIXED)
414 * are sampled multiple times per scan. The number of samples averaged are set during initialization
415 * with \ref group_sar_init_struct_sampleCtrl using one of the values from \ref cy_en_sar_sample_ctrl_avg_cnt_t.
416 * Channels that are not averaged or use the \ref CY_SAR_AVG_MODE_INTERLEAVED mode are only sampled once per scan.
417 *
418 * The total scan time is the sum of each channel's sample time multiplied by the samples per scan.
419 *
420 * \image html sar_scan_rate_eqn.png
421 *
422 * where N is the total number of channels in the scan.
423 *
424 * \section group_sar_sarmux SARMUX and SARSEQ
425 *
426 * The SARMUX is an analog programmable multiplexer. Its switches can be controlled by the SARSEQ or firmware.
427 * and the inputs can come from:
428 * - a dedicated port (can support 8 single-ended channels or 4 differential channels)
429 * - an internal die temperature (DieTemp) sensor
430 * - CTB output via SARBUS0/1 (if CTBs are available on the device)
431 * - AMUXBUSA/B
432 *
433 * The following figure shows the SARMUX switches. See the device datasheet for the exact location of SARMUX pins.
434 *
435 * \image html sar_sarmux_switches.png
436 *
437 * When using the SARSEQ, the following configurations must be performed:
438 * - enable SARSEQ control of required switches (see \ref group_sar_init_struct_muxSwitchSqCtrl)
439 * - close the required switches with firmware (see \ref group_sar_init_struct_muxSwitch)
440 * - configure the POS_PORT_ADDR and POS_PIN_ADDR, and if used, the NEG_PORT_ADDR and NEG_PIN_ADDR (see \ref group_sar_init_struct_chanConfig)
441 *
442 * While firmware can control every switch in the SARMUX, not every switch can be controlled by the SARSEQ (green switches in the above figure).
443 * Additionally, switches outside of the SARMUX such as the AMUXBUSA/B switches or
444 * CTB switches will require separate function calls (see \ref group_gpio "GPIO" and \ref group_ctb "CTB" drivers).
445 * The SARSEQ can control three switches in the \ref group_ctb "CTB" driver (see \ref Cy_CTB_EnableSarSeqCtrl).
446 * These switches need to be enabled for SARSEQ control if the CTB outputs are used as the SARMUX inputs.
447 *
448 * The following table shows the required POS_PORT_ADDR and POS_PIN_ADDR settings
449 * for different input connections.
450 *
451 * <table class="doxtable">
452 * <tr>
453 * <th>Input Connection Selection</th>
454 * <th>POS_PORT_ADDR</th>
455 * <th>POS_PIN_ADDR</th>
456 * </tr>
457 * <tr>
458 * <td>SARMUX dedicated port</td>
459 * <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX</td>
460 * <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_0 through \ref CY_SAR_CHAN_POS_PIN_ADDR_7</td>
461 * </tr>
462 * <tr>
463 * <td>DieTemp sensor</td>
464 * <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX_VIRT</td>
465 * <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_0</td>
466 * </tr>
467 * <tr>
468 * <td>AMUXBUSA</td>
469 * <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX_VIRT</td>
470 * <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_2</td>
471 * </tr>
472 * <tr>
473 * <td>AMUXBUSB</td>
474 * <td>\ref CY_SAR_POS_PORT_ADDR_SARMUX_VIRT</td>
475 * <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_3</td>
476 * </tr>
477 * <tr>
478 * <td>CTB0 Opamp0 1x output</td>
479 * <td>\ref CY_SAR_POS_PORT_ADDR_CTB0</td>
480 * <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_2</td>
481 * </tr>
482 * <tr>
483 * <td>CTB0 Opamp1 1x output</td>
484 * <td>\ref CY_SAR_POS_PORT_ADDR_CTB0</td>
485 * <td>\ref CY_SAR_CHAN_POS_PIN_ADDR_3</td>
486 * </tr>
487 * </table>
488 *
489 * \subsection group_sar_sarmux_dietemp Input from DieTemp sensor
490 *
491 * When using the DieTemp sensor, always use single-ended mode.
492 * The temperature sensor can be routed to Vplus using the \ref CY_SAR_MUX_FW_TEMP_VPLUS switch.
493 * Connecting this switch will also enable the sensor. Set the \ref group_sar_acquisition_time "acquisition time" to
494 * be at least 1 us to meet the settling time of the temperature sensor.
495 *
496 * \image html sar_sarmux_dietemp.png
497 *
498 * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_DIETEMP
499 *
500 * \subsection group_sar_sarmux_se_diff Input from SARMUX port
501 *
502 * The following figure and code snippet show how two GPIOs on the SARMUX dedicated port
503 * are connected to the SARADC as separate single-ended channels and as a differential-pair channel.
504 *
505 * \image html sar_sarmux_dedicated_port.png
506 *
507 * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_SE_DIFF
508 *
509 * \subsection group_sar_sarmux_ctb Input from CTB output visa SARBUS0/1
510 *
511 * The following figure and code snippet show how the two opamp outputs from the CTB
512 * are connected to the SARADC as separate single-ended channels and as a differential-pair channel.
513 * Note that separate function calls are needed to configure and enable the opamps, perform required analog routing,
514 * and enable SARSEQ control of the switches contained in the CTB.
515 *
516 * \image html sar_sarmux_ctb.png
517 *
518 * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_CTB
519 *
520 * \subsection group_sar_sarmux_amuxbus Input from other pins through AMUXBUSA/B
521 *
522 * The following figure and code snippet show how two GPIOs on any port through the AMUXBUSA and AMUXBUSB
523 * are connected to the SARADC as separate single-ended channels and as a differential-pair channel.
524 * Note that separate function calls are needed to route the device pins to the SARMUX. The AMUXBUSes
525 * are separated into multiple segments and these segments are connected/disconnected using the AMUX_SPLIT_CTL
526 * registers in the HSIOM.
527 *
528 * \image html sar_sarmux_amuxbus.png
529 *
530 * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_AMUXBUS
531 *
532 *
533 * To connect SARMUX to any other non-dedicated port, you may need to close additional HSIOM switches to route signals
534 * through AMUXBUS.
535 * For more detail, see the device TRM, AMUX splitting.
536 *
537 * The following code snippet is an alternative pin configuration. To connect Port 1 to AMUXBUS, close the left and
538 * right switches of AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6].
539 *
540 * \warning
541 * This snippet shows how to configure pins for CY8C6347BZI-BLD53.
542 *
543 * \snippet sar/snippet/main.c SNIPPET_SAR_SARMUX_CUSTOM_PORT
544 *
545 * \section group_sar_low_power Low Power Support
546 * This SAR driver provides a callback function to handle power mode transitions.
547 * The \ref Cy_SAR_DeepSleepCallback function ensures that SAR conversions are stopped
548 * before Deep Sleep entry. Upon wakeup, the callback
549 * enables the hardware and continuous conversions, if previously enabled.
550 *
551 * To trigger the callback execution, the callback must be registered before calling \ref Cy_SysPm_CpuEnterDeepSleep. Refer to
552 * \ref group_syspm driver for more information about power mode transitions and
553 * callback registration.
554 *
555 * Recall that during configuration of the \ref group_sar_init_struct_ctrl "ctrl" field,
556 * the SARMUX can be configured to remain enabled in Deep Sleep mode.
557 * All other blocks (SARADC, REFBUF, and SARSEQ) do not support Deep Sleep mode operation.
558 *
559 * \section group_sar_more_information More Information
560 * For more information on the SAR ADC subsystem, refer to the technical reference manual (TRM).
561 *
562 * \section group_sar_changelog Changelog
563 * <table class="doxtable">
564 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
565 * <tr>
566 * <td>2.10</td>
567 * <td>The FIFO level validation in debug mode is fixed in the Cy_SAR_FifoSetLevel().</td>
568 * <td>Bug fixing.</td>
569 * </tr>
570 * <tr>
571 * <td>2.0.1</td>
572 * <td>Minor documentation updates.</td>
573 * <td>Documentation enhancement.</td>
574 * </tr>
575 * <tr>
576 * <td rowspan="4">2.0</td>
577 * <td>Added the next PASS_ver2 features: \ref group_sar_functions_lp, \ref group_sar_functions_fifo, and \ref group_sar_functions_trig.</td>
578 * <td>New silicon support.</td>
579 * </tr>
580 * <tr>
581 * <td>The Result Format check is added to the \ref Cy_SAR_Init function when the interleaved averaging mode is used.</td>
582 * <td>HW bug workaround.</td>
583 * </tr>
584 * <tr>
585 * <td>\ref Cy_SAR_Enable and \ref Cy_SAR_Disable functions behavior is changed -
586 * now \ref Cy_SAR_Disable checks the busy status before shutting down, and \ref Cy_SAR_Enable doesn't.</td>
587 * <td>Bug fixing.</td>
588 * </tr>
589 * <tr>
590 * <td>Fixed/Documented MISRA 2012 violations.</td>
591 * <td>MISRA 2012 compliance.</td>
592 * </tr>
593 * <tr>
594 * <td>1.20.3</td>
595 * <td>Minor documentation updates.</td>
596 * <td>Documentation enhancement.</td>
597 * </tr>
598 * <tr>
599 * <td>1.20.2</td>
600 * <td>Code snippets update.</td>
601 * <td>PDL infrastructure update, documentation enhancement.</td>
602 * </tr>
603 * <tr>
604 * <td>1.20.1</td>
605 * <td>Code snippets update.</td>
606 * <td>PDL infrastructure update, documentation enhancement.</td>
607 * </tr>
608 * <tr>
609 * <td rowspan="2">1.20</td>
610 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
611 * <td>Driver library directory-structure simplification.</td>
612 * </tr>
613 * <tr>
614 * <td>Added register access layer. Use register access macros instead
615 * of direct register access using dereferenced pointers.</td>
616 * <td>Makes register access device-independent, so that the PDL does
617 * not need to be recompiled for each supported part number.</td>
618 * </tr>
619 * <tr>
620 * <td rowspan="3">1.10</td>
621 * <td> Added workaround for parts with out of range CAP_TRIM in Init API.</td>
622 * <td> Correct CAP_TRIM is necessary achieving specified SAR ADC linearity</td>
623 * </tr>
624 * <tr>
625 * <td> Turn off the entire hardware block only if the SARMUX is not enabled
626 * for Deep Sleep operation.
627 * </td>
628 * <td> Improvement of the \ref Cy_SAR_DeepSleep flow</td>
629 * </tr>
630 * <tr>
631 * <td>Updated "Low Power Support" section to describe registering the Deep Sleep callback.
632 * Added parenthesis around logical AND operation in Sleep API.</td>
633 * <td>Documentation update and clarification</td>
634 * </tr>
635 * <tr>
636 * <td>1.0</td>
637 * <td>Initial version</td>
638 * <td></td>
639 * </tr>
640 * </table>
641 *
642 * \defgroup group_sar_macros Macros
643 * \{
644 * \defgroup group_sar_macros_interrupt Interrupt Masks
645 * \}
646 * \defgroup group_sar_functions Functions
647 * \{
648 * \defgroup group_sar_functions_basic Initialization and Basic Functions
649 * \defgroup group_sar_functions_power Low Power Callback
650 * \defgroup group_sar_functions_config Run-time Configuration Functions
651 * \defgroup group_sar_functions_countsto Counts Conversion Functions
652 * \defgroup group_sar_functions_interrupt Interrupt Functions
653 * \defgroup group_sar_functions_switches SARMUX Switch Control Functions
654 * \defgroup group_sar_functions_helper Useful Configuration Query Functions
655 * \defgroup group_sar_functions_lp Low Power features control Functions
656 * \defgroup group_sar_functions_fifo FIFO buffer control Functions
657 * \defgroup group_sar_functions_trig Common triggering Functions for multiple SAR instances
658 * \}
659 * \defgroup group_sar_data_structures Data Structures
660 * \defgroup group_sar_enums Enumerated Types
661 * \{
662 * \defgroup group_sar_ctrl_register_enums Control Register Enums
663 * \defgroup group_sar_sample_ctrl_register_enums Sample Control Register Enums
664 * \defgroup group_sar_sample_time_shift_enums Sample Time Register Enums
665 * \defgroup group_sar_range_thres_register_enums Range Interrupt Register Enums
666 * \defgroup group_sar_chan_config_register_enums Channel Configuration Register Enums
667 * \defgroup group_sar_mux_switch_register_enums SARMUX Switch Control Register Enums
668 * \}
669 */
670
671 #if !defined(CY_SAR_H)
672 #define CY_SAR_H
673
674 #include "cy_device.h"
675
676 #ifdef CY_IP_MXS40PASS_SAR
677
678 #include <stdint.h>
679 #include <stdbool.h>
680 #include <stddef.h>
681 #include "cy_syslib.h"
682 #include "cy_syspm.h"
683
684 #if defined(__cplusplus)
685 extern "C" {
686 #endif
687
688 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 11.3', 27, \
689 'SAR_Type will typecast to either SAR_V1_Type or SAR_V2_Type but not both on PDL initialization based on the target device at compile time.')
690
691 /** \addtogroup group_sar_macros
692 * \{
693 */
694
695 /** Driver major version */
696 #define CY_SAR_DRV_VERSION_MAJOR 2
697
698 /** Driver minor version */
699 #define CY_SAR_DRV_VERSION_MINOR 10
700
701 /** SAR driver identifier */
702 #define CY_SAR_ID CY_PDL_DRV_ID(0x01u)
703
704 /** \cond Legacy definition, use CY_SAR_SEQ_NUM_CHANNELS instead */
705 #define CY_SAR_MAX_NUM_CHANNELS (PASS_SAR_SAR_CHANNELS)
706 /** \endcond */
707
708 /** Number of sequencer channels */
709 #define CY_SAR_SEQ_NUM_CHANNELS (PASS_SAR_SAR_CHANNELS)
710
711 /** Number of all channels including the injection channel */
712 #define CY_SAR_NUM_CHANNELS (CY_SAR_SEQ_NUM_CHANNELS + 1UL)
713
714 /** Injection channel index */
715 #define CY_SAR_INJ_CHANNEL (CY_SAR_SEQ_NUM_CHANNELS)
716
717 /** Channels mask */
718 #define CY_SAR_CHANNELS_MASK ((1UL << CY_SAR_SEQ_NUM_CHANNELS) - 1UL)
719
720 /** Injection channel mask */
721 #define CY_SAR_INJ_CHAN_MASK (1UL << CY_SAR_INJ_CHANNEL)
722
723
724 /** \addtogroup group_sar_macros_interrupt
725 * \{
726 */
727
728 /** Interrupt masks */
729 #define CY_SAR_INTR_EOS (SAR_INTR_MASK_EOS_MASK_Msk) /**< Enable end of scan (EOS) interrupt */
730 #define CY_SAR_INTR_OVERFLOW (SAR_INTR_MASK_OVERFLOW_MASK_Msk) /**< Enable overflow interrupt */
731 #define CY_SAR_INTR_FW_COLLISION (SAR_INTR_MASK_FW_COLLISION_MASK_Msk) /**< Enable firmware collision interrupt */
732 #define CY_SAR_INTR_INJ_EOC (SAR_INTR_INJ_EOC_INTR_Msk) /**< Enable injection channel end of conversion (EOC) interrupt */
733 #define CY_SAR_INTR_INJ_SATURATE (SAR_INTR_INJ_SATURATE_INTR_Msk) /**< Enable injection channel saturation interrupt */
734 #define CY_SAR_INTR_INJ_RANGE (SAR_INTR_INJ_RANGE_INTR_Msk) /**< Enable injection channel range detection interrupt */
735 #define CY_SAR_INTR_INJ_COLLISION (SAR_INTR_INJ_COLLISION_INTR_Msk) /**< Enable injection channel firmware collision interrupt */
736 #define CY_SAR_INTR_FIFO_LEVEL (PASS_FIFO_V2_INTR_FIFO_LEVEL_Msk) /**< Enable FIFO level interrupt */
737 #define CY_SAR_INTR_FIFO_OVERFLOW (PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Msk) /**< Enable FIFO overflow interrupt */
738 #define CY_SAR_INTR_FIFO_UNDERFLOW (PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Msk) /**< Enable FIFO underflow interrupt */
739
740 /** Combined interrupt mask */
741 #define CY_SAR_INTR (CY_SAR_INTR_EOS | \
742 CY_SAR_INTR_OVERFLOW | \
743 CY_SAR_INTR_FW_COLLISION | \
744 CY_SAR_INTR_INJ_EOC | \
745 CY_SAR_INTR_INJ_SATURATE | \
746 CY_SAR_INTR_INJ_RANGE | \
747 CY_SAR_INTR_INJ_COLLISION)
748
749 /** Combined interrupt mask for FIFO */
750 #define CY_SAR_INTR_FIFO (CY_SAR_INTR_FIFO_LEVEL | \
751 CY_SAR_INTR_FIFO_OVERFLOW | \
752 CY_SAR_INTR_FIFO_UNDERFLOW)
753 /** \} group_sar_macros_interrupt */
754
755 /** \defgroup group_sysanalog_sar_select SAR block instance masks
756 * \{
757 * Specifies the SAR block instance.
758 */
759 #define CY_SAR_SAR0 (1UL) /**< SAR 0 instance */
760 #define CY_SAR_SAR1 (2UL) /**< SAR 1 instance */
761 #define CY_SAR_SAR2 (4UL) /**< SAR 2 instance */
762 #define CY_SAR_SAR3 (8UL) /**< SAR 3 instance */
763 #define CY_SAR_INSTANCE_MASK(base) (1UL << CY_SAR_INSTANCE(base)) /**< Convert SAR base to instance mask. Could be used instead of SAR 0 - SAR 3 instance masks */
764 #define CY_SAR_TIMER (1UL<<31UL) /**< Trigger source is Timer. Used only for simultTrigSource configuration in \ref cy_stc_sar_common_config_t */
765 /** \} group_sysanalog_sar_select */
766
767 /** \cond INTERNAL */
768 #define CY_SAR_DEINIT (0UL) /**< De-init value for most SAR registers */
769 #define CY_SAR_SAMPLE_TIME_DEINIT ((3UL << SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos) | (3UL << SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos)) /**< De-init value for the SAMPLE_TIME* registers */
770 #define CY_SAR_CLEAR_ALL_SWITCHES (0x3FFFFFFFUL) /**< Value to clear all SARMUX switches */
771 #define CY_SAR_DEINIT_SQ_CTRL (SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk \
772 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk \
773 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk \
774 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk \
775 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk \
776 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk \
777 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk \
778 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk \
779 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk \
780 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk \
781 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk \
782 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk \
783 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk \
784 | SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk)
785 #define CY_SAR_REG_CTRL_MASK (SAR_CTRL_PWR_CTRL_VREF_Msk \
786 | SAR_CTRL_VREF_SEL_Msk \
787 | SAR_CTRL_VREF_BYP_CAP_EN_Msk \
788 | SAR_CTRL_NEG_SEL_Msk \
789 | SAR_CTRL_SAR_HW_CTRL_NEGVREF_Msk \
790 | SAR_CTRL_COMP_DLY_Msk \
791 | SAR_CTRL_REFBUF_EN_Msk \
792 | SAR_CTRL_COMP_PWR_Msk \
793 | SAR_CTRL_DEEPSLEEP_ON_Msk \
794 | SAR_CTRL_DSI_SYNC_CONFIG_Msk \
795 | SAR_CTRL_DSI_MODE_Msk \
796 | SAR_CTRL_SWITCH_DISABLE_Msk \
797 | SAR_CTRL_ENABLED_Msk)
798 #define CY_SAR_REG_SAMPLE_CTRL_MASK (SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk \
799 | SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk \
800 | SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk \
801 | SAR_SAMPLE_CTRL_AVG_CNT_Msk \
802 | SAR_SAMPLE_CTRL_AVG_SHIFT_Msk \
803 | SAR_SAMPLE_CTRL_AVG_MODE_Msk \
804 | SAR_SAMPLE_CTRL_CONTINUOUS_Msk \
805 | SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk \
806 | SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk \
807 | SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk \
808 | SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Msk \
809 | SAR_SAMPLE_CTRL_REPEAT_INVALID_Msk \
810 | SAR_SAMPLE_CTRL_VALID_SEL_Msk \
811 | SAR_SAMPLE_CTRL_VALID_SEL_EN_Msk \
812 | SAR_SAMPLE_CTRL_VALID_IGNORE_Msk \
813 | SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk \
814 | SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk)
815 #define CY_SAR_REG_CHAN_CONFIG_MASK (SAR_CHAN_CONFIG_POS_PIN_ADDR_Msk \
816 | SAR_CHAN_CONFIG_POS_PORT_ADDR_Msk \
817 | SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk \
818 | SAR_CHAN_CONFIG_AVG_EN_Msk \
819 | SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk \
820 | SAR_CHAN_CONFIG_NEG_PIN_ADDR_Msk \
821 | SAR_CHAN_CONFIG_NEG_PORT_ADDR_Msk \
822 | SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk \
823 | SAR_CHAN_CONFIG_DSI_OUT_EN_Msk)
824 #define CY_SAR_REG_SAMPLE_TIME_MASK (SAR_SAMPLE_TIME01_SAMPLE_TIME0_Msk | SAR_SAMPLE_TIME01_SAMPLE_TIME1_Msk)
825
826 #define CY_SAR_2US_DELAY (2u) /**< Delay used in Enable API function to avoid SAR deadlock */
827 #define CY_SAR_10V_COUNTS (10.0F) /**< Value of 10 in volts */
828 #define CY_SAR_10MV_COUNTS (10000) /**< Value of 10 in millivolts */
829 #define CY_SAR_10UV_COUNTS (10000000L) /**< Value of 10 in microvolts */
830 #define CY_SAR_WRK_MAX_12BIT (0x00001000L) /**< Maximum SAR work register value for a 12-bit resolution */
831 #define CY_SAR_RANGE_LIMIT_MAX (0xFFFFUL) /**< Maximum value for the low and high range interrupt threshold values */
832 #define CY_SAR_CAP_TRIM_MAX (0x3FUL) /**< Maximum value for CAP_TRIM */
833 #define CY_SAR_CAP_TRIM_MIN (0x00UL) /**< Maximum value for CAP_TRIM */
834 #define CY_SAR_CAP_TRIM (0x0BUL) /**< Correct cap trim value */
835
836 /* Macros for conditions used in CY_ASSERT calls */
837 #define CY_SAR_CHANNUM(chan) ((chan) < CY_SAR_MAX_NUM_CHANNELS) /* legacy */
838 #define CY_SAR_CHANMASK(mask) (0UL == ((mask) & ~CY_SAR_CHANNELS_MASK))
839 #define CY_SAR_INJMASK(mask) (0UL == ((mask) & ~(CY_SAR_INJ_CHAN_MASK | CY_SAR_CHANNELS_MASK)))
840 #define CY_SAR_RANGECOND(cond) ((cond) <= CY_SAR_RANGE_COND_OUTSIDE)
841 #define CY_SAR_INTRMASK(mask) (0UL == ((mask) & ~CY_SAR_INTR))
842 #define CY_SAR_FIFO_INTRMASK(mask) (0UL == ((mask) & ~CY_SAR_INTR_FIFO))
843 #define CY_SAR_TRIGGER(mode) (((mode) == CY_SAR_TRIGGER_MODE_FW_ONLY) || \
844 ((mode) == CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE) || \
845 ((mode) == CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL))
846 #define CY_SAR_RETURN(mode) (((mode) == CY_SAR_RETURN_STATUS) || \
847 ((mode) == CY_SAR_WAIT_FOR_RESULT) || \
848 ((mode) == CY_SAR_RETURN_STATUS_INJ) || \
849 ((mode) == CY_SAR_WAIT_FOR_RESULT_INJ))
850 #define CY_SAR_STARTCONVERT(mode) (((mode) == CY_SAR_START_CONVERT_SINGLE_SHOT) || ((mode) == CY_SAR_START_CONVERT_CONTINUOUS))
851 #define CY_SAR_RANGE_LIMIT(limit) ((limit) <= CY_SAR_RANGE_LIMIT_MAX)
852 #define CY_SAR_SWITCHSELECT(select) ((select) == CY_SAR_MUX_SWITCH0)
853 #define CY_SAR_SWITCHMASK(mask) ((mask) <= CY_SAR_CLEAR_ALL_SWITCHES)
854 #define CY_SAR_SWITCHSTATE(state) (((state) == CY_SAR_SWITCH_OPEN) || ((state) == CY_SAR_SWITCH_CLOSE))
855 #define CY_SAR_SQMASK(mask) (((mask) & (~CY_SAR_DEINIT_SQ_CTRL)) == 0UL)
856 #define CY_SAR_SQCTRL(ctrl) (((ctrl) == CY_SAR_SWITCH_SEQ_CTRL_ENABLE) || ((ctrl) == CY_SAR_SWITCH_SEQ_CTRL_DISABLE))
857 #define CY_SAR_CTRL(value) (((value) & (~CY_SAR_REG_CTRL_MASK)) == 0UL)
858 #define CY_SAR_SAMPLE_CTRL(value) (((value) & (~CY_SAR_REG_SAMPLE_CTRL_MASK)) == 0UL)
859 #define CY_SAR_SAMPLE_TIME(value) (((value) & (~CY_SAR_REG_SAMPLE_TIME_MASK)) == 0UL)
860 #define CY_SAR_CHAN_CONFIG(value) (((value) & (~CY_SAR_REG_CHAN_CONFIG_MASK)) == 0UL)
861 #define CY_SAR_IS_FIFO_LEVEL_VALID(level) ((level) <= PASS_FIFO_V2_LEVEL_LEVEL_Msk)
862 #define CY_SAR_IS_CLK_VALID(clock) (((clock) == CY_SAR_CLK_PERI) || \
863 ((clock) == CY_SAR_CLK_DEEPSLEEP))
864
865 #define CY_SAR_IS_DSCLK(base) ((uint32_t)CY_SAR_CLK_DEEPSLEEP == _FLD2VAL(PASS_V2_SAR_CLOCK_SEL_CLOCK_SEL, PASS_SAR_CLOCK_SEL(base)))
866 /** \endcond */
867
868 /** \} group_sar_macro */
869
870
871 /** \cond
872 * These arrays exposed here for BWC
873 * Not recommended to directly use in application code
874 */
875 extern volatile int16_t Cy_SAR_offset[CY_SAR_NUM_CHANNELS][CY_SAR_INSTANCES];
876 extern volatile int32_t Cy_SAR_countsPer10Volt[CY_SAR_NUM_CHANNELS][CY_SAR_INSTANCES];
877 /** \endcond */
878
879
880 /** \addtogroup group_sar_enums
881 * \{
882 */
883
884 /******************************************************************************
885 * Enumerations
886 *****************************************************************************/
887
888 /** The SAR status/error code definitions */
889 typedef enum
890 {
891 CY_SAR_SUCCESS = 0x00UL, /**< Success */
892 CY_SAR_BAD_PARAM = CY_SAR_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Invalid input parameters */
893 CY_SAR_TIMEOUT = CY_SAR_ID | CY_PDL_STATUS_ERROR | 0x02UL, /**< A timeout occurred */
894 CY_SAR_CONVERSION_NOT_COMPLETE = CY_SAR_ID | CY_PDL_STATUS_ERROR | 0x03UL, /**< SAR conversion is not complete */
895 } cy_en_sar_status_t;
896
897 /** Definitions for starting a conversion used in \ref Cy_SAR_StartConvert */
898 typedef enum
899 {
900 CY_SAR_START_CONVERT_SINGLE_SHOT = 0UL, /**< Start a single scan (one shot) from firmware */
901 CY_SAR_START_CONVERT_CONTINUOUS = 1UL, /**< Continuously scan enabled channels and ignores all triggers, firmware or hardware */
902 } cy_en_sar_start_convert_sel_t;
903
904 /** Definitions for the return mode used in \ref Cy_SAR_IsEndConversion */
905 typedef enum
906 {
907 CY_SAR_RETURN_STATUS = 0UL, /**< Immediately returns the conversion status. */
908 CY_SAR_WAIT_FOR_RESULT = 1UL, /**< Does not return a result until the conversion of all sequential channels is complete. This mode is blocking. */
909 CY_SAR_RETURN_STATUS_INJ = 2UL, /**< Immediately returns the conversion status of the injection channel. */
910 CY_SAR_WAIT_FOR_RESULT_INJ = 3UL, /**< Does not return a result until the conversion of injection channels is complete. This mode is blocking. */
911 } cy_en_sar_return_mode_t;
912
913 /** Switch state definitions */
914 typedef enum
915 {
916 CY_SAR_SWITCH_OPEN = 0UL, /**< Open the switch */
917 CY_SAR_SWITCH_CLOSE = 1UL /**< Close the switch */
918 } cy_en_sar_switch_state_t;
919
920 /** Definitions for sequencer control of switches */
921 typedef enum
922 {
923 CY_SAR_SWITCH_SEQ_CTRL_DISABLE = 0UL, /**< Disable sequencer control of switch */
924 CY_SAR_SWITCH_SEQ_CTRL_ENABLE = 1UL /**< Enable sequencer control of switch */
925 } cy_en_sar_switch_sar_seq_ctrl_t;
926
927 /** Switch register selection for \ref Cy_SAR_SetAnalogSwitch and \ref Cy_SAR_GetAnalogSwitch */
928 typedef enum
929 {
930 CY_SAR_MUX_SWITCH0 = 0UL, /**< SARMUX switch control register */
931 } cy_en_sar_switch_register_sel_t;
932
933 /** \addtogroup group_sar_ctrl_register_enums
934 * This set of enumerations aids in configuring the SAR CTRL register
935 * \{
936 */
937 /** Reference voltage buffer power mode definitions */
938 typedef enum
939 {
940 CY_SAR_VREF_PWR_100 = 0UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< Full power (100%) */
941 CY_SAR_VREF_PWR_80 = 1UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 80% power */
942 CY_SAR_VREF_PWR_60 = 2UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 60% power */
943 CY_SAR_VREF_PWR_50 = 3UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 50% power */
944 CY_SAR_VREF_PWR_40 = 4UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 40% power */
945 CY_SAR_VREF_PWR_30 = 5UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 30% power */
946 CY_SAR_VREF_PWR_20 = 6UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 20% power */
947 CY_SAR_VREF_PWR_10 = 7UL << SAR_CTRL_PWR_CTRL_VREF_Pos, /**< 10% power */
948 } cy_en_sar_ctrl_pwr_ctrl_vref_t;
949
950 /** Reference voltage selection definitions */
951 typedef enum
952 {
953 CY_SAR_VREF_SEL_BGR = 4UL << SAR_CTRL_VREF_SEL_Pos, /**< System wide bandgap from \ref group_sysanalog "AREF" (Vref buffer on) */
954 CY_SAR_VREF_SEL_EXT = 5UL << SAR_CTRL_VREF_SEL_Pos, /**< External Vref direct from a pin */
955 CY_SAR_VREF_SEL_VDDA_DIV_2 = 6UL << SAR_CTRL_VREF_SEL_Pos, /**< Vdda/2 (Vref buffer on) */
956 CY_SAR_VREF_SEL_VDDA = 7UL << SAR_CTRL_VREF_SEL_Pos /**< Vdda */
957 } cy_en_sar_ctrl_vref_sel_t;
958
959 /** Vref bypass cap enable.
960 * When enabled, a bypass capacitor should
961 * be connected to the dedicated Vref pin of the device.
962 * Refer to the device datasheet for the minimum bypass capacitor value to use.
963 */
964 typedef enum
965 {
966 CY_SAR_BYPASS_CAP_DISABLE = 0UL << SAR_CTRL_VREF_BYP_CAP_EN_Pos, /**< Disable Vref bypass cap */
967 CY_SAR_BYPASS_CAP_ENABLE = 1UL << SAR_CTRL_VREF_BYP_CAP_EN_Pos /**< Enable Vref bypass cap */
968 } cy_en_sar_ctrl_bypass_cap_t;
969
970 /** Negative terminal (Vminus) selection definitions for single-ended channels.
971 *
972 * The Vminus input for single ended channels can be connected to
973 * Vref, VSSA, or routed out to an external pin.
974 * The options for routing to a pin are through Pin 1, Pin 3, Pin 5, or Pin 7
975 * of the SARMUX dedicated port or an acore wire in AROUTE, if available on the device.
976 *
977 * \ref CY_SAR_NEG_SEL_VSSA_KELVIN comes straight from a Vssa pad without any shared branches
978 * so as to keep quiet and avoid voltage drops.
979 */
980 typedef enum
981 {
982 CY_SAR_NEG_SEL_VSSA_KELVIN = 0UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to VSSA_KELVIN */
983 CY_SAR_NEG_SEL_P1 = 2UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 1 of SARMUX dedicated port */
984 CY_SAR_NEG_SEL_P3 = 3UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 3 of SARMUX dedicated port */
985 CY_SAR_NEG_SEL_P5 = 4UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 5 of SARMUX dedicated port */
986 CY_SAR_NEG_SEL_P7 = 5UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to Pin 6 of SARMUX dedicated port */
987 CY_SAR_NEG_SEL_ACORE = 6UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to an ACORE in AROUTE */
988 CY_SAR_NEG_SEL_VREF = 7UL << SAR_CTRL_NEG_SEL_Pos, /**< Connect Vminus to VREF input of SARADC */
989 } cy_en_sar_ctrl_neg_sel_t;
990
991 /** Enable hardware control of the switch between Vref and the Vminus input */
992 typedef enum
993 {
994 CY_SAR_CTRL_NEGVREF_FW_ONLY = 0UL << SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos, /**< Only firmware control of the switch */
995 CY_SAR_CTRL_NEGVREF_HW = 1UL << SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos /**< Enable hardware control of the switch */
996 } cy_en_sar_ctrl_hw_ctrl_negvref_t;
997
998 /** Configure the comparator latch delay */
999 typedef enum
1000 {
1001 CY_SAR_CTRL_COMP_DLY_2P5 = 0UL << SAR_CTRL_COMP_DLY_Pos, /**< 2.5 ns delay, use for SAR conversion rate up to 2.5 Msps */
1002 CY_SAR_CTRL_COMP_DLY_4 = 1UL << SAR_CTRL_COMP_DLY_Pos, /**< 4 ns delay, use for SAR conversion rate up to 2.0 Msps */
1003 CY_SAR_CTRL_COMP_DLY_10 = 2UL << SAR_CTRL_COMP_DLY_Pos, /**< 10 ns delay, use for SAR conversion rate up to 1.5 Msps */
1004 CY_SAR_CTRL_COMP_DLY_12 = 3UL << SAR_CTRL_COMP_DLY_Pos /**< 12 ns delay, use for SAR conversion rate up to 1 Msps */
1005 } cy_en_sar_ctrl_comp_delay_t;
1006
1007 /** Configure the comparator power mode */
1008 typedef enum
1009 {
1010 CY_SAR_COMP_PWR_100 = 0UL << SAR_CTRL_COMP_PWR_Pos, /**< 100% power, use this for > 2 Msps */
1011 CY_SAR_COMP_PWR_80 = 1UL << SAR_CTRL_COMP_PWR_Pos, /**< 80% power, use this for 1.5 - 2 Msps */
1012 CY_SAR_COMP_PWR_60 = 2UL << SAR_CTRL_COMP_PWR_Pos, /**< 60% power, use this for 1.0 - 1.5 Msps */
1013 CY_SAR_COMP_PWR_50 = 3UL << SAR_CTRL_COMP_PWR_Pos, /**< 50% power, use this for 500 ksps - 1 Msps */
1014 CY_SAR_COMP_PWR_40 = 4UL << SAR_CTRL_COMP_PWR_Pos, /**< 40% power, use this for 250 - 500 ksps */
1015 CY_SAR_COMP_PWR_30 = 5UL << SAR_CTRL_COMP_PWR_Pos, /**< 30% power, use this for 100 - 250 ksps */
1016 CY_SAR_COMP_PWR_20 = 6UL << SAR_CTRL_COMP_PWR_Pos, /**< 20% power, use this for TDB sps */
1017 CY_SAR_COMP_PWR_10 = 7UL << SAR_CTRL_COMP_PWR_Pos, /**< 10% power, use this for < 100 ksps */
1018 } cy_en_sar_ctrl_comp_pwr_t;
1019
1020 /** Enable or disable the SARMUX during Deep Sleep power mode. */
1021 typedef enum
1022 {
1023 CY_SAR_DEEPSLEEP_SARMUX_OFF = 0UL << SAR_CTRL_DEEPSLEEP_ON_Pos, /**< Disable SARMUX operation during Deep Sleep */
1024 CY_SAR_DEEPSLEEP_SARMUX_ON = 1UL << SAR_CTRL_DEEPSLEEP_ON_Pos /**< Enable SARMUX operation during Deep Sleep */
1025 } cy_en_sar_ctrl_sarmux_deep_sleep_t;
1026
1027 /** Enable or disable the SARSEQ control of routing switches */
1028 typedef enum
1029 {
1030 CY_SAR_SARSEQ_SWITCH_ENABLE = 0UL << SAR_CTRL_SWITCH_DISABLE_Pos, /**< Enable the SARSEQ to change the routing switches defined in the channel configurations */
1031 CY_SAR_SARSEQ_SWITCH_DISABLE = 1UL << SAR_CTRL_SWITCH_DISABLE_Pos /**< Disable the SARSEQ. It is up to the firmware to set the routing switches */
1032 } cy_en_sar_ctrl_sarseq_routing_switches_t;
1033
1034 /* \} */
1035
1036 /** \addtogroup group_sar_sample_ctrl_register_enums
1037 * This set of enumerations are used in configuring the SAR SAMPLE_CTRL register
1038 * \{
1039 */
1040 /** Configure result alignment, either left or right aligned.
1041 *
1042 * \note
1043 * Averaging always uses right alignment. If the \ref CY_SAR_LEFT_ALIGN
1044 * is selected with averaging enabled, it is ignored.
1045 *
1046 * \note
1047 * The voltage conversion functions (\ref Cy_SAR_CountsTo_Volts, \ref Cy_SAR_CountsTo_mVolts,
1048 * \ref Cy_SAR_CountsTo_uVolts) are only valid for right alignment.
1049 * */
1050 typedef enum
1051 {
1052 CY_SAR_RIGHT_ALIGN = 0UL << SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos, /**< Right align result data to bits [11:0] with sign extension to 16 bits if channel is signed */
1053 CY_SAR_LEFT_ALIGN = 1UL << SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos /**< Left align result data to bits [15:4] */
1054 } cy_en_sar_sample_ctrl_result_align_t;
1055
1056 /** Configure format, signed or unsigned, of single-ended channels */
1057 typedef enum
1058 {
1059 CY_SAR_SINGLE_ENDED_UNSIGNED = 0UL << SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos, /**< Result data for single-ended channels is unsigned */
1060 CY_SAR_SINGLE_ENDED_SIGNED = 1UL << SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos /**< Result data for single-ended channels is signed */
1061 } cy_en_sar_sample_ctrl_single_ended_format_t;
1062
1063 /** Configure format, signed or unsigned, of differential channels */
1064 typedef enum
1065 {
1066 CY_SAR_DIFFERENTIAL_UNSIGNED = 0UL << SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos, /**< Result data for differential channels is unsigned */
1067 CY_SAR_DIFFERENTIAL_SIGNED = 1UL << SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos /**< Result data for differential channels is signed */
1068 } cy_en_sar_sample_ctrl_differential_format_t;
1069
1070 /** Configure number of samples for averaging.
1071 * This applies only to channels with averaging enabled.
1072 */
1073 typedef enum
1074 {
1075 CY_SAR_AVG_CNT_2 = 0UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 2 */
1076 CY_SAR_AVG_CNT_4 = 1UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 4 */
1077 CY_SAR_AVG_CNT_8 = 2UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 8 */
1078 CY_SAR_AVG_CNT_16 = 3UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 16 */
1079 CY_SAR_AVG_CNT_32 = 4UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 32 */
1080 CY_SAR_AVG_CNT_64 = 5UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 64 */
1081 CY_SAR_AVG_CNT_128 = 6UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos, /**< Set samples averaged to 128 */
1082 CY_SAR_AVG_CNT_256 = 7UL << SAR_SAMPLE_CTRL_AVG_CNT_Pos /**< Set samples averaged to 256 */
1083 } cy_en_sar_sample_ctrl_avg_cnt_t;
1084
1085 /** Configure the averaging mode.
1086 *
1087 * - Sequential accumulate and dump: a channel will be sampled back to back.
1088 * The result is added to a running sum in a 20-bit register. At the end
1089 * of the scan, the accumulated value is shifted right to fit into 16 bits
1090 * and stored into the CHAN_RESULT register.
1091 * - Sequential fixed: a channel will be sampled back to back.
1092 * The result is added to a running sum in a 20-bit register. At the end
1093 * of the scan, the accumulated value is shifted right to fit into 12 bits
1094 * and stored into the CHAN_RESULT register.
1095 * - Interleaved: a channel will be sampled once per scan.
1096 * The result is added to a running sum in a 16-bit register.
1097 * In the scan where the final averaging count is reached,
1098 * the accumulated value is shifted right to fit into 12 bits
1099 * and stored into the CHAN_RESULT register.
1100 * In all other scans, the CHAN_RESULT will have an invalid result.
1101 * In interleaved mode, make sure that the averaging
1102 * count is low enough to ensure that the intermediate value does not exceed 16 bits,
1103 * that is averaging count is 16 or less. Otherwise, the MSBs will be lost.
1104 * In the special case that averaging is enabled for all enabled channels
1105 * and interleaved mode is used, the interrupt frequency
1106 * will be reduced by a factor of the number of samples averaged.
1107 */
1108 typedef enum
1109 {
1110 CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM = 0UL, /**< Set mode to sequential accumulate and dump */
1111 CY_SAR_AVG_MODE_SEQUENTIAL_FIXED = SAR_SAMPLE_CTRL_AVG_SHIFT_Msk, /**< Set mode to sequential 12-bit fixed */
1112 CY_SAR_AVG_MODE_INTERLEAVED = SAR_SAMPLE_CTRL_AVG_MODE_Msk, /**< Set mode to interleaved. Number of samples per scan must be 16 or less. */
1113 } cy_en_sar_sample_ctrl_avg_mode_t;
1114
1115 /** Configure the trigger mode.
1116 *
1117 * Firmware triggering is always enabled and can be single shot or continuous.
1118 * Additionally, hardware triggering can be enabled with the option to be
1119 * edge or level sensitive.
1120 */
1121 typedef enum
1122 {
1123 CY_SAR_TRIGGER_MODE_FW_ONLY = 0UL, /**< Firmware trigger only, disable hardware trigger*/
1124 CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE = SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk, /**< Enable edge sensitive hardware trigger. Each rising edge will trigger a single scan. */
1125 CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL = SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk | SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk, /**< Enable level sensitive hardware trigger. The SAR will continuously scan while the trigger signal is high. */
1126 } cy_en_sar_sample_ctrl_trigger_mode_t;
1127
1128 /* \} */
1129
1130 /** \addtogroup group_sar_sample_time_shift_enums
1131 * This set of enumerations aids in configuring the SAR SAMPLE_TIME* registers
1132 * \{
1133 */
1134 /** Configure the sample time by using these shifts */
1135 typedef enum
1136 {
1137 CY_SAR_SAMPLE_TIME0_SHIFT = SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos, /**< Shift for sample time 0 */
1138 CY_SAR_SAMPLE_TIME1_SHIFT = SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos, /**< Shift for sample time 1 */
1139 CY_SAR_SAMPLE_TIME2_SHIFT = SAR_SAMPLE_TIME23_SAMPLE_TIME2_Pos, /**< Shift for sample time 2 */
1140 CY_SAR_SAMPLE_TIME3_SHIFT = SAR_SAMPLE_TIME23_SAMPLE_TIME3_Pos, /**< Shift for sample time 3 */
1141 } cy_en_sar_sample_time_shift_t;
1142 /* \} */
1143
1144 /** \addtogroup group_sar_range_thres_register_enums
1145 * This set of enumerations aids in configuring the SAR RANGE* registers
1146 * \{
1147 */
1148 /** Configure the lower and upper thresholds for range detection
1149 *
1150 * The SARSEQ supports range detection to allow for automatic detection of sample
1151 * values compared to two programmable thresholds without CPU involvement.
1152 * Range detection is defined by two global thresholds and a condition.
1153 * The RANGE_LOW value defines the lower threshold and RANGE_HIGH defines
1154 * the upper threshold of the range.
1155 *
1156 * Range detect is done after averaging, alignment, and sign extension (if applicable).
1157 * In other words, the thresholds values must have the same data format as the result data.
1158 * Range detection is always done for all channels scanned. By making RANGE_INTR_MASK=0,
1159 * the firmware can choose to ignore the range detect interrupt for any channel.
1160 */
1161 typedef enum
1162 {
1163 CY_SAR_RANGE_LOW_SHIFT = SAR_RANGE_THRES_RANGE_LOW_Pos, /**< Shift for setting lower limit of range detection */
1164 CY_SAR_RANGE_HIGH_SHIFT = SAR_RANGE_THRES_RANGE_HIGH_Pos, /**< Shift for setting upper limit of range detection */
1165 } cy_en_sar_range_thres_shift_t;
1166
1167 /** Configure the condition (below, inside, above, or outside) of the range detection interrupt */
1168 typedef enum
1169 {
1170 CY_SAR_RANGE_COND_BELOW = 0UL, /**< Range interrupt detected when result < RANGE_LOW */
1171 CY_SAR_RANGE_COND_INSIDE = 1UL, /**< Range interrupt detected when RANGE_LOW <= result < RANGE_HIGH */
1172 CY_SAR_RANGE_COND_ABOVE = 2UL, /**< Range interrupt detected when RANGE_HIGH <= result */
1173 CY_SAR_RANGE_COND_OUTSIDE = 3UL, /**< Range interrupt detected when result < RANGE_LOW || RANGE_HIGH <= result */
1174 } cy_en_sar_range_detect_condition_t;
1175 /* \} */
1176
1177 /** \addtogroup group_sar_chan_config_register_enums
1178 * This set of enumerations aids in configuring the SAR CHAN_CONFIG register
1179 * \{
1180 */
1181 /** Configure the input mode of the channel
1182 *
1183 * - Single ended channel: the \ref cy_en_sar_ctrl_neg_sel_t selection in the \ref group_sar_init_struct_ctrl register
1184 * determines what drives the Vminus pin
1185 * - Differential paired: Vplus and Vminus are a pair. Bit 0 of \ref cy_en_sar_chan_config_pos_pin_addr_t "POS_PIN_ADDR"
1186 * is ignored and considered to be 0.
1187 * In other words, \ref cy_en_sar_chan_config_pos_pin_addr_t "POS_PIN_ADDR" points to the even pin of a pin pair.
1188 * The even pin is connected to Vplus and the odd pin is connected to Vminus.
1189 * \ref cy_en_sar_chan_config_pos_port_addr_t "POS_PORT_ADDR" is used to identify the port that contains the pins.
1190 * - Differential unpaired: The \ref cy_en_sar_chan_config_neg_pin_addr_t "NEG_PIN_ADDR" and
1191 * \ref cy_en_sar_chan_config_neg_port_addr_t "NEG_PORT_ADDR" determine what drives the Vminus pin.
1192 * This is a variation of differential mode with no even-odd pair limitation
1193 */
1194 typedef enum
1195 {
1196 CY_SAR_CHAN_SINGLE_ENDED = 0UL, /**< Single ended channel */
1197 CY_SAR_CHAN_DIFFERENTIAL_PAIRED = SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk, /**< Differential with even-odd pair limitation */
1198 CY_SAR_CHAN_DIFFERENTIAL_UNPAIRED = SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk /**< Differential with no even-odd pair limitation */
1199 } cy_en_sar_chan_config_input_mode_t;
1200
1201 /** Configure address of the pin connected to the Vplus terminal of the SARADC. */
1202 typedef enum
1203 {
1204 CY_SAR_CHAN_POS_PIN_ADDR_0 = 0UL, /**< Pin 0 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1205 CY_SAR_CHAN_POS_PIN_ADDR_1 = 1UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 1 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1206 CY_SAR_CHAN_POS_PIN_ADDR_2 = 2UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 2 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1207 CY_SAR_CHAN_POS_PIN_ADDR_3 = 3UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 3 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1208 CY_SAR_CHAN_POS_PIN_ADDR_4 = 4UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 4 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1209 CY_SAR_CHAN_POS_PIN_ADDR_5 = 5UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 5 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1210 CY_SAR_CHAN_POS_PIN_ADDR_6 = 6UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 6 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1211 CY_SAR_CHAN_POS_PIN_ADDR_7 = 7UL << SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos, /**< Pin 7 on port specified in \ref cy_en_sar_chan_config_pos_port_addr_t */
1212 } cy_en_sar_chan_config_pos_pin_addr_t;
1213
1214 /** Configure address of the port that contains the pin connected to the Vplus terminal of the SARADC
1215 *
1216 * - \ref CY_SAR_POS_PORT_ADDR_SARMUX is for the dedicated SARMUX port (8 pins)
1217 * - Port 1 through 4 are respectively the pins of CTB0, CTB1, CTB2, and CTB3 (if present)
1218 * - Port 7, 5, and 6 (VPORT0/1/2) are the groups of internal signals that can be selected
1219 * in the SARMUX or AROUTE (if present).
1220 *
1221 * See the \ref group_sar_sarmux section for more guidance.
1222 */
1223 typedef enum
1224 {
1225 CY_SAR_POS_PORT_ADDR_SARMUX = 0UL, /**< Dedicated SARMUX port with 8 possible pins */
1226 CY_SAR_POS_PORT_ADDR_CTB0 = 1UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB0, if present */
1227 CY_SAR_POS_PORT_ADDR_CTB1 = 2UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB1, if present */
1228 CY_SAR_POS_PORT_ADDR_CTB2 = 3UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB2, if present */
1229 CY_SAR_POS_PORT_ADDR_CTB3 = 4UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< Outputs from CTB3, if present */
1230 CY_SAR_POS_PORT_ADDR_AROUTE_VIRT2 = 5UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT2), if present */
1231 CY_SAR_POS_PORT_ADDR_AROUTE_VIRT1 = 6UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT1), if present */
1232 CY_SAR_POS_PORT_ADDR_SARMUX_VIRT = 7UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< SARMUX virtual port for DieTemp and AMUXBUSA/B */
1233 } cy_en_sar_chan_config_pos_port_addr_t;
1234
1235 /** Enable or disable averaging for the channel */
1236 typedef enum
1237 {
1238 CY_SAR_CHAN_AVG_DISABLE = 0UL, /**< Disable averaging for the channel */
1239 CY_SAR_CHAN_AVG_ENABLE = 1UL << SAR_CHAN_CONFIG_AVG_EN_Pos /**< Enable averaging for the channel */
1240 } cy_en_sar_chan_config_avg_en_t;
1241
1242 /** Select which sample time to use for the channel.
1243 * There are four global samples times available set by \ref group_sar_init_struct_sampleTime01 and
1244 * \ref group_sar_init_struct_sampleTime23.
1245 */
1246 typedef enum
1247 {
1248 CY_SAR_CHAN_SAMPLE_TIME_0 = 0UL, /**< Use sample time 0 for the channel */
1249 CY_SAR_CHAN_SAMPLE_TIME_1 = 1UL << SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos, /**< Use sample time 1 for the channel */
1250 CY_SAR_CHAN_SAMPLE_TIME_2 = 2UL << SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos, /**< Use sample time 2 for the channel */
1251 CY_SAR_CHAN_SAMPLE_TIME_3 = 3UL << SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos, /**< Use sample time 3 for the channel */
1252 } cy_en_sar_chan_config_sample_time_t;
1253
1254 /** Configure address of the pin connected to the Vminus terminal of the SARADC. */
1255 typedef enum
1256 {
1257 CY_SAR_CHAN_NEG_PIN_ADDR_0 = 0UL, /**< Pin 0 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1258 CY_SAR_CHAN_NEG_PIN_ADDR_1 = 1UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 1 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1259 CY_SAR_CHAN_NEG_PIN_ADDR_2 = 2UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 2 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1260 CY_SAR_CHAN_NEG_PIN_ADDR_3 = 3UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 3 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1261 CY_SAR_CHAN_NEG_PIN_ADDR_4 = 4UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 4 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1262 CY_SAR_CHAN_NEG_PIN_ADDR_5 = 5UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 5 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1263 CY_SAR_CHAN_NEG_PIN_ADDR_6 = 6UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 6 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1264 CY_SAR_CHAN_NEG_PIN_ADDR_7 = 7UL << SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos, /**< Pin 7 on port specified in \ref cy_en_sar_chan_config_neg_port_addr_t */
1265 } cy_en_sar_chan_config_neg_pin_addr_t;
1266
1267 /** Configure address of the port that contains the pin connected to the Vminus terminal of the SARADC.
1268 *
1269 * - Port 0 is 8 pins of the SARMUX
1270 * - Port 7, 5, and 6 (VPORT0/1/2) are the groups of internal signals that can be selected
1271 * in the SARMUX or AROUTE (if present).
1272 */
1273 typedef enum
1274 {
1275 CY_SAR_NEG_PORT_ADDR_SARMUX = 0UL, /**< Dedicated SARMUX port with 8 possible pins */
1276 CY_SAR_NEG_PORT_ADDR_AROUTE_VIRT2 = 5UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT2), if present */
1277 CY_SAR_NEG_PORT_ADDR_AROUTE_VIRT1 = 6UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT1), if present */
1278 CY_SAR_NEG_PORT_ADDR_SARMUX_VIRT = 7UL << SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos, /**< SARMUX virtual port for AMUXBUSA/B */
1279 } cy_en_sar_chan_config_neg_port_addr_t;
1280
1281
1282 /** Configure address of the port that contains the pin connected to the Vplus terminal of the injection channel
1283 *
1284 * - \ref CY_SAR_INJ_PORT_ADDR_SARMUX is for the dedicated SARMUX port (8 pins)
1285 * - Ports 1 through 4 are respectively the pins of CTB0, CTB1, CTB2, and CTB3 (if present)
1286 * - Ports 7 and 6 are the groups of internal signals that can be selected
1287 * in the SARMUX or AROUTE (if present).
1288 *
1289 * See the \ref group_sar_sarmux section for more guidance.
1290 */
1291 typedef enum
1292 {
1293 CY_SAR_INJ_PORT_ADDR_SARMUX = 0UL, /**< Dedicated SARMUX port with 8 possible pins */
1294 CY_SAR_INJ_PORT_ADDR_CTB0 = 1UL << SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos, /**< Outputs from CTB0, if present */
1295 CY_SAR_INJ_PORT_ADDR_CTB1 = 2UL << SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos, /**< Outputs from CTB1, if present */
1296 CY_SAR_INJ_PORT_ADDR_CTB2 = 3UL << SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos, /**< Outputs from CTB2, if present */
1297 CY_SAR_INJ_PORT_ADDR_CTB3 = 4UL << SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos, /**< Outputs from CTB3, if present */
1298 CY_SAR_INJ_PORT_ADDR_AROUTE_VIRT = 6UL << SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos, /**< AROUTE virtual port (VPORT), if present */
1299 CY_SAR_INJ_PORT_ADDR_SARMUX_VIRT = 7UL << SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos, /**< SARMUX virtual port for DieTemp and AMUXBUSA/B */
1300 } cy_en_sar_inj_chan_config_port_addr_t;
1301
1302
1303 /* \} */
1304
1305 /** \cond left here for BWC, deprecated for new designs */
1306 typedef enum
1307 {
1308 CY_SAR_INTR_MASK_NONE = 0UL,
1309 CY_SAR_INTR_EOS_MASK = SAR_INTR_MASK_EOS_MASK_Msk,
1310 CY_SAR_INTR_OVERFLOW_MASK = SAR_INTR_MASK_OVERFLOW_MASK_Msk,
1311 CY_SAR_INTR_FW_COLLISION_MASK = SAR_INTR_MASK_FW_COLLISION_MASK_Msk,
1312 } cy_en_sar_intr_mask_t;
1313 /* \endcond */
1314
1315
1316 /** \addtogroup group_sar_mux_switch_register_enums
1317 * This set of enumerations aids in configuring the \ref group_sar_init_struct_muxSwitch and \ref group_sar_init_struct_muxSwitchSqCtrl registers
1318 * \{
1319 */
1320
1321 /** Firmware control for the SARMUX switches to connect analog signals to the SAR ADC
1322 *
1323 * To close multiple switches, "OR" the enum values together.
1324 *
1325 * See the \ref group_sar_sarmux section for more guidance.
1326 */
1327 typedef enum
1328 {
1329 /* SARMUX pins to Vplus */
1330 CY_SAR_MUX_FW_P0_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk, /**< Switch between Pin 0 of SARMUX and Vplus of SARADC */
1331 CY_SAR_MUX_FW_P1_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk, /**< Switch between Pin 1 of SARMUX and Vplus of SARADC */
1332 CY_SAR_MUX_FW_P2_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk, /**< Switch between Pin 2 of SARMUX and Vplus of SARADC */
1333 CY_SAR_MUX_FW_P3_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk, /**< Switch between Pin 3 of SARMUX and Vplus of SARADC */
1334 CY_SAR_MUX_FW_P4_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk, /**< Switch between Pin 4 of SARMUX and Vplus of SARADC */
1335 CY_SAR_MUX_FW_P5_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk, /**< Switch between Pin 5 of SARMUX and Vplus of SARADC */
1336 CY_SAR_MUX_FW_P6_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk, /**< Switch between Pin 6 of SARMUX and Vplus of SARADC */
1337 CY_SAR_MUX_FW_P7_VPLUS = SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk, /**< Switch between Pin 7 of SARMUX and Vplus of SARADC */
1338
1339 /* SARMUX pins to Vminus */
1340 CY_SAR_MUX_FW_P0_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk, /**< Switch between Pin 0 of SARMUX and Vminus of SARADC */
1341 CY_SAR_MUX_FW_P1_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk, /**< Switch between Pin 1 of SARMUX and Vminus of SARADC */
1342 CY_SAR_MUX_FW_P2_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk, /**< Switch between Pin 2 of SARMUX and Vminus of SARADC */
1343 CY_SAR_MUX_FW_P3_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk, /**< Switch between Pin 3 of SARMUX and Vminus of SARADC */
1344 CY_SAR_MUX_FW_P4_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk, /**< Switch between Pin 4 of SARMUX and Vminus of SARADC */
1345 CY_SAR_MUX_FW_P5_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk, /**< Switch between Pin 5 of SARMUX and Vminus of SARADC */
1346 CY_SAR_MUX_FW_P6_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk, /**< Switch between Pin 6 of SARMUX and Vminus of SARADC */
1347 CY_SAR_MUX_FW_P7_VMINUS = SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk, /**< Switch between Pin 7 of SARMUX and Vminus of SARADC */
1348
1349 /* Vssa to Vminus and temperature sensor to Vplus */
1350 CY_SAR_MUX_FW_VSSA_VMINUS = SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk, /**< Switch between VSSA and Vminus of SARADC */
1351 CY_SAR_MUX_FW_TEMP_VPLUS = SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk, /**< Switch between the DieTemp sensor and vplus of SARADC */
1352
1353 /* Amuxbus A and B to Vplus and Vminus */
1354 CY_SAR_MUX_FW_AMUXBUSA_VPLUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk, /**< Switch between AMUXBUSA and vplus of SARADC */
1355 CY_SAR_MUX_FW_AMUXBUSB_VPLUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk, /**< Switch between AMUXBUSB and vplus of SARADC */
1356 CY_SAR_MUX_FW_AMUXBUSA_VMINUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk, /**< Switch between AMUXBUSA and vminus of SARADC */
1357 CY_SAR_MUX_FW_AMUXBUSB_VMINUS = SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk, /**< Switch between AMUXBUSB and vminus of SARADC */
1358
1359 /* Sarbus 0 and 1 to Vplus and Vminus */
1360 CY_SAR_MUX_FW_SARBUS0_VPLUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk, /**< Switch between SARBUS0 and vplus of SARADC */
1361 CY_SAR_MUX_FW_SARBUS1_VPLUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk, /**< Switch between SARBUS1 and vplus of SARADC */
1362 CY_SAR_MUX_FW_SARBUS0_VMINUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk, /**< Switch between SARBUS0 and vminus of SARADC */
1363 CY_SAR_MUX_FW_SARBUS1_VMINUS = SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk, /**< Switch between SARBUS1 and vminus of SARADC */
1364
1365 /* SARMUX pins to Core IO */
1366 CY_SAR_MUX_FW_P4_COREIO0 = SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk, /**< Switch between Pin 4 of SARMUX and coreio0, if present */
1367 CY_SAR_MUX_FW_P5_COREIO1 = SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk, /**< Switch between Pin 5 of SARMUX and coreio1, if present */
1368 CY_SAR_MUX_FW_P6_COREIO2 = SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk, /**< Switch between Pin 6 of SARMUX and coreio2, if present */
1369 CY_SAR_MUX_FW_P7_COREIO3 = SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk, /**< Switch between Pin 7 of SARMUX and coreio3, if present */
1370 } cy_en_sar_mux_switch_fw_ctrl_t;
1371
1372 /** Mask definitions of SARMUX switches that can be controlled by the SARSEQ.
1373 *
1374 * To enable sequencer control of multiple switches, "OR" the enum values together.
1375 *
1376 * See the \ref group_sar_sarmux section for more guidance.
1377 */
1378 typedef enum
1379 {
1380 CY_SAR_MUX_SQ_CTRL_P0 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk, /**< Enable SARSEQ control of Pin 0 switches (for Vplus and Vminus) of SARMUX dedicated port */
1381 CY_SAR_MUX_SQ_CTRL_P1 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk, /**< Enable SARSEQ control of Pin 1 switches (for Vplus and Vminus) of SARMUX dedicated port */
1382 CY_SAR_MUX_SQ_CTRL_P2 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk, /**< Enable SARSEQ control of Pin 2 switches (for Vplus and Vminus) of SARMUX dedicated port */
1383 CY_SAR_MUX_SQ_CTRL_P3 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk, /**< Enable SARSEQ control of Pin 3 switches (for Vplus and Vminus) of SARMUX dedicated port */
1384 CY_SAR_MUX_SQ_CTRL_P4 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk, /**< Enable SARSEQ control of Pin 4 switches (for Vplus and Vminus) of SARMUX dedicated port */
1385 CY_SAR_MUX_SQ_CTRL_P5 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk, /**< Enable SARSEQ control of Pin 5 switches (for Vplus and Vminus) of SARMUX dedicated port */
1386 CY_SAR_MUX_SQ_CTRL_P6 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk, /**< Enable SARSEQ control of Pin 6 switches (for Vplus and Vminus) of SARMUX dedicated port */
1387 CY_SAR_MUX_SQ_CTRL_P7 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk, /**< Enable SARSEQ control of Pin 7 switches (for Vplus and Vminus) of SARMUX dedicated port */
1388 CY_SAR_MUX_SQ_CTRL_VSSA = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk, /**< Enable SARSEQ control of the switch between VSSA and Vminus */
1389 CY_SAR_MUX_SQ_CTRL_TEMP = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk, /**< Enable SARSEQ control of the switch between DieTemp and Vplus */
1390 CY_SAR_MUX_SQ_CTRL_AMUXBUSA = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk, /**< Enable SARSEQ control of AMUXBUSA switches (for Vplus and Vminus) */
1391 CY_SAR_MUX_SQ_CTRL_AMUXBUSB = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk, /**< Enable SARSEQ control of AMUXBUSB switches (for Vplus and Vminus) */
1392 CY_SAR_MUX_SQ_CTRL_SARBUS0 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk, /**< Enable SARSEQ control of SARBUS0 switches (for Vplus and Vminus) */
1393 CY_SAR_MUX_SQ_CTRL_SARBUS1 = SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk, /**< Enable SARSEQ control of SARBUS1 switches (for Vplus and Vminus) */
1394 } cy_en_sar_mux_switch_sq_ctrl_t;
1395
1396 /* \} */
1397
1398
1399 /** For PASS_V2 the SAR clock can come from:
1400 * - one of the CLK_PERI dividers
1401 * - PASS Deep Sleep Clock (CLK_DPSLP)
1402 */
1403 typedef enum
1404 {
1405 CY_SAR_CLK_PERI = 0UL, /**< SAR clock source is one of \ref group_sysclk "PERI" dividers (SAR is only operational in chip ACTIVE mode) */
1406 CY_SAR_CLK_DEEPSLEEP = 1UL /**< SAR clock source is \ref group_sysanalog_dpslp "CLK_DPSLP" (SAR can be operational in both chip ACTIVE and DEEPSLEEP modes) */
1407 } cy_en_sar_clock_source_t;
1408
1409 /** Definitions for simultaneous scan trigger signal event selection */
1410 typedef enum
1411 {
1412 CY_SAR_SIMULT_TRIG_EVENT_EDGE = 0UL, /**< Positive edge detected on the trigger signal triggers a new scan */
1413 CY_SAR_SIMULT_TRIG_EVENT_LEVEL = 1UL, /**< SAR will do continuous scans as long as the trigger signal remains high */
1414 } cy_en_sar_simult_trig_event_sel_t;
1415
1416 /** Definitions for simultaneous scan trigger synchronization */
1417 typedef enum
1418 {
1419 CY_SAR_SIMULT_TRIG_SYNC_NONE = 0UL, /**< Bypass clock domain synchronization of the simultaneous trigger signal */
1420 CY_SAR_SIMULT_TRIG_SYNC_SAR_CLOCK = 1UL, /**< Synchronize the simultaneous trigger signal to the SAR clock domain */
1421 } cy_en_sar_simult_trig_sync_sel_t;
1422
1423 /** Definitions for simultaneous scan sampling mode */
1424 typedef enum
1425 {
1426 CY_SAR_SIMULT_TRIG_SAMPLE_SINGLE = 0UL, /**< Perform single scan on the trigger event */
1427 CY_SAR_SIMULT_TRIG_SAMPLE_SCAN_CNT = 1UL, /**< On the trigger event perform number of scans, specified by scanCount */
1428 } cy_en_sar_simult_trig_sample_sel_t;
1429
1430 /** Definitions for simultaneous scan interrupt generation */
1431 typedef enum
1432 {
1433 CY_SAR_SIMULT_TRIG_INTR_EOS = 0UL, /**< Generate interrupt on each End of Sample event */
1434 CY_SAR_SIMULT_TRIG_INTR_SCAN_CNT = 1UL, /**< Generate interrupt on End of Sample event only when sample number = scanCount */
1435 }cy_en_sar_simult_trig_intr_sel_t;
1436
1437 /** \} group_sar_enums */
1438
1439 /** \addtogroup group_sar_data_structures
1440 * \{
1441 */
1442
1443 /***************************************
1444 * Configuration Structures
1445 ***************************************/
1446
1447 /** FIFO configuration structure **/
1448 typedef struct
1449 {
1450 bool chanId; /**< Enable the channel ID in the results */
1451 bool chainToNext; /**< Chain the FIFO to the next FIFO */
1452 bool clrTrIntrOnRead; /**< Enable the FIFO level trigger (and optional level interrupt) clearing on FIFO read */
1453 uint32_t level; /**< A trigger (and optional interrupt) event occurs when the number of FIFO entries overcomes the Level setting. Range: 1..256 */
1454 bool trOut; /**< SAR output trigger is set by the 'level' condition */
1455 } cy_stc_sar_fifo_config_t;
1456
1457
1458 /** This structure is used to initialize the SAR ADC subsystem.
1459 *
1460 * The SAR ADC subsystem is highly configurable with many options.
1461 * When calling \ref Cy_SAR_Init, provide a pointer to the structure containing this configuration data.
1462 * A set of enumerations is provided in this
1463 * driver to help with configuring this structure.
1464 *
1465 * See the \ref group_sar_initialization section for guidance.
1466 **/
1467 typedef struct
1468 {
1469 uint32_t ctrl; /**< Control register settings (applies to all channels) */
1470 uint32_t sampleCtrl; /**< Sample control register settings (applies to all channels) */
1471 uint32_t sampleTime01; /**< Sample time in ADC clocks for Sample Time 0 and 1 */
1472 uint32_t sampleTime23; /**< Sample time in ADC clocks for Sample Time 2 and 3 */
1473 uint32_t rangeThres; /**< Range detect threshold register for all channels */
1474 cy_en_sar_range_detect_condition_t rangeCond; /**< Range detect condition (below, inside, output, or above) for all channels */
1475 uint32_t chanEn; /**< Enable bits for the channels */
1476 uint32_t chanConfig[CY_SAR_NUM_CHANNELS]; /**< Channel configuration */
1477 uint32_t intrMask; /**< Interrupt enable mask */
1478 uint32_t satIntrMask; /**< Saturation detection interrupt enable mask */
1479 uint32_t rangeIntrMask; /**< Range detection interrupt enable mask */
1480 uint32_t muxSwitch; /**< SARMUX firmware switches to connect analog signals to SAR */
1481 uint32_t muxSwitchSqCtrl; /**< Enable SARSEQ control of specific SARMUX switches */
1482 bool configRouting; /**< Configure or ignore routing related registers (muxSwitch, muxSwitchSqCtrl) */
1483 uint32_t vrefMvValue; /**< Reference voltage in millivolts used in converting counts to volts */
1484 cy_en_sar_clock_source_t clock; /**< Clock source selection (enable/disable SAR operation in the Deep Sleep mode). Ignored for PASS_ver1. */
1485 cy_stc_sar_fifo_config_t const * fifoCfgPtr; /**< Pointer to the FIFO configuration structure \ref cy_stc_sar_fifo_config_t, if NULL - the FIFO is not used. Should be NULL for PASS_ver1. */
1486 bool trTimer; /**< SAR is being triggered from the Timer \ref group_sysanalog_timer . Ignored for PASS_ver1. */
1487 bool scanCnt; /**< Enable the scanning counter, configured by \ref Cy_SAR_CommonInit. Ignored for PASS_ver1. */
1488 bool scanCntIntr; /**< EOS interrupt on scanning counter event. Ignored for PASS_ver1. */
1489 } cy_stc_sar_config_t;
1490
1491 /** SAR triggering configuration structure */
1492 typedef struct
1493 {
1494 uint32_t pwrUpDelay; /**< Power up delay for SAR blocks in Deep Sleep Clock cycles. Range 0..255. */
1495 uint32_t scanCount; /**< Configures the number of samples SAR will take when triggered. Range 1..256. */
1496 uint32_t simultControl; /**< Configures the SAR ADCs for simultaneous control. The value is a combined mask, created using following macros:
1497 * - CY_SAR_SAR0
1498 * - CY_SAR_SAR1
1499 * - CY_SAR_SAR2
1500 * - CY_SAR_SAR3
1501 * See \ref group_sysanalog_sar_select
1502 */
1503 uint32_t simultTrigSource; /**< Configures the trigger source for simultaneous SAR hardware trigger. Use one of the following values:
1504 * - CY_SAR_SAR0
1505 * - CY_SAR_SAR1
1506 * - CY_SAR_SAR2
1507 * - CY_SAR_SAR3
1508 * - CY_SAR_TIMER
1509 * See \ref group_sysanalog_sar_select
1510 */
1511 cy_en_sar_simult_trig_event_sel_t simultTrigEvent; /**< Configures simultaneous trigger signal event */
1512 cy_en_sar_simult_trig_sync_sel_t simultTrigSync; /**< Enables synchronization of trigger signal */
1513 cy_en_sar_simult_trig_sample_sel_t simultSamplesPerTrigger; /**< Configures scan sampling mode for each trigger event */
1514 cy_en_sar_simult_trig_intr_sel_t simultEOSIntrSelect; /**< Configures EOS interrupt condition */
1515 }cy_stc_sar_common_config_t ;
1516
1517 /** This structure is used by the driver to backup the state of the SAR
1518 * before entering sleep so that it can be re-enabled after waking up */
1519 typedef struct
1520 {
1521 uint32_t hwEnabled; /**< SAR enabled state */
1522 uint32_t continuous; /**< State of the continuous bit */
1523 } cy_stc_sar_state_backup_t;
1524
1525 /** Structure to read the FIFO buffer */
1526 typedef struct
1527 {
1528 uint16_t value; /**< SAR sample */
1529 uint16_t channel; /**< SAR channel */
1530 } cy_stc_sar_fifo_read_t;
1531
1532 /** \} group_sar_data_structures */
1533
1534 /** \addtogroup group_sar_functions
1535 * \{
1536 */
1537
1538 /** This macro is for backward compatibility macro for driver v1.10 and before,
1539 * the preferred API is \ref Cy_SAR_DeepSleep */
1540 #define Cy_SAR_Sleep Cy_SAR_DeepSleep
1541
1542 /***************************************
1543 * Function Prototypes
1544 ***************************************/
1545
1546 /** \addtogroup group_sar_functions_trig
1547 * This set of functions is for initialization and usage of SAR common settings
1548 * and simultaneous triggering.
1549 * \{
1550 */
1551 cy_en_sar_status_t Cy_SAR_CommonInit(PASS_Type *base, const cy_stc_sar_common_config_t * trigConfig);
1552 __STATIC_INLINE void Cy_SAR_SimultStart(PASS_Type *base, uint32_t sarMask, cy_en_sar_start_convert_sel_t mode);
1553 __STATIC_INLINE void Cy_SAR_SimultStop(PASS_Type *base, uint32_t sarMask);
1554 /** \} */
1555
1556
1557 /** \addtogroup group_sar_functions_basic
1558 * This set of functions is for initialization and basic usage
1559 * \{
1560 */
1561 cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config);
1562 cy_en_sar_status_t Cy_SAR_DeInit(SAR_Type *base, bool deInitRouting);
1563 void Cy_SAR_Enable(SAR_Type *base);
1564 void Cy_SAR_Disable(SAR_Type *base);
1565 void Cy_SAR_StartConvert(SAR_Type *base, cy_en_sar_start_convert_sel_t startSelect);
1566 void Cy_SAR_StopConvert(SAR_Type *base);
1567 cy_en_sar_status_t Cy_SAR_IsEndConversion(SAR_Type *base, cy_en_sar_return_mode_t retMode);
1568 int16_t Cy_SAR_GetResult16(const SAR_Type *base, uint32_t chan);
1569 int32_t Cy_SAR_GetResult32(const SAR_Type *base, uint32_t chan);
1570 __STATIC_INLINE uint32_t Cy_SAR_GetChanResultUpdated(const SAR_Type *base);
1571 __STATIC_INLINE void Cy_SAR_EnableInjection(SAR_Type *base, bool tailgating);
1572 /** \} */
1573
1574 /** \addtogroup group_sar_functions_power
1575 * This set of functions is for Deep Sleep entry and exit
1576 * \{
1577 */
1578 cy_en_syspm_status_t Cy_SAR_DeepSleepCallback(const cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode);
1579 void Cy_SAR_DeepSleep(SAR_Type *base);
1580 void Cy_SAR_Wakeup(SAR_Type *base);
1581 /** \} */
1582
1583 /** \addtogroup group_sar_functions_config
1584 * This set of functions allows changes to the SAR configuration
1585 * after initialization.
1586 * \{
1587 */
1588 void Cy_SAR_SetConvertMode(SAR_Type *base, cy_en_sar_sample_ctrl_trigger_mode_t mode);
1589 __STATIC_INLINE void Cy_SAR_SetChanMask(SAR_Type *base, uint32_t enableMask);
1590 void Cy_SAR_SetLowLimit(SAR_Type *base, uint32_t lowLimit);
1591 void Cy_SAR_SetHighLimit(SAR_Type *base, uint32_t highLimit);
1592 __STATIC_INLINE void Cy_SAR_SetRangeCond(SAR_Type *base, cy_en_sar_range_detect_condition_t cond);
1593 /** \} */
1594
1595 /** \addtogroup group_sar_functions_countsto
1596 * This set of functions performs counts to *volts conversions.
1597 * \{
1598 */
1599 int16_t Cy_SAR_RawCounts2Counts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
1600 float32_t Cy_SAR_CountsTo_Volts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
1601 int16_t Cy_SAR_CountsTo_mVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
1602 int32_t Cy_SAR_CountsTo_uVolts(const SAR_Type *base, uint32_t chan, int16_t adcCounts);
1603 cy_en_sar_status_t Cy_SAR_SetChannelOffset(const SAR_Type *base, uint32_t chan, int16_t offset);
1604 cy_en_sar_status_t Cy_SAR_SetChannelGain(const SAR_Type *base, uint32_t chan, int32_t adcGain);
1605 /** \} */
1606
1607
1608 /** \cond
1609 * Deprecated functions
1610 * Don't support multi-instance
1611 * For existing projects the mapping is on SAR0 instance
1612 * Strongly not recommended for new designs
1613 * Use Cy_SAR_SetChannelOffset and Cy_SAR_SetChannelGain instead
1614 */
Cy_SAR_SetOffset(uint32_t chan,int16_t offset)1615 __STATIC_INLINE cy_en_sar_status_t Cy_SAR_SetOffset(uint32_t chan, int16_t offset)
1616 {
1617 return (Cy_SAR_SetChannelOffset(CY_SAR0_BASE, chan, offset));
1618 }
1619
Cy_SAR_SetGain(uint32_t chan,int32_t adcGain)1620 __STATIC_INLINE cy_en_sar_status_t Cy_SAR_SetGain(uint32_t chan, int32_t adcGain)
1621 {
1622 return (Cy_SAR_SetChannelGain(CY_SAR0_BASE, chan, adcGain));
1623 }
1624 /** \endcond */
1625
1626
1627 /** \addtogroup group_sar_functions_switches
1628 * This set of functions is for controlling/querying the SARMUX switches
1629 * \{
1630 */
1631 void Cy_SAR_SetAnalogSwitch(SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect, uint32_t switchMask, cy_en_sar_switch_state_t state);
1632 uint32_t Cy_SAR_GetAnalogSwitch(const SAR_Type *base, cy_en_sar_switch_register_sel_t switchSelect);
1633 __STATIC_INLINE void Cy_SAR_SetVssaVminusSwitch(SAR_Type *base, cy_en_sar_switch_state_t state);
1634 void Cy_SAR_SetSwitchSarSeqCtrl(SAR_Type *base, uint32_t switchMask, cy_en_sar_switch_sar_seq_ctrl_t ctrl);
1635 __STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_sar_seq_ctrl_t ctrl);
1636 /** \} */
1637
1638 /** \addtogroup group_sar_functions_interrupt
1639 * This set of functions are related to SAR interrupts.
1640 * \{
1641 */
1642 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatus(const SAR_Type *base);
1643 __STATIC_INLINE void Cy_SAR_ClearInterrupt(SAR_Type *base, uint32_t intrMask);
1644 __STATIC_INLINE void Cy_SAR_SetInterrupt(SAR_Type *base, uint32_t intrMask);
1645 __STATIC_INLINE void Cy_SAR_SetInterruptMask(SAR_Type *base, uint32_t intrMask);
1646 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptMask(const SAR_Type *base);
1647 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatusMasked(const SAR_Type *base);
1648
1649 __STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatus(const SAR_Type *base);
1650 __STATIC_INLINE void Cy_SAR_ClearRangeInterrupt(SAR_Type *base, uint32_t chanMask);
1651 __STATIC_INLINE void Cy_SAR_SetRangeInterrupt(SAR_Type *base, uint32_t chanMask);
1652 __STATIC_INLINE void Cy_SAR_SetRangeInterruptMask(SAR_Type *base, uint32_t chanMask);
1653 __STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptMask(const SAR_Type *base);
1654 __STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatusMasked(const SAR_Type *base);
1655
1656 __STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatus(const SAR_Type *base);
1657 __STATIC_INLINE void Cy_SAR_ClearSatInterrupt(SAR_Type *base, uint32_t chanMask);
1658 __STATIC_INLINE void Cy_SAR_SetSatInterrupt(SAR_Type *base, uint32_t chanMask);
1659 __STATIC_INLINE void Cy_SAR_SetSatInterruptMask(SAR_Type *base, uint32_t chanMask);
1660 __STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptMask(const SAR_Type *base);
1661 __STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatusMasked(const SAR_Type *base);
1662
1663 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptCause(const SAR_Type *base);
1664 /** \} */
1665
1666
1667 /** \addtogroup group_sar_functions_helper
1668 * This set of functions is for useful configuration query
1669 * \{
1670 */
1671 bool Cy_SAR_IsChannelSigned(const SAR_Type *base, uint32_t chan);
1672 bool Cy_SAR_IsChannelSingleEnded(const SAR_Type *base, uint32_t chan);
1673 __STATIC_INLINE bool Cy_SAR_IsChannelDifferential(const SAR_Type *base, uint32_t chan);
1674 /** \} */
1675
1676 /** \addtogroup group_sar_functions_lp
1677 * \{
1678 */
1679
1680 cy_en_sar_status_t Cy_SAR_ScanCountEnable(const SAR_Type * base);
1681 __STATIC_INLINE void Cy_SAR_ScanCountDisable(const SAR_Type * base);
1682 __STATIC_INLINE void Cy_SAR_SelectClock(const SAR_Type * base, cy_en_sar_clock_source_t clock);
1683 /** \} */
1684
1685
1686 /** \addtogroup group_sar_functions_fifo
1687 * \{
1688 */
1689 __STATIC_INLINE void Cy_SAR_FifoRead(const SAR_Type *base, cy_stc_sar_fifo_read_t * readStruct);
1690 __STATIC_INLINE uint32_t Cy_SAR_FifoGetDataCount(const SAR_Type *base);
1691 __STATIC_INLINE void Cy_SAR_FifoSetLevel(const SAR_Type *base, uint32_t level);
1692 __STATIC_INLINE void Cy_SAR_ClearFifoInterrupt(const SAR_Type *base, uint32_t intrMask);
1693 __STATIC_INLINE void Cy_SAR_SetFifoInterrupt(const SAR_Type *base, uint32_t intrMask);
1694 __STATIC_INLINE void Cy_SAR_SetFifoInterruptMask(const SAR_Type *base, uint32_t intrMask);
1695 __STATIC_INLINE uint32_t Cy_SAR_GetFifoInterruptStatus(const SAR_Type *base);
1696 __STATIC_INLINE uint32_t Cy_SAR_GetFifoInterruptMask(const SAR_Type *base);
1697 __STATIC_INLINE uint32_t Cy_SAR_GetFifoInterruptStatusMasked(const SAR_Type *base);
1698 /** \} */
1699
1700 /** \addtogroup group_sar_functions_basic
1701 * \{
1702 */
1703
1704
1705 /*******************************************************************************
1706 * Function Name: Cy_SAR_GetChanResultUpdated
1707 ****************************************************************************//**
1708 *
1709 * Return whether the RESULT register has been updated or not.
1710 * If the bit is high, the corresponding channel RESULT register was updated,
1711 * i.e. was sampled during the previous scan and, in case of Interleaved averaging,
1712 * reached the averaging count.
1713 * If the bit is low, the corresponding channel is not enabled or the averaging count
1714 * is not yet reached for Interleaved averaging.
1715 *
1716 * \param base
1717 * Pointer to structure describing registers
1718 *
1719 * \return
1720 * Each bit of the result corresponds to the channel.
1721 * Bit 0 is for channel 0, etc.
1722 *
1723 * \funcusage
1724 *
1725 * \snippet sar/snippet/main.c SNIPPET_SAR_GET_CHAN_RESULT_UPDATED
1726 *
1727 *******************************************************************************/
Cy_SAR_GetChanResultUpdated(const SAR_Type * base)1728 __STATIC_INLINE uint32_t Cy_SAR_GetChanResultUpdated(const SAR_Type *base)
1729 {
1730 return SAR_CHAN_RESULT_UPDATED(base);
1731 }
1732
1733
1734 /*******************************************************************************
1735 * Function Name: Cy_SAR_EnableInjection
1736 ****************************************************************************//**
1737 *
1738 * Triggers the injection channel sample.
1739 *
1740 * \param base
1741 * Pointer to structure describing registers
1742 *
1743 * \param tailgating
1744 * Injection channel tailgating enable:
1745 * - true: The addressed pin is sampled after the next trigger and after all enabled channels have been scanned.
1746 * - false: SAR is immediately triggered when the SAR is not busy.
1747 * If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan.
1748 *
1749 * \funcusage \snippet sar/snippet/main.c SNIPPET_SAR_IS_END_CONVERSION
1750 *
1751 *******************************************************************************/
Cy_SAR_EnableInjection(SAR_Type * base,bool tailgating)1752 __STATIC_INLINE void Cy_SAR_EnableInjection(SAR_Type *base, bool tailgating)
1753 {
1754 SAR_INJ_CHAN_CONFIG(base) = _CLR_SET_FLD32U(SAR_INJ_CHAN_CONFIG(base), SAR_INJ_CHAN_CONFIG_INJ_TAILGATING, tailgating ? 1UL : 0UL) | SAR_INJ_CHAN_CONFIG_INJ_START_EN_Msk;
1755 }
1756
1757
1758 /** \} */
1759
1760 /** \addtogroup group_sar_functions_config
1761 * \{
1762 */
1763
1764
1765 /*******************************************************************************
1766 * Function Name: Cy_SAR_SetChanMask
1767 ****************************************************************************//**
1768 *
1769 * Set the enable/disable mask for the channels.
1770 *
1771 * \param base
1772 * Pointer to structure describing registers
1773 *
1774 * \param enableMask
1775 * Channel enable/disable mask. Each bit corresponds to a channel.
1776 * - 0: the corresponding channel is disabled.
1777 * - 1: the corresponding channel is enabled; it will be included in the next scan.
1778 *
1779 * \return None
1780 *
1781 * \funcusage
1782 *
1783 * \snippet sar/snippet/main.c SNIPPET_SAR_SET_CHAN_MASK
1784 *
1785 *******************************************************************************/
Cy_SAR_SetChanMask(SAR_Type * base,uint32_t enableMask)1786 __STATIC_INLINE void Cy_SAR_SetChanMask(SAR_Type *base, uint32_t enableMask)
1787 {
1788 CY_ASSERT_L2(CY_SAR_CHANMASK(enableMask));
1789
1790 SAR_CHAN_EN(base) = enableMask;
1791 }
1792
1793
1794 /*******************************************************************************
1795 * Function Name: Cy_SAR_SetRangeCond
1796 ****************************************************************************//**
1797 *
1798 * Set the condition in which range detection interrupts are triggered.
1799 *
1800 * \param base
1801 * Pointer to structure describing registers
1802 *
1803 * \param cond
1804 * A value of the enum \ref cy_en_sar_range_detect_condition_t.
1805 *
1806 * \return None
1807 *
1808 * \funcusage
1809 *
1810 * \snippet sar/snippet/main.c SNIPPET_SAR_SET_RANGE_COND
1811 *
1812 *******************************************************************************/
Cy_SAR_SetRangeCond(SAR_Type * base,cy_en_sar_range_detect_condition_t cond)1813 __STATIC_INLINE void Cy_SAR_SetRangeCond(SAR_Type *base, cy_en_sar_range_detect_condition_t cond)
1814 {
1815 CY_ASSERT_L3(CY_SAR_RANGECOND(cond));
1816
1817 SAR_RANGE_COND(base) = (uint32_t)cond << SAR_RANGE_COND_RANGE_COND_Pos;
1818 }
1819
1820 /** \} */
1821
1822 /** \addtogroup group_sar_functions_interrupt
1823 * \{
1824 */
1825 /*******************************************************************************
1826 * Function Name: Cy_SAR_GetInterruptStatus
1827 ****************************************************************************//**
1828 *
1829 * Return the interrupt register status.
1830 *
1831 * \param base
1832 * Pointer to structure describing registers
1833 *
1834 * \return Interrupt status
1835 *
1836 * \funcusage
1837 *
1838 * \snippet sar/snippet/main.c SNIPPET_SAR_ISR
1839 *
1840 *******************************************************************************/
Cy_SAR_GetInterruptStatus(const SAR_Type * base)1841 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatus(const SAR_Type *base)
1842 {
1843 return SAR_INTR(base);
1844 }
1845
1846
1847 /*******************************************************************************
1848 * Function Name: Cy_SAR_ClearInterrupt
1849 ****************************************************************************//**
1850 *
1851 * Clear the interrupt.
1852 * The interrupt must be cleared with this function so that the hardware
1853 * can set subsequent interrupts and those interrupts can be forwarded
1854 * to the interrupt controller, if enabled.
1855 *
1856 * \param base
1857 * Pointer to structure describing registers
1858 *
1859 * \param intrMask
1860 * The mask of interrupts to clear. Typically this will be the value returned
1861 * from \ref Cy_SAR_GetInterruptStatus.
1862 * Alternately, select one or more values from \ref group_sar_macros_interrupt and "OR" them together.
1863 * - \ref CY_SAR_INTR_EOS
1864 * - \ref CY_SAR_INTR_OVERFLOW
1865 * - \ref CY_SAR_INTR_FW_COLLISION
1866 * - \ref CY_SAR_INTR_INJ_EOC
1867 * - \ref CY_SAR_INTR_INJ_SATURATE
1868 * - \ref CY_SAR_INTR_INJ_RANGE
1869 * - \ref CY_SAR_INTR_INJ_COLLISION
1870 *
1871 * \return None
1872 *
1873 *******************************************************************************/
Cy_SAR_ClearInterrupt(SAR_Type * base,uint32_t intrMask)1874 __STATIC_INLINE void Cy_SAR_ClearInterrupt(SAR_Type *base, uint32_t intrMask)
1875 {
1876 CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask));
1877 SAR_INTR(base) = intrMask & CY_SAR_INTR;
1878 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
1879 (void) SAR_INTR(base);
1880 }
1881
1882
1883 /*******************************************************************************
1884 * Function Name: Cy_SAR_SetInterrupt
1885 ****************************************************************************//**
1886 *
1887 * Trigger an interrupt with software.
1888 *
1889 * \param base
1890 * Pointer to structure describing registers
1891 *
1892 * \param intrMask
1893 * The mask of interrupts to set.
1894 * Select one or more values from \ref group_sar_macros_interrupt and "OR" them together.
1895 * - \ref CY_SAR_INTR_EOS
1896 * - \ref CY_SAR_INTR_OVERFLOW
1897 * - \ref CY_SAR_INTR_FW_COLLISION
1898 * - \ref CY_SAR_INTR_INJ_EOC
1899 * - \ref CY_SAR_INTR_INJ_SATURATE
1900 * - \ref CY_SAR_INTR_INJ_RANGE
1901 * - \ref CY_SAR_INTR_INJ_COLLISION
1902 *
1903 * \return None
1904 *
1905 *******************************************************************************/
Cy_SAR_SetInterrupt(SAR_Type * base,uint32_t intrMask)1906 __STATIC_INLINE void Cy_SAR_SetInterrupt(SAR_Type *base, uint32_t intrMask)
1907 {
1908 CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask));
1909
1910 SAR_INTR_SET(base) = intrMask & CY_SAR_INTR;
1911 }
1912
1913
1914 /*******************************************************************************
1915 * Function Name: Cy_SAR_SetInterruptMask
1916 ****************************************************************************//**
1917 *
1918 * Enable which interrupts can trigger the CPU interrupt controller.
1919 *
1920 * \param base
1921 * Pointer to structure describing registers
1922 *
1923 * \param intrMask
1924 * The mask of interrupts. Select one or more values from \ref group_sar_macros_interrupt
1925 * and "OR" them together:
1926 * - \ref CY_SAR_INTR_EOS
1927 * - \ref CY_SAR_INTR_OVERFLOW
1928 * - \ref CY_SAR_INTR_FW_COLLISION
1929 * - \ref CY_SAR_INTR_INJ_EOC
1930 * - \ref CY_SAR_INTR_INJ_SATURATE
1931 * - \ref CY_SAR_INTR_INJ_RANGE
1932 * - \ref CY_SAR_INTR_INJ_COLLISION
1933 *
1934 * \return None
1935 *
1936 * \funcusage
1937 *
1938 * \snippet sar/snippet/main.c SNIPPET_SAR_SET_INTERRUPT_MASK
1939 *
1940 *******************************************************************************/
Cy_SAR_SetInterruptMask(SAR_Type * base,uint32_t intrMask)1941 __STATIC_INLINE void Cy_SAR_SetInterruptMask(SAR_Type *base, uint32_t intrMask)
1942 {
1943 CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask));
1944
1945 SAR_INTR_MASK(base) = intrMask & CY_SAR_INTR;
1946 }
1947
1948
1949 /*******************************************************************************
1950 * Function Name: Cy_SAR_GetInterruptMask
1951 ****************************************************************************//**
1952 *
1953 * Return which interrupts can trigger the CPU interrupt controller
1954 * as configured by \ref Cy_SAR_SetInterruptMask.
1955 *
1956 * \param base
1957 * Pointer to structure describing registers
1958 *
1959 * \return
1960 * Interrupt mask. Compare this value with masks in \ref group_sar_macros_interrupt.
1961 *
1962 * \funcusage
1963 *
1964 * \snippet sar/snippet/main.c SNIPPET_SAR_GET_INTERRUPT_MASK
1965 *
1966 *******************************************************************************/
Cy_SAR_GetInterruptMask(const SAR_Type * base)1967 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptMask(const SAR_Type *base)
1968 {
1969 return SAR_INTR_MASK(base);
1970 }
1971
1972
1973 /*******************************************************************************
1974 * Function Name: Cy_SAR_GetInterruptStatusMasked
1975 ****************************************************************************//**
1976 *
1977 * Return the bitwise AND between the interrupt request and mask registers.
1978 * See \ref Cy_SAR_GetInterruptStatus and \ref Cy_SAR_GetInterruptMask.
1979 *
1980 * \param base
1981 * Pointer to structure describing registers
1982 *
1983 * \return
1984 * Bitwise AND of the interrupt request and mask registers
1985 *
1986 *******************************************************************************/
Cy_SAR_GetInterruptStatusMasked(const SAR_Type * base)1987 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptStatusMasked(const SAR_Type *base)
1988 {
1989 return SAR_INTR_MASKED(base);
1990 }
1991
1992
1993 /*******************************************************************************
1994 * Function Name: Cy_SAR_GetRangeInterruptStatus
1995 ****************************************************************************//**
1996 *
1997 * Return the range interrupt register status.
1998 * If the status bit is low for a channel, the channel may not be enabled
1999 * (\ref Cy_SAR_SetChanMask), range detection is not enabled for the
2000 * channel (\ref Cy_SAR_SetRangeInterruptMask), or range detection was not
2001 * triggered for the channel.
2002 *
2003 * \param base
2004 * Pointer to structure describing registers
2005 *
2006 * \return
2007 * The range interrupt status for all channels. Bit 0 is for channel 0, etc.
2008 *
2009 * \funcusage
2010 *
2011 * \snippet sar/snippet/main.c SNIPPET_SAR_GET_RANGE_INTERRUPT_STATUS
2012 *
2013 *******************************************************************************/
Cy_SAR_GetRangeInterruptStatus(const SAR_Type * base)2014 __STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatus(const SAR_Type *base)
2015 {
2016 return SAR_RANGE_INTR(base);
2017 }
2018
2019
2020 /*******************************************************************************
2021 * Function Name: Cy_SAR_ClearRangeInterrupt
2022 ****************************************************************************//**
2023 *
2024 * Clear the range interrupt for the specified channel mask.
2025 * The interrupt must be cleared with this function so that
2026 * the hardware can set subset interrupts and those interrupts can
2027 * be forwarded to the interrupt controller, if enabled.
2028 *
2029 * \param base
2030 * Pointer to structure describing registers
2031 *
2032 * \param chanMask
2033 * The channel mask. Bit 0 is for channel 0, etc.
2034 * Typically, this is the value returned from \ref Cy_SAR_GetRangeInterruptStatus.
2035 *
2036 * \return None
2037 *
2038 *******************************************************************************/
Cy_SAR_ClearRangeInterrupt(SAR_Type * base,uint32_t chanMask)2039 __STATIC_INLINE void Cy_SAR_ClearRangeInterrupt(SAR_Type *base, uint32_t chanMask)
2040 {
2041 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
2042
2043 SAR_RANGE_INTR(base) = chanMask & CY_SAR_CHANNELS_MASK;
2044
2045 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
2046 (void) SAR_RANGE_INTR(base);
2047 }
2048
2049
2050 /*******************************************************************************
2051 * Function Name: Cy_SAR_SetRangeInterrupt
2052 ****************************************************************************//**
2053 *
2054 * Trigger a range interrupt with software for the specific channel mask.
2055 *
2056 * \param base
2057 * Pointer to structure describing registers
2058 *
2059 * \param chanMask
2060 * The channel mask. Bit 0 is for channel 0, etc.
2061 *
2062 * \return None
2063 *
2064 *******************************************************************************/
Cy_SAR_SetRangeInterrupt(SAR_Type * base,uint32_t chanMask)2065 __STATIC_INLINE void Cy_SAR_SetRangeInterrupt(SAR_Type *base, uint32_t chanMask)
2066 {
2067 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
2068
2069 SAR_RANGE_INTR_SET(base) = chanMask & CY_SAR_CHANNELS_MASK;
2070 }
2071
2072
2073 /*******************************************************************************
2074 * Function Name: Cy_SAR_SetRangeInterruptMask
2075 ****************************************************************************//**
2076 *
2077 * Enable which channels can trigger a range interrupt.
2078 *
2079 * \param base
2080 * Pointer to structure describing registers
2081 *
2082 * \param chanMask
2083 * The channel mask. Bit 0 is for channel 0, etc.
2084 *
2085 * \return None
2086 *
2087 * \funcusage
2088 *
2089 * \snippet sar/snippet/main.c SNIPPET_SAR_SET_RANGE_INTERRUPT_MASK
2090 *
2091 *******************************************************************************/
Cy_SAR_SetRangeInterruptMask(SAR_Type * base,uint32_t chanMask)2092 __STATIC_INLINE void Cy_SAR_SetRangeInterruptMask(SAR_Type *base, uint32_t chanMask)
2093 {
2094 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
2095
2096 SAR_RANGE_INTR_MASK(base) = chanMask & CY_SAR_CHANNELS_MASK;
2097 }
2098
2099
2100 /*******************************************************************************
2101 * Function Name: Cy_SAR_GetRangeInterruptMask
2102 ****************************************************************************//**
2103 *
2104 * Return which interrupts can trigger a range interrupt as configured by
2105 * \ref Cy_SAR_SetRangeInterruptMask.
2106 *
2107 * \param base
2108 * Pointer to structure describing registers
2109 *
2110 * \return
2111 * The range interrupt mask
2112 *
2113 *******************************************************************************/
Cy_SAR_GetRangeInterruptMask(const SAR_Type * base)2114 __STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptMask(const SAR_Type *base)
2115 {
2116 return SAR_RANGE_INTR_MASK(base);
2117 }
2118
2119
2120 /*******************************************************************************
2121 * Function Name: Cy_SAR_GetRangeInterruptStatusMasked
2122 ****************************************************************************//**
2123 *
2124 * Return the bitwise AND between the range interrupt request and mask registers.
2125 * See \ref Cy_SAR_GetRangeInterruptStatus and \ref Cy_SAR_GetRangeInterruptMask.
2126 *
2127 * \param base
2128 * Pointer to structure describing registers
2129 *
2130 * \return
2131 * Bitwise AND between of range interrupt request and mask
2132 *
2133 *******************************************************************************/
Cy_SAR_GetRangeInterruptStatusMasked(const SAR_Type * base)2134 __STATIC_INLINE uint32_t Cy_SAR_GetRangeInterruptStatusMasked(const SAR_Type *base)
2135 {
2136 return SAR_RANGE_INTR_MASKED(base);
2137 }
2138
2139
2140 /*******************************************************************************
2141 * Function Name: Cy_SAR_GetSatInterruptStatus
2142 ****************************************************************************//**
2143 *
2144 * Return the saturate interrupt register status.
2145 * If the status bit is low for a channel, the channel may not be enabled
2146 * (\ref Cy_SAR_SetChanMask), saturation detection is not enabled for the
2147 * channel (\ref Cy_SAR_SetSatInterruptMask), or saturation detection was not
2148 * triggered for the channel.
2149 *
2150 * \param base
2151 * Pointer to structure describing registers
2152 *
2153 * \return
2154 * The saturate interrupt status for all channels. Bit 0 is for channel 0, etc.
2155 *
2156 * \funcusage
2157 *
2158 * \snippet sar/snippet/main.c SNIPPET_SAR_GET_SAT_INTERRUPT_STATUS
2159 *
2160 *******************************************************************************/
Cy_SAR_GetSatInterruptStatus(const SAR_Type * base)2161 __STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatus(const SAR_Type *base)
2162 {
2163 return SAR_SATURATE_INTR(base);
2164 }
2165
2166
2167 /*******************************************************************************
2168 * Function Name: Cy_SAR_ClearSatInterrupt
2169 ****************************************************************************//**
2170 *
2171 * Clear the saturate interrupt for the specified channel mask.
2172 * The interrupt must be cleared with this function so that the hardware
2173 * can set subsequent interrupts and those interrupts can be forwarded
2174 * to the interrupt controller, if enabled.
2175 *
2176 * \param base
2177 * Pointer to structure describing registers
2178 *
2179 * \param chanMask
2180 * The channel mask. Bit 0 is for channel 0, etc.
2181 * Typically, this is the value returned from \ref Cy_SAR_GetSatInterruptStatus.
2182 *
2183 * \return None
2184 *
2185 *******************************************************************************/
Cy_SAR_ClearSatInterrupt(SAR_Type * base,uint32_t chanMask)2186 __STATIC_INLINE void Cy_SAR_ClearSatInterrupt(SAR_Type *base, uint32_t chanMask)
2187 {
2188 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
2189
2190 SAR_SATURATE_INTR(base) = chanMask & CY_SAR_CHANNELS_MASK;
2191
2192 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
2193 (void) SAR_SATURATE_INTR(base);
2194 }
2195
2196
2197 /*******************************************************************************
2198 * Function Name: Cy_SAR_SetSatInterrupt
2199 ****************************************************************************//**
2200 *
2201 * Trigger a saturate interrupt with software for the specific channel mask.
2202 *
2203 * \param base
2204 * Pointer to structure describing registers
2205 *
2206 * \param chanMask
2207 * The channel mask. Bit 0 is for channel 0, etc.
2208 *
2209 * \return None
2210 *
2211 *******************************************************************************/
Cy_SAR_SetSatInterrupt(SAR_Type * base,uint32_t chanMask)2212 __STATIC_INLINE void Cy_SAR_SetSatInterrupt(SAR_Type *base, uint32_t chanMask)
2213 {
2214 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
2215
2216 SAR_SATURATE_INTR_SET(base) = chanMask & CY_SAR_CHANNELS_MASK;
2217 }
2218
2219
2220 /*******************************************************************************
2221 * Function Name: Cy_SAR_SetSatInterruptMask
2222 ****************************************************************************//**
2223 *
2224 * Enable which channels can trigger a saturate interrupt.
2225 *
2226 * \param base
2227 * Pointer to structure describing registers
2228 *
2229 * \param chanMask
2230 * The channel mask. Bit 0 is for channel 0, etc.
2231 *
2232 * \return None
2233 *
2234 * \funcusage
2235 *
2236 * \snippet sar/snippet/main.c SNIPPET_SAR_GET_SAT_INTERRUPT_MASK
2237 *
2238 *******************************************************************************/
Cy_SAR_SetSatInterruptMask(SAR_Type * base,uint32_t chanMask)2239 __STATIC_INLINE void Cy_SAR_SetSatInterruptMask(SAR_Type *base, uint32_t chanMask)
2240 {
2241 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask));
2242
2243 SAR_SATURATE_INTR_MASK(base) = chanMask & CY_SAR_CHANNELS_MASK;
2244 }
2245
2246
2247 /*******************************************************************************
2248 * Function Name: Cy_SAR_GetSatInterruptMask
2249 ****************************************************************************//**
2250 *
2251 * Return which interrupts can trigger a saturate interrupt as configured
2252 * by \ref Cy_SAR_SetSatInterruptMask.
2253 *
2254 * \param base
2255 * Pointer to structure describing registers
2256 *
2257 * \return
2258 * The saturate interrupt mask. Bit 0 is for channel 0, etc.
2259 *
2260 *******************************************************************************/
Cy_SAR_GetSatInterruptMask(const SAR_Type * base)2261 __STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptMask(const SAR_Type *base)
2262 {
2263 return SAR_SATURATE_INTR_MASK(base);
2264 }
2265
2266 /*******************************************************************************
2267 * Function Name: Cy_SAR_GetSatInterruptStatusMasked
2268 ****************************************************************************//**
2269 *
2270 * Return the bitwise AND between the saturate interrupt request and mask registers.
2271 * See \ref Cy_SAR_GetSatInterruptStatus and \ref Cy_SAR_GetSatInterruptMask.
2272 *
2273 * \param base
2274 * Pointer to structure describing registers
2275 *
2276 * \return
2277 * Bitwise AND of the saturate interrupt request and mask
2278 *
2279 *******************************************************************************/
Cy_SAR_GetSatInterruptStatusMasked(const SAR_Type * base)2280 __STATIC_INLINE uint32_t Cy_SAR_GetSatInterruptStatusMasked(const SAR_Type *base)
2281 {
2282 return SAR_SATURATE_INTR_MASKED(base);
2283 }
2284
2285
2286 /*******************************************************************************
2287 * Function Name: Cy_SAR_GetInterruptCause
2288 ****************************************************************************//**
2289 *
2290 * Return the cause of the interrupt.
2291 * The interrupt routine can be called due to one of the following events:
2292 * - End of scan (EOS)
2293 * - Overflow
2294 * - Firmware collision
2295 * - Saturation detected on one or more channels
2296 * - Range detected on one or more channels
2297 *
2298 * \param base
2299 * Pointer to structure describing registers
2300 *
2301 * \return
2302 * Mask of what caused the interrupt. Compare this value with one of these masks:
2303 * - SAR_INTR_CAUSE_EOS_MASKED_MIR_Msk : EOS caused the interrupt
2304 * - SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk : Overflow caused the interrupt
2305 * - SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk : Firmware collision cause the interrupt
2306 * - SAR_INTR_CAUSE_SATURATE_MASKED_RED_Msk : Saturation detection on one or more channels caused the interrupt
2307 * - SAR_INTR_CAUSE_RANGE_MASKED_RED_Msk : Range detection on one or more channels caused the interrupt
2308 *
2309 *******************************************************************************/
Cy_SAR_GetInterruptCause(const SAR_Type * base)2310 __STATIC_INLINE uint32_t Cy_SAR_GetInterruptCause(const SAR_Type *base)
2311 {
2312 return SAR_INTR_CAUSE(base);
2313 }
2314 /** \} */
2315
2316 /** \addtogroup group_sar_functions_helper
2317 * \{
2318 */
2319
2320
2321 /*******************************************************************************
2322 * Function Name: Cy_SAR_IsChannelDifferential
2323 ****************************************************************************//**
2324 *
2325 * Return true of channel is differential, else false.
2326 *
2327 * \param base
2328 * Pointer to structure describing registers
2329 *
2330 * \param chan
2331 * The channel to check, starting at 0.
2332 *
2333 * \return
2334 * A false is return if chan is invalid.
2335 *
2336 * \funcusage
2337 *
2338 * \snippet sar/snippet/main.c SNIPPET_SAR_IS_CHANNEL_DIFF
2339 *
2340 *******************************************************************************/
Cy_SAR_IsChannelDifferential(const SAR_Type * base,uint32_t chan)2341 __STATIC_INLINE bool Cy_SAR_IsChannelDifferential(const SAR_Type *base, uint32_t chan)
2342 {
2343 return !Cy_SAR_IsChannelSingleEnded(base, chan);
2344 }
2345 /** \} */
2346
2347 /** \addtogroup group_sar_functions_switches
2348 * \{
2349 */
2350 /*******************************************************************************
2351 * Function Name: Cy_SAR_SetVssaVminusSwitch
2352 ****************************************************************************//**
2353 *
2354 * Open or close the switch between VSSA and Vminus of the SARADC through firmware.
2355 * This function calls \ref Cy_SAR_SetAnalogSwitch with switchSelect set to
2356 * \ref CY_SAR_MUX_SWITCH0 and switchMask set to SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk.
2357 *
2358 * \param base
2359 * Pointer to structure describing registers
2360 *
2361 * \param state
2362 * Open or close the switch. Select a value from \ref cy_en_sar_switch_state_t.
2363 *
2364 * \return None
2365 *
2366 * \funcusage
2367 *
2368 * \snippet sar/snippet/main.c SNIPPET_SAR_VSSA_VMINUS_SWITCH
2369 *
2370 *******************************************************************************/
Cy_SAR_SetVssaVminusSwitch(SAR_Type * base,cy_en_sar_switch_state_t state)2371 __STATIC_INLINE void Cy_SAR_SetVssaVminusSwitch(SAR_Type *base, cy_en_sar_switch_state_t state)
2372 {
2373 Cy_SAR_SetAnalogSwitch(base, CY_SAR_MUX_SWITCH0, SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk, state);
2374 }
2375
2376
2377 /*******************************************************************************
2378 * Function Name: Cy_SAR_SetVssaSarSeqCtrl
2379 ****************************************************************************//**
2380 *
2381 * Enable or disable SARSEQ control of the switch between VSSA and Vminus of the SARADC.
2382 * This function calls \ref Cy_SAR_SetSwitchSarSeqCtrl
2383 * with switchMask set to SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk.
2384 *
2385 * \param base
2386 * Pointer to structure describing registers
2387 *
2388 * \param ctrl
2389 * Enable or disable control. Select a value from \ref cy_en_sar_switch_sar_seq_ctrl_t.
2390 *
2391 * \return None
2392 *
2393 * \funcusage
2394 *
2395 * \snippet sar/snippet/main.c SNIPPET_SAR_VSSA_SARSEQ_CTRL
2396 *
2397 *******************************************************************************/
Cy_SAR_SetVssaSarSeqCtrl(SAR_Type * base,cy_en_sar_switch_sar_seq_ctrl_t ctrl)2398 __STATIC_INLINE void Cy_SAR_SetVssaSarSeqCtrl(SAR_Type *base, cy_en_sar_switch_sar_seq_ctrl_t ctrl)
2399 {
2400 Cy_SAR_SetSwitchSarSeqCtrl(base, SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk, ctrl);
2401 }
2402 /** \} */
2403
2404
2405 /** \addtogroup group_sar_functions_lp
2406 * \{
2407 */
2408
2409
2410 /*******************************************************************************
2411 * Function Name: Cy_SAR_ScanCountDisable
2412 ****************************************************************************//**
2413 *
2414 * Disables the Scanning Counter.
2415 *
2416 * \param base
2417 * Pointer to the structure of SAR instance registers.
2418 *
2419 * \funcusage \snippet sar/snippet/main.c SNIPPET_SAR_DS
2420 *
2421 *******************************************************************************/
Cy_SAR_ScanCountDisable(const SAR_Type * base)2422 __STATIC_INLINE void Cy_SAR_ScanCountDisable(const SAR_Type *base)
2423 {
2424 if (!CY_PASS_V1)
2425 {
2426 uint32_t interruptState = Cy_SysLib_EnterCriticalSection();
2427 PASS_SAR_OVR_CTRL(CY_PASS_V2_ADDR) &= ~(CY_SAR_INSTANCE_MASK(base) << PASS_V2_SAR_OVR_CTRL_TR_SCAN_CNT_SEL_Pos);
2428 Cy_SysLib_ExitCriticalSection(interruptState);
2429 }
2430 }
2431
2432
2433 /*******************************************************************************
2434 * Function Name: Cy_SAR_SelectClock
2435 ****************************************************************************//**
2436 *
2437 * Switch the SAR input clock source.
2438 * Suitable for PASS_V2 only.
2439 * In case of CY_SAR_CLK_DEEPSLEEP it enables SAR operation in Deep Sleep mode.
2440 *
2441 * \param base
2442 * Pointer to the structure of SAR instance registers.
2443 *
2444 * \param clock
2445 * The SAR clock source \ref cy_en_sar_clock_source_t.
2446 *
2447 * \funcusage \snippet sar/snippet/main.c SNIPPET_SAR_DS
2448 *
2449 *******************************************************************************/
Cy_SAR_SelectClock(const SAR_Type * base,cy_en_sar_clock_source_t clock)2450 __STATIC_INLINE void Cy_SAR_SelectClock(const SAR_Type * base, cy_en_sar_clock_source_t clock)
2451 {
2452 CY_ASSERT_L1(!CY_PASS_V1); /* Deep Sleep Clock is not supported */
2453
2454 if (!CY_PASS_V1)
2455 {
2456 CY_ASSERT_L3(CY_SAR_IS_CLK_VALID(clock));
2457 PASS_SAR_CLOCK_SEL(base) = _VAL2FLD(PASS_V2_SAR_CLOCK_SEL_CLOCK_SEL, clock);
2458 PASS_SAR_DPSLP_CTRL(base) = _BOOL2FLD(PASS_V2_SAR_DPSLP_CTRL_ENABLED, (CY_SAR_CLK_DEEPSLEEP == clock));
2459 }
2460 }
2461 /** \} */
2462
2463
2464 /** \addtogroup group_sar_functions_fifo
2465 * \{
2466 */
2467
2468 /*******************************************************************************
2469 * Function Name: Cy_SAR_FifoRead
2470 ****************************************************************************//**
2471 *
2472 * Reads FIFO word-by-word.
2473 *
2474 * \return Subsequent data sample
2475 *
2476 * \funcusage \snippet sar/snippet/main.c SNIPPET_FIFO
2477 *
2478 *******************************************************************************/
Cy_SAR_FifoRead(const SAR_Type * base,cy_stc_sar_fifo_read_t * readStruct)2479 __STATIC_INLINE void Cy_SAR_FifoRead(const SAR_Type * base, cy_stc_sar_fifo_read_t * readStruct)
2480 {
2481 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2482
2483 if(!CY_PASS_V1)
2484 {
2485 uint32_t locReg = PASS_FIFO_RD_DATA(base);
2486 readStruct->channel = (uint16_t)_FLD2VAL(PASS_FIFO_V2_RD_DATA_CHAN_ID, locReg);
2487 readStruct->value = (uint16_t)_FLD2VAL(PASS_FIFO_V2_RD_DATA_RESULT, locReg);
2488 }
2489 }
2490
2491
2492 /*******************************************************************************
2493 * Function Name: Cy_SAR_FifoGetDataCount
2494 ****************************************************************************//**
2495 *
2496 * Returns a number of non-empty FIFO cells.
2497 *
2498 * \return Number of FIFO samples.
2499 *
2500 * \funcusage \snippet sar/snippet/main.c SNIPPET_FIFO
2501 *
2502 *******************************************************************************/
Cy_SAR_FifoGetDataCount(const SAR_Type * base)2503 __STATIC_INLINE uint32_t Cy_SAR_FifoGetDataCount(const SAR_Type * base)
2504 {
2505 uint32_t retVal = 0UL;
2506
2507 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2508
2509 if(!CY_PASS_V1)
2510 {
2511 retVal = PASS_FIFO_USED(base);
2512 }
2513
2514 return (retVal);
2515 }
2516
2517
2518 /*******************************************************************************
2519 * Function Name: Cy_SAR_ClearFifoInterrupt
2520 ****************************************************************************//**
2521 *
2522 * Clear the FIFO interrupt.
2523 * The interrupt must be cleared with this function so that the hardware
2524 * can set subsequent interrupts and those interrupts can be forwarded
2525 * to the interrupt controller, if enabled.
2526 *
2527 * \param base
2528 * Pointer to structure describing registers
2529 *
2530 * \param intrMask
2531 * The mask of interrupts to clear. Typically this will be the value returned
2532 * from \ref Cy_SAR_GetFifoInterruptStatus.
2533 * Alternately, select one or more values from \ref group_sar_macros_interrupt and "OR" them together.
2534 * - \ref CY_SAR_INTR_FIFO_LEVEL
2535 * - \ref CY_SAR_INTR_FIFO_OVERFLOW
2536 * - \ref CY_SAR_INTR_FIFO_UNDERFLOW
2537 *
2538 * \return None
2539 *
2540 *******************************************************************************/
Cy_SAR_ClearFifoInterrupt(const SAR_Type * base,uint32_t intrMask)2541 __STATIC_INLINE void Cy_SAR_ClearFifoInterrupt(const SAR_Type * base, uint32_t intrMask)
2542 {
2543 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2544
2545 if(!CY_PASS_V1)
2546 {
2547 CY_ASSERT_L2(CY_SAR_FIFO_INTRMASK(intrMask));
2548 PASS_FIFO_INTR(base) = intrMask & CY_SAR_INTR_FIFO;
2549 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
2550 (void) PASS_FIFO_INTR(base);
2551 }
2552 }
2553
2554
2555 /*******************************************************************************
2556 * Function Name: Cy_SAR_SetFifoInterrupt
2557 ****************************************************************************//**
2558 *
2559 * Trigger an interrupt with software.
2560 *
2561 * \param base
2562 * Pointer to structure describing registers
2563 *
2564 * \param intrMask
2565 * The mask of interrupts to set.
2566 * Select one or more values from \ref group_sar_macros_interrupt and "OR" them together.
2567 * - \ref CY_SAR_INTR_FIFO_LEVEL
2568 * - \ref CY_SAR_INTR_FIFO_OVERFLOW
2569 * - \ref CY_SAR_INTR_FIFO_UNDERFLOW
2570 *
2571 * \return None
2572 *
2573 *******************************************************************************/
Cy_SAR_SetFifoInterrupt(const SAR_Type * base,uint32_t intrMask)2574 __STATIC_INLINE void Cy_SAR_SetFifoInterrupt(const SAR_Type * base, uint32_t intrMask)
2575 {
2576 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2577
2578 if(!CY_PASS_V1)
2579 {
2580 CY_ASSERT_L2(CY_SAR_FIFO_INTRMASK(intrMask));
2581 PASS_FIFO_INTR_SET(base) = intrMask & CY_SAR_INTR_FIFO;
2582 }
2583 }
2584
2585
2586 /*******************************************************************************
2587 * Function Name: Cy_SAR_SetFifoInterruptMask
2588 ****************************************************************************//**
2589 *
2590 * Enable which interrupts can trigger the CPU interrupt controller.
2591 *
2592 * \param base
2593 * Pointer to structure describing registers
2594 *
2595 * \param intrMask
2596 * The mask of interrupts. Select one or more values from \ref group_sar_macros_interrupt
2597 * and "OR" them together:
2598 * - \ref CY_SAR_INTR_FIFO_LEVEL
2599 * - \ref CY_SAR_INTR_FIFO_OVERFLOW
2600 * - \ref CY_SAR_INTR_FIFO_UNDERFLOW
2601 *
2602 * \return None
2603 *
2604 *******************************************************************************/
Cy_SAR_SetFifoInterruptMask(const SAR_Type * base,uint32_t intrMask)2605 __STATIC_INLINE void Cy_SAR_SetFifoInterruptMask(const SAR_Type * base, uint32_t intrMask)
2606 {
2607 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2608
2609 if(!CY_PASS_V1)
2610 {
2611 CY_ASSERT_L2(CY_SAR_FIFO_INTRMASK(intrMask));
2612 PASS_FIFO_INTR_MASK(base) = intrMask & CY_SAR_INTR_FIFO;
2613 }
2614 }
2615
2616
2617 /*******************************************************************************
2618 * Function Name: Cy_SAR_GetFifoInterruptStatus
2619 ****************************************************************************//**
2620 *
2621 * Return the interrupt register status.
2622 *
2623 * \param base
2624 * Pointer to structure describing registers
2625 *
2626 * \return Interrupt status \ref group_sar_macros_interrupt.
2627 *
2628 *******************************************************************************/
Cy_SAR_GetFifoInterruptStatus(const SAR_Type * base)2629 __STATIC_INLINE uint32_t Cy_SAR_GetFifoInterruptStatus(const SAR_Type * base)
2630 {
2631 uint32_t retVal = 0UL;
2632
2633 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2634
2635 if(!CY_PASS_V1)
2636 {
2637 retVal = PASS_FIFO_INTR(base);
2638 }
2639
2640 return (retVal);
2641 }
2642
2643
2644 /*******************************************************************************
2645 * Function Name: Cy_SAR_GetFifoInterruptMask
2646 ****************************************************************************//**
2647 *
2648 * Return which interrupts can trigger the CPU interrupt controller
2649 * as configured by \ref Cy_SAR_SetFifoInterruptMask.
2650 *
2651 * \param base
2652 * Pointer to structure describing registers
2653 *
2654 * \return
2655 * Interrupt mask. Compare this value with masks in \ref group_sar_macros_interrupt.
2656 *
2657 *******************************************************************************/
Cy_SAR_GetFifoInterruptMask(const SAR_Type * base)2658 __STATIC_INLINE uint32_t Cy_SAR_GetFifoInterruptMask(const SAR_Type * base)
2659 {
2660 uint32_t retVal = 0UL;
2661
2662 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2663
2664 if(!CY_PASS_V1)
2665 {
2666 retVal = PASS_FIFO_INTR_MASK(base);
2667 }
2668
2669 return (retVal);
2670 }
2671
2672
2673 /*******************************************************************************
2674 * Function Name: Cy_SAR_GetFifoInterruptStatusMasked
2675 ****************************************************************************//**
2676 *
2677 * Return the bitwise AND between the interrupt request and mask registers.
2678 * See \ref Cy_SAR_GetFifoInterruptStatus and \ref Cy_SAR_GetFifoInterruptMask.
2679 *
2680 * \param base
2681 * Pointer to structure describing registers
2682 *
2683 * \return
2684 * Bitwise AND of the interrupt request and mask registers \ref group_sar_macros_interrupt.
2685 *
2686 *******************************************************************************/
Cy_SAR_GetFifoInterruptStatusMasked(const SAR_Type * base)2687 __STATIC_INLINE uint32_t Cy_SAR_GetFifoInterruptStatusMasked(const SAR_Type * base)
2688 {
2689 uint32_t retVal = 0UL;
2690
2691 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2692
2693 if(!CY_PASS_V1)
2694 {
2695 retVal = PASS_FIFO_INTR_MASKED(base);
2696 }
2697
2698 return (retVal);
2699 }
2700
2701
2702 /*******************************************************************************
2703 * Function Name: Cy_SAR_FifoSetLevel
2704 ****************************************************************************//**
2705 *
2706 * Sets the FIFO trigger level which specifies how many samples FIFO should
2707 * contain in order to generate trigger event.
2708 *
2709 * \param base
2710 * Pointer to structure describing registers
2711 *
2712 * \param level The FIFO trigger level to be set. Range: 1..256.
2713 *
2714 * \return None
2715 *
2716 *******************************************************************************/
Cy_SAR_FifoSetLevel(const SAR_Type * base,uint32_t level)2717 __STATIC_INLINE void Cy_SAR_FifoSetLevel(const SAR_Type *base, uint32_t level)
2718 {
2719 CY_ASSERT_L1(!CY_PASS_V1); /* FIFO is not supported */
2720
2721 if(!CY_PASS_V1)
2722 {
2723 uint32_t locLevel = level - 1UL; /* Convert the user value into the machine value */
2724 CY_ASSERT_L2(CY_SAR_IS_FIFO_LEVEL_VALID(locLevel));
2725 PASS_FIFO_LEVEL(base) = _VAL2FLD(PASS_FIFO_V2_LEVEL_LEVEL, locLevel);
2726 }
2727 }
2728
2729 /** \} */
2730
2731 /*******************************************************************************
2732 * Function Name: Cy_SAR_SimultStart
2733 ****************************************************************************//**
2734 *
2735 * Simultaneously starts two or more SARs.
2736 *
2737 * \param base
2738 * Pointer to structure describing PASS registers.
2739 *
2740 * \param sarMask specifies which SAR instances will be started.
2741 * Mask should contain at least two SAR instances for operation.
2742 *
2743 * \param mode specifies mode of SARs operation.
2744 *
2745 * \return None
2746 *
2747 * \funcusage
2748 * \snippet sar/snippet/main.c SAR_SNIPPET_SIMULT_START_STOP
2749 *
2750 *******************************************************************************/
Cy_SAR_SimultStart(PASS_Type * base,uint32_t sarMask,cy_en_sar_start_convert_sel_t mode)2751 __STATIC_INLINE void Cy_SAR_SimultStart(PASS_Type *base, uint32_t sarMask, cy_en_sar_start_convert_sel_t mode)
2752 {
2753 CY_ASSERT_L1(!CY_PASS_V1); /* SAR simultaneous start feature is not supported on PASS_ver1 IP block. */
2754
2755 if (!CY_PASS_V1)
2756 {
2757 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 11.3', 'Deviate Pointer type conversions');
2758 PASS_SAR_SIMULT_FW_START_CTRL(base) =
2759 (_VAL2FLD(PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER, sarMask) |
2760 ((mode == CY_SAR_START_CONVERT_CONTINUOUS) ? _VAL2FLD(PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS, sarMask) : 0UL));
2761 }
2762 }
2763
2764
2765 /*******************************************************************************
2766 * Function Name: Cy_SAR_SimultStop
2767 ****************************************************************************//**
2768 *
2769 * Stops the selected SARs.
2770 *
2771 * \param base
2772 * Pointer to structure describing PASS registers.
2773 *
2774 * \param sarMask specifies which SAR instances should be stopped.
2775 *
2776 * \return None
2777 *
2778 * \funcusage
2779 * \snippet sar/snippet/main.c SAR_SNIPPET_SIMULT_START_STOP
2780 *
2781 *******************************************************************************/
Cy_SAR_SimultStop(PASS_Type * base,uint32_t sarMask)2782 __STATIC_INLINE void Cy_SAR_SimultStop(PASS_Type *base, uint32_t sarMask)
2783 {
2784 if (!CY_PASS_V1)
2785 {
2786 CY_MISRA_DEVIATE_LINE('MISRA C-2012 Rule 11.3', 'Deviate Pointer type conversions');
2787 PASS_SAR_SIMULT_FW_START_CTRL(base) = _VAL2FLD(PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS, (~sarMask));
2788 }
2789 }
2790
2791 /** \} group_sar_functions */
2792 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 11.3')
2793
2794 #if defined(__cplusplus)
2795 }
2796 #endif
2797
2798 #endif /* CY_IP_MXS40PASS_SAR */
2799
2800 #endif /** !defined(CY_SAR_H) */
2801
2802 /** \} group_sar */
2803
2804 /* [] END OF FILE */
2805
