1 /***************************************************************************//** 2 * \file cy_pra.h 3 * \version 2.40.1 4 * 5 * \brief The header file of the PRA driver. The API is not intended to 6 * be used directly by the user application. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation 11 * (an Infineon company) or an affiliate of Cypress Semiconductor Corporation. 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 28 /** 29 * \addtogroup group_pra 30 * \{ 31 * \note The Protection Register Access (PRA) driver is intended for the PSoC 64 32 * devices only and provides other PDL drivers access to the registers that have 33 * secure access restrictions. It is not intended to be used directly by user 34 * application. 35 * 36 * The PRA driver is used to protect the system from invalid configurations that 37 * could potentially cause the system to be unstable or indirectly allow access 38 * to registers and memory that are protected. This is done using several 39 * methods: 40 * * Allow only valid register settings. 41 * * Force a specified sequence of operations when writing to a register. 42 * * Totally block access to registers that are deemed critical to security. 43 * * Allow only known, well defined system configurations. 44 * * Allow access to non-critical registers that are protected by a fixed PPU. 45 * 46 * On PSoC 64 devices, secure firmware protects entire regions of registers 47 * with the fixed PPUs, however there are some registers within that regions 48 * that should not be protected but, are protected due to fixed PPU 49 * granularity. 50 * 51 * The list of the registers that can be accessed by PRA driver directly is 52 * defined in the cy_pra.h file with the CY_PRA_INDX_ prefix. 53 * 54 * Most PDL drivers are not affected or use the PRA driver. Only the following 55 * PDL drivers are affected by this driver: 56 * * \ref group_lvd 57 * * \ref group_syslib 58 * * \ref group_sysclk 59 * * \ref group_syspm 60 * * \ref group_arm_system_timer 61 * * \ref group_wdt 62 * * \ref group_flash 63 * * \ref group_sysint (PSoC 64 CYB06xx7 devices only) 64 * * \ref group_prot (PSoC 64 CYB06xx7 devices only) 65 * * \ref group_gpio 66 * 67 * The execution time of the functions that access the protected registers is 68 * increased on the PSoC 64 devices because the access is performed on Cortex-M0+ 69 * via the IPC command (both CPU cores run at 8 MHz): 70 * * The access to the protected register may take about 50 us, while access 71 * to the unprotected one may take about 3 us. 72 * * The initial device configuration may take up to 1.75 ms for PSoC 64 devices, 73 * while for the other devices it may take about 0.3 ms. 74 * * The transition Active to DeepSleep to Active may take about 2 times longer. 75 * 76 * \section group_pra_basic_operation Basic Operation 77 * The PRA driver uses an IPC channel to transfer register data between the user 78 * application running on the Cortex-CM4 and the secure Cortex-CM0+ CPU. The 79 * secure processor performs the data validation and correct register write 80 * sequence to ensure proper stable operation of the system. Function status and 81 * requested data is also returned via the IPC channel. 82 * 83 * The PDL driver that accesses protected registers, generates request to the 84 * PRA driver and it passes request over the IPC to secure Cortex-M0+, where 85 * request is validated and executed, and, then, reports result back to the 86 * driver on Cortex-M4 side. 87 * 88 * \image html pra_high_level_diagram.png 89 * 90 * \section group_pra_device_config Device Configuration 91 * For PSoC 64 device, device configuration (like system clock settings and 92 * power modes) is applied on the secure Cortex-M0+. The device configuration 93 * can be initiated from either of the core or both the cores. The device 94 * configuration structure \ref cy_stc_pra_system_config_t is initialized 95 * with Device Configurator. For Cortext-M4 application, it passed to the 96 * secure Cortex-M0+ core through IPC for validation and register the update 97 * in the cybsp_init() function. For Cortext-M0+ application, this device 98 * configuration structure is directly validated and applied. 99 * 100 * \note The external clocks (ECO, WCO, and EXTCLK) require 101 * additional configuration to be allowed to source CLK_HF0 (clocks both 102 * Cortex-M0+ and Cortex-M4 CPUs) in order to prevent clock tampering. 103 * See \ref group_pra_external_clocks for details. 104 * 105 * \note The ALTHF (BLE ECO) is not allowed to source CLK_HF0 (clocks both 106 * Cortex-M0+ and Cortex-M4 CPUs) in order to prevent clock tampering. 107 * 108 * \note The internal low-frequency clocks (ILO and PILO) are not allowed to 109 * source the CLK_HF0 directly and through PLL or FLL. 110 * 111 * \note The clock source for Cortex-M4 SysTick cannot be configured with 112 * the Device Configurator. Enabling CLK_ALT_SYS_TICK will result in a 113 * compilation error. SysTick still can be configured in run-time with 114 * some limitations. For more details, refer to \ref Cy_SysTick_SetClockSource() 115 * in \ref group_arm_system_timer. 116 * 117 * \note 118 * When EXT_CLK is source to HF0 then the drive mode for EXT_CLK pin is hard coded 119 * to CY_GPIO_DM_HIGHZ. So user has to make sure this pin configuration is not 120 * overwritten from secure application. 121 * 122 *\section group_pra_external_clocks External Clock Sources 123 * The PSoC 64 devices must be provisioned with the external clocks 124 * (ECO, WCO, and EXTCLK) configuration before routing these 125 * clocks to CLK_HF0. To do that, update the JSON 126 * file (delivered with CySecureTools) with the "extclk" node in the 127 * custom data section as shown below. The configuration fields in the 128 * JSON file match the fields in the Device Configurator. 129 * 130 * For more details, refer to the PSoC 64 Secure MCU Secure Boot SDK User Guide. 131 * 132 *\code{json} 133 * For EXTCLK: 134 * "custom_data_sections": ["extclk"], 135 * "extclk": { 136 * "extClkEnable": 1, 137 * "extClkFreqHz": 24000000, 138 * "extClkPort": 0, 139 * "extClkPinNum": 0, 140 * "extClkHsiom": 0 141 * } 142 * 143 * For ECO: 144 * "custom_data_sections": ["extclk"], 145 * "extclk": { 146 * "ecoEnable": 1, 147 * "ecoFreqHz": 24000000, 148 * "ecoLoad": 18, 149 * "ecoEsr": 50, 150 * "ecoDriveLevel": 100, 151 * "ecoInPort": 12, 152 * "ecoOutPort": 12, 153 * "ecoInPinNum": 6, 154 * "ecoOutPinNum": 7, 155 * } 156 * 157 * For WCO: 158 * "custom_data_sections": ["extclk"], 159 * "extclk": { 160 * "wcoEnable": 1, 161 * "bypassEnable": 0 162 * "wcoInPort": 0, 163 * "wcoOutPort": 0, 164 * "wcoInPinNum": 0, 165 * "wcoOutPinNum": 1 166 * } 167 *\endcode 168 * 169 *\note The same "extclk" section is used for all external clocks. If more than 170 * one external clock source is required, please append its parameters. 171 * 172 *\section group_pra_sram_power_config SRAM Power Mode Configurations 173 * The PSoC 64 devices must be provisioned with the SRAM power mode configuration 174 * to protects secure core memory. To do that, update the JSON 175 * file (delivered with CySecureTools) with the "srampwrmode" node in the 176 * custom data section as shown below. 177 * 178 * For more details, refer to the PSoC 64 Secure MCU Secure Boot SDK User Guide. 179 * 180 *\code{json} 181 * "custom_data_sections": ["srampwrmode"], 182 * "sram0": [ 183 * { 184 * "macroNum": 1, // bits 0 185 * "powerMode": 6, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 186 * }, 187 * { 188 * "macroNum": 2, // bits 1 189 * "powerMode": 1, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 190 * }, 191 * { 192 * "macroNum": 65532, // bits [15-2] = 0xFFFC 193 * "powerMode": 7, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 194 * } 195 * ], 196 * "sram1": [ 197 * { 198 * "macroNum": 1, // bit 0 199 * "powerMode": 7, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 200 * } 201 * ], 202 * "sram2": [ 203 * { 204 * "macroNum": 1, // bit 0 205 * "powerMode": 7, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 206 * } 207 * ] 208 *\endcode 209 * 210 *\note If a particular configuration(either SRAM or macro section) is 211 * not present in the policy file but available in the device then SRAM MACRO 212 * can be allowed to be modified to any of power modes (ON, RETAIN and OFF). 213 * 214 * \section group_pra_standalone Using without BSPs 215 * If PDL is used in Standalone mode without Board Support Package (BSP), 216 * do the following: 217 * * 1) Call the \ref Cy_PRA_Init function prior to executing 218 * API of any of the drivers listed above. By default, this function is 219 * called from \ref SystemInit on both CPU cores. 220 * * 2) Call the \ref Cy_PRA_SystemConfig function with the initial 221 * device configuration passed as a parameter. Refer to Section "Function Usage" 222 * of the \ref Cy_PRA_SystemConfig function for more details. 223 * 224 * \section group_pra_more_information More Information 225 * See the device technical reference manual (TRM) reference manual (TRM) for 226 * the list of the protected registers. 227 * 228 * \section group_pra_changelog Changelog 229 * <table class="doxtable"> 230 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 231 * <tr> 232 * <td>2.40.1</td> 233 * <td>Coverity errors fixed.</td> 234 * <td>Bug fixes.</td> 235 * </tr> 236 * <tr> 237 * <td>2.40</td> 238 * <td>Initialize internal data structure to initial values when external 239 * clock policy pointer is NULL to avoid null pointer de-referencing.</td> 240 * <td>Defect fix.</td> 241 * </tr> 242 * <tr> 243 * <td rowspan="4">2.30</td> 244 * <td>System Configuration can be done from CM0+ using PRA API with 245 * CY_PRA_MSG_TYPE_SYS_CFG_FUNC and CY_PRA_FUNC_INIT_CYCFG_DEVICE arguments.</td> 246 * <td>Enhancement based on customer feedback.</td> 247 * </tr> 248 * <tr> 249 * <td>System configuration structure is updated with appropriate value, when 250 * cm0+ application calls any PDL API accessing to FUNCTION_POLICY registers.</td> 251 * <td>Enhancement based on customer feedback.</td> 252 * </tr> 253 * <tr> 254 * <td>Fixed MISRA 2012 violations.</td> 255 * <td>MISRA 2012 compliance.</td> 256 * </tr> 257 * <tr> 258 * <td>Updated doxygen for External clock source to HF0.</td> 259 * <td>Documentation enhancement.</td> 260 * </tr> 261 * <tr> 262 * <td>2.20</td> 263 * <td>Allowing external clocks (EXT_CLK, ECO and WCO) can be source to secure core. 264 * Provide interface for validating and configuring SRAM power modes.</td> 265 * <td>External clock support and 266 * SRAM power mode configuration support.</td> 267 * </tr> 268 * <tr> 269 * <td rowspan="3">2.10</td> 270 * <td>Removed include of cy_gpio.h from the driver's c source files. 271 * Added some source code comments.</td> 272 * <td>Source code cleanup.</td> 273 * </tr> 274 * <tr> 275 * <td>Updated attribute usage for the linker section placement.</td> 276 * <td>Enhancement based on usability feedback.</td> 277 * </tr> 278 * <tr> 279 * <td>Fixed MISRA 2012 violations.</td> 280 * <td>MISRA 2012 compliance.</td> 281 * </tr> 282 * <tr> 283 * <td rowspan="6">2.0</td> 284 * <td> Added PSoC 64 CYB06xx7 devices support.</td> 285 * <td> New devices support.</td> 286 * </tr> 287 * <tr> 288 * <td> 289 * Updated Cy_PRA_Init() to compare the major and minor version of the PRA driver on the 290 * Cortex-M0+ and Cortex-M4 sides and halt Cortex-M4 if the versions are different. 291 * </td> 292 * <td> Ensure that the same PRA driver version is used on the Cortex-M0+ and Cortex-M4 sides.</td> 293 * </tr> 294 * <tr> 295 * <td> Fixed the location of the \ref cy_stc_pra_system_config_t description in the documentation. 296 * </td> 297 * <td>Documentation update.</td> 298 * </tr> 299 * <tr> 300 * <td> Corrected the reference to the \ref group_arm_system_timer function with the 301 * limitation description - \ref Cy_SysTick_SetClockSource(). 302 * </td> 303 * <td> Documentation update.</td> 304 * </tr> 305 * <tr> 306 * <td> The state of the following clocks changes only when the requested state 307 * differs from the actual state in the hardware: 308 * HF1-HF5, TIMER, PUMP, BLE_ECO, ILO, PILO, and WCO. 309 * </td> 310 * <td> Improved the \ref Cy_PRA_SystemConfig() function execution time.</td> 311 * </tr> 312 * <tr> 313 * <td> Renamed altHfFreq to altHFclkFreq in \ref cy_stc_pra_system_config_t.</td> 314 * <td> Eliminated the naming conflict with the SysClk driver.</td> 315 * </tr> 316 * <tr> 317 * <td>1.0</td> 318 * <td>Initial version</td> 319 * <td></td> 320 * </tr> 321 * </table> 322 * 323 * \defgroup group_pra_macros Macros 324 * \defgroup group_pra_functions Functions 325 * \defgroup group_pra_enums Enumerated Types 326 * \defgroup group_pra_stc Data Structures 327 */ 328 329 #if !defined(CY_PRA_H) 330 #define CY_PRA_H 331 332 #include "cy_device.h" 333 334 #if defined (CY_IP_MXS40SRSS) 335 336 #include <stdint.h> 337 #include <stdbool.h> 338 #include "cy_systick.h" 339 #include "cy_ble_clk.h" 340 #include "cy_device_headers.h" 341 342 #if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) 343 344 #ifdef __cplusplus 345 extern "C" { 346 #endif 347 348 /*************************************** 349 * Constants 350 ***************************************/ 351 352 /** \cond INTERNAL */ 353 354 #if defined(CY_DEVICE_PSOC6ABLE2) 355 #define CY_PRA_REG_INDEX_COUNT (157U) 356 #else 357 #define CY_PRA_REG_INDEX_COUNT (147U) 358 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 359 #define CY_PRA_EXTCLK_PIN_NR (5U) /* Protected pins: EXTCLK, ECO_IN, ECO_OUT, WCO_IN, WCO_OUT */ 360 #define CY_PRA_SRAM_MAX_NR CPUSS_SRAM_COUNT 361 #define CY_PRA_SRAM_MACRO_MAX_NR (16U) 362 363 #define CY_PRA_MSG_TYPE_REG32_GET (1U) 364 #define CY_PRA_MSG_TYPE_REG32_CLR_SET (2U) 365 #define CY_PRA_MSG_TYPE_REG32_SET (3U) 366 #define CY_PRA_MSG_TYPE_CM0_WAKEUP (4U) 367 #define CY_PRA_MSG_TYPE_SYS_CFG_FUNC (5U) 368 #define CY_PRA_MSG_TYPE_SECURE_ONLY (6U) 369 #define CY_PRA_MSG_TYPE_FUNC_POLICY (7U) 370 #define CY_PRA_MSG_TYPE_VERSION_CHECK (8U) 371 #define CY_PRA_MSG_TYPE_EXTCLK_PIN_LIST (9U) 372 #define CY_PRA_MSG_TYPE_EXTCLK_ADJHSIOM_LIST (10U) 373 374 /* IPC */ 375 #define CY_PRA_IPC_NOTIFY_INTR (0x1UL << CY_IPC_INTR_PRA) 376 #define CY_PRA_IPC_CHAN_INTR (0x1UL << CY_IPC_CHAN_PRA) 377 #define CY_PRA_IPC_NONE_INTR (0UL) 378 379 /* Registers Index */ 380 #define CY_PRA_INDX_SRSS_PWR_LVD_CTL (0U) 381 #define CY_PRA_INDX_SRSS_SRSS_INTR (1U) 382 #define CY_PRA_INDX_SRSS_SRSS_INTR_SET (2U) 383 #define CY_PRA_INDX_SRSS_SRSS_INTR_MASK (3U) 384 #define CY_PRA_INDX_SRSS_SRSS_INTR_CFG (4U) 385 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_1 (5U) 386 /* Do not change the index below because it is used in flash loaders */ 387 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_2 (6U) 388 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_3 (7U) 389 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_4 (8U) 390 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_5 (9U) 391 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_6 (10U) 392 #define CY_PRA_INDX_FLASHC_FLASH_CMD (11U) 393 #define CY_PRA_INDX_SRSS_PWR_HIBERNATE (12U) 394 #define CY_PRA_INDX_SRSS_CLK_MFO_CONFIG (13U) 395 #define CY_PRA_INDX_SRSS_CLK_MF_SELECT (14U) 396 #define CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK (15U) 397 /* There are MS_NR (16) registers. The index 16 to 31 are used. */ 398 #define CY_PRA_INDX_PROT_MPU_MS_CTL (16u) 399 /* The next index should be 32. */ 400 /* EXT CLK port has 21 registers. The index 32 to 52 are used. */ 401 #define CY_PRA_INDX_GPIO_EXTCLK_PRT (32U) 402 /* ECO in-Port has 21 registers. The index 53 to 73 are used */ 403 #define CY_PRA_INDX_GPIO_ECO_IN_PRT (53U) 404 /* ECO out-Port has 21 registers. The index 74 to 94 are used */ 405 #define CY_PRA_INDX_GPIO_ECO_OUT_PRT (74U) 406 /* HSIOM PORT has 2 registers. The index 95 to 115 are used */ 407 #define CY_PRA_INDX_GPIO_WCO_IN_PRT (95U) 408 /* WCO out-Port has 21 registers. The index 116 to 136 are used */ 409 #define CY_PRA_INDX_GPIO_WCO_OUT_PRT (116U) 410 /* HSIOM PORT has 2 registers. The index 137 to 138 are used */ 411 #define CY_PRA_INDEX_HSIOM_EXTCLK_PRT (137U) 412 /* HSIOM PORT has 2 registers. The index 139 to 140 are used */ 413 #define CY_PRA_INDEX_HSIOM_ECO_IN_PRT (139U) 414 /* HSIOM PORT has 2 registers. The index 141 to 142 are used */ 415 #define CY_PRA_INDEX_HSIOM_ECO_OUT_PRT (141U) 416 /* HSIOM PORT has 2 registers. The index 143 to 144 are used */ 417 #define CY_PRA_INDEX_HSIOM_WCO_IN_PRT (143U) 418 /* HSIOM PORT has 2 registers. The index 145 to 146 are used */ 419 #define CY_PRA_INDEX_HSIOM_WCO_OUT_PRT (145U) 420 421 #if defined(CY_DEVICE_PSOC6ABLE2) 422 /* HSIOM PORT has 2 registers. The index 147 to 148 are used */ 423 #define CY_PRA_INDEX_HSIOM_EXTCLK_ADJ_PRT (147U) 424 /* HSIOM PORT has 2 registers. The index 149 to 150 are used */ 425 #define CY_PRA_INDEX_HSIOM_ECO_IN_ADJ_PRT (149U) 426 /* HSIOM PORT has 2 registers. The index 151 to 152 are used */ 427 #define CY_PRA_INDEX_HSIOM_ECO_OUT_ADJ_PRT (151U) 428 /* HSIOM PORT has 2 registers. The index 153 to 154 are used */ 429 #define CY_PRA_INDEX_HSIOM_WCO_IN_ADJ_PRT (153U) 430 /* HSIOM PORT has 2 registers. The index 155 to 156 are used */ 431 #define CY_PRA_INDEX_HSIOM_WCO_OUT_ADJ_PRT (155U) 432 /* The next index should be 157 */ 433 #else 434 /* The next index should be 147 */ 435 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 436 437 /* GPIO PORT REG Sub Index */ 438 #define CY_PRA_SUB_INDEX_PORT_OUT (0U) 439 #define CY_PRA_SUB_INDEX_PORT_OUT_CLR (1U) 440 #define CY_PRA_SUB_INDEX_PORT_OUT_SET (2U) 441 #define CY_PRA_SUB_INDEX_PORT_OUT_INV (3U) 442 #define CY_PRA_SUB_INDEX_PORT_IN (4U) 443 #define CY_PRA_SUB_INDEX_PORT_INTR (5U) 444 #define CY_PRA_SUB_INDEX_PORT_INTR_MASK (6U) 445 #define CY_PRA_SUB_INDEX_PORT_INTR_MASKED (7U) 446 #define CY_PRA_SUB_INDEX_PORT_INTR_SET (8U) 447 #define CY_PRA_SUB_INDEX_PORT_INTR_CFG (9U) 448 #define CY_PRA_SUB_INDEX_PORT_CFG (10U) 449 #define CY_PRA_SUB_INDEX_PORT_CFG_IN (11U) 450 #define CY_PRA_SUB_INDEX_PORT_CFG_OUT (12U) 451 #define CY_PRA_SUB_INDEX_PORT_CFG_SIO (13U) 452 453 /* HSIOM PORT REG sub index */ 454 #define CY_PRA_SUB_INDEX_HSIOM_PORT0 (0U) 455 #define CY_PRA_SUB_INDEX_HSIOM_PORT1 (1U) 456 457 458 /* Functions Index */ 459 #define CY_PRA_FUNC_INIT_CYCFG_DEVICE (0U) 460 461 #define CY_PRA_CLK_FUNC_ECO_DISABLE (8U) 462 #define CY_PRA_CLK_FUNC_FLL_DISABLE (9U) 463 #define CY_PRA_CLK_FUNC_PLL_DISABLE (10U) 464 #define CY_PRA_CLK_FUNC_ILO_ENABLE (11U) 465 #define CY_PRA_CLK_FUNC_ILO_DISABLE (12U) 466 #define CY_PRA_CLK_FUNC_ILO_HIBERNATE_ON (13U) 467 #define CY_PRA_CLK_FUNC_PILO_ENABLE (14U) 468 #define CY_PRA_CLK_FUNC_PILO_DISABLE (15U) 469 #define CY_PRA_CLK_FUNC_PILO_SET_TRIM (16U) 470 #define CY_PRA_CLK_FUNC_WCO_ENABLE (17U) 471 #define CY_PRA_CLK_FUNC_WCO_DISABLE (18U) 472 #define CY_PRA_CLK_FUNC_WCO_BYPASS (19U) 473 #define CY_PRA_CLK_FUNC_HF_ENABLE (20U) 474 #define CY_PRA_CLK_FUNC_HF_DISABLE (21U) 475 #define CY_PRA_CLK_FUNC_HF_SET_SOURCE (22U) 476 #define CY_PRA_CLK_FUNC_HF_SET_DIVIDER (23U) 477 #define CY_PRA_CLK_FUNC_FAST_SET_DIVIDER (24U) 478 #define CY_PRA_CLK_FUNC_PERI_SET_DIVIDER (25U) 479 #define CY_PRA_CLK_FUNC_LF_SET_SOURCE (26U) 480 #define CY_PRA_CLK_FUNC_TIMER_SET_SOURCE (27U) 481 #define CY_PRA_CLK_FUNC_TIMER_SET_DIVIDER (28U) 482 #define CY_PRA_CLK_FUNC_TIMER_ENABLE (29U) 483 #define CY_PRA_CLK_FUNC_TIMER_DISABLE (30U) 484 #define CY_PRA_CLK_FUNC_PUMP_SET_SOURCE (31U) 485 #define CY_PRA_CLK_FUNC_PUMP_SET_DIVIDER (32U) 486 #define CY_PRA_CLK_FUNC_PUMP_ENABLE (33U) 487 #define CY_PRA_CLK_FUNC_PUMP_DISABLE (34U) 488 #define CY_PRA_CLK_FUNC_BAK_SET_SOURCE (35U) 489 #define CY_PRA_CLK_FUNC_ECO_CONFIGURE (36U) 490 #define CY_PRA_CLK_FUNC_ECO_ENABLE (37U) 491 #define CY_PRA_CLK_FUNC_PATH_SET_SOURCE (38U) 492 #define CY_PRA_CLK_FUNC_FLL_MANCONFIG (39U) 493 #define CY_PRA_CLK_FUNC_FLL_ENABLE (40U) 494 #define CY_PRA_CLK_FUNC_PLL_MANCONFIG (41U) 495 #define CY_PRA_CLK_FUNC_PLL_ENABLE (42U) 496 #define CY_PRA_CLK_FUNC_SLOW_SET_DIVIDER (43U) 497 #define CY_PRA_CLK_FUNC_DS_BEFORE_TRANSITION (44U) 498 #define CY_PRA_CLK_FUNC_DS_AFTER_TRANSITION (45U) 499 #define CY_PRA_CLK_FUNC_EXT_CLK_SET_FREQUENCY (46U) 500 #define CY_PRA_CLK_FUNC_ILO_TRIM (47U) 501 #define CY_PRA_CLK_FUNC_SET_PILO_TRIM (48U) 502 #define CY_PRA_CLK_FUNC_UPDATE_PILO_TRIM_STEP (49U) 503 #define CY_PRA_CLK_FUNC_START_MEASUREMENT (50U) 504 #define CY_PRA_CLK_FUNC_PILO_INITIAL_TRIM (51U) 505 506 #define CY_PRA_PM_FUNC_HIBERNATE (102U) 507 #define CY_PRA_PM_FUNC_CM4_DP_FLAG_SET (103U) 508 #define CY_PRA_PM_FUNC_LDO_SET_VOLTAGE (104U) 509 #define CY_PRA_PM_FUNC_BUCK_ENABLE (105U) 510 #define CY_PRA_PM_FUNC_SET_MIN_CURRENT (106U) 511 #define CY_PRA_PM_FUNC_SET_NORMAL_CURRENT (107U) 512 #define CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2 (108U) 513 #define CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2 (109U) 514 #define CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL (110U) 515 #define CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2 (111U) 516 #define CY_PRA_PM_FUNC_SRAM_MACRO_PWR_MODE (112U) /* Apply power mode to particular macro */ 517 #define CY_PRA_PM_FUNC_SRAM_PWR_MODE (113U) /* Apply power mode to entire sram */ 518 519 #define CY_PRA_BLE_CLK_FUNC_ECO_CONFIGURE (200U) 520 #define CY_PRA_BLE_CLK_FUNC_ECO_RESET (201U) 521 522 #define CY_PRA_GPIO_FUNC_SECPIN (300U) 523 524 #define CY_PRA_PM_SRAM_PWR_MODE_OFF_Pos (0UL) 525 #define CY_PRA_PM_SRAM_PWR_MODE_OFF_Msk (0x1UL) 526 #define CY_PRA_PM_SRAM_PWR_MODE_RETAIN_Pos (1UL) 527 #define CY_PRA_PM_SRAM_PWR_MODE_RETAIN_Msk (0x2UL) 528 #define CY_PRA_PM_SRAM_PWR_MODE_ON_Pos (2UL) 529 #define CY_PRA_PM_SRAM_PWR_MODE_ON_Msk (0x4UL) 530 531 #define CY_PRA_SRAM0_INDEX (0U) /* SRAM0 index */ 532 #define CY_PRA_SRAM1_INDEX (1U) /* SRAM1 index */ 533 #define CY_PRA_SRAM2_INDEX (2U) /* SRAM2 index */ 534 535 /** Driver major version */ 536 #define CY_PRA_DRV_VERSION_MAJOR 2 537 538 /** Driver minor version */ 539 #define CY_PRA_DRV_VERSION_MINOR 40 540 541 /** Protected Register Access driver ID */ 542 #define CY_PRA_ID (CY_PDL_DRV_ID(0x46U)) 543 544 /** \endcond */ 545 546 /** 547 * \addtogroup group_pra_enums 548 * \{ 549 */ 550 /** Status definitions of the PRA function return values. */ 551 typedef enum 552 { 553 CY_PRA_STATUS_SUCCESS = 0x0U, /**< Returns success */ 554 CY_PRA_STATUS_ACCESS_DENIED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFFU, /**< Access denied - PRA does not allow a call from Non-Secure */ 555 CY_PRA_STATUS_INVALID_PARAM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFEU, /**< Invalid parameter */ 556 CY_PRA_STATUS_ERROR_PROCESSING = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFDU, /**< An error while applying the device configuration */ 557 CY_PRA_STATUS_REQUEST_SENT = CY_PRA_ID | CY_PDL_STATUS_INFO | 0xFFCU, /**< The IPC message status when sent from Non-Secure to Secure */ 558 CY_PRA_STATUS_ERROR_SYSPM_FAIL = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFBU, /**< SysPM failure */ 559 CY_PRA_STATUS_ERROR_SYSPM_TIMEOUT = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFAU, /**< SysPM operation timeout */ 560 CY_PRA_STATUS_ERROR_PRA_VERSION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFF9U, /**< The driver version mismatch between Cortex-M0+ and Cortex-M4 */ 561 /* Reserve 0xFF9 - 0xFF0 */ 562 563 CY_PRA_STATUS_INVALID_PARAM_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEFU, /**< Returns Error while validating the ECO parameters */ 564 CY_PRA_STATUS_INVALID_PARAM_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEEU, /**< Returns Error while validating the CLK_EXT parameters */ 565 CY_PRA_STATUS_INVALID_PARAM_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEDU, /**< Returns Error while validating the CLK_ALTHF parameters */ 566 CY_PRA_STATUS_INVALID_PARAM_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFECU, /**< Returns Error while validating the CLK_ILO parameters */ 567 CY_PRA_STATUS_INVALID_PARAM_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEBU, /**< Returns Error while validating the CLK_PILO parameters */ 568 CY_PRA_STATUS_INVALID_PARAM_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEAU, /**< Returns Error while validating the CLK_WCO parameters */ 569 CY_PRA_STATUS_INVALID_ECO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFE9U, /**< Returns Error while validating the provisioned CLK_ECO policy */ 570 CY_PRA_STATUS_INVALID_EXTCLK_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFE8U, /**< Returns Error while validating the provisioned CLK_EXT policy */ 571 CY_PRA_STATUS_INVALID_WCO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFE7U, /**< Returns Error while validating the provisioned CLK_WCO policy */ 572 /* Reserve for other source clocks 0xFE6 - 0xFE0 */ 573 574 CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDFU, /**< Returns Error while validating PATH_MUX0 */ 575 CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDEU, /**< Returns Error while validating PATH_MUX1 */ 576 CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDDU, /**< Returns Error while validating PATH_MUX2 */ 577 CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDCU, /**< Returns Error while validating PATH_MUX3 */ 578 CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDBU, /**< Returns Error while validating PATH_MUX4 */ 579 CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDAU, /**< Returns Error while validating PATH_MUX5 */ 580 /* Reserve for other path-mux 0xFD9 - 0xFD0 */ 581 582 CY_PRA_STATUS_INVALID_PARAM_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFCFU, /**< Returns Error while validating FLL */ 583 /* Reserve for other FLLs 0xFCE - 0xFC0 */ 584 585 CY_PRA_STATUS_INVALID_PARAM_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBFU, /**< Returns Error while validating PLL0 */ 586 CY_PRA_STATUS_INVALID_PARAM_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBEU, /**< Returns Error while validating PLL1 */ 587 CY_PRA_STATUS_INVALID_PARAM_PLL_NUM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBDU, /**< Returns Error for the invalid PLL number */ 588 /* Reserve for other PLLs 0xFBC - 0xFB0 */ 589 590 CY_PRA_STATUS_INVALID_PARAM_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFAFU, /**< Returns Error while validating CLK_LF */ 591 /* Reserve for other clocks 0xFAE - 0xFA0 */ 592 593 CY_PRA_STATUS_INVALID_PARAM_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9FU, /**< Returns Error while validating CLK_HF0 */ 594 CY_PRA_STATUS_INVALID_PARAM_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9EU, /**< Returns Error while validating CLK_HF1 */ 595 CY_PRA_STATUS_INVALID_PARAM_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9DU, /**< Returns Error while validating CLK_HF2 */ 596 CY_PRA_STATUS_INVALID_PARAM_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9CU, /**< Returns Error while validating CLK_HF3 */ 597 CY_PRA_STATUS_INVALID_PARAM_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9BU, /**< Returns Error while validating CLK_HF4 */ 598 CY_PRA_STATUS_INVALID_PARAM_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9AU, /**< Returns Error while validating CLK_HF5 */ 599 /* Reserve for other HF clocks 0xF99 - 0xF90 */ 600 601 CY_PRA_STATUS_INVALID_PARAM_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8FU, /**< Returns Error while validating CLK_PUMP */ 602 CY_PRA_STATUS_INVALID_PARAM_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8EU, /**< Returns Error while validating CLK_BAK */ 603 CY_PRA_STATUS_INVALID_PARAM_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8DU, /**< Returns Error while validating CLK_FAST */ 604 CY_PRA_STATUS_INVALID_PARAM_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8CU, /**< Returns Error while validating CLK_PERI */ 605 CY_PRA_STATUS_INVALID_PARAM_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8BU, /**< Returns Error while validating CLK_SLOW */ 606 CY_PRA_STATUS_INVALID_PARAM_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8AU, /**< Returns Error while validating CLK_ALT_SYS_TICK */ 607 CY_PRA_STATUS_INVALID_PARAM_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF89U, /**< Returns Error while validating CLK_TIMER */ 608 /* Reserve for other HF clocks 0xF88 - 0xF70 */ 609 610 CY_PRA_STATUS_ERROR_PROCESSING_PWR = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF6FU, /**< Returns Error while initializing power */ 611 /* Reserve 0xF6E - 0xF60*/ 612 613 CY_PRA_STATUS_ERROR_PROCESSING_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5FU, /**< Returns Error while initializing ECO */ 614 CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5EU, /**< Returns Error while enabling CLK_EXT */ 615 CY_PRA_STATUS_ERROR_PROCESSING_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5DU, /**< Returns Error while enabling CLK_ALTHF */ 616 CY_PRA_STATUS_ERROR_PROCESSING_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5CU, /**< Returns Error while enabling/disabling CLK_ILO */ 617 CY_PRA_STATUS_ERROR_PROCESSING_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5BU, /**< Returns Error while enabling/disabling CLK_ALTHF */ 618 CY_PRA_STATUS_ERROR_PROCESSING_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5AU, /**< Returns Error while enabling/disabling CLK_WCO */ 619 CY_PRA_STATUS_ERROR_PROCESSING_ECO_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF59U, /**< Returns Error while enabling CLK_ECO */ 620 CY_PRA_STATUS_ERROR_PROCESSING_ECO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF58U, /**< Returns Error if failed to process the provisioned CLK_ECO policy */ 621 CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF57U, /**< Returns Error if failed to process the provisioned CLK_EXT policy */ 622 CY_PRA_STATUS_ERROR_PROCESSING_WCO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF56U, /**< Returns Error if failed to process the provisioned CLK_WCO policy */ 623 /* Reserve for other source clocks 0xF55 - 0xF50 */ 624 625 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4FU, /**< Returns Error while setting PATH_MUX0 */ 626 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4EU, /**< Returns Error while setting PATH_MUX1 */ 627 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4DU, /**< Returns Error while setting PATH_MUX2 */ 628 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4CU, /**< Returns Error while setting PATH_MUX3 */ 629 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4BU, /**< Returns Error while setting PATH_MUX4 */ 630 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4AU, /**< Returns Error while setting PATH_MUX5 */ 631 /* Reserve for other path-mux 0xF49 - 0xF40 */ 632 633 CY_PRA_STATUS_ERROR_PROCESSING_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3FU, /**< Returns Error while enabling/disabling FLL */ 634 CY_PRA_STATUS_ERROR_PROCESSING_FLL0_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3EU, /**< Returns Error while trying to enable an already enabled FLL */ 635 /* Reserve for other FLLs 0xF3D - 0xF30 */ 636 637 CY_PRA_STATUS_ERROR_PROCESSING_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2FU, /**< Returns Error while enabling/disabling PLL0 */ 638 CY_PRA_STATUS_ERROR_PROCESSING_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2EU, /**< Returns Error while enabling/disabling PLL1 */ 639 CY_PRA_STATUS_ERROR_PROCESSING_PLL_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2DU, /**< Returns Error while trying to enable an already enabled PLL */ 640 /* Reserve for other PLLs 0xF2C - 0xF20 */ 641 642 CY_PRA_STATUS_ERROR_PROCESSING_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF1FU, /**< Returns Error while enabling/disabling CLK_LF */ 643 /* Reserve for other clocks 0xF1E - 0xF10 */ 644 645 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0FU, /**< Returns Error while enabling/disabling CLK_HF0 */ 646 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0EU, /**< Returns Error while enabling/disabling CLK_HF1 */ 647 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0DU, /**< Returns Error while enabling/disabling CLK_HF2 */ 648 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0CU, /**< Returns Error while enabling/disabling CLK_HF3 */ 649 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0BU, /**< Returns Error while enabling/disabling CLK_HF4 */ 650 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0AU, /**< Returns Error while enabling/disabling CLK_HF5 */ 651 652 /* Reserve for other HF clocks 0xF09 - 0xF00 */ 653 CY_PRA_STATUS_ERROR_PROCESSING_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFFU, /**< Returns Error while enabling/disabling CLK_PUMP */ 654 CY_PRA_STATUS_ERROR_PROCESSING_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFEU, /**< Returns Error while enabling/disabling CLK_BAK */ 655 CY_PRA_STATUS_ERROR_PROCESSING_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFDU, /**< Returns Error while enabling/disabling CLK_FAST */ 656 CY_PRA_STATUS_ERROR_PROCESSING_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFCU, /**< Returns Error while enabling/disabling CLK_PERI */ 657 CY_PRA_STATUS_ERROR_PROCESSING_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFBU, /**< Returns Error while enabling/disabling CLK_SLOW */ 658 CY_PRA_STATUS_ERROR_PROCESSING_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFAU, /**< Returns Error while enabling/disabling CLK_ALT_SYS_TICK */ 659 CY_PRA_STATUS_ERROR_PROCESSING_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEF9U, /**< Returns Error while enabling/disabling CLK_TIMER */ 660 } cy_en_pra_status_t; 661 662 /** GPIO PIN protection type */ 663 typedef enum 664 { 665 CY_PRA_PIN_SECURE, /**< Is a secure PIN. Can't be updated from CM4 application through register level PRA policy. This PIN can only be updated through service-level policy */ 666 CY_PRA_PIN_SECURE_UNCONSTRAINED, /**< Is a secure PIN. Can be updated from CM4 application through register level PRA policy */ 667 CY_PRA_PIN_SECURE_NONE, /**< Not a secure PIN */ 668 } cy_en_pra_pin_prot_type_t; 669 /** \} group_pra_enums */ 670 671 672 /******************************************************************************* 673 * Data Structures 674 ******************************************************************************/ 675 676 /** \cond INTERNAL */ 677 /** PRA register access */ 678 typedef struct 679 { 680 volatile uint32_t * addr; /**< A protected register address */ 681 uint32_t writeMask; /**< The write mask. Zero grants access, one - no access. */ 682 } cy_stc_pra_reg_policy_t; 683 684 /** Message used for communication */ 685 typedef struct 686 { 687 uint16_t praCommand; /**< The message type. Refer to \ref group_pra_macros. */ 688 uint16_t praIndex; /**< The register or function index. */ 689 cy_en_pra_status_t praStatus; /**< The status */ 690 uint32_t praData1; /**< The first data word. The usage depends on \ref group_pra_macros. */ 691 uint32_t praData2; /**< The second data word. The usage depends on \ref group_pra_macros. */ 692 } cy_stc_pra_msg_t; 693 694 /* External clock pin structure */ 695 typedef struct 696 { 697 GPIO_PRT_Type *port; /**< Port Number */ 698 uint32_t pinNum; /**< Bit fields for each secure pin number */ 699 uint16_t index; /**< GPIO Port base address index */ 700 uint16_t hsiomIndex; /**< HSIOM Port base address index */ 701 } cy_stc_pra_extclk_pin_t; 702 703 #if defined(CY_DEVICE_PSOC6ABLE2) 704 /* External clock adjacent HSIOM index structure */ 705 typedef struct 706 { 707 GPIO_PRT_Type *port; /**< Port Number */ 708 uint16_t hsiomIndex; /**< HSIOM Port base address index */ 709 } cy_stc_pra_extclk_hsiom_t; 710 711 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 712 713 /** \endcond */ 714 715 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 716 /** \cond INTERNAL */ 717 /* contains power mode configuration of a macro */ 718 typedef struct 719 { 720 uint32_t sramMacros; /**< Bit fields for each SRAM macro number */ 721 uint32_t sramPwrMode; /**< Bit fields for SRAM power modes. bit 0->OFF, bit 1->RETAIN bit 2->ON */ 722 } cy_pra_sram_pwr_macro_config_t; 723 724 /* contains all macro configurations of a sram */ 725 typedef struct 726 { 727 cy_pra_sram_pwr_macro_config_t macroConfigs[CY_PRA_SRAM_MACRO_MAX_NR]; /**< SRAM macro configurations */ 728 uint32_t macroConfigCount; /**< Number of macros present in in policy file */ 729 } cy_pra_sram_pwr_mode_config_t; 730 731 /** \endcond */ 732 733 /** \cond INTERNAL */ 734 extern cy_pra_sram_pwr_mode_config_t sramPwrModeConfig[CY_PRA_SRAM_MAX_NR]; 735 /** \endcond */ 736 737 #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ 738 739 /** \cond INTERNAL */ 740 /* Public for testing purposes */ 741 extern cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT]; 742 743 #if (CY_CPU_CORTEX_M4) 744 745 extern cy_stc_pra_extclk_pin_t secExtclkPinList[CY_PRA_EXTCLK_PIN_NR]; 746 #if defined(CY_DEVICE_PSOC6ABLE2) 747 748 extern cy_stc_pra_extclk_hsiom_t secExtClkAdjHsiomList[CY_PRA_EXTCLK_PIN_NR]; 749 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 750 #endif /* (CY_CPU_CORTEX_M4) */ 751 /** \endcond */ 752 753 754 /******************************************************************************* 755 * Function Prototypes 756 *******************************************************************************/ 757 758 /** 759 * \addtogroup group_pra_functions 760 * \{ 761 */ 762 void Cy_PRA_Init(void); 763 764 /** \cond INTERNAL */ 765 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 766 void Cy_PRA_UpdateExtClockRegIndex(void); 767 void Cy_PRA_CloseSrssMain2(void); 768 void Cy_PRA_OpenSrssMain2(void); 769 #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ 770 /** \endcond */ 771 772 cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask); 773 774 #if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN) 775 776 cy_en_pra_pin_prot_type_t Cy_PRA_GetPinProtType(GPIO_PRT_Type *base, uint32_t pinNum); 777 778 bool Cy_PRA_IsPortSecure(GPIO_PRT_Type *base); 779 780 uint16_t Cy_PRA_GetPortRegIndex(GPIO_PRT_Type *base, uint16_t subIndex); 781 782 uint16_t Cy_PRA_GetHsiomRegIndex(GPIO_PRT_Type *base, uint16_t subIndex); 783 784 #if defined(CY_DEVICE_PSOC6ABLE2) 785 bool Cy_PRA_IsHsiomSecure(GPIO_PRT_Type *base); 786 uint16_t Cy_PRA_GetAdjHsiomRegIndex(GPIO_PRT_Type *base, uint16_t subIndex); 787 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 788 789 /** \} group_pra_functions */ 790 791 /** 792 * \addtogroup group_pra_macros 793 * \{ 794 */ 795 796 /******************************************************************************* 797 * Macro Name: CY_PRA_REG32_CLR_SET(regIndex, field, value) 798 ****************************************************************************//** 799 * 800 * Provides get-clear-modify-write operations with a name field and value and 801 * writes a resulting value to the 32-bit register. 802 * 803 * \note An attempt to access not-supported registers (not secure and 804 * not listed in the TRM) results in an error. The list of the registers that 805 * can be accessed by the PRA driver directly is defined in the cy_pra.h file 806 * with the CY_PRA_INDX_ prefix. 807 * 808 * \param regIndex The register address index. 809 * 810 * \param field The field to be updated. 811 * 812 * \param value The value to write. 813 * 814 *******************************************************************************/ 815 #define CY_PRA_REG32_CLR_SET(regIndex, field, value) \ 816 (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_CLR_SET, (regIndex), ((uint32_t)(~(field ## _Msk))), (_VAL2FLD(field, (value)))) 817 818 819 /******************************************************************************* 820 * Macro Name: CY_PRA_REG32_SET(regIndex, value) 821 ****************************************************************************//** 822 * 823 * Writes the 32-bit value to the specified register. 824 * 825 * \note An attempt to access not-supported registers (not secure and 826 * not listed in the TRM) results in an error. The list of the registers that 827 * can be accessed by the PRA driver directly is defined in the cy_pra.h file 828 * with the CY_PRA_INDX_ prefix. 829 * 830 * \param regIndex The register address index. 831 * 832 * \param value The value to write. 833 * 834 *******************************************************************************/ 835 #define CY_PRA_REG32_SET(regIndex, value) \ 836 (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_SET, (regIndex), (value), 0UL) 837 838 839 /******************************************************************************* 840 * Macro Name: CY_PRA_REG32_GET(regIndex) 841 ****************************************************************************//** 842 * 843 * Reads the 32-bit value from the specified register. 844 * 845 * \note An attempt to access not-supported registers (not secure and 846 * not listed in the TRM) results in an error. The list of the registers that 847 * can be accessed by the PRA driver directly is defined in the cy_pra.h file 848 * with the CY_PRA_INDX_ prefix. 849 * 850 * \param regIndex The register address index. 851 * 852 * \return The read value. 853 * 854 *******************************************************************************/ 855 #define CY_PRA_REG32_GET(regIndex) \ 856 (uint32_t) Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_GET, (regIndex), 0UL, 0UL) 857 858 859 /******************************************************************************* 860 * Macro Name: CY_PRA_CM0_WAKEUP() 861 ****************************************************************************//** 862 * 863 * The request to wake up the Cortex-M0+ core. 864 * 865 *******************************************************************************/ 866 #define CY_PRA_CM0_WAKEUP() \ 867 (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_CM0_WAKEUP, (uint16_t) 0U, 0UL, 0UL) 868 869 #endif /* (CY_CPU_CORTEX_M4) */ 870 871 /******************************************************************************* 872 * Macro Name: CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) 873 ****************************************************************************//** 874 * 875 * Calls the specified function with the provided parameter and returns the 876 * execution status. 877 * 878 * \param msgType The function type. 879 * 880 * \param funcIndex The function reference. 881 * 882 * \param param The pointer to the function parameter. 883 * 884 * \return The function execution status. 885 * 886 *******************************************************************************/ 887 #define CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) \ 888 Cy_PRA_SendCmd((msgType), (funcIndex), (uint32_t)(param), 0UL) 889 890 891 /******************************************************************************* 892 * Macro Name: CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) 893 ****************************************************************************//** 894 * 895 * Calls the specified function without a parameter and returns the 896 * execution status. 897 * 898 * \param msgType The function type. 899 * 900 * \param funcIndex The function reference. 901 * 902 * \return The function execution status. 903 * 904 *******************************************************************************/ 905 #define CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) \ 906 Cy_PRA_SendCmd((msgType), (funcIndex), 0UL, 0UL) 907 908 909 /******************************************************************************* 910 * Macro Name: CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) 911 ****************************************************************************//** 912 * 913 * Calls the specified function with the provided parameter and returns void. 914 * 915 * \param msgType The function type. 916 * 917 * \param funcIndex The function reference. 918 * 919 * \param param The pointer to the function parameter. 920 * 921 *******************************************************************************/ 922 #define CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) \ 923 (void)Cy_PRA_SendCmd((msgType), (funcIndex), (uint32_t)(param), 0UL) 924 925 926 /******************************************************************************* 927 * Macro Name: CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) 928 ****************************************************************************//** 929 * 930 * Calls the specified function without a parameter and returns void. 931 * 932 * \param msgType The function type. 933 * 934 * \param funcIndex The function reference. 935 * 936 *******************************************************************************/ 937 #define CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) \ 938 (void)Cy_PRA_SendCmd((msgType), (funcIndex), 0UL, 0UL) 939 940 941 #if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN) 942 943 /******************************************************************************* 944 * Macro Name: CY_PRA_GET_PIN_PROT_TYPE(base, pinNum) 945 ****************************************************************************//** 946 * 947 * Compares the PORT and PIN number with secure PIN list and returns PIN 948 * protection type. 949 * 950 * \param base GPIO Port address 951 * 952 * \param pinNum GPIO PIN number 953 * 954 * \return The categories of PIN. 955 * 956 *******************************************************************************/ 957 #define CY_PRA_GET_PIN_PROT_TYPE(base, pinNum) \ 958 Cy_PRA_GetPinProtType(base, pinNum) 959 960 /******************************************************************************* 961 * Macro Name: CY_PRA_IS_PORT_SECURE(base) 962 ****************************************************************************//** 963 * 964 * Compares the PORT with secure PIN list and returns PORT protection status. 965 * 966 * \param base GPIO Port address 967 * 968 * \return true if port is secure otherwise false. 969 * 970 *******************************************************************************/ 971 #define CY_PRA_IS_PORT_SECURE(base) \ 972 Cy_PRA_IsPortSecure(base) 973 974 #if defined(CY_DEVICE_PSOC6ABLE2) 975 /******************************************************************************* 976 * Macro Name: CY_PRA_IS_HSIOM_SECURE(base) 977 ****************************************************************************//** 978 * 979 * Compares the PORT with secure adjacent HSIOM list and returns protection status. 980 * 981 * \param base GPIO Port address 982 * 983 * \return true if HSIOM is secure otherwise false. 984 * 985 *******************************************************************************/ 986 #define CY_PRA_IS_HSIOM_SECURE(base) \ 987 Cy_PRA_IsHsiomSecure(base) 988 989 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 990 991 /******************************************************************************* 992 * Macro Name: CY_PRA_GET_PORT_INDEX(base, pinNum, subIndex) 993 ****************************************************************************//** 994 * 995 * Compares the PORT and PIN number with secure PIN list and returns PORT index 996 * 997 * \param base GPIO Port address 998 * 999 * \param subIndex register index of GPIO PORT 1000 * 1001 * \return PRA GPIO PORT register index 1002 * 1003 *******************************************************************************/ 1004 #define CY_PRA_GET_PORT_REG_INDEX(base, subIndex) \ 1005 Cy_PRA_GetPortRegIndex(base, subIndex) 1006 1007 /******************************************************************************* 1008 * Macro Name: CY_PRA_GET_HSIOM_REG_INDEX(base, subIndex) 1009 ****************************************************************************//** 1010 * 1011 * Compares the PORT with secure PIN list and returns HSIOM port index 1012 * 1013 * \param base GPIO Port address 1014 * 1015 * \param subIndex register index of HSIOM PORT 1016 * 1017 * \return PRA HSIOM PORT register index 1018 * 1019 *******************************************************************************/ 1020 #define CY_PRA_GET_HSIOM_REG_INDEX(base, subIndex) \ 1021 Cy_PRA_GetHsiomRegIndex(base, subIndex) 1022 1023 #if defined(CY_DEVICE_PSOC6ABLE2) 1024 /******************************************************************************* 1025 * Macro Name: CY_PRA_GET_ADJHSIOM_REG_INDEX(base, subIndex) 1026 ****************************************************************************//** 1027 * 1028 * Compares the PORT with adjacent HSIOM list and returns HSIOM port index 1029 * 1030 * \param base GPIO Port address 1031 * 1032 * \param subIndex register index of HSIOM PORT 1033 * 1034 * \return PRA HSIOM PORT register index 1035 * 1036 *******************************************************************************/ 1037 #define CY_PRA_GET_ADJHSIOM_REG_INDEX(base, subIndex) \ 1038 Cy_PRA_GetAdjHsiomRegIndex(base, subIndex) 1039 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 1040 1041 /** \} group_pra_macros */ 1042 1043 #endif /* (CY_CPU_CORTEX_M4) */ 1044 1045 #ifdef __cplusplus 1046 } 1047 #endif 1048 1049 #endif /* (CY_DEVICE_SECURE) */ 1050 1051 #endif /* defined (CY_IP_MXS40SRSS) */ 1052 1053 #endif /* #if !defined(CY_PRA_H) */ 1054 1055 /** \} group_pra */ 1056 1057 /* [] END OF FILE */ 1058
