1 /***************************************************************************//** 2 * \file cy_pra.h 3 * \version 2.30 4 * 5 * \brief The header file of the PRA driver. The API is not intended to 6 * be used directly by the user application. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2020 Cypress Semiconductor Corporation 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 27 /** 28 * \addtogroup group_pra 29 * \{ 30 * \note The Protection Register Access (PRA) driver is intended for the PSoC 64 31 * devices only and provides other PDL drivers access to the registers that have 32 * secure access restrictions. It is not intended to be used directly by user 33 * application. 34 * 35 * The PRA driver is used to protect the system from invalid configurations that 36 * could potentially cause the system to be unstable or indirectly allow access 37 * to registers and memory that are protected. This is done using several 38 * methods: 39 * * Allow only valid register settings. 40 * * Force a specified sequence of operations when writing to a register. 41 * * Totally block access to registers that are deemed critical to security. 42 * * Allow only known, well defined system configurations. 43 * * Allow access to non-critical registers that are protected by a fixed PPU. 44 * 45 * On PSoC 64 devices, secure firmware protects entire regions of registers 46 * with the fixed PPUs, however there are some registers within that regions 47 * that should not be protected but, are protected due to fixed PPU 48 * granularity. 49 * 50 * The list of the registers that can be accessed by PRA driver directly is 51 * defined in the cy_pra.h file with the CY_PRA_INDX_ prefix. 52 * 53 * Most PDL drivers are not affected or use the PRA driver. Only the following 54 * PDL drivers are affected by this driver: 55 * * \ref group_lvd 56 * * \ref group_syslib 57 * * \ref group_sysclk 58 * * \ref group_syspm 59 * * \ref group_arm_system_timer 60 * * \ref group_wdt 61 * * \ref group_flash 62 * * \ref group_sysint (PSoC 64 CYB06xx7 devices only) 63 * * \ref group_prot (PSoC 64 CYB06xx7 devices only) 64 * * \ref group_gpio 65 * 66 * The execution time of the functions that access the protected registers is 67 * increased on the PSoC 64 devices because the access is performed on Cortex-M0+ 68 * via the IPC command (both CPU cores run at 8 MHz): 69 * * The access to the protected register may take about 50 us, while access 70 * to the unprotected one may take about 3 us. 71 * * The initial device configuration may take up to 1.75 ms for PSoC 64 devices, 72 * while for the other devices it may take about 0.3 ms. 73 * * The transition Active to DeepSleep to Active may take about 2 times longer. 74 * 75 * \section group_pra_basic_operation Basic Operation 76 * The PRA driver uses an IPC channel to transfer register data between the user 77 * application running on the Cortex-CM4 and the secure Cortex-CM0+ CPU. The 78 * secure processor performs the data validation and correct register write 79 * sequence to ensure proper stable operation of the system. Function status and 80 * requested data is also returned via the IPC channel. 81 * 82 * The PDL driver that accesses protected registers, generates request to the 83 * PRA driver and it passes request over the IPC to secure Cortex-M0+, where 84 * request is validated and executed, and, then, reports result back to the 85 * driver on Cortex-M4 side. 86 * 87 * \image html pra_high_level_diagram.png 88 * 89 * \section group_pra_device_config Device Configuration 90 * For PSoC 64 device, device configuration (like system clock settings and 91 * power modes) is applied on the secure Cortex-M0+. The device configuration 92 * can be initiated from either of the core or both the cores. The device 93 * configuration structure \ref cy_stc_pra_system_config_t is initialized 94 * with Device Configurator. For Cortext-M4 application, it passed to the 95 * secure Cortex-M0+ core through IPC for validation and register the update 96 * in the cybsp_init() function. For Cortext-M0+ application, this device 97 * configuration structure is directly validated and applied. 98 * 99 * \note The external clocks (ECO, WCO, and EXTCLK) require 100 * additional configuration to be allowed to source CLK_HF0 (clocks both 101 * Cortex-M0+ and Cortex-M4 CPUs) in order to prevent clock tampering. 102 * See \ref group_pra_external_clocks for details. 103 * 104 * \note The ALTHF (BLE ECO) is not allowed to source CLK_HF0 (clocks both 105 * Cortex-M0+ and Cortex-M4 CPUs) in order to prevent clock tampering. 106 * 107 * \note The internal low-frequency clocks (ILO and PILO) are not allowed to 108 * source the CLK_HF0 directly and through PLL or FLL. 109 * 110 * \note The clock source for Cortex-M4 SysTick cannot be configured with 111 * the Device Configurator. Enabling CLK_ALT_SYS_TICK will result in a 112 * compilation error. SysTick still can be configured in run-time with 113 * some limitations. For more details, refer to \ref Cy_SysTick_SetClockSource() 114 * in \ref group_arm_system_timer. 115 * 116 * \note 117 * When EXT_CLK is source to HF0 then the drive mode for EXT_CLK pin is hard coded 118 * to CY_GPIO_DM_HIGHZ. So user has to make sure this pin configuration is not 119 * overwritten from secure application. 120 * 121 *\section group_pra_external_clocks External Clock Sources 122 * The PSoC 64 devices must be provisioned with the external clocks 123 * (ECO, WCO, and EXTCLK) configuration before routing these 124 * clocks to CLK_HF0. To do that, update the JSON 125 * file (delivered with CySecureTools) with the "extclk" node in the 126 * custom data section as shown below. The configuration fields in the 127 * JSON file match the fields in the Device Configurator. 128 * 129 * For more details, refer to the PSoC 64 Secure MCU Secure Boot SDK User Guide. 130 * 131 *\code{json} 132 * For EXTCLK: 133 * "custom_data_sections": ["extclk"], 134 * "extclk": { 135 * "extClkEnable": 1, 136 * "extClkFreqHz": 24000000, 137 * "extClkPort": 0, 138 * "extClkPinNum": 0, 139 * "extClkHsiom": 0 140 * } 141 * 142 * For ECO: 143 * "custom_data_sections": ["extclk"], 144 * "extclk": { 145 * "ecoEnable": 1, 146 * "ecoFreqHz": 24000000, 147 * "ecoLoad": 18, 148 * "ecoEsr": 50, 149 * "ecoDriveLevel": 100, 150 * "ecoInPort": 12, 151 * "ecoOutPort": 12, 152 * "ecoInPinNum": 6, 153 * "ecoOutPinNum": 7, 154 * } 155 * 156 * For WCO: 157 * "custom_data_sections": ["extclk"], 158 * "extclk": { 159 * "wcoEnable": 1, 160 * "bypassEnable": 0 161 * "wcoInPort": 0, 162 * "wcoOutPort": 0, 163 * "wcoInPinNum": 0, 164 * "wcoOutPinNum": 1 165 * } 166 *\endcode 167 * 168 *\note The same "extclk" section is used for all external clocks. If more than 169 * one external clock source is required, please append its parameters. 170 * 171 *\section group_pra_sram_power_config SRAM Power Mode Configurations 172 * The PSoC 64 devices must be provisioned with the SRAM power mode configuration 173 * to protects secure core memory. To do that, update the JSON 174 * file (delivered with CySecureTools) with the "srampwrmode" node in the 175 * custom data section as shown below. 176 * 177 * For more details, refer to the PSoC 64 Secure MCU Secure Boot SDK User Guide. 178 * 179 *\code{json} 180 * "custom_data_sections": ["srampwrmode"], 181 * "sram0": [ 182 * { 183 * "macroNum": 1, // bits 0 184 * "powerMode": 6, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 185 * }, 186 * { 187 * "macroNum": 2, // bits 1 188 * "powerMode": 1, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 189 * }, 190 * { 191 * "macroNum": 65532, // bits [15-2] = 0xFFFC 192 * "powerMode": 7, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 193 * } 194 * ], 195 * "sram1": [ 196 * { 197 * "macroNum": 1, // bit 0 198 * "powerMode": 7, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 199 * } 200 * ], 201 * "sram2": [ 202 * { 203 * "macroNum": 1, // bit 0 204 * "powerMode": 7, // bit 2 = ON, bit 1 = RETAIN, bit 0 = OFF 205 * } 206 * ] 207 *\endcode 208 * 209 *\note If a particular configuration(either SRAM or macro section) is 210 * not present in the policy file but available in the device then SRAM MACRO 211 * can be allowed to be modified to any of power modes (ON, RETAIN and OFF). 212 * 213 * \section group_pra_standalone Using without BSPs 214 * If PDL is used in Standalone mode without Board Support Package (BSP), 215 * do the following: 216 * * 1) Call the \ref Cy_PRA_Init function prior to executing 217 * API of any of the drivers listed above. By default, this function is 218 * called from \ref SystemInit on both CPU cores. 219 * * 2) Call the \ref Cy_PRA_SystemConfig function with the initial 220 * device configuration passed as a parameter. Refer to Section "Function Usage" 221 * of the \ref Cy_PRA_SystemConfig function for more details. 222 * 223 * \section group_pra_more_information More Information 224 * See the device technical reference manual (TRM) reference manual (TRM) for 225 * the list of the protected registers. 226 * 227 * \section group_pra_changelog Changelog 228 * <table class="doxtable"> 229 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 230 * <tr> 231 * <td rowspan="4">2.30</td> 232 * <td>System Configuration can be done from CM0+ using PRA API with 233 * CY_PRA_MSG_TYPE_SYS_CFG_FUNC and CY_PRA_FUNC_INIT_CYCFG_DEVICE arguments.</td> 234 * <td>Enhancement based on customer feedback.</td> 235 * </tr> 236 * <tr> 237 * <td>System configuration structure is updated with appropriate value, when 238 * cm0+ applicaton calls any PDL API accessing to FUNCTION_POLICY registers.</td> 239 * <td>Enhancement based on customer feedback.</td> 240 * </tr> 241 * <tr> 242 * <td>Fixed MISRA 2012 violations.</td> 243 * <td>MISRA 2012 compliance.</td> 244 * </tr> 245 * <tr> 246 * <td>Updated doxygen for External clock source to HF0.</td> 247 * <td>Documentation enhancement.</td> 248 * </tr> 249 * <tr> 250 * <td>2.20</td> 251 * <td>Allowing external clocks (EXT_CLK, ECO and WCO) can be source to secure core. 252 * Provide interface for validating and configuring SRAM power modes.</td> 253 * <td>External clock support and 254 * SRAM power mode configuration support.</td> 255 * </tr> 256 * <tr> 257 * <td rowspan="3">2.10</td> 258 * <td>Removed include of cy_gpio.h from the driver's c source files. 259 * Added some source code comments.</td> 260 * <td>Source code cleanup.</td> 261 * </tr> 262 * <tr> 263 * <td>Updated attribute usage for the linker section placement.</td> 264 * <td>Enhancement based on usability feedback.</td> 265 * </tr> 266 * <tr> 267 * <td>Fixed MISRA 2012 violations.</td> 268 * <td>MISRA 2012 compliance.</td> 269 * </tr> 270 * <tr> 271 * <td rowspan="6">2.0</td> 272 * <td> Added PSoC 64 CYB06xx7 devices support.</td> 273 * <td> New devices support.</td> 274 * </tr> 275 * <tr> 276 * <td> 277 * Updated Cy_PRA_Init() to compare the major and minor version of the PRA driver on the 278 * Cortex-M0+ and Cortex-M4 sides and halt Cortex-M4 if the versions are different. 279 * </td> 280 * <td> Ensure that the same PRA driver version is used on the Cortex-M0+ and Cortex-M4 sides.</td> 281 * </tr> 282 * <tr> 283 * <td> Fixed the location of the \ref cy_stc_pra_system_config_t description in the documentation. 284 * </td> 285 * <td>Documentation update.</td> 286 * </tr> 287 * <tr> 288 * <td> Corrected the reference to the \ref group_arm_system_timer function with the 289 * limitation description - \ref Cy_SysTick_SetClockSource(). 290 * </td> 291 * <td> Documentation update.</td> 292 * </tr> 293 * <tr> 294 * <td> The state of the following clocks changes only when the requested state 295 * differs from the actual state in the hardware: 296 * HF1-HF5, TIMER, PUMP, BLE_ECO, ILO, PILO, and WCO. 297 * </td> 298 * <td> Improved the \ref Cy_PRA_SystemConfig() function execution time.</td> 299 * </tr> 300 * <tr> 301 * <td> Renamed altHfFreq to altHFclkFreq in \ref cy_stc_pra_system_config_t.</td> 302 * <td> Eliminated the naming conflict with the SysClk driver.</td> 303 * </tr> 304 * <tr> 305 * <td>1.0</td> 306 * <td>Initial version</td> 307 * <td></td> 308 * </tr> 309 * </table> 310 * 311 * \defgroup group_pra_macros Macros 312 * \defgroup group_pra_functions Functions 313 * \defgroup group_pra_enums Enumerated Types 314 * \defgroup group_pra_stc Data Structures 315 */ 316 317 #if !defined(CY_PRA_H) 318 #define CY_PRA_H 319 320 #include "cy_device.h" 321 322 #if defined (CY_IP_MXS40SRSS) 323 324 #include <stdint.h> 325 #include <stdbool.h> 326 #include "cy_systick.h" 327 #include "cy_ble_clk.h" 328 #include "cy_device_headers.h" 329 330 #if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) 331 332 #ifdef __cplusplus 333 extern "C" { 334 #endif 335 336 /*************************************** 337 * Constants 338 ***************************************/ 339 340 /** \cond INTERNAL */ 341 342 #if defined(CY_DEVICE_PSOC6ABLE2) 343 #define CY_PRA_REG_INDEX_COUNT (157U) 344 #else 345 #define CY_PRA_REG_INDEX_COUNT (147U) 346 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 347 #define CY_PRA_EXTCLK_PIN_NR (5U) /* Protected pins: EXTCLK, ECO_IN, ECO_OUT, WCO_IN, WCO_OUT */ 348 #define CY_PRA_SRAM_MAX_NR CPUSS_SRAM_COUNT 349 #define CY_PRA_SRAM_MACRO_MAX_NR (16U) 350 351 #define CY_PRA_MSG_TYPE_REG32_GET (1U) 352 #define CY_PRA_MSG_TYPE_REG32_CLR_SET (2U) 353 #define CY_PRA_MSG_TYPE_REG32_SET (3U) 354 #define CY_PRA_MSG_TYPE_CM0_WAKEUP (4U) 355 #define CY_PRA_MSG_TYPE_SYS_CFG_FUNC (5U) 356 #define CY_PRA_MSG_TYPE_SECURE_ONLY (6U) 357 #define CY_PRA_MSG_TYPE_FUNC_POLICY (7U) 358 #define CY_PRA_MSG_TYPE_VERSION_CHECK (8U) 359 #define CY_PRA_MSG_TYPE_EXTCLK_PIN_LIST (9U) 360 #define CY_PRA_MSG_TYPE_EXTCLK_ADJHSIOM_LIST (10U) 361 362 /* IPC */ 363 #define CY_PRA_IPC_NOTIFY_INTR (0x1UL << CY_IPC_INTR_PRA) 364 #define CY_PRA_IPC_CHAN_INTR (0x1UL << CY_IPC_CHAN_PRA) 365 #define CY_PRA_IPC_NONE_INTR (0UL) 366 367 /* Registers Index */ 368 #define CY_PRA_INDX_SRSS_PWR_LVD_CTL (0U) 369 #define CY_PRA_INDX_SRSS_SRSS_INTR (1U) 370 #define CY_PRA_INDX_SRSS_SRSS_INTR_SET (2U) 371 #define CY_PRA_INDX_SRSS_SRSS_INTR_MASK (3U) 372 #define CY_PRA_INDX_SRSS_SRSS_INTR_CFG (4U) 373 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_1 (5U) 374 /* Do not change the index below abecause it is used in flash loaders */ 375 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_2 (6U) 376 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_3 (7U) 377 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_4 (8U) 378 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_5 (9U) 379 #define CY_PRA_INDX_SRSS_CLK_ROOT_SELECT_6 (10U) 380 #define CY_PRA_INDX_FLASHC_FLASH_CMD (11U) 381 #define CY_PRA_INDX_SRSS_PWR_HIBERNATE (12U) 382 #define CY_PRA_INDX_SRSS_CLK_MFO_CONFIG (13U) 383 #define CY_PRA_INDX_SRSS_CLK_MF_SELECT (14U) 384 #define CY_PRA_INDX_FLASHC_FM_CTL_BOOKMARK (15U) 385 /* There are MS_NR (16) registers. The index 16 to 31 are used. */ 386 #define CY_PRA_INDX_PROT_MPU_MS_CTL (16u) 387 /* The next index should be 32. */ 388 /* EXT CLK port has 21 registers. The index 32 to 52 are used. */ 389 #define CY_PRA_INDX_GPIO_EXTCLK_PRT (32U) 390 /* ECO in-Port has 21 registers. The index 53 to 73 are used */ 391 #define CY_PRA_INDX_GPIO_ECO_IN_PRT (53U) 392 /* ECO out-Port has 21 registers. The index 74 to 94 are used */ 393 #define CY_PRA_INDX_GPIO_ECO_OUT_PRT (74U) 394 /* HSIOM PORT has 2 registers. The index 95 to 115 are used */ 395 #define CY_PRA_INDX_GPIO_WCO_IN_PRT (95U) 396 /* WCO out-Port has 21 registers. The index 116 to 136 are used */ 397 #define CY_PRA_INDX_GPIO_WCO_OUT_PRT (116U) 398 /* HSIOM PORT has 2 registers. The index 137 to 138 are used */ 399 #define CY_PRA_INDEX_HSIOM_EXTCLK_PRT (137U) 400 /* HSIOM PORT has 2 registers. The index 139 to 140 are used */ 401 #define CY_PRA_INDEX_HSIOM_ECO_IN_PRT (139U) 402 /* HSIOM PORT has 2 registers. The index 141 to 142 are used */ 403 #define CY_PRA_INDEX_HSIOM_ECO_OUT_PRT (141U) 404 /* HSIOM PORT has 2 registers. The index 143 to 144 are used */ 405 #define CY_PRA_INDEX_HSIOM_WCO_IN_PRT (143U) 406 /* HSIOM PORT has 2 registers. The index 145 to 146 are used */ 407 #define CY_PRA_INDEX_HSIOM_WCO_OUT_PRT (145U) 408 409 #if defined(CY_DEVICE_PSOC6ABLE2) 410 /* HSIOM PORT has 2 registers. The index 147 to 148 are used */ 411 #define CY_PRA_INDEX_HSIOM_EXTCLK_ADJ_PRT (147U) 412 /* HSIOM PORT has 2 registers. The index 149 to 150 are used */ 413 #define CY_PRA_INDEX_HSIOM_ECO_IN_ADJ_PRT (149U) 414 /* HSIOM PORT has 2 registers. The index 151 to 152 are used */ 415 #define CY_PRA_INDEX_HSIOM_ECO_OUT_ADJ_PRT (151U) 416 /* HSIOM PORT has 2 registers. The index 153 to 154 are used */ 417 #define CY_PRA_INDEX_HSIOM_WCO_IN_ADJ_PRT (153U) 418 /* HSIOM PORT has 2 registers. The index 155 to 156 are used */ 419 #define CY_PRA_INDEX_HSIOM_WCO_OUT_ADJ_PRT (155U) 420 /* The next index should be 157 */ 421 #else 422 /* The next index should be 147 */ 423 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 424 425 /* GPIO PORT REG Sub Index */ 426 #define CY_PRA_SUB_INDEX_PORT_OUT (0U) 427 #define CY_PRA_SUB_INDEX_PORT_OUT_CLR (1U) 428 #define CY_PRA_SUB_INDEX_PORT_OUT_SET (2U) 429 #define CY_PRA_SUB_INDEX_PORT_OUT_INV (3U) 430 #define CY_PRA_SUB_INDEX_PORT_IN (4U) 431 #define CY_PRA_SUB_INDEX_PORT_INTR (5U) 432 #define CY_PRA_SUB_INDEX_PORT_INTR_MASK (6U) 433 #define CY_PRA_SUB_INDEX_PORT_INTR_MASKED (7U) 434 #define CY_PRA_SUB_INDEX_PORT_INTR_SET (8U) 435 #define CY_PRA_SUB_INDEX_PORT_INTR_CFG (9U) 436 #define CY_PRA_SUB_INDEX_PORT_CFG (10U) 437 #define CY_PRA_SUB_INDEX_PORT_CFG_IN (11U) 438 #define CY_PRA_SUB_INDEX_PORT_CFG_OUT (12U) 439 #define CY_PRA_SUB_INDEX_PORT_CFG_SIO (13U) 440 441 /* HSIOM PORT REG sub index */ 442 #define CY_PRA_SUB_INDEX_HSIOM_PORT0 (0U) 443 #define CY_PRA_SUB_INDEX_HSIOM_PORT1 (1U) 444 445 446 /* Functions Index */ 447 #define CY_PRA_FUNC_INIT_CYCFG_DEVICE (0U) 448 449 #define CY_PRA_CLK_FUNC_ECO_DISABLE (8U) 450 #define CY_PRA_CLK_FUNC_FLL_DISABLE (9U) 451 #define CY_PRA_CLK_FUNC_PLL_DISABLE (10U) 452 #define CY_PRA_CLK_FUNC_ILO_ENABLE (11U) 453 #define CY_PRA_CLK_FUNC_ILO_DISABLE (12U) 454 #define CY_PRA_CLK_FUNC_ILO_HIBERNATE_ON (13U) 455 #define CY_PRA_CLK_FUNC_PILO_ENABLE (14U) 456 #define CY_PRA_CLK_FUNC_PILO_DISABLE (15U) 457 #define CY_PRA_CLK_FUNC_PILO_SET_TRIM (16U) 458 #define CY_PRA_CLK_FUNC_WCO_ENABLE (17U) 459 #define CY_PRA_CLK_FUNC_WCO_DISABLE (18U) 460 #define CY_PRA_CLK_FUNC_WCO_BYPASS (19U) 461 #define CY_PRA_CLK_FUNC_HF_ENABLE (20U) 462 #define CY_PRA_CLK_FUNC_HF_DISABLE (21U) 463 #define CY_PRA_CLK_FUNC_HF_SET_SOURCE (22U) 464 #define CY_PRA_CLK_FUNC_HF_SET_DIVIDER (23U) 465 #define CY_PRA_CLK_FUNC_FAST_SET_DIVIDER (24U) 466 #define CY_PRA_CLK_FUNC_PERI_SET_DIVIDER (25U) 467 #define CY_PRA_CLK_FUNC_LF_SET_SOURCE (26U) 468 #define CY_PRA_CLK_FUNC_TIMER_SET_SOURCE (27U) 469 #define CY_PRA_CLK_FUNC_TIMER_SET_DIVIDER (28U) 470 #define CY_PRA_CLK_FUNC_TIMER_ENABLE (29U) 471 #define CY_PRA_CLK_FUNC_TIMER_DISABLE (30U) 472 #define CY_PRA_CLK_FUNC_PUMP_SET_SOURCE (31U) 473 #define CY_PRA_CLK_FUNC_PUMP_SET_DIVIDER (32U) 474 #define CY_PRA_CLK_FUNC_PUMP_ENABLE (33U) 475 #define CY_PRA_CLK_FUNC_PUMP_DISABLE (34U) 476 #define CY_PRA_CLK_FUNC_BAK_SET_SOURCE (35U) 477 #define CY_PRA_CLK_FUNC_ECO_CONFIGURE (36U) 478 #define CY_PRA_CLK_FUNC_ECO_ENABLE (37U) 479 #define CY_PRA_CLK_FUNC_PATH_SET_SOURCE (38U) 480 #define CY_PRA_CLK_FUNC_FLL_MANCONFIG (39U) 481 #define CY_PRA_CLK_FUNC_FLL_ENABLE (40U) 482 #define CY_PRA_CLK_FUNC_PLL_MANCONFIG (41U) 483 #define CY_PRA_CLK_FUNC_PLL_ENABLE (42U) 484 #define CY_PRA_CLK_FUNC_SLOW_SET_DIVIDER (43U) 485 #define CY_PRA_CLK_FUNC_DS_BEFORE_TRANSITION (44U) 486 #define CY_PRA_CLK_FUNC_DS_AFTER_TRANSITION (45U) 487 #define CY_PRA_CLK_FUNC_EXT_CLK_SET_FREQUENCY (46U) 488 #define CY_PRA_CLK_FUNC_ILO_TRIM (47U) 489 #define CY_PRA_CLK_FUNC_SET_PILO_TRIM (48U) 490 #define CY_PRA_CLK_FUNC_UPDATE_PILO_TRIM_STEP (49U) 491 #define CY_PRA_CLK_FUNC_START_MEASUREMENT (50U) 492 #define CY_PRA_CLK_FUNC_PILO_INITIAL_TRIM (51U) 493 494 #define CY_PRA_PM_FUNC_HIBERNATE (102U) 495 #define CY_PRA_PM_FUNC_CM4_DP_FLAG_SET (103U) 496 #define CY_PRA_PM_FUNC_LDO_SET_VOLTAGE (104U) 497 #define CY_PRA_PM_FUNC_BUCK_ENABLE (105U) 498 #define CY_PRA_PM_FUNC_SET_MIN_CURRENT (106U) 499 #define CY_PRA_PM_FUNC_SET_NORMAL_CURRENT (107U) 500 #define CY_PRA_PM_FUNC_BUCK_ENABLE_VOLTAGE2 (108U) 501 #define CY_PRA_PM_FUNC_BUCK_DISABLE_VOLTAGE2 (109U) 502 #define CY_PRA_PM_FUNC_BUCK_VOLTAGE2_HW_CTRL (110U) 503 #define CY_PRA_PM_FUNC_BUCK_SET_VOLTAGE2 (111U) 504 #define CY_PRA_PM_FUNC_SRAM_MACRO_PWR_MODE (112U) /* Apply power mode to particular macro */ 505 #define CY_PRA_PM_FUNC_SRAM_PWR_MODE (113U) /* Apply power mode to entire sram */ 506 507 #define CY_PRA_BLE_CLK_FUNC_ECO_CONFIGURE (200U) 508 #define CY_PRA_BLE_CLK_FUNC_ECO_RESET (201U) 509 510 #define CY_PRA_GPIO_FUNC_SECPIN (300U) 511 512 #define CY_PRA_PM_SRAM_PWR_MODE_OFF_Pos (0UL) 513 #define CY_PRA_PM_SRAM_PWR_MODE_OFF_Msk (0x1UL) 514 #define CY_PRA_PM_SRAM_PWR_MODE_RETAIN_Pos (1UL) 515 #define CY_PRA_PM_SRAM_PWR_MODE_RETAIN_Msk (0x2UL) 516 #define CY_PRA_PM_SRAM_PWR_MODE_ON_Pos (2UL) 517 #define CY_PRA_PM_SRAM_PWR_MODE_ON_Msk (0x4UL) 518 519 #define CY_PRA_SRAM0_INDEX (0U) /* SRAM0 index */ 520 #define CY_PRA_SRAM1_INDEX (1U) /* SRAM1 index */ 521 #define CY_PRA_SRAM2_INDEX (2U) /* SRAM2 index */ 522 523 /** Driver major version */ 524 #define CY_PRA_DRV_VERSION_MAJOR 2 525 526 /** Driver minor version */ 527 #define CY_PRA_DRV_VERSION_MINOR 30 528 529 /** Protected Register Access driver ID */ 530 #define CY_PRA_ID (CY_PDL_DRV_ID(0x46U)) 531 532 /** \endcond */ 533 534 /** 535 * \addtogroup group_pra_enums 536 * \{ 537 */ 538 /** Status definitions of the PRA function return values. */ 539 typedef enum 540 { 541 CY_PRA_STATUS_SUCCESS = 0x0U, /**< Returns success */ 542 CY_PRA_STATUS_ACCESS_DENIED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFFU, /**< Access denied - PRA does not allow a call from Non-Secure */ 543 CY_PRA_STATUS_INVALID_PARAM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFEU, /**< Invalid parameter */ 544 CY_PRA_STATUS_ERROR_PROCESSING = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFDU, /**< An error while applying the device configuration */ 545 CY_PRA_STATUS_REQUEST_SENT = CY_PRA_ID | CY_PDL_STATUS_INFO | 0xFFCU, /**< The IPC message status when sent from Non-Secure to Secure */ 546 CY_PRA_STATUS_ERROR_SYSPM_FAIL = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFBU, /**< SysPM failure */ 547 CY_PRA_STATUS_ERROR_SYSPM_TIMEOUT = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFFAU, /**< SysPM operation timeout */ 548 CY_PRA_STATUS_ERROR_PRA_VERSION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFF9U, /**< The driver version mismatch between Cortex-M0+ and Cortex-M4 */ 549 /* Reserve 0xFF9 - 0xFF0 */ 550 551 CY_PRA_STATUS_INVALID_PARAM_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEFU, /**< Returns Error while validating the ECO parameters */ 552 CY_PRA_STATUS_INVALID_PARAM_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEEU, /**< Returns Error while validating the CLK_EXT parameters */ 553 CY_PRA_STATUS_INVALID_PARAM_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEDU, /**< Returns Error while validating the CLK_ALTHF parameters */ 554 CY_PRA_STATUS_INVALID_PARAM_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFECU, /**< Returns Error while validating the CLK_ILO parameters */ 555 CY_PRA_STATUS_INVALID_PARAM_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEBU, /**< Returns Error while validating the CLK_PILO parameters */ 556 CY_PRA_STATUS_INVALID_PARAM_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFEAU, /**< Returns Error while validating the CLK_WCO parameters */ 557 CY_PRA_STATUS_INVALID_ECO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFE9U, /**< Returns Error while validating the provisioned CLK_ECO policy */ 558 CY_PRA_STATUS_INVALID_EXTCLK_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFE8U, /**< Returns Error while validating the provisioned CLK_EXT policy */ 559 CY_PRA_STATUS_INVALID_WCO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFE7U, /**< Returns Error while validating the provisioned CLK_WCO policy */ 560 /* Reserve for other source clocks 0xFE6 - 0xFE0 */ 561 562 CY_PRA_STATUS_INVALID_PARAM_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDFU, /**< Returns Error while validating PATH_MUX0 */ 563 CY_PRA_STATUS_INVALID_PARAM_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDEU, /**< Returns Error while validating PATH_MUX1 */ 564 CY_PRA_STATUS_INVALID_PARAM_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDDU, /**< Returns Error while validating PATH_MUX2 */ 565 CY_PRA_STATUS_INVALID_PARAM_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDCU, /**< Returns Error while validating PATH_MUX3 */ 566 CY_PRA_STATUS_INVALID_PARAM_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDBU, /**< Returns Error while validating PATH_MUX4 */ 567 CY_PRA_STATUS_INVALID_PARAM_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFDAU, /**< Returns Error while validating PATH_MUX5 */ 568 /* Reserve for other path-mux 0xFD9 - 0xFD0 */ 569 570 CY_PRA_STATUS_INVALID_PARAM_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFCFU, /**< Returns Error while validating FLL */ 571 /* Reserve for other FLLs 0xFCE - 0xFC0 */ 572 573 CY_PRA_STATUS_INVALID_PARAM_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBFU, /**< Returns Error while validating PLL0 */ 574 CY_PRA_STATUS_INVALID_PARAM_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBEU, /**< Returns Error while validating PLL1 */ 575 CY_PRA_STATUS_INVALID_PARAM_PLL_NUM = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFBDU, /**< Returns Error for the invalid PLL number */ 576 /* Reserve for other PLLs 0xFBC - 0xFB0 */ 577 578 CY_PRA_STATUS_INVALID_PARAM_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xFAFU, /**< Returns Error while validating CLK_LF */ 579 /* Reserve for other clocks 0xFAE - 0xFA0 */ 580 581 CY_PRA_STATUS_INVALID_PARAM_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9FU, /**< Returns Error while validating CLK_HF0 */ 582 CY_PRA_STATUS_INVALID_PARAM_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9EU, /**< Returns Error while validating CLK_HF1 */ 583 CY_PRA_STATUS_INVALID_PARAM_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9DU, /**< Returns Error while validating CLK_HF2 */ 584 CY_PRA_STATUS_INVALID_PARAM_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9CU, /**< Returns Error while validating CLK_HF3 */ 585 CY_PRA_STATUS_INVALID_PARAM_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9BU, /**< Returns Error while validating CLK_HF4 */ 586 CY_PRA_STATUS_INVALID_PARAM_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF9AU, /**< Returns Error while validating CLK_HF5 */ 587 /* Reserve for other HF clocks 0xF99 - 0xF90 */ 588 589 CY_PRA_STATUS_INVALID_PARAM_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8FU, /**< Returns Error while validating CLK_PUMP */ 590 CY_PRA_STATUS_INVALID_PARAM_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8EU, /**< Returns Error while validating CLK_BAK */ 591 CY_PRA_STATUS_INVALID_PARAM_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8DU, /**< Returns Error while validating CLK_FAST */ 592 CY_PRA_STATUS_INVALID_PARAM_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8CU, /**< Returns Error while validating CLK_PERI */ 593 CY_PRA_STATUS_INVALID_PARAM_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8BU, /**< Returns Error while validating CLK_SLOW */ 594 CY_PRA_STATUS_INVALID_PARAM_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF8AU, /**< Returns Error while validating CLK_ALT_SYS_TICK */ 595 CY_PRA_STATUS_INVALID_PARAM_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF89U, /**< Returns Error while validating CLK_TIMER */ 596 /* Reserve for other HF clocks 0xF88 - 0xF70 */ 597 598 CY_PRA_STATUS_ERROR_PROCESSING_PWR = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF6FU, /**< Returns Error while initializing power */ 599 /* Reserve 0xF6E - 0xF60*/ 600 601 CY_PRA_STATUS_ERROR_PROCESSING_ECO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5FU, /**< Returns Error while initializing ECO */ 602 CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5EU, /**< Returns Error while enabling CLK_EXT */ 603 CY_PRA_STATUS_ERROR_PROCESSING_ALTHF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5DU, /**< Returns Error while enabling CLK_ALTHF */ 604 CY_PRA_STATUS_ERROR_PROCESSING_ILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5CU, /**< Returns Error while enabling/disabling CLK_ILO */ 605 CY_PRA_STATUS_ERROR_PROCESSING_PILO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5BU, /**< Returns Error while enabling/disabling CLK_ALTHF */ 606 CY_PRA_STATUS_ERROR_PROCESSING_WCO = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF5AU, /**< Returns Error while enabling/disabling CLK_WCO */ 607 CY_PRA_STATUS_ERROR_PROCESSING_ECO_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF59U, /**< Returns Error while enabling CLK_ECO */ 608 CY_PRA_STATUS_ERROR_PROCESSING_ECO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF58U, /**< Returns Error if failed to process the provisioned CLK_ECO policy */ 609 CY_PRA_STATUS_ERROR_PROCESSING_EXTCLK_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF57U, /**< Returns Error if failed to process the provisioned CLK_EXT policy */ 610 CY_PRA_STATUS_ERROR_PROCESSING_WCO_PROVISION = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF56U, /**< Returns Error if failed to process the provisioned CLK_WCO policy */ 611 /* Reserve for other source clocks 0xF55 - 0xF50 */ 612 613 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4FU, /**< Returns Error while setting PATH_MUX0 */ 614 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4EU, /**< Returns Error while setting PATH_MUX1 */ 615 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4DU, /**< Returns Error while setting PATH_MUX2 */ 616 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4CU, /**< Returns Error while setting PATH_MUX3 */ 617 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4BU, /**< Returns Error while setting PATH_MUX4 */ 618 CY_PRA_STATUS_ERROR_PROCESSING_PATHMUX5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF4AU, /**< Returns Error while setting PATH_MUX5 */ 619 /* Reserve for other path-mux 0xF49 - 0xF40 */ 620 621 CY_PRA_STATUS_ERROR_PROCESSING_FLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3FU, /**< Returns Error while enabling/disabling FLL */ 622 CY_PRA_STATUS_ERROR_PROCESSING_FLL0_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF3EU, /**< Returns Error while trying to enable an already enabled FLL */ 623 /* Reserve for other FLLs 0xF3D - 0xF30 */ 624 625 CY_PRA_STATUS_ERROR_PROCESSING_PLL0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2FU, /**< Returns Error while enabling/disabling PLL0 */ 626 CY_PRA_STATUS_ERROR_PROCESSING_PLL1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2EU, /**< Returns Error while enabling/disabling PLL1 */ 627 CY_PRA_STATUS_ERROR_PROCESSING_PLL_ENABLED = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF2DU, /**< Returns Error while trying to enable an already enabled PLL */ 628 /* Reserve for other PLLs 0xF2C - 0xF20 */ 629 630 CY_PRA_STATUS_ERROR_PROCESSING_CLKLF = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF1FU, /**< Returns Error while enabling/disabling CLK_LF */ 631 /* Reserve for other clocks 0xF1E - 0xF10 */ 632 633 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF0 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0FU, /**< Returns Error while enabling/disabling CLK_HF0 */ 634 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF1 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0EU, /**< Returns Error while enabling/disabling CLK_HF1 */ 635 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF2 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0DU, /**< Returns Error while enabling/disabling CLK_HF2 */ 636 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF3 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0CU, /**< Returns Error while enabling/disabling CLK_HF3 */ 637 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF4 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0BU, /**< Returns Error while enabling/disabling CLK_HF4 */ 638 CY_PRA_STATUS_ERROR_PROCESSING_CLKHF5 = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xF0AU, /**< Returns Error while enabling/disabling CLK_HF5 */ 639 640 /* Reserve for other HF clocks 0xF09 - 0xF00 */ 641 CY_PRA_STATUS_ERROR_PROCESSING_CLKPUMP = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFFU, /**< Returns Error while enabling/disabling CLK_PUMP */ 642 CY_PRA_STATUS_ERROR_PROCESSING_CLKBAK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFEU, /**< Returns Error while enabling/disabling CLK_BAK */ 643 CY_PRA_STATUS_ERROR_PROCESSING_CLKFAST = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFDU, /**< Returns Error while enabling/disabling CLK_FAST */ 644 CY_PRA_STATUS_ERROR_PROCESSING_CLKPERI = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFCU, /**< Returns Error while enabling/disabling CLK_PERI */ 645 CY_PRA_STATUS_ERROR_PROCESSING_CLKSLOW = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFBU, /**< Returns Error while enabling/disabling CLK_SLOW */ 646 CY_PRA_STATUS_ERROR_PROCESSING_SYSTICK = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEFAU, /**< Returns Error while enabling/disabling CLK_ALT_SYS_TICK */ 647 CY_PRA_STATUS_ERROR_PROCESSING_CLKTIMER = CY_PRA_ID | CY_PDL_STATUS_ERROR | 0xEF9U, /**< Returns Error while enabling/disabling CLK_TIMER */ 648 } cy_en_pra_status_t; 649 650 /** GPIO PIN protection type */ 651 typedef enum 652 { 653 CY_PRA_PIN_SECURE, /**< Is a secure PIN. Can't be updated from CM4 application through register level PRA policy. This PIN can only be updated through service-level policy */ 654 CY_PRA_PIN_SECURE_UNCONSTRAINED, /**< Is a secure PIN. Can be updated from CM4 application through register level PRA policy */ 655 CY_PRA_PIN_SECURE_NONE, /**< Not a secure PIN */ 656 } cy_en_pra_pin_prot_type_t; 657 /** \} group_pra_enums */ 658 659 660 /******************************************************************************* 661 * Data Structures 662 ******************************************************************************/ 663 664 /** \cond INTERNAL */ 665 /** PRA register access */ 666 typedef struct 667 { 668 volatile uint32_t * addr; /**< A protected register address */ 669 uint32_t writeMask; /**< The write mask. Zero grants access, one - no access. */ 670 } cy_stc_pra_reg_policy_t; 671 672 /** Message used for communication */ 673 typedef struct 674 { 675 uint16_t praCommand; /**< The message type. Refer to \ref group_pra_macros. */ 676 uint16_t praIndex; /**< The register or function index. */ 677 cy_en_pra_status_t praStatus; /**< The status */ 678 uint32_t praData1; /**< The first data word. The usage depends on \ref group_pra_macros. */ 679 uint32_t praData2; /**< The second data word. The usage depends on \ref group_pra_macros. */ 680 } cy_stc_pra_msg_t; 681 682 /* External clock pin structure */ 683 typedef struct 684 { 685 GPIO_PRT_Type *port; /**< Port Number */ 686 uint32_t pinNum; /**< Bit fields for each secure pin number */ 687 uint16_t index; /**< GPIO Port base address index */ 688 uint16_t hsiomIndex; /**< HSIOM Port base address index */ 689 } cy_stc_pra_extclk_pin_t; 690 691 #if defined(CY_DEVICE_PSOC6ABLE2) 692 /* External clock adjacent HSIOM index structure */ 693 typedef struct 694 { 695 GPIO_PRT_Type *port; /**< Port Number */ 696 uint16_t hsiomIndex; /**< HSIOM Port base address index */ 697 } cy_stc_pra_extclk_hsiom_t; 698 699 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 700 701 /** \endcond */ 702 703 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 704 /** \cond INTERNAL */ 705 /* contains power mode configuration of a macro */ 706 typedef struct 707 { 708 uint32_t sramMacros; /**< Bit fields for each SRAM macro number */ 709 uint32_t sramPwrMode; /**< Bit fields for SRAM power modes. bit 0->OFF, bit 1->RETAIN bit 2->ON */ 710 } cy_pra_sram_pwr_macro_config_t; 711 712 /* contains all macro configurations of a sram */ 713 typedef struct 714 { 715 cy_pra_sram_pwr_macro_config_t macroConfigs[CY_PRA_SRAM_MACRO_MAX_NR]; /**< SRAM macro configurations */ 716 uint32_t macroConfigCount; /**< Number of macros present in in policy file */ 717 } cy_pra_sram_pwr_mode_config_t; 718 719 /** \endcond */ 720 721 /** \cond INTERNAL */ 722 extern cy_pra_sram_pwr_mode_config_t sramPwrModeConfig[CY_PRA_SRAM_MAX_NR]; 723 /** \endcond */ 724 725 #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ 726 727 /** \cond INTERNAL */ 728 /* Public for testing purposes */ 729 extern cy_stc_pra_reg_policy_t regIndexToAddr[CY_PRA_REG_INDEX_COUNT]; 730 731 extern cy_stc_pra_extclk_pin_t secExtclkPinList[CY_PRA_EXTCLK_PIN_NR]; 732 #if defined(CY_DEVICE_PSOC6ABLE2) 733 extern cy_stc_pra_extclk_hsiom_t secExtClkAdjHsiomList[CY_PRA_EXTCLK_PIN_NR]; 734 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 735 /** \endcond */ 736 737 738 /******************************************************************************* 739 * Function Prototypes 740 *******************************************************************************/ 741 742 /** 743 * \addtogroup group_pra_functions 744 * \{ 745 */ 746 void Cy_PRA_Init(void); 747 748 /** \cond INTERNAL */ 749 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 750 void Cy_PRA_UpdateExtClockRegIndex(void); 751 void Cy_PRA_CloseSrssMain2(void); 752 void Cy_PRA_OpenSrssMain2(void); 753 #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ 754 /** \endcond */ 755 756 cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask); 757 758 #if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN) 759 760 cy_en_pra_pin_prot_type_t Cy_PRA_GetPinProtType(GPIO_PRT_Type *base, uint32_t pinNum); 761 762 bool Cy_PRA_IsPortSecure(GPIO_PRT_Type *base); 763 764 uint16_t Cy_PRA_GetPortRegIndex(GPIO_PRT_Type *base, uint16_t subIndex); 765 766 uint16_t Cy_PRA_GetHsiomRegIndex(GPIO_PRT_Type *base, uint16_t subIndex); 767 768 #if defined(CY_DEVICE_PSOC6ABLE2) 769 bool Cy_PRA_IsHsiomSecure(GPIO_PRT_Type *base); 770 uint16_t Cy_PRA_GetAdjHsiomRegIndex(GPIO_PRT_Type *base, uint16_t subIndex); 771 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 772 773 /** \} group_pra_functions */ 774 775 /** 776 * \addtogroup group_pra_macros 777 * \{ 778 */ 779 780 /******************************************************************************* 781 * Macro Name: CY_PRA_REG32_CLR_SET(regIndex, field, value) 782 ****************************************************************************//** 783 * 784 * Provides get-clear-modify-write operations with a name field and value and 785 * writes a resulting value to the 32-bit register. 786 * 787 * \note An attempt to access not-supported registers (not secure and 788 * not listed in the TRM) results in an error. The list of the registers that 789 * can be accessed by the PRA driver directly is defined in the cy_pra.h file 790 * with the CY_PRA_INDX_ prefix. 791 * 792 * \param regIndex The register address index. 793 * 794 * \param field The field to be updated. 795 * 796 * \param value The value to write. 797 * 798 *******************************************************************************/ 799 #define CY_PRA_REG32_CLR_SET(regIndex, field, value) \ 800 (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_CLR_SET, (regIndex), ((uint32_t)(~(field ## _Msk))), (_VAL2FLD(field, (value)))) 801 802 803 /******************************************************************************* 804 * Macro Name: CY_PRA_REG32_SET(regIndex, value) 805 ****************************************************************************//** 806 * 807 * Writes the 32-bit value to the specified register. 808 * 809 * \note An attempt to access not-supported registers (not secure and 810 * not listed in the TRM) results in an error. The list of the registers that 811 * can be accessed by the PRA driver directly is defined in the cy_pra.h file 812 * with the CY_PRA_INDX_ prefix. 813 * 814 * \param regIndex The register address index. 815 * 816 * \param value The value to write. 817 * 818 *******************************************************************************/ 819 #define CY_PRA_REG32_SET(regIndex, value) \ 820 (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_SET, (regIndex), (value), 0UL) 821 822 823 /******************************************************************************* 824 * Macro Name: CY_PRA_REG32_GET(regIndex) 825 ****************************************************************************//** 826 * 827 * Reads the 32-bit value from the specified register. 828 * 829 * \note An attempt to access not-supported registers (not secure and 830 * not listed in the TRM) results in an error. The list of the registers that 831 * can be accessed by the PRA driver directly is defined in the cy_pra.h file 832 * with the CY_PRA_INDX_ prefix. 833 * 834 * \param regIndex The register address index. 835 * 836 * \return The read value. 837 * 838 *******************************************************************************/ 839 #define CY_PRA_REG32_GET(regIndex) \ 840 (uint32_t) Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_REG32_GET, (regIndex), 0UL, 0UL) 841 842 843 /******************************************************************************* 844 * Macro Name: CY_PRA_CM0_WAKEUP() 845 ****************************************************************************//** 846 * 847 * The request to wake up the Cortex-M0+ core. 848 * 849 *******************************************************************************/ 850 #define CY_PRA_CM0_WAKEUP() \ 851 (void)Cy_PRA_SendCmd(CY_PRA_MSG_TYPE_CM0_WAKEUP, (uint16_t) 0U, 0UL, 0UL) 852 853 #endif /* (CY_CPU_CORTEX_M4) */ 854 855 /******************************************************************************* 856 * Macro Name: CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) 857 ****************************************************************************//** 858 * 859 * Calls the specified function with the provided parameter and returns the 860 * execution status. 861 * 862 * \param msgType The function type. 863 * 864 * \param funcIndex The function reference. 865 * 866 * \param param The pointer to the function parameter. 867 * 868 * \return The function execution status. 869 * 870 *******************************************************************************/ 871 #define CY_PRA_FUNCTION_CALL_RETURN_PARAM(msgType, funcIndex, param) \ 872 Cy_PRA_SendCmd((msgType), (funcIndex), (uint32_t)(param), 0UL) 873 874 875 /******************************************************************************* 876 * Macro Name: CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) 877 ****************************************************************************//** 878 * 879 * Calls the specified function without a parameter and returns the 880 * execution status. 881 * 882 * \param msgType The function type. 883 * 884 * \param funcIndex The function reference. 885 * 886 * \return The function execution status. 887 * 888 *******************************************************************************/ 889 #define CY_PRA_FUNCTION_CALL_RETURN_VOID(msgType, funcIndex) \ 890 Cy_PRA_SendCmd((msgType), (funcIndex), 0UL, 0UL) 891 892 893 /******************************************************************************* 894 * Macro Name: CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) 895 ****************************************************************************//** 896 * 897 * Calls the specified function with the provided parameter and returns void. 898 * 899 * \param msgType The function type. 900 * 901 * \param funcIndex The function reference. 902 * 903 * \param param The pointer to the function parameter. 904 * 905 *******************************************************************************/ 906 #define CY_PRA_FUNCTION_CALL_VOID_PARAM(msgType, funcIndex, param) \ 907 (void)Cy_PRA_SendCmd((msgType), (funcIndex), (uint32_t)(param), 0UL) 908 909 910 /******************************************************************************* 911 * Macro Name: CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) 912 ****************************************************************************//** 913 * 914 * Calls the specified function without a parameter and returns void. 915 * 916 * \param msgType The function type. 917 * 918 * \param funcIndex The function reference. 919 * 920 *******************************************************************************/ 921 #define CY_PRA_FUNCTION_CALL_VOID_VOID(msgType, funcIndex) \ 922 (void)Cy_PRA_SendCmd((msgType), (funcIndex), 0UL, 0UL) 923 924 925 #if (CY_CPU_CORTEX_M4) || defined (CY_DOXYGEN) 926 927 /******************************************************************************* 928 * Macro Name: CY_PRA_GET_PIN_PROT_TYPE(base, pinNum) 929 ****************************************************************************//** 930 * 931 * Compares the PORT and PIN number with secure PIN list and returns PIN 932 * protection type. 933 * 934 * \param base GPIO Port address 935 * 936 * \param pinNum GPIO PIN number 937 * 938 * \return The categories of PIN. 939 * 940 *******************************************************************************/ 941 #define CY_PRA_GET_PIN_PROT_TYPE(base, pinNum) \ 942 Cy_PRA_GetPinProtType(base, pinNum) 943 944 /******************************************************************************* 945 * Macro Name: CY_PRA_IS_PORT_SECURE(base) 946 ****************************************************************************//** 947 * 948 * Compares the PORT with secure PIN list and returns PORT protection status. 949 * 950 * \param base GPIO Port address 951 * 952 * \return true if port is secure otherwise false. 953 * 954 *******************************************************************************/ 955 #define CY_PRA_IS_PORT_SECURE(base) \ 956 Cy_PRA_IsPortSecure(base) 957 958 #if defined(CY_DEVICE_PSOC6ABLE2) 959 /******************************************************************************* 960 * Macro Name: CY_PRA_IS_HSIOM_SECURE(base) 961 ****************************************************************************//** 962 * 963 * Compares the PORT with secure adjacent HSIOM list and returns protection status. 964 * 965 * \param base GPIO Port address 966 * 967 * \return true if HSIOM is secure otherwise false. 968 * 969 *******************************************************************************/ 970 #define CY_PRA_IS_HSIOM_SECURE(base) \ 971 Cy_PRA_IsHsiomSecure(base) 972 973 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 974 975 /******************************************************************************* 976 * Macro Name: CY_PRA_GET_PORT_INDEX(base, pinNum, subIndex) 977 ****************************************************************************//** 978 * 979 * Compares the PORT and PIN number with secure PIN list and returns PORT index 980 * 981 * \param base GPIO Port address 982 * 983 * \param subIndex register index of GPIO PORT 984 * 985 * \return PRA GPIO PORT register index 986 * 987 *******************************************************************************/ 988 #define CY_PRA_GET_PORT_REG_INDEX(base, subIndex) \ 989 Cy_PRA_GetPortRegIndex(base, subIndex) 990 991 /******************************************************************************* 992 * Macro Name: CY_PRA_GET_HSIOM_REG_INDEX(base, subIndex) 993 ****************************************************************************//** 994 * 995 * Compares the PORT with secure PIN list and returns HSIOM port index 996 * 997 * \param base GPIO Port address 998 * 999 * \param subIndex register index of HSIOM PORT 1000 * 1001 * \return PRA HSIOM PORT register index 1002 * 1003 *******************************************************************************/ 1004 #define CY_PRA_GET_HSIOM_REG_INDEX(base, subIndex) \ 1005 Cy_PRA_GetHsiomRegIndex(base, subIndex) 1006 1007 #if defined(CY_DEVICE_PSOC6ABLE2) 1008 /******************************************************************************* 1009 * Macro Name: CY_PRA_GET_ADJHSIOM_REG_INDEX(base, subIndex) 1010 ****************************************************************************//** 1011 * 1012 * Compares the PORT with adjacent HSIOM list and returns HSIOM port index 1013 * 1014 * \param base GPIO Port address 1015 * 1016 * \param subIndex register index of HSIOM PORT 1017 * 1018 * \return PRA HSIOM PORT register index 1019 * 1020 *******************************************************************************/ 1021 #define CY_PRA_GET_ADJHSIOM_REG_INDEX(base, subIndex) \ 1022 Cy_PRA_GetAdjHsiomRegIndex(base, subIndex) 1023 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ 1024 1025 /** \} group_pra_macros */ 1026 1027 #endif /* (CY_CPU_CORTEX_M4) */ 1028 1029 #ifdef __cplusplus 1030 } 1031 #endif 1032 1033 #endif /* (CY_DEVICE_SECURE) */ 1034 1035 #endif /* defined (CY_IP_MXS40SRSS) */ 1036 1037 #endif /* #if !defined(CY_PRA_H) */ 1038 1039 /** \} group_pra */ 1040 1041 /* [] END OF FILE */ 1042
