1 /***************************************************************************//** 2 * \file cy_pra_cfg.h 3 * \version 2.30 4 * 5 * \brief The header file of the PRA driver. The API is not intended to 6 * be used directly by the user application. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2020 Cypress Semiconductor Corporation 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 #if !defined(CY_PRA_CFG_H) 27 #define CY_PRA_CFG_H 28 29 #include "cy_device.h" 30 31 #if defined (CY_IP_MXS40SRSS) 32 33 #include <stdint.h> 34 #include <stdbool.h> 35 #include "cy_pra.h" 36 #include "cy_sysclk.h" 37 #include "cy_systick.h" 38 #include "cy_ble_clk.h" 39 #include "cy_device_headers.h" 40 41 #if defined (CY_DEVICE_SECURE) || defined (CY_DOXYGEN) 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 48 /******************************************************************************* 49 * Type Definitions 50 *******************************************************************************/ 51 52 /** \cond INTERNAL */ 53 54 #define CY_PRA_FREQUENCY_HZ_CONVERSION 1000000UL 55 #define CY_PRA_150MHZ_FREQUENCY 150UL 56 #define CY_PRA_FLL_ENABLE_TIMEOUT 200000UL 57 #define CY_PRA_ECO_ENABLE_TIMEOUT 3000UL 58 #define CY_PRA_WCO_ENABLE_TIMEOUT 1000000UL 59 #define CY_PRA_IMO_SRC_FREQUENCY 8000000UL 60 #define CY_PRA_ILO_SRC_FREQUENCY 32000UL 61 #define CY_PRA_WCO_SRC_FREQUENCY 32768UL 62 #define CY_PRA_PILO_SRC_FREQUENCY 32768UL 63 #define CY_PRA_DEFAULT_SRC_FREQUENCY 0xFFFFFFFEUL 64 #define CY_PRA_ULP_MODE_MAX_FREQUENCY 50000000UL 65 #define CY_PRA_LP_MODE_MAX_FREQUENCY 100000000UL 66 #define CY_PRA_ALTHF_MIN_FREQUENCY 2000000UL 67 #define CY_PRA_ALTHF_MAX_FREQUENCY 32000000UL 68 #define CY_PRA_ALTHF_FREQ_16MHZ 16000000UL 69 #define CY_PRA_ALTHF_FREQ_32MHZ 32000000UL 70 #define CY_PRA_ALTHF_MIN_STARTUP_TIME 400UL 71 #define CY_PRA_ALTHF_MAX_STARTUP_TIME 4704UL 72 #define CY_PRA_ALTHF_MIN_LOAD 0 73 #define CY_PRA_ALTHF_MAX_LOAD 251 74 75 #define CY_PRA_ECO_FREQ_MIN (16000000UL) /* 16 MHz */ 76 #define CY_PRA_ECO_FREQ_MAX (35000000UL) /* 35 MHz */ 77 #define CY_PRA_ECO_CSM_MIN (1UL) /* 1 pF */ 78 #define CY_PRA_ECO_CSM_MAX (100UL) /* 100 pF */ 79 #define CY_PRA_ECO_ESR_MIN (1UL) /* 1 Ohm */ 80 #define CY_PRA_ECO_ESR_MAX (1000UL) /* 1000 Ohm */ 81 #define CY_PRA_ECO_DRV_MIN (1UL) /* 1 kW */ 82 #define CY_PRA_ECO_DRV_MAX (1000UL) /* 1 mW */ 83 84 #define CY_PRA_FLL_SRC_MIN_FREQUENCY (1000UL) /* 1 KHz */ 85 #define CY_PRA_FLL_SRC_MAX_FREQUENCY (100000000UL) /* 100 MHz */ 86 #define CY_PRA_FLL_OUT_MIN_FREQUENCY (24000000UL) /* 24 MHz */ 87 #define CY_PRA_FLL_ULP_OUT_MAX_FREQUENCY (50000000UL) /* 50 MHz */ 88 #define CY_PRA_FLL_OUT_MAX_FREQUENCY ((CY_HF_CLK_MAX_FREQ > 100000000UL) ? (100000000UL) : (CY_HF_CLK_MAX_FREQ)) 89 #define CY_PRA_FLL_MIN_MULTIPLIER 1UL 90 #define CY_PRA_FLL_MAX_MULTIPLIER 262143UL 91 #define CY_PRA_FLL_MIN_REFDIV 1UL 92 #define CY_PRA_FLL_MAX_REFDIV 8191UL 93 #define CY_PRA_FLL_MAX_LOCK_TOLERENCE 511UL 94 95 #define CY_PRA_PLL_SRC_MIN_FREQUENCY (4000000UL) /* 4 MHz */ 96 #define CY_PRA_PLL_SRC_MAX_FREQUENCY (64000000UL) /* 64 MHz */ 97 #define CY_PRA_PLL_LOW_OUT_MIN_FREQUENCY (10625000UL) /* 10.625 MHz */ 98 #define CY_PRA_PLL_OUT_MIN_FREQUENCY (12500000UL) /* 12.5 MHz */ 99 #define CY_PRA_PLL_ULP_OUT_MAX_FREQUENCY (50000000UL) /* 50 MHz */ 100 #define CY_PRA_PLL_OUT_MAX_FREQUENCY (CY_HF_CLK_MAX_FREQ) 101 102 #define CY_PRA_HF0_MIN_FREQUENCY 200000UL 103 #define CY_PRA_PUMP_OUT_MAX_FREQUENCY 400000000UL 104 #define CY_PRA_BAK_OUT_MAX_FREQUENCY 100000UL 105 #define CY_PRA_FAST_OUT_MAX_FREQUENCY 400000000UL 106 #define CY_PRA_TIMER_OUT_MAX_FREQUENCY 400000000UL 107 #define CY_PRA_SLOW_OUT_MAX_FREQUENCY 100000000UL 108 #define CY_PRA_SYSTICK_OUT_MAX_FREQUENCY 400000000UL 109 #define CY_PRA_ULP_MODE_HF0_MAX_FREQUENCY 25000000UL 110 111 #define CY_PRA_DEFAULT_ZERO 0U 112 #define CY_PRA_DATA_ENABLE 1UL 113 #define CY_PRA_DATA_DISABLE 0UL 114 #define CY_PRA_CLKHF_0 0UL 115 #define CY_PRA_CLKHF_1 1UL 116 #define CY_PRA_CLKHF_2 2UL 117 #define CY_PRA_CLKHF_3 3UL 118 #define CY_PRA_CLKHF_4 4UL 119 #define CY_PRA_CLKHF_5 5UL 120 #define CY_PRA_CLKPATH_0 0U 121 #define CY_PRA_CLKPATH_1 1U 122 #define CY_PRA_CLKPATH_2 2U 123 #define CY_PRA_CLKPATH_3 3U 124 #define CY_PRA_CLKPATH_4 4U 125 #define CY_PRA_CLKPATH_5 5U 126 #define CY_PRA_CLKPLL_1 1U 127 #define CY_PRA_CLKPLL_2 2U 128 #define CY_PRA_DIVIDER_0 0U 129 #define CY_PRA_DIVIDER_1 1U 130 #define CY_PRA_DIVIDER_2 2U 131 #define CY_PRA_DIVIDER_4 4U 132 #define CY_PRA_DIVIDER_8 8U 133 134 /** \endcond */ 135 136 137 /** 138 * \addtogroup group_pra_stc 139 * \{ 140 */ 141 142 /** System configuration structure */ 143 typedef struct 144 { 145 bool powerEnable; /**< Power is enabled or disabled */ 146 bool ldoEnable; /**< Core Regulator */ 147 bool pmicEnable; /**< Power using external PMIC output */ 148 bool vBackupVDDDEnable; /**< vBackup source using VDD or Direct supply */ 149 bool ulpEnable; /**< System Active Power mode is ULP */ 150 bool ecoEnable; /**< ECO Enable */ 151 bool extClkEnable; /**< EXTCLK Enable */ 152 bool iloEnable; /**< ILO Enable */ 153 bool wcoEnable; /**< WCO Enable */ 154 bool fllEnable; /**< FLL Enable */ 155 bool pll0Enable; /**< PLL0 Enable */ 156 bool pll1Enable; /**< PLL1 Enable */ 157 bool path0Enable; /**< PATH_MUX0 Enable */ 158 bool path1Enable; /**< PATH_MUX1 Enable */ 159 bool path2Enable; /**< PATH_MUX2 Enable */ 160 bool path3Enable; /**< PATH_MUX3 Enable */ 161 bool path4Enable; /**< PATH_MUX4 Enable */ 162 bool path5Enable; /**< PATH_MUX5 Enable */ 163 bool clkFastEnable; /**< CLKFAST Enable */ 164 bool clkPeriEnable; /**< CLKPERI Enable */ 165 bool clkSlowEnable; /**< CLKSLOW Enable */ 166 bool clkHF0Enable; /**< CLKHF0 Enable */ 167 bool clkHF1Enable; /**< CLKHF1 Enable */ 168 bool clkHF2Enable; /**< CLKHF2 Enable */ 169 bool clkHF3Enable; /**< CLKHF3 Enable */ 170 bool clkHF4Enable; /**< CLKHF4 Enable */ 171 bool clkHF5Enable; /**< CLKHF5 Enable */ 172 bool clkPumpEnable; /**< CLKPUMP Enable */ 173 bool clkLFEnable; /**< CLKLF Enable */ 174 bool clkBakEnable; /**< CLKBAK Enable */ 175 bool clkTimerEnable; /**< CLKTIMER Enable */ 176 bool clkAltSysTickEnable; /**< CLKALTSYSTICK Enable */ 177 bool piloEnable; /**< PILO Enable */ 178 bool clkAltHfEnable; /**< BLE ECO Clock Enable */ 179 180 /* Power */ 181 cy_en_syspm_ldo_voltage_t ldoVoltage; /**< LDO Voltage (LP or ULP) */ 182 cy_en_syspm_buck_voltage1_t buckVoltage; /**< Buck Voltage */ 183 bool pwrCurrentModeMin; /**< Minimum core regulator current mode */ 184 185 /* System clocks */ 186 /* IMO is always enabled */ 187 /* ECO Configuration */ 188 uint32_t ecoFreqHz; /**< ECO Frequency in Hz */ 189 uint32_t ecoLoad; /**< Parallel Load Capacitance (pF) */ 190 uint32_t ecoEsr; /**< Equivalent series resistance (ohm) */ 191 uint32_t ecoDriveLevel; /**< Drive Level (uW) */ 192 GPIO_PRT_Type *ecoInPort; /**< ECO input port */ 193 GPIO_PRT_Type *ecoOutPort; /**< ECO output port */ 194 uint32_t ecoInPinNum; /**< ECO input pin number */ 195 uint32_t ecoOutPinNum; /**< ECO output pin number */ 196 197 /* EXTCLK Configuration */ 198 uint32_t extClkFreqHz; /**< External clock frequency in Hz */ 199 GPIO_PRT_Type *extClkPort; /**< External connection port */ 200 uint32_t extClkPinNum; /**< External connection pin */ 201 en_hsiom_sel_t extClkHsiom; /**< IO mux value */ 202 203 /* ILO Configuration */ 204 bool iloHibernateON; /**< Run in Hibernate Mode */ 205 206 /* WCO Configuration */ 207 bool bypassEnable; /**< Clock port bypass to External sine wave or to normal crystal */ 208 GPIO_PRT_Type *wcoInPort; /**< WCO Input port */ 209 GPIO_PRT_Type *wcoOutPort; /**< WCO Output port */ 210 uint32_t wcoInPinNum; /**< WCO Input pin */ 211 uint32_t wcoOutPinNum; /**< WCO Output pin */ 212 213 /* FLL Configuration */ 214 uint32_t fllOutFreqHz; /**< FLL Output Frequency in Hz */ 215 uint32_t fllMult; /**< CLK_FLL_CONFIG register, FLL_MULT bits */ 216 uint16_t fllRefDiv; /**< CLK_FLL_CONFIG2 register, FLL_REF_DIV bits */ 217 cy_en_fll_cco_ranges_t fllCcoRange; /**< CLK_FLL_CONFIG4 register, CCO_RANGE bits */ 218 bool enableOutputDiv; /**< CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit */ 219 uint16_t lockTolerance; /**< CLK_FLL_CONFIG2 register, LOCK_TOL bits */ 220 uint8_t igain; /**< CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits */ 221 uint8_t pgain; /**< CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits */ 222 uint16_t settlingCount; /**< CLK_FLL_CONFIG3 register, SETTLING_COUNT bits */ 223 cy_en_fll_pll_output_mode_t outputMode; /**< CLK_FLL_CONFIG3 register, BYPASS_SEL bits */ 224 uint16_t ccoFreq; /**< CLK_FLL_CONFIG4 register, CCO_FREQ bits */ 225 226 /* Number of PLL available for the device is defined in CY_SRSS_NUM_PLL 227 * Max 2 instances of PLLs are defined */ 228 229 /* PLL0 Configuration */ 230 uint32_t pll0OutFreqHz; /**< PLL0 output frequency in Hz */ 231 uint8_t pll0FeedbackDiv; /**< PLL0 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ 232 uint8_t pll0ReferenceDiv; /**< PLL0 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ 233 uint8_t pll0OutputDiv; /**< PLL0 CLK_PLL_CONFIG register, OUTPUT_DIV bits */ 234 bool pll0LfMode; /**< PLL0 CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 235 cy_en_fll_pll_output_mode_t pll0OutputMode; /**< PLL0 CLK_PLL_CONFIG register, BYPASS_SEL bits */ 236 237 /* PLL1 Configuration */ 238 uint32_t pll1OutFreqHz; /**< PLL1 output frequency in Hz */ 239 uint8_t pll1FeedbackDiv; /**< PLL1 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits */ 240 uint8_t pll1ReferenceDiv; /**< PLL1 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits */ 241 uint8_t pll1OutputDiv; /**< PLL1 CLK_PLL_CONFIG register, OUTPUT_DIV bits */ 242 bool pll1LfMode; /**< PLL1 CLK_PLL_CONFIG register, PLL_LF_MODE bit */ 243 cy_en_fll_pll_output_mode_t pll1OutputMode; /**< PLL1 CLK_PLL_CONFIG register, BYPASS_SEL bits */ 244 245 /* The number of clock paths available for the device is defined in CY_SRSS_NUM_CLKPATH. 246 * Max 6 clock paths are defined */ 247 248 /* Clock Paths Configuration */ 249 cy_en_clkpath_in_sources_t path0Src; /**< Input multiplexer0 clock source */ 250 cy_en_clkpath_in_sources_t path1Src; /**< Input multiplexer1 clock source */ 251 cy_en_clkpath_in_sources_t path2Src; /**< Input multiplexer2 clock source */ 252 cy_en_clkpath_in_sources_t path3Src; /**< Input multiplexer3 clock source */ 253 cy_en_clkpath_in_sources_t path4Src; /**< Input multiplexer4 clock source */ 254 cy_en_clkpath_in_sources_t path5Src; /**< Input multiplexer5 clock source */ 255 256 /* Clock Dividers */ 257 uint8_t clkFastDiv; /**< Fast clock divider. User has to pass actual divider-1 */ 258 uint8_t clkPeriDiv; /**< Peri clock divider. User has to pass actual divider-1 */ 259 uint8_t clkSlowDiv; /**< Slow clock divider. User has to pass actual divider-1 */ 260 261 /* The number of HF clocks is defined in the device specific header CY_SRSS_NUM_HFROOT 262 * Max 6 HFs are defined */ 263 /* HF Configurations */ 264 cy_en_clkhf_in_sources_t hf0Source; /**< HF0 Source Clock Path */ 265 cy_en_clkhf_dividers_t hf0Divider; /**< HF0 Divider */ 266 uint32_t hf0OutFreqMHz; /**< HF0 Output Frequency in MHz */ 267 cy_en_clkhf_in_sources_t hf1Source; /**< HF1 Source Clock Path */ 268 cy_en_clkhf_dividers_t hf1Divider; /**< HF1 Divider */ 269 uint32_t hf1OutFreqMHz; /**< HF1 Output Frequency in MHz */ 270 cy_en_clkhf_in_sources_t hf2Source; /**< HF2 Source Clock Path */ 271 cy_en_clkhf_dividers_t hf2Divider; /**< HF2 Divider */ 272 uint32_t hf2OutFreqMHz; /**< HF2 Output Frequency in MHz */ 273 cy_en_clkhf_in_sources_t hf3Source; /**< HF3 Source Clock Path */ 274 cy_en_clkhf_dividers_t hf3Divider; /**< HF3 Divider */ 275 uint32_t hf3OutFreqMHz; /**< HF3 Output Frequency in MHz */ 276 cy_en_clkhf_in_sources_t hf4Source; /**< HF4 Source Clock Path */ 277 cy_en_clkhf_dividers_t hf4Divider; /**< HF4 Divider */ 278 uint32_t hf4OutFreqMHz; /**< HF4 Output Frequency in MHz */ 279 cy_en_clkhf_in_sources_t hf5Source; /**< HF5 Source Clock Path */ 280 cy_en_clkhf_dividers_t hf5Divider; /**< HF5 Divider */ 281 uint32_t hf5OutFreqMHz; /**< HF5 Output Frequency in MHz */ 282 cy_en_clkpump_in_sources_t pumpSource; /**< PUMP Source Clock Path */ 283 cy_en_clkpump_divide_t pumpDivider; /**< PUMP Divider */ 284 285 /* Misc clock configurations */ 286 cy_en_clklf_in_sources_t clkLfSource; /**< Clock LF Source */ 287 cy_en_clkbak_in_sources_t clkBakSource; /**< Clock Backup domain Source */ 288 cy_en_clktimer_in_sources_t clkTimerSource; /**< Clock Timer Source */ 289 uint8_t clkTimerDivider; /**< Clock Timer Divider */ 290 cy_en_systick_clock_source_t clkSrcAltSysTick; /**< SysTick Source */ 291 292 /* BLE ECO */ 293 uint32_t altHFcLoad; /**< Load Cap (pF) */ 294 uint32_t altHFxtalStartUpTime; /**< Startup Time (us) */ 295 uint32_t altHFclkFreq; /**< Clock Frequency. 0 -> 16MHz and 1 -> 32MHz. Any other value except 0 and 1 is invalid */ 296 uint32_t altHFsysClkDiv; /**< Clock Divider */ 297 uint32_t altHFvoltageReg; /**< BLE Voltage Regulator */ 298 } cy_stc_pra_system_config_t; 299 /** \} group_pra_stc */ 300 301 /** \cond INTERNAL */ 302 /* External clock provisioned configuration */ 303 typedef struct 304 { 305 bool extClkEnable; /* EXTCLK Enable */ 306 bool ecoEnable; /* ECO Enable */ 307 bool wcoEnable; /* WCO Enable */ 308 bool bypassEnable; /* WCO Clock port bypass to External sine wave or to normal crystal */ 309 310 /* EXTCLK Configuration */ 311 uint32_t extClkFreqHz; /* External clock frequency in Hz */ 312 GPIO_PRT_Type *extClkPort; /* External connection port */ 313 uint32_t extClkPinNum; /* External connection pin */ 314 315 /* ECO Configuration */ 316 uint32_t ecoFreqHz; /* ECO Frequency in Hz */ 317 uint32_t ecoLoad; /* Parallel Load Capacitance (pF) */ 318 uint32_t ecoEsr; /* Equivalent series resistance (ohm) */ 319 uint32_t ecoDriveLevel; /* Drive Level (uW) */ 320 GPIO_PRT_Type *ecoInPort; /* ECO input port */ 321 GPIO_PRT_Type *ecoOutPort; /* ECO output port */ 322 uint32_t ecoInPinNum; /* ECO input pin number */ 323 uint32_t ecoOutPinNum; /* ECO output pin number */ 324 325 /* WCO Configuration */ 326 GPIO_PRT_Type *wcoInPort; /* WCO Input port */ 327 GPIO_PRT_Type *wcoOutPort; /* WCO Output port */ 328 uint32_t wcoInPinNum; /* WCO Input pin */ 329 uint32_t wcoOutPinNum; /* WCO Output pin */ 330 331 } cy_stc_pra_extclk_policy_t; 332 /** \endcond */ 333 334 /******************************************************************************* 335 * Global variables 336 *******************************************************************************/ 337 /** \cond INTERNAL */ 338 /* External clock provisioned configuration */ 339 extern cy_stc_pra_extclk_policy_t *extClkPolicyPtr; 340 /** \endcond */ 341 342 /******************************************************************************* 343 * Function Prototypes 344 *******************************************************************************/ 345 346 /** 347 * \addtogroup group_pra_functions 348 * \{ 349 */ 350 351 cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConfig); 352 353 /** \} group_pra_functions */ 354 355 #if (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) 356 uint32_t Cy_PRA_CalculateFLLOutFreq(const cy_stc_pra_system_config_t *devConfig); 357 uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig); 358 #endif /* (CY_CPU_CORTEX_M0P) || defined (CY_DOXYGEN) */ 359 360 #ifdef __cplusplus 361 } 362 #endif 363 364 #endif /* (CY_DEVICE_SECURE) */ 365 366 #endif /* defined (CY_IP_MXS40SRSS) */ 367 368 #endif /* #if !defined(CY_PRA_CFG_H) */ 369 370 /* [] END OF FILE */ 371
