1 /***************************************************************************//**
2 * \file cy_pdm_pcm_v2.h
3 * \version 1.10
4 *
5 * The header file of the PDM_PCM driver.
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright 2019-2022 Cypress Semiconductor Corporation
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 *     http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *******************************************************************************/
24 
25 /**
26 * \addtogroup group_pdm_pcm_v2
27 * \{
28 * \note IP Supported: PDM
29 * \note Device Categories: CAT1B and CAT1D. Please refer <a href="usergroup1.html">Device Catalog</a>.
30 *
31 * The pulse-density modulation to pulse-code modulation (PDM-PCM) driver provides an
32 * API to manage PDM-PCM conversion. A PDM-PCM converter is used
33 * to convert 1-bit digital audio streaming data to PCM data.
34 *
35 * The functions and other declarations used in this driver are in cy_pdm_pcm_v2.h.
36 * You can include cy_pdl.h (ModusToolbox only) to get access to all functions
37 * and declarations in the PDL.
38 *
39 * Features:
40 *        - Supports up to 8 PDM receivers
41 *        - Supports Stereo/Mono dual mode PDM (pulse-density-modulated) to PCM (pulse-code-modulated) conversion
42 *        - Half rate sampling to reduce system power consumption
43 *        - CIC filter, FIR filter, DC block filter signal processing path
44 *        - Programmable interface clock
45 *        - Programmable FIR filter coefficients
46 *        - Programmable CIC and FIR filter decimation
47 *        - Programmable DC blocking coefficient
48 *        - Programmable PCM word size (8, 10, 12, 14, 16, 18, 20, 24, 32 bits)
49 *        - Programmable sampling delay, to cope with different master-slavemaster roundtrip delays
50 *        - 64 entry RX FIFO with interrupt and trigger support
51 *        - Debug/freeze trigger support
52 *        - Receiver activate trigger support
53 *        - Test mode support, the IP includes a programmable PDM pattern    generator
54 *
55 * Pulse-density modulation, or PDM, represents
56 * an analog signal with a binary signal. In a PDM signal, specific amplitude values
57 * are not encoded into codewords of pulses of different weight as they would be
58 * in pulse-code modulation (PCM); rather, the relative density of the pulses corresponds
59 * to the analog signal's amplitude. The output of a 1-bit DAC is the same
60 * as the PDM encoding of the signal.
61 *
62 * Pulse-code modulation (PCM) is the method used to digitally represent sampled analog signals.
63 * It is the standard form of digital audio in computers, compact discs, digital telephony,
64 * and other digital audio applications. In a PCM stream, the amplitude of the analog signal
65 * is sampled regularly at uniform intervals, and each sample is quantized
66 * to the nearest value within a range of digital steps.
67 *
68 * \section group_pdm_pcm_configuration_considerations_v2 Configuration Considerations
69 *
70 * To set up a PDM-PCM, provide the configuration parameters in the
71 * \ref cy_stc_pdm_pcm_config_v2_t structure.
72 *
73 * Input frequency from source clock and the sampling rate Fs, is expressed as follows:
74 * <br>
75 * <b> CLK_IF_SRSS_FREQ = (CLOCK_CTL.CLOCK_DIV + 1) * M * Fs </b>
76 * <br>
77 * where M is the oversampling rate at the PDM source
78 * ![](pdm_pcm_sampling_rate.png)
79 *
80 * To initialize the PDM-PCM channels, call \ref Cy_PDM_PCM_Channel_Init function, providing the
81 * filled \ref cy_stc_pdm_pcm_channel_config_t structure
82 * To initialize the PDM-PCM block, call the \ref Cy_PDM_PCM_Init function, providing the
83 * filled \ref cy_stc_pdm_pcm_config_v2_t structure.
84 *
85 * If you use a DMA, the DMA channel should be previously configured. PDM-PCM interrupts
86 * (if applicable) can be enabled by calling \ref Cy_PDM_PCM_SetInterruptMask.
87 *
88 * For example, if the trigger interrupt is used during operation, the ISR
89 * should call the \ref Cy_PDM_PCM_ReadFifo as many times as required for your
90 * FIFO payload. Then call \ref Cy_PDM_PCM_Channel_ClearInterrupt with appropriate parameters.
91 *
92 * If a DMA is used and the DMA channel is properly configured, no CPU activity
93 * (or application code) is needed for PDM-PCM operation.
94 *
95 * \section group_pdm_pcm_changelog_v2 Changelog
96 * <table class="doxtable">
97 *   <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
98 *   <tr>
99 *     <td>1.10</td>
100 *     <td>Minor documentation updates.</td>
101 *     <td>Documentation enhancement.</td>
102 *     <td></td>
103 *   </tr>
104 *   <tr>
105 *     <td>1.0</td>
106 *     <td>Initial version</td>
107 *     <td></td>
108 *   </tr>
109 * </table>
110 *
111 * \defgroup group_pdm_pcm_macros_v2 Macros
112 * \defgroup group_pdm_pcm_functions_v2 Functions
113 * \defgroup group_pdm_pcm_data_structures_v2 Data Structures
114 * \defgroup group_pdm_pcm_enums_v2 Enumerated Types
115 *
116 */
117 
118 #if !defined (CY_PDM_PCM_V2_H__)
119 #define CY_PDM_PCM_V2_H__
120 
121 /******************************************************************************/
122 /* Include files                                                              */
123 /******************************************************************************/
124 
125 #include "cy_device.h"
126 
127 #if defined (CY_IP_MXPDM)
128 
129 #include "cy_syslib.h"
130 #include <stdint.h>
131 #include <stddef.h>
132 #include <stdbool.h>
133 
134 #ifdef __cplusplus
135 extern "C"
136 {
137 #endif
138 
139 /******************************************************************************
140  * Global definitions
141  ******************************************************************************/
142 
143 /* Macros */
144 /**
145 * \addtogroup group_pdm_pcm_macros_v2
146 * \{
147 */
148 
149 /** The driver major version */
150 #define CY_PDM_PCM_V2_DRV_VERSION_MAJOR       1
151 
152 /** The driver minor version */
153 #define CY_PDM_PCM_V2_DRV_VERSION_MINOR       1
154 
155 /** The PDM-PCM driver identifier */
156 #define CY_PDM_PCM_V2_ID                       CY_PDL_DRV_ID(0x73u)
157 
158 /**
159 * \defgroup group_pdm_pcm_macros_interrupt_masks_v2 Interrupt Masks
160 * \{
161 */
162 
163 /** More entries in the RX FIFO than specified by Trigger Level*/
164 #define CY_PDM_PCM_INTR_RX_TRIGGER         (PDM_CH_INTR_RX_FIFO_TRIGGER_Msk)
165 /** Attempt to write to a full RX FIFO*/
166 #define CY_PDM_PCM_INTR_RX_OVERFLOW       (PDM_CH_INTR_RX_FIFO_OVERFLOW_Msk)
167 /** Attempt to read from an empty RX FIFO*/
168 #define CY_PDM_PCM_INTR_RX_UNDERFLOW        (PDM_CH_INTR_RX_FIFO_UNDERFLOW_Msk)
169 /** CIC filter PCM samples are produced at a faster rate than the FIR filter can process them*/
170 #define CY_PDM_PCM_INTR_RX_FIR_OVERFLOW       (PDM_CH_INTR_RX_FIR_OVERFLOW_Msk)
171 /** when PDM samples are generated too fast*/
172 #define CY_PDM_PCM_INTR_RX_IF_OVERFLOW       (PDM_CH_INTR_RX_IF_OVERFLOW_Msk)
173 
174 /** \} group_pdm_pcm_macros_interrupt_masks_v2 */
175 
176 /** \} group_pdm_pcm_macros_v2 */
177 
178 /**
179 * \addtogroup group_pdm_pcm_enums_v2
180 * \{
181 */
182 
183 /** PDM Word Length*/
184 typedef enum
185 {
186     CY_PDM_PCM_WSIZE_8_BIT      = 0U,         /**< Word length: 8 bit*/
187     CY_PDM_PCM_WSIZE_10_BIT     = 1U,         /**< Word length: 10 bit*/
188     CY_PDM_PCM_WSIZE_12_BIT     = 2U,         /**< Word length: 12 bit*/
189     CY_PDM_PCM_WSIZE_14_BIT     = 3U,         /**< Word length: 14 bit*/
190     CY_PDM_PCM_WSIZE_16_BIT     = 4U,         /**< Word length: 16 bit*/
191     CY_PDM_PCM_WSIZE_18_BIT     = 5U,         /**< Word length: 18 bit*/
192     CY_PDM_PCM_WSIZE_20_BIT     = 6U,         /**< Word length: 20 bit*/
193     CY_PDM_PCM_WSIZE_24_BIT     = 7U,         /**< Word length: 24 bit*/
194     CY_PDM_PCM_WSIZE_32_BIT     = 8U          /**< Word length: 32 bit*/
195 } cy_en_pdm_pcm_word_size_t;
196 
197 /** cy_en_pdm_pcm_clock_sel_t*/
198 typedef enum
199 {
200     CY_PDM_PCM_SEL_SRSS_CLOCK   = 0U,         /**< Interface clock is selected as clk_if_srss[0]*/
201     CY_PDM_PCM_SEL_PDM_DATA0    = 1U,         /**< Interface clock is selected as pdm_data[0]*/
202     CY_PDM_PCM_SEL_PDM_DATA1    = 2U,         /**< Interface clock is selected as pdm_data[1]*/
203     CY_PDM_PCM_SEL_OFF          = 3U          /**< Interface clock clk_if is off*/
204 } cy_en_pdm_pcm_clock_sel_t;
205 
206 /** PDM Halve Rate Sampling*/
207 typedef enum
208 {
209     CY_PDM_PCM_RATE_FULL       = 0U,         /**< Channel full*/
210     CY_PDM_PCM_RATE_HALVE      = 1U          /**< Channel halve*/
211 } cy_en_pdm_pcm_halve_rate_sel_t;
212 
213 /** CIC DECIMATION CODE*/
214 typedef enum
215 {
216     CY_PDM_PCM_CHAN_CIC_DECIM_2   = 0U,         /**< CIC Filter PCM Frequency is 1/2 * PDM Frequency*/
217     CY_PDM_PCM_CHAN_CIC_DECIM_4   = 1U,         /**< CIC Filter PCM Frequency is 1/4 * PDM Frequency*/
218     CY_PDM_PCM_CHAN_CIC_DECIM_8   = 2U,         /**< CIC Filter PCM Frequency is 1/8 * PDM Frequency*/
219     CY_PDM_PCM_CHAN_CIC_DECIM_16  = 3U,         /**< CIC Filter PCM Frequency is 1/16 * PDM Frequency*/
220     CY_PDM_PCM_CHAN_CIC_DECIM_32  = 4U          /**< CIC Filter PCM Frequency is 1/32 * PDM Frequency*/
221 } cy_en_pdm_pcm_ch_cic_decimcode_t;
222 
223 /** FIR0 DECIMATION CODE*/
224 typedef enum
225 {
226     CY_PDM_PCM_CHAN_FIR0_DECIM_1  = 0U,         /**< FIR0 Filter PCM Frequency is 1/1 * PCM Frequency*/
227     CY_PDM_PCM_CHAN_FIR0_DECIM_2  = 1U,         /**< FIR0 Filter PCM Frequency is 1/2 * PCM Frequency*/
228     CY_PDM_PCM_CHAN_FIR0_DECIM_3  = 2U,         /**< FIR0 Filter PCM Frequency is 1/3 * PCM Frequency*/
229     CY_PDM_PCM_CHAN_FIR0_DECIM_4  = 3U,         /**< FIR0 Filter PCM Frequency is 1/4 * PCM Frequency*/
230     CY_PDM_PCM_CHAN_FIR0_DECIM_5  = 4U          /**< FIR0 Filter PCM Frequency is 1/5 * PCM Frequency*/
231 } cy_en_pdm_pcm_ch_fir0_decimcode_t;
232 
233 /** FIR1 DECIMATION CODE*/
234 typedef enum
235 {
236     CY_PDM_PCM_CHAN_FIR1_DECIM_1   = 0U,         /**< FIR1 Filter PCM Frequency is 1/1 * PCM Frequency*/
237     CY_PDM_PCM_CHAN_FIR1_DECIM_2   = 1U,         /**< FIR1 Filter PCM Frequency is 1/2 * PCM Frequency*/
238     CY_PDM_PCM_CHAN_FIR1_DECIM_3   = 2U,         /**< FIR1 Filter PCM Frequency is 1/3 * PCM Frequency*/
239     CY_PDM_PCM_CHAN_FIR1_DECIM_4   = 3U,         /**< FIR1 Filter PCM Frequency is 1/4 * PCM Frequency*/
240 } cy_en_pdm_pcm_ch_fir1_decimcode_t;
241 
242 /** DC Block CODE*/
243 typedef enum
244 {
245     CY_PDM_PCM_CHAN_DCBLOCK_CODE_1   = 0U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-0))*/
246     CY_PDM_PCM_CHAN_DCBLOCK_CODE_2   = 1U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-1))*/
247     CY_PDM_PCM_CHAN_DCBLOCK_CODE_4   = 2U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-2))*/
248     CY_PDM_PCM_CHAN_DCBLOCK_CODE_8   = 3U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-3))*/
249     CY_PDM_PCM_CHAN_DCBLOCK_CODE_16  = 4U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-4))*/
250     CY_PDM_PCM_CHAN_DCBLOCK_CODE_32  = 5U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-5))*/
251     CY_PDM_PCM_CHAN_DCBLOCK_CODE_64  = 6U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-6))*/
252     CY_PDM_PCM_CHAN_DCBLOCK_CODE_128 = 7U,         /**< DCBLOCK Filter alpha = 1 - (1/2^(12-7))*/
253 } cy_en_pdm_pcm_ch_dcblock_coef_t;
254 
255 /** \cond INTERNAL */
256 /** PDM Output Mode*/
257 typedef enum
258 {
259     CY_PDM_PCM_OUT_CHAN_LEFT   = 1U,         /**< Channel mono left*/
260     CY_PDM_PCM_OUT_CHAN_RIGHT  = 2U,         /**< Channel mono right*/
261     CY_PDM_PCM_OUT_STEREO      = 3U          /**< Channel stereo*/
262 } cy_en_pdm_pcm_out_t;
263 /** \endcond */
264 
265 /** The PDM-PCM status codes*/
266 typedef enum
267 {
268     CY_PDM_PCM_SUCCESS         = 0x00UL,    /**< Success status code*/
269     CY_PDM_PCM_BAD_PARAM       = CY_PDM_PCM_V2_ID | CY_PDL_STATUS_ERROR |0x01UL     /**< Bad parameter status code*/
270 } cy_en_pdm_pcm_status_t;
271 
272 /** \} group_pdm_pcm_enums_v2 */
273 
274 
275 /**
276 * \addtogroup group_pdm_pcm_data_structures_v2
277 * \{
278 */
279 
280 /******************************************************************************
281  * Global type definitions
282  ******************************************************************************/
283 
284  /** PDM-PCM Test Mode configuration */
285  typedef struct
286  {
287      uint8_t drive_delay_hi;                /**< Interface drive delay on the high phase of the PDM interface clock.
288                                              This field specifies when a PDM value is driven expressed in clk_if clock cycles.
289                                              DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]:
290                                             "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm.
291                                             "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm.
292                                             ...
293                                             "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm*/
294      uint8_t drive_delay_lo;                /**< Interface drive delay on the low phase of the PDM interface clock.
295                                              This field specifies when a PDM value is driven expressed in clk_if clock cycles.
296                                              DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]:
297                                             "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm.
298                                             "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm.
299                                             ...
300                                             "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm*/
301      uint8_t mode_hi;                        /**< Pattern generator mode on the high phase of the PDM interface clock.
302                                             This field specifies the type of pattern driven by the generator:
303                                             "0": constant 0's
304                                             "1": constant 1's
305                                             "2": alternating 0's and 1's (clock pattern)
306                                             "3": sine wave */
307      uint8_t mode_lo;                        /**< Pattern generator mode on the low phase of the PDM interface clock.
308                                             This field specifies the type of pattern driven by the generator:
309                                             "0": constant 0's
310                                             "1": constant 1's
311                                             "2": alternating 0's and 1's (clock pattern)
312                                             "3": sine wave */
313      uint8_t audio_freq_div;                /**< Frequency division factor (legal range [3, 13]) to obtain audio frequency
314                                             from the PDM clock frequency. This field determines the frequency of the sine wave
315                                             generated by the pattern generator when MODE=3. The formula is below:
316                                             Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV) */
317      bool    enable;            /**<  enable*/
318 
319 
320  }cy_stc_test_config_t;
321 
322  /** PDM-PCM fir coeff_data structure */
323  typedef struct
324  {
325 
326     int16_t         coeff_data0;            /**<  filter taps coefficients data 0*/
327     int16_t         coeff_data1;            /**<  filter taps coefficients data 1*/
328  }cy_stc_pdm_pcm_fir_coeff_t;
329 
330  /** PDM-PCM Channel initialization configuration */
331  typedef struct
332  {
333     uint8_t                               sampledelay;    /**< Interface sample delay. This field specifies when a PDM value is captured. The value that user assigns here will be incremented by 1 and assigned internally */
334 
335     cy_en_pdm_pcm_word_size_t             wordSize;       /**< see #cy_en_pdm_pcm_word_size_t */
336     bool                                 signExtension;  /**< Word extension type:
337                                                         - 0: extension by zero
338                                                         - 1: extension by sign bits */
339 
340     uint8_t                              rxFifoTriggerLevel;  /**< Fifo interrupt trigger level (in words),
341                                                         range: 0 - 63  */
342 
343     bool                                fir0_enable;    /**< FIR 0 filter coefficient enable (does NOT effect FIR filter scaling and FIR filter decimation):
344                                                          - 0: Disabled
345                                                          - 1: Enabled */
346 
347 
348     cy_en_pdm_pcm_ch_cic_decimcode_t     cic_decim_code; /**< CIC filter decimation. The CIC filter PCM frequency is a fraction of the PDM frequency. \ref cy_en_pdm_pcm_ch_cic_decimcode_t */
349 
350     cy_en_pdm_pcm_ch_fir0_decimcode_t    fir0_decim_code;/**< FIR filter decimation. The FIR filter PCM frequency is a fraction of the CIC filter PCM frequency. \ref cy_en_pdm_pcm_ch_fir0_decimcode_t */
351 
352     uint8_t                                fir0_scale;        /**< FIR 0 filter PCM scaling. range 0-31 */
353 
354     cy_en_pdm_pcm_ch_fir1_decimcode_t    fir1_decim_code;/**< FIR filter decimation. The FIR filter PCM frequency is a fraction of the FIR0 filter PCM frequency. \ref cy_en_pdm_pcm_ch_fir1_decimcode_t */
355 
356     uint8_t                                fir1_scale;        /**< FIR 1 filter PCM scaling. range 0 to 31 */
357 
358     bool                                   dc_block_disable;  /**< Disables DC BLOCK if set to true. This is for debug only. To be used for test modes 0,1 and 2 in test config ie. if the input is constant 0's or constant 1's or alternating 0's and 1's*/
359 
360     cy_en_pdm_pcm_ch_dcblock_coef_t        dc_block_code;    /**< DC blocker coefficient. \ref cy_en_pdm_pcm_ch_dcblock_coef_t*/
361  } cy_stc_pdm_pcm_channel_config_t;
362 
363 
364 /** PDM-PCM initialization configuration */
365 typedef struct
366 {
367     uint8_t                             clkDiv;         /**< PDM Clock Divider
368                                                         This configures a frequency of PDM CLK. The configured frequency
369                                                         is used to operate PDM core. The value that user assigns here will be incremented by 1 and assigned internally. For example, if the clkDiv value is 0, it is internally incremented by 1.*/
370     cy_en_pdm_pcm_clock_sel_t           clksel;         /**< Interface clock clk_if selection. \ref cy_en_pdm_pcm_clock_sel_t */
371     cy_en_pdm_pcm_halve_rate_sel_t      halverate;      /**< Halve rate sampling. \ref cy_en_pdm_pcm_halve_rate_sel_t*/
372     uint8_t                             route;          /**< Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver.
373                                                         Each PDM receiver j has a dedicated     1-bit control field: PDM receiver j uses DATA_SEL[j].
374                                                         The 1-bit field DATA_SEL[j] specification is as follows:
375                                                         '0': PDM receiver j uses data input signal "pdm_data[j]".
376                                                         '1': PDM receiver j uses data input signal "pdm_data[j ^ 1]" (the lower bit of the index is inverted)*/
377 
378 
379     uint8_t fir0_coeff_user_value;    /**< FIR 0 filter coefficient enable. User has to configure the coeff values. 0: Disabled. 1: Enabled*/
380 
381     uint8_t fir1_coeff_user_value;    /**< FIR 1 filter coefficient enable. User has to configure the coeff values. 0: Disabled. 1: Enabled*/
382 
383     cy_stc_pdm_pcm_fir_coeff_t             fir0_coeff[8];   /**<  The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients
384                                                             (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7.
385                                                             The FIR filter coefficients have no default values:
386                                                             the coefficients MUST be programmed BEFORE the filter is enabled.
387                                                             By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies*/
388 
389     cy_stc_pdm_pcm_fir_coeff_t             fir1_coeff[14];        /**< The (symmetric) 55-taps finite impulse response (FIR) filter
390                                                             with 14-bit signed coefficients (in the range [-8192, 8191])
391                                                             are specified by FIR1_COEFF0, ..., FIR1_COEFF13.
392                                                             The (default) FIR filter has built in droop correction.
393                                                             The filter gain (sum of the coefficients) is 13921 and the default
394                                                             coefficients (as specified by FIR1_COEFFx.DATA0/1[13:0]) are:
395                                                             (-2,   21), (26,  -17), (-41,   25), (68, -33),
396                                                             (-107,   41), (160,  -48), (-230,   54), (325, -56),
397                                                             (-453,   51), (631,  -31), (-894,  -21), (1326, 172),
398                                                             (-2191, -770), (4859, 8191)*/
399 } cy_stc_pdm_pcm_config_v2_t;
400 
401 /** \cond INTERNAL */
402 typedef cy_stc_pdm_pcm_config_v2_t cy_stc_pdm_pcm_config_t;
403 /** \endcond */
404 
405 /** \} group_pdm_pcm_data_structures_v2 */
406 
407 
408 /** \cond INTERNAL */
409 /******************************************************************************
410  * Local definitions
411 *******************************************************************************/
412 /** Define bit mask for all available interrupt sources */
413 #define CY_PDM_PCM_INTR_MASK        (CY_PDM_PCM_INTR_RX_TRIGGER           | \
414                                      CY_PDM_PCM_INTR_RX_FIR_OVERFLOW     | \
415                                      CY_PDM_PCM_INTR_RX_OVERFLOW          | \
416                                      CY_PDM_PCM_INTR_RX_IF_OVERFLOW      | \
417                                      CY_PDM_PCM_INTR_RX_UNDERFLOW)
418 
419 /* Non-zero default values */
420 #define CY_PDM_PCM_CH_IF_CTL_DEFAULT    (0x3U)
421 
422 #define CY_PDM_PCM_CLK_DIV_MAX 255
423 
424 #define CY_PDM_PCM_CH_CIC_DECIM_CODE_DEFAULT    (0x4U)
425 #define CY_PDM_PCM_CH_FIR0_DECIM_CODE_DEFAULT   (0x0U)
426 #define CY_PDM_PCM_CH_FIR0_SCALE_DEFAULT           (0x0U)
427 #define CY_PDM_PCM_CH_FIR1_DECIM_CODE_DEFAULT   (0x1U)
428 #define CY_PDM_PCM_CH_FIR1_SCALE_DEFAULT           (0x0FU)
429 #define CY_PDM_PCM_CH_FIR1_ENABLE_DEFAULT       (0x1U)
430 #define CY_PDM_PCM_CH_DCBLOCK_CODE_DEFAULT       (0x1U)
431 #define CY_PDM_PCM_CH_DCBLOCK_ENABLE_DEFAULT       (0x1U)
432 
433 #define PDM_TEST_CTL_DRIVE_DELAY_HI_DEFAULT       (0x00U)
434 #define PDM_TEST_CTL_DRIVE_DELAY_LO_DEFAULT       (0x04U)
435 #define PDM_TEST_CTL_MODE_HI_DEFAULT               (0x3U)
436 #define PDM_TEST_CTL_MODE_LO_DEFAULT               (0x3U)
437 #define PDM_TEST_CTL_AUDIO_FREQ_DIV_DEFAULT       (0x7U)
438 #define PDM_TEST_CTL_CH_ENABLED_DEFAULT           (0x0U)
439 
440 #define PDM_CLOCK_CTL_CLOCK_DIV_DEFAULT           (0x07U)
441 #define PDM_CLOCK_CTL_CLOCK_SEL_DEFAULT           (0x3U)
442 #define PDM_CLOCK_CTL_HALVE_DEFAULT               (0x0U)
443 
444 
445 #define CY_PDM_PCM_ENABLE  (0x1U)
446 #define CY_PDM_PCM_DISABLE (0x0U)
447 
448 
449 
450 #define CY_PDM_PCM_CH_CTL_WORDSIZE_DEFAULT        (0x0U)
451 #define CY_PDM_PCM_CH_CTL_WORDSIGN_EXT_DEFAULT  (0x100U)
452 #define CY_PDM_PCM_CH_CTL_CH_ENABLE_DEFAULT        (0x00000000U)
453 
454 #define CY_PDM_PCM_TEST_CTL_DEFAULT (_VAL2FLD(PDM_TEST_CTL_DRIVE_DELAY_HI, PDM_TEST_CTL_DRIVE_DELAY_HI_DEFAULT) | \
455                                 _VAL2FLD(PDM_TEST_CTL_DRIVE_DELAY_LO, PDM_TEST_CTL_DRIVE_DELAY_LO_DEFAULT) | \
456                                 _VAL2FLD(PDM_TEST_CTL_MODE_HI, PDM_TEST_CTL_MODE_HI_DEFAULT) | \
457                                 _VAL2FLD(PDM_TEST_CTL_MODE_LO, PDM_TEST_CTL_MODE_LO_DEFAULT) | \
458                                 _VAL2FLD(PDM_TEST_CTL_AUDIO_FREQ_DIV, PDM_TEST_CTL_AUDIO_FREQ_DIV_DEFAULT) | \
459                                 _VAL2FLD(PDM_TEST_CTL_CH_ENABLED, PDM_TEST_CTL_CH_ENABLED_DEFAULT))
460 
461 #define CY_PDM_PCM_CLK_CTL_DEFAULT (_VAL2FLD(PDM_CLOCK_CTL_CLOCK_DIV, PDM_CLOCK_CTL_CLOCK_DIV_DEFAULT) | \
462                                 _VAL2FLD(PDM_CLOCK_CTL_CLOCK_SEL, PDM_CLOCK_CTL_CLOCK_SEL_DEFAULT) | \
463                                 _VAL2FLD(PDM_CLOCK_CTL_HALVE, PDM_CLOCK_CTL_HALVE_DEFAULT))
464 
465 #define CY_PDM_PCM_CH_CTL_DEFAULT (_VAL2FLD(PDM_CH_CTL_WORD_SIZE, CY_PDM_PCM_CH_CTL_WORDSIZE_DEFAULT) | \
466                                 _VAL2FLD(PDM_CH_CTL_WORD_SIGN_EXTEND, CY_PDM_PCM_CH_CTL_WORDSIGN_EXT_DEFAULT) | \
467                                 _VAL2FLD(PDM_CH_CTL_ENABLED, CY_PDM_PCM_CH_CTL_CH_ENABLE_DEFAULT))
468 
469 #define CY_PDM_PCM_CH_FIR1_DEFAULT (_VAL2FLD(PDM_CH_FIR1_CTL_DECIM2, CY_PDM_PCM_CH_FIR1_DECIM_CODE_DEFAULT) | \
470                                 _VAL2FLD(PDM_CH_FIR1_CTL_SCALE, CY_PDM_PCM_CH_FIR1_SCALE_DEFAULT) | \
471                                 _VAL2FLD(PDM_CH_FIR1_CTL_ENABLED, CY_PDM_PCM_CH_FIR1_ENABLE_DEFAULT))
472 
473 #define CY_PDM_PCM_CH_DCBLOCK_DEFAULT (_VAL2FLD(PDM_CH_DC_BLOCK_CTL_CODE, CY_PDM_PCM_CH_DCBLOCK_CODE_DEFAULT) | \
474                                 _VAL2FLD(PDM_CH_DC_BLOCK_CTL_ENABLED, CY_PDM_PCM_CH_DCBLOCK_ENABLE_DEFAULT))
475 
476 
477 
478 /* Macros for conditions used by CY_ASSERT calls */
479 
480 #define CY_PDM_PCM_IS_CLK_DIV_VALID(clkDiv)    (((clkDiv)  >= 1U) && ((clkDiv) <= CY_PDM_PCM_CLK_DIV_MAX))
481 
482 #define CY_PDM_PCM_IS_CLK_SEL_VALID(clksel)    (((clksel) == CY_PDM_PCM_SEL_SRSS_CLOCK)   || \
483                                                 ((clksel) == CY_PDM_PCM_SEL_PDM_DATA0)       || \
484                                                 ((clksel) == CY_PDM_PCM_SEL_PDM_DATA1)    || \
485                                                 ((clksel) == CY_PDM_PCM_SEL_OFF))
486 
487 #define CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(halverate) (((halverate) == CY_PDM_PCM_RATE_FULL)  || \
488                                                        ((halverate) == CY_PDM_PCM_RATE_HALVE))
489 
490 #define CY_PDM_PCM_IS_ROUTE_VALID(route)        ((route) <= 126)
491 
492 #define CY_PDM_PCM_IS_CH_SET_VALID(chanselect)    (((chanselect) >= 1U) && ((chanselect) <= 255))
493 
494 #define CY_PDM_PCM_IS_SAMPLE_DELAY_VALID(sampledelay)    ((sampledelay) <= 255)
495 
496 #define CY_PDM_PCM_IS_WORD_SIZE_VALID(wordSize) (((wordSize) == CY_PDM_PCM_WSIZE_8_BIT) || \
497                                                 ((wordSize) == CY_PDM_PCM_WSIZE_10_BIT) || \
498                                                 ((wordSize) == CY_PDM_PCM_WSIZE_12_BIT) || \
499                                                 ((wordSize) == CY_PDM_PCM_WSIZE_14_BIT) || \
500                                                 ((wordSize) == CY_PDM_PCM_WSIZE_16_BIT) || \
501                                                 ((wordSize) == CY_PDM_PCM_WSIZE_18_BIT) || \
502                                                 ((wordSize) == CY_PDM_PCM_WSIZE_20_BIT) || \
503                                                 ((wordSize) == CY_PDM_PCM_WSIZE_24_BIT) || \
504                                                 ((wordSize) == CY_PDM_PCM_WSIZE_32_BIT))
505 
506 #define CY_PDM_PCM_IS_SCALE_VALID(scale)        ((scale) <= 31)
507 
508 #define CY_PDM_PCM_IS_ENABLE_VALID(enable)         ((enable == 0)||(enable == 1))
509 
510 #define CY_PDM_PCM_IS_SIGNEXTENSION_VALID(signExtension) ((signExtension == 0)||(signExtension == 1))
511 
512 #define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)  (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_INTR_MASK)))
513 #define CY_PDM_PCM_IS_TRIG_LEVEL(trigLevel)     ((trigLevel) <= 63)
514 
515 /** \endcond */
516 
517 /**
518 * \addtogroup group_pdm_pcm_functions_v2
519 * \{
520 */
521 
522 cy_en_pdm_pcm_status_t Cy_PDM_PCM_Channel_Init(PDM_Type * base, cy_stc_pdm_pcm_channel_config_t const * channel_config, uint8_t channel_num);
523 void Cy_PDM_PCM_Channel_DeInit(PDM_Type * base, uint8_t channel_num);
524 
525 cy_en_pdm_pcm_status_t   Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config);
526                 void     Cy_PDM_PCM_DeInit(PDM_Type * base);
527 
528 cy_en_pdm_pcm_status_t      Cy_PDM_PCM_test_Init(PDM_Type * base, cy_stc_pdm_pcm_config_v2_t const * config, cy_stc_test_config_t const * test_config);
529 
530 __STATIC_INLINE void      Cy_PDM_PCM_Activate_Channel(PDM_Type * base, uint8_t channel_num);
531 __STATIC_INLINE void      Cy_PDM_PCM_DeActivate_Channel(PDM_Type * base, uint8_t channel_num);
532 __STATIC_INLINE void     Cy_PDM_PCM_SetRateSampling(PDM_Type * base, cy_en_pdm_pcm_halve_rate_sel_t rate);
533 
534 __STATIC_INLINE void     Cy_PDM_PCM_Channel_Enable(PDM_Type * base, uint8_t channel_num);
535 __STATIC_INLINE void     Cy_PDM_PCM_Channel_Disable(PDM_Type * base, uint8_t channel_num);
536 __STATIC_INLINE void     Cy_PDM_PCM_Channel_Set_Cic_DecimCode(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_cic_decimcode_t decimcode);
537 __STATIC_INLINE void     Cy_PDM_PCM_Channel_Set_Fir0(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_fir0_decimcode_t decimcode,uint8_t scale);
538 __STATIC_INLINE void     Cy_PDM_PCM_Channel_Set_Fir1(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_fir1_decimcode_t decimcode,uint8_t scale);
539 __STATIC_INLINE void     Cy_PDM_PCM_Channel_Set_DCblock(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_dcblock_coef_t coef);
540 __STATIC_INLINE void     Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base, uint8_t channel_num, uint32_t interrupt);
541 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptMask(PDM_Type const * base, uint8_t channel_num);
542 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatusMasked(PDM_Type const * base, uint8_t channel_num);
543 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatus(PDM_Type const * base, uint8_t channel_num);
544 __STATIC_INLINE void     Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt);
545 __STATIC_INLINE void     Cy_PDM_PCM_Channel_SetInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt);
546 __STATIC_INLINE uint8_t  Cy_PDM_PCM_Channel_GetNumInFifo(PDM_Type const * base, uint8_t channel_num);
547 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifo(PDM_Type const * base, uint8_t channel_num);
548 __STATIC_INLINE void     Cy_PDM_PCM_Channel_FreezeFifo(PDM_Type * base, uint8_t channel_num);
549 __STATIC_INLINE void     Cy_PDM_PCM_Channel_UnfreezeFifo(PDM_Type * base, uint8_t channel_num);
550 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifoSilent(PDM_Type const * base, uint8_t channel_num);
551 
552 
553 /** \} group_pdm_pcm_functions_v2 */
554 
555 /**
556 * \addtogroup group_pdm_pcm_functions_v2
557 * \{
558 */
559 
560 /******************************************************************************
561 * Function Name: Cy_PDM_PCM_Channel_Enable
562 ***************************************************************************//**
563 *
564 * Enables the PDM-PCM data conversion.
565 *
566 * \param base The pointer to the  PDM-PCM instance address.
567 * \param channel_num Channel number to be enabled
568 *
569 * \funcusage
570 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_Enable
571 *
572 ******************************************************************************/
Cy_PDM_PCM_Channel_Enable(PDM_Type * base,uint8_t channel_num)573 __STATIC_INLINE void Cy_PDM_PCM_Channel_Enable(PDM_Type * base, uint8_t channel_num)
574 {
575     PDM_PCM_CH_CTL(base,channel_num) |= PDM_CH_CTL_ENABLED_Msk;
576 
577 }
578 
579 /******************************************************************************
580 * Function Name: Cy_PDM_PCM_Channel_Disable
581 ***************************************************************************//**
582 *
583 * Disables the PDM-PCM data conversion.
584 *
585 * \param base The pointer to the PDM-PCM instance address.
586 * \param channel_num Channel number to be disabled
587 *
588 * \funcusage
589 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_Disable
590 *
591 ******************************************************************************/
Cy_PDM_PCM_Channel_Disable(PDM_Type * base,uint8_t channel_num)592 __STATIC_INLINE void Cy_PDM_PCM_Channel_Disable(PDM_Type * base, uint8_t channel_num)
593 {
594     PDM_PCM_CH_CTL(base,channel_num) &= (uint32_t) ~PDM_CH_CTL_ENABLED_Msk;
595 
596 }
597 
598 /******************************************************************************
599 * Function Name: Cy_PDM_PCM_Activate_Channel
600 ***************************************************************************//**
601 *
602 * Activates the PDM-PCM channel.
603 *
604 * \param base The pointer to the  PDM-PCM instance address.
605 * \param channel_num Channel number to be activated
606 *
607 * \funcusage
608 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Activate_Channel
609 *
610 ******************************************************************************/
Cy_PDM_PCM_Activate_Channel(PDM_Type * base,uint8_t channel_num)611 __STATIC_INLINE void Cy_PDM_PCM_Activate_Channel(PDM_Type * base, uint8_t channel_num)
612 {
613     PDM_PCM_CTL_SET(base) = (1UL << channel_num);
614 }
615 
616 /******************************************************************************
617 * Function Name: Cy_PDM_PCM_DeActivate_Channel
618 ***************************************************************************//**
619 *
620 * DeActivates the PDM-PCM channel.
621 *
622 * \param base The pointer to the  PDM-PCM instance address.
623 * \param channel_num Channel number to be deactivated
624 *
625 * \funcusage
626 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_DeActivate_Channel
627 *
628 ******************************************************************************/
Cy_PDM_PCM_DeActivate_Channel(PDM_Type * base,uint8_t channel_num)629 __STATIC_INLINE void Cy_PDM_PCM_DeActivate_Channel(PDM_Type * base, uint8_t channel_num)
630 {
631     PDM_PCM_CTL_CLR(base) = (1UL << channel_num);
632 }
633 
634 
635 /******************************************************************************
636 * Function Name: Cy_PDM_PCM_Channel_GetCurrentState
637 ***************************************************************************//**
638 *
639 * Returns the current PDM-PCM state (active/stopped).
640 *
641 * \param base The pointer to the PDM-PCM instance address.
642 * \param channel_num Channel number
643 * \return true if channel is active, false when stopped.
644 *
645 * \funcusage
646 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_GetCurrentState
647 *
648 ******************************************************************************/
Cy_PDM_PCM_Channel_GetCurrentState(PDM_Type const * base,uint8_t channel_num)649 __STATIC_INLINE bool Cy_PDM_PCM_Channel_GetCurrentState(PDM_Type const * base, uint8_t channel_num)
650 {
651     return ((bool) (PDM_PCM_CTL(base) & (1UL << channel_num)));
652 }
653 
654 
655 /******************************************************************************
656 * Function Name: Cy_PDM_PCM_Channel_SetRateSampling
657 ***************************************************************************//**
658 *
659 * Sets Halve rate Sampling rate.
660 *
661 * \param base The pointer to the PDM-PCM instance address.
662 * \param rate Halve rate sampling or Full rate sampling \ref cy_en_pdm_pcm_halve_rate_sel_t.
663 *
664 * \funcusage
665 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_SetRateSampling
666 *
667 ******************************************************************************/
Cy_PDM_PCM_SetRateSampling(PDM_Type * base,cy_en_pdm_pcm_halve_rate_sel_t rate)668 __STATIC_INLINE void Cy_PDM_PCM_SetRateSampling(PDM_Type * base, cy_en_pdm_pcm_halve_rate_sel_t rate)
669 {
670     CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(rate));
671     PDM_PCM_CLOCK_CTL(base) &= ~PDM_CLOCK_CTL_HALVE_Msk;
672     PDM_PCM_CLOCK_CTL(base) |= _VAL2FLD(PDM_CLOCK_CTL_HALVE, rate);
673 }
674 
675 /******************************************************************************
676 * Function Name: Cy_PDM_PCM_Channel_SetCicDecimCode
677 ***************************************************************************//**
678 *
679 * Sets  PDM-PCM CIC Filter Decimation code.
680 *
681 * \param base The pointer to the PDM-PCM instance address
682 * \param channel_num Channel number for which the CIC filter Decimation code to be set
683 * \param decimcode decimation code value to be set. \ref cy_en_pdm_pcm_ch_cic_decimcode_t.
684 *
685 * \funcusage
686 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_Set_Cic_DecimCode
687 *
688 ******************************************************************************/
Cy_PDM_PCM_Channel_Set_Cic_DecimCode(PDM_Type * base,uint8_t channel_num,cy_en_pdm_pcm_ch_cic_decimcode_t decimcode)689 __STATIC_INLINE void  Cy_PDM_PCM_Channel_Set_Cic_DecimCode(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_cic_decimcode_t decimcode)
690 {
691     PDM_PCM_CH_CIC_CTL(base, channel_num) = (uint32_t)decimcode;
692 }
693 
694 
695 /******************************************************************************
696 * Function Name: Cy_PDM_PCM_Channel_Set_Fir0
697 ***************************************************************************//**
698 *
699 * Sets  PDM-PCM FIR0 Filter Decim code and Scale.
700 * The FIR filter coefficients have no default values:
701 * the coefficients MUST be programmed BEFORE the filter is enabled.
702 * By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies.
703 * For other frequencies it is a pass through.
704 *
705 * \param base The pointer to the PDM-PCM instance address
706 * \param channel_num Channel number for which the FIR0 Decimation code and the filter to be set.
707 * \param decimcode Decimation code value to be set. \ref cy_en_pdm_pcm_ch_fir0_decimcode_t.
708 * \param scale Scale value to be set.
709 *
710 * \funcusage
711 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_Set_Fir0
712 *
713 ******************************************************************************/
Cy_PDM_PCM_Channel_Set_Fir0(PDM_Type * base,uint8_t channel_num,cy_en_pdm_pcm_ch_fir0_decimcode_t decimcode,uint8_t scale)714 __STATIC_INLINE void  Cy_PDM_PCM_Channel_Set_Fir0(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_fir0_decimcode_t decimcode,uint8_t scale)
715 {
716     CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(scale));
717     PDM_PCM_CH_FIR0_CTL(base, channel_num) &= ~(PDM_CH_FIR0_CTL_DECIM3_Msk | PDM_CH_FIR0_CTL_SCALE_Msk);
718     PDM_PCM_CH_FIR0_CTL(base, channel_num) |= _VAL2FLD(PDM_CH_FIR0_CTL_DECIM3,  decimcode) |
719                                               _VAL2FLD(PDM_CH_FIR0_CTL_SCALE,        scale);
720 }
721 
722 /******************************************************************************
723 * Function Name: Cy_PDM_PCM_Channel_Set_Fir1
724 ***************************************************************************//**
725 *
726 * Sets  PDM-PCM FIR1 Filter Decimation code and Scale.
727 *
728 * \param base The pointer to the PDM-PCM instance address
729 * \param channel_num Channel number for which the FIR1 Decimation code and the filter to be set.
730 * \param decimcode Decimation code value to be set. \ref cy_en_pdm_pcm_ch_fir1_decimcode_t.
731 * \param scale Scale value to be set.
732 *
733 * \funcusage
734 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_Set_Fir1
735 *
736 ******************************************************************************/
Cy_PDM_PCM_Channel_Set_Fir1(PDM_Type * base,uint8_t channel_num,cy_en_pdm_pcm_ch_fir1_decimcode_t decimcode,uint8_t scale)737 __STATIC_INLINE void  Cy_PDM_PCM_Channel_Set_Fir1(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_fir1_decimcode_t decimcode,uint8_t scale)
738 {
739     CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(scale));
740     PDM_PCM_CH_FIR1_CTL(base, channel_num) &= ~(PDM_CH_FIR1_CTL_DECIM2_Msk | PDM_CH_FIR1_CTL_SCALE_Msk);
741     PDM_PCM_CH_FIR1_CTL(base, channel_num) |= _VAL2FLD(PDM_CH_FIR1_CTL_DECIM2,  decimcode) |
742                                              _VAL2FLD(PDM_CH_FIR1_CTL_SCALE,        scale);
743 }
744 
745 
746 
747 /******************************************************************************
748 * Function Name: Cy_PDM_PCM_Channel_Set_DCblock
749 ***************************************************************************//**
750 *
751 * Sets the DC blocker filter with programmable coefficient.
752 * The filter is used to remove a DC component.
753 *
754 * \param base The pointer to the PDM-PCM instance address
755 * \param channel_num Channel number for which DC block coef to be set.
756 * \param coef coef value to be set. \ref cy_en_pdm_pcm_ch_dcblock_coef_t.
757 *
758 * \funcusage
759 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_Set_DCblock
760 *
761 ******************************************************************************/
Cy_PDM_PCM_Channel_Set_DCblock(PDM_Type * base,uint8_t channel_num,cy_en_pdm_pcm_ch_dcblock_coef_t coef)762 __STATIC_INLINE void  Cy_PDM_PCM_Channel_Set_DCblock(PDM_Type * base, uint8_t channel_num, cy_en_pdm_pcm_ch_dcblock_coef_t coef)
763 {
764     PDM_PCM_CH_DC_BLOCK_CTL(base, channel_num) &= ~(PDM_CH_DC_BLOCK_CTL_CODE_Msk);
765     PDM_PCM_CH_DC_BLOCK_CTL(base, channel_num) |= _VAL2FLD(PDM_CH_DC_BLOCK_CTL_CODE,    coef);
766 }
767 
768 /******************************************************************************
769 * Function Name: Cy_PDM_PCM_Channel_SetInterruptMask
770 ***************************************************************************//**
771 *
772 * Sets one or more PDM-PCM interrupt factor bits (sets the INTR_MASK register).
773 *
774 * \param base The pointer to the PDM-PCM instance address
775 * \param channel_num Channel number
776 * \param interrupt Interrupt bit mask
777 * \ref group_pdm_pcm_macros_interrupt_masks_v2.
778 *
779 * \funcusage
780 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_SetInterruptMask
781 *
782 ******************************************************************************/
Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base,uint8_t channel_num,uint32_t interrupt)783 __STATIC_INLINE void Cy_PDM_PCM_Channel_SetInterruptMask(PDM_Type * base, uint8_t channel_num, uint32_t interrupt)
784 {
785     CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt));
786     PDM_PCM_INTR_RX_MASK(base, channel_num) = interrupt;
787 }
788 
789 
790 /******************************************************************************
791 * Function Name: Cy_PDM_PCM_Channel_GetInterruptMask
792 ***************************************************************************//**
793 *
794 * Returns the PDM-PCM interrupt mask (a content of the INTR_MASK register).
795 *
796 * \param base The pointer to the PDM-PCM instance address.
797 * \param channel_num Channel number
798 * \return The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2.
799 *
800 ******************************************************************************/
Cy_PDM_PCM_Channel_GetInterruptMask(PDM_Type const * base,uint8_t channel_num)801 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptMask(PDM_Type const * base, uint8_t channel_num)
802 {
803     return (PDM_PCM_INTR_RX_MASK(base, channel_num));
804 }
805 
806 
807 /******************************************************************************
808 * Function Name: Cy_PDM_PCM_Channel_GetInterruptStatusMasked
809 ***************************************************************************//**
810 *
811 * Reports the status of enabled (masked) PDM-PCM interrupt sources.
812 * (an INTR_MASKED register).
813 *
814 * \param base The pointer to the PDM-PCM instance address.
815 * \param channel_num Channel number
816 * \return The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2.
817 *
818 * \funcusage
819 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_ReadFifo
820 *
821 *****************************************************************************/
Cy_PDM_PCM_Channel_GetInterruptStatusMasked(PDM_Type const * base,uint8_t channel_num)822 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatusMasked(PDM_Type const * base, uint8_t channel_num)
823 {
824     return (PDM_PCM_INTR_RX_MASKED(base, channel_num));
825 }
826 
827 
828 /******************************************************************************
829 * Function Name: Cy_PDM_PCM_Channel_GetInterruptStatus
830 ***************************************************************************//**
831 *
832 * Reports the status of PDM-PCM interrupt sources (an INTR register).
833 *
834 * \param base The pointer to the PDM-PCM instance address.
835 * \param channel_num Channel number
836 * \return The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2.
837 *
838 * \funcusage
839 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_ReadFifo
840 *
841 ******************************************************************************/
Cy_PDM_PCM_Channel_GetInterruptStatus(PDM_Type const * base,uint8_t channel_num)842 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_GetInterruptStatus(PDM_Type const * base, uint8_t channel_num)
843 {
844     return (PDM_PCM_INTR_RX(base, channel_num));
845 }
846 
847 
848 /******************************************************************************
849 * Function Name: Cy_PDM_PCM_Channel_ClearInterrupt
850 ***************************************************************************//**
851 *
852 * Clears one or more PDM-PCM interrupt statuses (sets an INTR register's bits).
853 *
854 * \param base The pointer to the PDM-PCM instance address
855 * \param channel_num Channel number
856 * \param interrupt
857 *  The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2.
858 *
859 * \funcusage
860 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_ClearInterrupt
861 *
862 ******************************************************************************/
Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base,uint8_t channel_num,uint32_t interrupt)863 __STATIC_INLINE void Cy_PDM_PCM_Channel_ClearInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt)
864 {
865     CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt));
866     PDM_PCM_INTR_RX(base, channel_num) = interrupt;
867     /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
868     (void) PDM_PCM_INTR_RX(base, channel_num);
869 }
870 
871 
872 /******************************************************************************
873 * Function Name: Cy_PDM_PCM_Channel_SetInterrupt
874 ***************************************************************************//**
875 *
876 * Sets one or more interrupt source statuses (sets an INTR_SET register).
877 *
878 * \param base The pointer to the PDM-PCM instance address.
879 * \param channel_num Channel number
880 * \param interrupt
881 *  The interrupt bit mask \ref group_pdm_pcm_macros_interrupt_masks_v2.
882 *
883 ******************************************************************************/
Cy_PDM_PCM_Channel_SetInterrupt(PDM_Type * base,uint8_t channel_num,uint32_t interrupt)884 __STATIC_INLINE void Cy_PDM_PCM_Channel_SetInterrupt(PDM_Type * base, uint8_t channel_num, uint32_t interrupt)
885 {
886     CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt));
887     PDM_PCM_INTR_RX_SET(base, channel_num) = interrupt;
888 }
889 
890 
891 /******************************************************************************
892 * Function Name: Cy_PDM_PCM_Channel_GetNumInFifo
893 ***************************************************************************//**
894 *
895 * Reports the current number of used words in the output data FIFO.
896 *
897 * \param base The pointer to the PDM-PCM instance address.
898 * \param channel_num Channel number
899 * \return The current number of used FIFO words (range is 0 - 63).
900 *
901 * \funcusage
902 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_GetNumInFifo
903 *
904 ******************************************************************************/
Cy_PDM_PCM_Channel_GetNumInFifo(PDM_Type const * base,uint8_t channel_num)905 __STATIC_INLINE uint8_t Cy_PDM_PCM_Channel_GetNumInFifo(PDM_Type const * base, uint8_t channel_num)
906 {
907     return (uint8_t) (_FLD2VAL(PDM_CH_RX_FIFO_STATUS_USED, PDM_PCM_RX_FIFO_STATUS(base, channel_num)));
908 }
909 
910 
911 /******************************************************************************
912 * Function Name: Cy_PDM_PCM_Channel_ReadFifo
913 ***************************************************************************//**
914 *
915 * Reads ("pops") one word from the output data FIFO.
916 *
917 * \param base The pointer to the PDM-PCM instance address.
918 * \param channel_num Channel number
919 * \return The data word read from the FIFO is returned.
920 *
921 * \funcusage
922 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_ReadFifo
923 *
924 ******************************************************************************/
Cy_PDM_PCM_Channel_ReadFifo(PDM_Type const * base,uint8_t channel_num)925 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifo(PDM_Type const * base, uint8_t channel_num)
926 {
927     return (PDM_PCM_RX_FIFO_RD(base, channel_num));
928 }
929 
930 /******************************************************************************
931 * Function Name: Cy_PDM_PCM_Channel_FreezeFifo
932 ***************************************************************************//**
933 *
934 * Freezes the RX FIFO (Debug purpose).
935 *
936 * \param base The pointer to the PDM-PCM instance address.
937 * \param channel_num Channel number
938 *
939 * \funcusage
940 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_FreezeFifo
941 *
942 ******************************************************************************/
Cy_PDM_PCM_Channel_FreezeFifo(PDM_Type * base,uint8_t channel_num)943 __STATIC_INLINE void Cy_PDM_PCM_Channel_FreezeFifo(PDM_Type * base, uint8_t channel_num)
944 {
945     PDM_PCM_RX_FIFO_CTL(base, channel_num) |= PDM_CH_RX_FIFO_CTL_FREEZE_Msk;
946 }
947 
948 
949 /******************************************************************************
950 * Function Name: Cy_PDM_PCM_Channel_UnfreezeFifo
951 ***************************************************************************//**
952 *
953 * Unfreezes the RX FIFO (Debug purpose).
954 *
955 * \param base The pointer to the PDM-PCM instance address.
956 * \param channel_num Channel number
957 *
958 * \funcusage
959 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_UnfreezeFifo
960 *
961 ******************************************************************************/
Cy_PDM_PCM_Channel_UnfreezeFifo(PDM_Type * base,uint8_t channel_num)962 __STATIC_INLINE void Cy_PDM_PCM_Channel_UnfreezeFifo(PDM_Type * base, uint8_t channel_num)
963 {
964     PDM_PCM_RX_FIFO_CTL(base, channel_num) &= (uint32_t) ~PDM_CH_RX_FIFO_CTL_FREEZE_Msk;
965 }
966 
967 
968 /******************************************************************************
969 * Function Name: Cy_PDM_PCM_Channel_ReadFifoSilent
970 ***************************************************************************//**
971 *
972 * Reads the RX FIFO silent (without touching the FIFO function).
973 *
974 * \param base Pointer to PDM-PCM instance address.
975 * \param channel_num Channel number
976 * \return Silent FIFO value is read and returned.
977 *
978 * \funcusage
979 * \snippet pdm_pcmv2/snippet/main.c snippet_Cy_PDM_PCM_Channel_ReadFifoSilent
980 *
981 ******************************************************************************/
Cy_PDM_PCM_Channel_ReadFifoSilent(PDM_Type const * base,uint8_t channel_num)982 __STATIC_INLINE uint32_t Cy_PDM_PCM_Channel_ReadFifoSilent(PDM_Type const * base, uint8_t channel_num)
983 {
984     return (PDM_PCM_RX_FIFO_RD_SILENT(base, channel_num));
985 }
986 
987 /** \} group_pdm_pcm_functions_v2 */
988 
989 #ifdef __cplusplus
990 }
991 #endif  /* of __cplusplus */
992 
993 #endif /* CY_IP_MXPDM */
994 
995 #endif /* CY_PDM_PCM_V2_H__ */
996 
997 /** \} group_pdm_pcm_v2 */
998 
999 
1000 /* [] END OF FILE */
1001