1 /***************************************************************************//**
2 * \file cy_device.h
3 * \version 2.0
4 *
5 * This file specifies the structure for core and peripheral block HW base
6 * addresses, versions, and parameters.
7 *
8 ********************************************************************************/
9 #ifndef CY_DEVICE_H_
10 #define CY_DEVICE_H_
11 
12 #include <stdint.h>
13 #include <stddef.h>
14 #include "cy_utils.h"
15 #include "cy_device_headers.h"
16 #include "startup_cat1c.h"
17 #include "ip/cyip_cpuss.h"
18 
19 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 1, \
20 'Checked manually. The definition is a part of linker script.')
21 
22 /* Device descriptor type */
23 typedef struct
24 {
25     /* Base HW addresses */
26     uint32_t hsiomBase;
27     uint32_t gpioBase;
28 
29     /* IP block versions: [7:4] major, [3:0] minor */
30     uint8_t  dwVersion;
31 
32     /* Parameters */
33     uint8_t  cpussDw0ChNr;
34     uint8_t  cpussDw1ChNr;
35     uint8_t  epMonitorNr;
36 
37     /* Peripheral register offsets */
38 
39    /* DW registers */
40     uint16_t dwChOffset;
41     uint16_t dwChSize;
42     uint8_t  dwChCtlPrioPos;
43     uint8_t  dwChCtlPreemptablePos;
44     uint8_t  dwStatusChIdxPos;
45     uint32_t dwStatusChIdxMsk;
46 
47     uint8_t  tcpwmCC1Present;
48     uint8_t  tcpwmAMCPresent;
49     uint8_t  tcpwmSMCPrecent;
50 
51 } cy_stc_device_t;
52 
53 void Cy_PDL_Init(const cy_stc_device_t * device);
54 
55 /* Pointer to device configuration structure */
56 #define CY_DEVICE_CFG                   (&cy_deviceIpBlockCfg)
57 
58 /*******************************************************************************
59 *                   Global Variables
60 *******************************************************************************/
61 
62 extern const cy_stc_device_t   cy_deviceIpBlockCfg;
63 extern const cy_stc_device_t* cy_device;
64 
65 /*******************************************************************************
66 *                   Global Extern Functions
67 *******************************************************************************/
68 
69 #if defined(__ARMCC_VERSION)
70 #define interrupt_type __attribute__((interrupt))
71 #elif defined (__GNUC__)
72 #define interrupt_type __attribute__((interrupt))
73 #elif defined (__ICCARM__)
74 #define interrupt_type __irq
75 #else
76     #error "An unsupported toolchain"
77 #endif  /* (__ARMCC_VERSION) */
78 
79 /*******************************************************************************
80 *               Macro Definitions
81 *******************************************************************************/
82 /*******************************************************************************
83 *               Register Access Helper Macros
84 *******************************************************************************/
85 #define CY_DEVICE_CAT1C            /* Device Category */
86 #define CY_CRYPTO_V1                        (0U) /* CAT1C devices have only mxcrypto_v2 IP */
87 
88 /* Remapping the CBUS to SAHB address & Vice versa*/
89 #define CY_REMAP_ADDRESS_CBUS_TO_SAHB(addr)               (addr)
90 #define CY_REMAP_ADDRESS_SAHB_TO_CBUS(addr)               (addr)
91 
92 /*******************************************************************************
93 *                System Level
94 *******************************************************************************/
95 #define ENABLE_CM7_INSTRUCTION_CACHE
96 #if !defined CY_DISABLE_XMC7000_DATA_CACHE
97 #define ENABLE_CM7_DATA_CACHE
98 #endif
99 
100 /*******************************************************************************
101 *               Generic Macro Definitions
102 *******************************************************************************/
103 #define GET_ALIAS_ADDRESS(addr)             (uint32_t)(addr)
104 
105 /*******************************************************************************
106 *                CRYPTO
107 *******************************************************************************/
108 
109 /* The CRYPTO internal-memory buffer-size in 32-bit words. */
110 #define CY_CRYPTO_MEM_BUFF_SIZE_U32         (2048U)
111 
112 /*******************************************************************************
113 *                SYSLIB
114 *******************************************************************************/
115 #if defined(CORE_NAME_CM7_0) || defined(CORE_NAME_CM7_1)
116 #define CY_SYSLIB_DELAY_CALIBRATION_FACTOR    2U
117 #else
118 #define CY_SYSLIB_DELAY_CALIBRATION_FACTOR    1U
119 #endif
120 
121 /*******************************************************************************
122 *                SRSS
123 *******************************************************************************/
124 
125 #define CY_SRSS_NUM_CLKPATH                 SRSS_NUM_CLKPATH
126 #define CY_SRSS_NUM_PLL                     SRSS_NUM_TOTAL_PLL
127 #define CY_SRSS_NUM_PLL200M                 SRSS_NUM_PLL
128 #define CY_SRSS_NUM_PLL400M                 SRSS_NUM_PLL400M
129 #define CY_SRSS_NUM_HFROOT                  SRSS_NUM_HFROOT
130 #define CY_SRSS_ECO_PRESENT                 SRSS_ECO_PRESENT
131 #define CY_SRSS_FLL_PRESENT                 1
132 #define CY_SRSS_PLL_PRESENT                 SRSS_NUM_PLL
133 #define CY_SRSS_PLL400M_PRESENT             1
134 #define CY_SRSS_ALTHF_PRESENT               SRSS_ALTHF_PRESENT
135 #define CY_SRSS_DPLL_LP_PRESENT             0
136 #define CY_SRSS_IMO_PRESENT                 1
137 
138 #define CY_SRSS_ILO_COUNT                   2
139 
140 /** HF PATH # used for PERI PCLK */
141 #define CY_SYSCLK_CLK_PERI_HF_PATH_NUM     2U
142 
143 /** HF PATH # used for MEM CLK */
144 #define CY_SYSCLK_CLK_MEM_HF_PATH_NUM     0U
145 
146 
147 /** HF PATH # used for Core */
148 #ifdef CORE_NAME_CM0P_0
149 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM     0U
150 #else
151 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM     1U
152 #endif
153 
154 /** HF PATH # used for CLOCK FAST */
155 #define CY_SYSCLK_CLK_FAST_HF_NUM          1U
156 
157 /* HF PATH # Max Allowed Frequencies */
158 #define CY_SYSCLK_HF_MAX_FREQ(hfNum)       (350000000U)
159 
160 /** FLL Max Frequency */
161 #define  CY_SYSCLK_FLL_MAX_OUTPUT_FREQ     (100000000UL)
162 
163 /* Technology Independant Register set */
164 #define SRSS_CLK_DSI_SELECT                 (((SRSS_Type *) SRSS)->CLK_DSI_SELECT)
165 #define SRSS_CLK_OUTPUT_FAST                (((SRSS_Type *) SRSS)->CLK_OUTPUT_FAST)
166 #define SRSS_CLK_OUTPUT_SLOW                (((SRSS_Type *) SRSS)->CLK_OUTPUT_SLOW)
167 #define SRSS_CLK_CAL_CNT1                   (((SRSS_Type *) SRSS)->CLK_CAL_CNT1)
168 #define SRSS_CLK_CAL_CNT2                   (((SRSS_Type *) SRSS)->CLK_CAL_CNT2)
169 #define SRSS_SRSS_INTR                      (((SRSS_Type *) SRSS)->SRSS_INTR)
170 #define SRSS_SRSS_INTR_SET                  (((SRSS_Type *) SRSS)->SRSS_INTR_SET)
171 #define SRSS_SRSS_INTR_MASK                 (((SRSS_Type *) SRSS)->SRSS_INTR_MASK)
172 #define SRSS_SRSS_INTR_MASKED               (((SRSS_Type *) SRSS)->SRSS_INTR_MASKED)
173 #define SRSS_PWR_CTL                        (((SRSS_Type *) SRSS)->PWR_CTL)
174 #define SRSS_PWR_CTL2                       (((SRSS_Type *) SRSS)->PWR_CTL2)
175 #define SRSS_PWR_HIBERNATE                  (((SRSS_Type *) SRSS)->PWR_HIBERNATE)
176 #define SRSS_PWR_BUCK_CTL                   (((SRSS_Type *) SRSS)->PWR_BUCK_CTL)
177 #define SRSS_PWR_BUCK_CTL2                  (((SRSS_Type *) SRSS)->PWR_BUCK_CTL2)
178 #define SRSS_PWR_SSV_CTL                    (((SRSS_Type *) SRSS)->PWR_SSV_CTL)
179 #define SRSS_PWR_SSV_STATUS                 (((SRSS_Type *) SRSS)->PWR_SSV_STATUS)
180 #define SRSS_PWR_LVD_CTL                    (((SRSS_Type *) SRSS)->PWR_LVD_CTL)
181 #define SRSS_PWR_LVD_CTL2                   (((SRSS_Type *) SRSS)->PWR_LVD_CTL2)
182 #define SRSS_PWR_REGHC_CTL                  (((SRSS_Type *) SRSS)->PWR_REGHC_CTL)
183 #define SRSS_PWR_REGHC_STATUS               (((SRSS_Type *) SRSS)->PWR_REGHC_STATUS)
184 #define SRSS_PWR_REGHC_CTL2                 (((SRSS_Type *) SRSS)->PWR_REGHC_CTL2)
185 #define SRSS_PWR_REGHC_CTL4                 (((SRSS_Type *) SRSS)->PWR_REGHC_CTL4)
186 #define SRSS_PWR_HIB_DATA                   (((SRSS_Type *) SRSS)->PWR_HIB_DATA)
187 #define SRSS_PWR_PMIC_CTL                   (((SRSS_Type *) SRSS)->PWR_PMIC_CTL)
188 #define SRSS_PWR_PMIC_STATUS                (((SRSS_Type *) SRSS)->PWR_PMIC_STATUS)
189 #define SRSS_PWR_PMIC_CTL2                  (((SRSS_Type *) SRSS)->PWR_PMIC_CTL2)
190 #define SRSS_PWR_PMIC_CTL4                  (((SRSS_Type *) SRSS)->PWR_PMIC_CTL4)
191 #define SRSS_CLK_PATH_SELECT                (((SRSS_Type *) SRSS)->CLK_PATH_SELECT)
192 #define SRSS_CLK_ROOT_SELECT                (((SRSS_Type *) SRSS)->CLK_ROOT_SELECT)
193 #define SRSS_CLK_DIRECT_SELECT              (((SRSS_Type *) SRSS)->CLK_DIRECT_SELECT)
194 #define SRSS_CLK_ECO_STATUS                 (((SRSS_Type *) SRSS)->CLK_ECO_STATUS)
195 #define SRSS_CLK_ILO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG) /* BWC */
196 #define SRSS_CLK_ILO0_CONFIG                (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG)
197 #define SRSS_CLK_ILO1_CONFIG                (((SRSS_Type *) SRSS)->CLK_ILO1_CONFIG)
198 
199 #define SRSS_CLK_ILO_CONFIG_ENABLE_Msk      SRSS_CLK_ILO0_CONFIG_ENABLE_Msk /* BWC */
200 
201 #define SRSS_CLK_TRIM_ILO_CTL               (((SRSS_Type *) SRSS)->CLK_TRIM_ILO_CTL)
202 #define SRSS_CLK_PILO_CONFIG                (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG)
203 #define SRSS_CLK_ECO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG)
204 #define SRSS_CLK_ECO_CONFIG2                 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG2)
205 #define SRSS_CLK_MFO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_MFO_CONFIG)
206 #define SRSS_CLK_IHO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_IHO_CONFIG)
207 #define SRSS_CLK_ALTHF_CTL                  (((SRSS_Type *) SRSS)->CLK_ALTHF_CTL)
208 
209 #define SRSS_CLK_ILO0_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG)
210 #define SRSS_CLK_ILO1_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO1_CONFIG)
211 
212 #define SRSS_CSV_HF                         (((SRSS_Type *) SRSS)->CSV_HF)
213 #define SRSS_CLK_SELECT                     (((SRSS_Type *) SRSS)->CLK_SELECT)
214 #define SRSS_CLK_TIMER_CTL                  (((SRSS_Type *) SRSS)->CLK_TIMER_CTL)
215 #define SRSS_CLK_IMO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_IMO_CONFIG)
216 #define SRSS_CLK_ECO_PRESCALE               (((SRSS_Type *) SRSS)->CLK_ECO_PRESCALE)
217 #define SRSS_CLK_MF_SELECT                  (((SRSS_Type *) SRSS)->CLK_MF_SELECT)
218 #define SRSS_CSV_REF_SEL                    (((SRSS_Type *) SRSS)->CSV_REF_SEL)
219 #define SRSS_CSV_REF                        (((SRSS_Type *) SRSS)->CSV_REF)
220 #define SRSS_CSV_LF                         (((SRSS_Type *) SRSS)->CSV_LF)
221 #define SRSS_CSV_ILO                        (((SRSS_Type *) SRSS)->CSV_ILO)
222 #define SRSS_RES_CAUSE                      (((SRSS_Type *) SRSS)->RES_CAUSE)
223 #define SRSS_RES_CAUSE2                     (((SRSS_Type *) SRSS)->RES_CAUSE2)
224 #define SRSS_RES_CAUSE_EXTEND               (((SRSS_Type *) SRSS)->RES_CAUSE_EXTEND)
225 #define SRSS_CLK_LP_PLL                     (((SRSS_Type *) SRSS)->CLK_LP_PLL)
226 #define SRSS_CLK_IHO                        (((SRSS_Type *) SRSS)->CLK_IHO)
227 #define SRSS_TST_XRES_SECURE                (((SRSS_Type *) SRSS)->TST_XRES_SECURE)
228 #define SRSS_RES_PXRES_CTL                  (((SRSS_Type *) SRSS)->RES_PXRES_CTL)
229 
230 #define SRSS_CLK_FLL_CONFIG                 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG)
231 #define SRSS_CLK_FLL_CONFIG2                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG2)
232 #define SRSS_CLK_FLL_CONFIG3                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3)
233 #define SRSS_CLK_FLL_CONFIG4                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4)
234 #define SRSS_CLK_FLL_STATUS                 (((SRSS_Type *) SRSS)->CLK_FLL_STATUS)
235 
236 #define SRSS_PWR_LVD_STATUS                 (((SRSS_Type *) SRSS)->PWR_LVD_STATUS)
237 #define SRSS_PWR_LVD_STATUS2                 (((SRSS_Type *) SRSS)->PWR_LVD_STATUS2)
238 
239 #define SRSS_SRSS_INTR_CFG                  (((SRSS_Type *) SRSS)->SRSS_AINTR_CFG)
240 
241 #define SRSS_PWR_HIB_WAKE_CTL               (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL)
242 #define SRSS_PWR_HIB_WAKE_CTL2              (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL2)
243 #define SRSS_PWR_HIB_WAKE_CAUSE             (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CAUSE)
244 #define SRSS_RES_SOFT_CTL                   (((SRSS_Type *) SRSS)->RES_SOFT_CTL)
245 
246 #define SRSS_CLK_PLL_CONFIG                 (((SRSS_Type *) SRSS)->CLK_PLL_CONFIG)
247 #define SRSS_CLK_PLL_STATUS                 (((SRSS_Type *) SRSS)->CLK_PLL_STATUS)
248 
249 #define SRSS_FLL_PATH_NUM         (0UL)
250 
251 #if defined (CY_DEVICE_TVIIC2D6M)
252 #define SRSS_PLL_400M_0_PATH_NUM  (1UL)
253 #define SRSS_PLL_400M_1_PATH_NUM  (2UL)
254 #define SRSS_PLL_400M_2_PATH_NUM  (3UL)
255 #define SRSS_PLL_400M_3_PATH_NUM  (4UL)
256 #define SRSS_PLL_400M_4_PATH_NUM  (5UL)
257 #define SRSS_PLL_200M_0_PATH_NUM  (6UL)
258 #define SRSS_PLL_200M_1_PATH_NUM  (7UL)
259 #define SRSS_PLL_200M_2_PATH_NUM  (8UL)
260 #else
261 #define SRSS_PLL_400M_0_PATH_NUM  (1UL)
262 #define SRSS_PLL_400M_1_PATH_NUM  (2UL)
263 #define SRSS_PLL_200M_0_PATH_NUM  (3UL)
264 #define SRSS_PLL_200M_1_PATH_NUM  (4UL)
265 #endif
266 
267 #define SRSS_PLL400M_FRAC_BIT_COUNT (24ULL)
268 
269 #if (CY_IP_MXS40SRSS_VERSION >= 3)
270 #define SRSS_CLK_PLL_400M_CONFIG(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG)
271 #define SRSS_CLK_PLL_400M_CONFIG2(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG2)
272 #define SRSS_CLK_PLL_400M_CONFIG3(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG3)
273 #define SRSS_CLK_PLL_400M_STATUS(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].STATUS)
274 #endif
275 
276 
277 #define SRSS_WDT_CTL                        (((WDT_Type*) &SRSS->WDT_STRUCT)->CTL)
278 #define SRSS_WDT_LOWER_LIMIT                (((WDT_Type*) &SRSS->WDT_STRUCT)->LOWER_LIMIT)
279 #define SRSS_WDT_UPPER_LIMIT                (((WDT_Type*) &SRSS->WDT_STRUCT)->UPPER_LIMIT)
280 #define SRSS_WDT_WARN_LIMIT                 (((WDT_Type*) &SRSS->WDT_STRUCT)->WARN_LIMIT)
281 #define SRSS_WDT_CONFIG                     (((WDT_Type*) &SRSS->WDT_STRUCT)->CONFIG)
282 #define SRSS_WDT_CNT                        (((WDT_Type*) &SRSS->WDT_STRUCT)->CNT)
283 #define SRSS_WDT_LOCK                       (((WDT_Type*) &SRSS->WDT_STRUCT)->LOCK)
284 #define SRSS_WDT_SERVICE                    (((WDT_Type*) &SRSS->WDT_STRUCT)->SERVICE)
285 #define SRSS_WDT_INTR                       (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR)
286 #define SRSS_WDT_INTR_SET                   (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_SET)
287 #define SRSS_WDT_INTR_MASK                  (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_MASK)
288 #define SRSS_WDT_INTR_MASKED                (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_MASKED)
289 
290 
291 
292 #define SRSS_TST_DDFT_FAST_CTL_REG          (*(volatile uint32_t *) 0x40261104U)
293 #define SRSS_TST_DDFT_SLOW_CTL_REG          (*(volatile uint32_t *) 0x40261108U)
294 
295 #define SRSS_TST_DDFT_SLOW_CTL_MASK         (0x00001F1EU)
296 #define SRSS_TST_DDFT_FAST_CTL_MASK         (62U)
297 
298 
299 /*******************************************************************************
300 *                BACKUP
301 *******************************************************************************/
302 
303 #define BACKUP_PMIC_CTL                     (((BACKUP_Type *) BACKUP)->PMIC_CTL)
304 #define BACKUP_CTL                          (((BACKUP_Type *) BACKUP)->CTL)
305 #define BACKUP_RTC_TIME                     (((BACKUP_Type *) BACKUP)->RTC_TIME)
306 #define BACKUP_RTC_DATE                     (((BACKUP_Type *) BACKUP)->RTC_DATE)
307 #define BACKUP_RTC_RW                       (((BACKUP_Type *) BACKUP)->RTC_RW)
308 #define BACKUP_CAL_CTL                      (((BACKUP_Type *) BACKUP)->CAL_CTL)
309 #define BACKUP_ALM1_TIME                    (((BACKUP_Type *) BACKUP)->ALM1_TIME)
310 #define BACKUP_ALM1_DATE                    (((BACKUP_Type *) BACKUP)->ALM1_DATE)
311 #define BACKUP_ALM2_TIME                    (((BACKUP_Type *) BACKUP)->ALM2_TIME)
312 #define BACKUP_ALM2_DATE                    (((BACKUP_Type *) BACKUP)->ALM2_DATE)
313 #define BACKUP_STATUS                       (((BACKUP_Type *) BACKUP)->STATUS)
314 #define BACKUP_INTR                         (((BACKUP_Type *) BACKUP)->INTR)
315 #define BACKUP_INTR_SET                     (((BACKUP_Type *) BACKUP)->INTR_SET)
316 #define BACKUP_INTR_MASK                    (((BACKUP_Type *) BACKUP)->INTR_MASK)
317 #define BACKUP_INTR_MASKED                  (((BACKUP_Type *) BACKUP)->INTR_MASKED)
318 #define BACKUP_RESET                        (((BACKUP_Type *) BACKUP)->RESET)
319 #define BACKUP_LPECO_CTL                    (((BACKUP_Type *) BACKUP)->LPECO_CTL)
320 #define BACKUP_LPECO_PRESCALE               (((BACKUP_Type *) BACKUP)->LPECO_PRESCALE)
321 #define BACKUP_LPECO_STATUS                 (((BACKUP_Type *) BACKUP)->LPECO_STATUS)
322 #define BACKUP_BREG                         (((BACKUP_Type *) BACKUP)->BREG)
323 
324 
325 #define CY_SRSS_BACKUP_NUM_BREG             SRSS_BACKUP_NUM_BREG
326 
327 
328 /*******************************************************************************
329 *                CANFD
330 *******************************************************************************/
331 
332 #define CANFD_CTL(base)                           (((CANFD_Type *)(base))->CTL)
333 #define CANFD_STATUS(base)                        (((CANFD_Type *)(base))->STATUS)
334 #define CANFD_NBTP(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NBTP)
335 #define CANFD_IR(base, chan)                      (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IR)
336 #define CANFD_IE(base, chan)                      (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IE)
337 #define CANFD_ILS(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILS)
338 #define CANFD_ILE(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILE)
339 #define CANFD_CCCR(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CCCR)
340 #define CANFD_SIDFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.SIDFC)
341 #define CANFD_XIDFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDFC)
342 #define CANFD_XIDAM(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDAM)
343 #define CANFD_RXESC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXESC)
344 #define CANFD_RXF0C(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0C)
345 #define CANFD_RXF1C(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1C)
346 #define CANFD_RXFTOP_CTL(base, chan)              (((CANFD_Type *)(base))->CH[chan].RXFTOP_CTL)
347 #define CANFD_RXBC(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXBC)
348 #define CANFD_TXESC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXESC)
349 #define CANFD_TXEFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXEFC)
350 #define CANFD_TXBC(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBC)
351 #define CANFD_DBTP(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.DBTP)
352 #define CANFD_TDCR(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TDCR)
353 #define CANFD_GFC(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.GFC)
354 #define CANFD_TXBRP(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBRP)
355 #define CANFD_TXBAR(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBAR)
356 #define CANFD_TXBCR(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCR)
357 #define CANFD_TXBTO(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTO)
358 #define CANFD_TXBCF(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCF)
359 #define CANFD_TXBTIE(base, chan)                  (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTIE)
360 #define CANFD_TXBCIE(base, chan)                  (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCIE)
361 #define CANFD_NDAT1(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT1)
362 #define CANFD_NDAT2(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT2)
363 #define CANFD_RXF0S(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0S)
364 #define CANFD_RXFTOP0_DATA(base, chan)            (((CANFD_Type *)(base))->CH[chan].RXFTOP0_DATA)
365 #define CANFD_RXFTOP1_DATA(base, chan)            (((CANFD_Type *)(base))->CH[chan].RXFTOP1_DATA)
366 #define CANFD_RXF0A(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0A)
367 #define CANFD_RXF1S(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1S)
368 #define CANFD_RXF1A(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1A)
369 #define CANFD_PSR(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.PSR)
370 #define CANFD_TEST(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TEST)
371 #define CANFD_CREL(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CREL)
372 
373 #define CY_CANFD_CHANNELS_NUM                     (0x1UL)
374 
375 
376 /*******************************************************************************
377 *                FLASHC
378 *******************************************************************************/
379 #if ((CPUSS_FLASHC_PRESENT == 1) && (CPUSS_FLASHC_ECT == 1))
380 #define CY_IP_MXFLASHC_VERSION_ECT
381 #endif
382 
383 #define FLASHC_FLASH_CTL             (((FLASHC_Type *)(FLASHC))->FLASH_CTL)
384 #define FLASHC_FLASH_PWR_CTL         (((FLASHC_Type *)(FLASHC))->FLASH_PWR_CTL)
385 #define FLASHC_FLASH_CMD             (((FLASHC_Type *)(FLASHC))->FLASH_CMD)
386 #define FLASHC_ECC_CTL               (((FLASHC_Type *)(FLASHC))->ECC_CTL)
387 #define FLASHC_FM_SRAM_ECC_CTL0      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL0)
388 #define FLASHC_FM_SRAM_ECC_CTL1      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL1)
389 #define FLASHC_FM_SRAM_ECC_CTL2      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL2)
390 #define FLASHC_FM_SRAM_ECC_CTL3      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL3)
391 #define FLASHC_CM0_CA_CTL0           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL0)
392 #define FLASHC_CM0_CA_CTL1           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL1)
393 #define FLASHC_CM0_CA_CTL2           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL2)
394 #define FLASHC_CM0_CA_STATUS0        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS0)
395 #define FLASHC_CM0_CA_STATUS1        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS1)
396 #define FLASHC_CM0_CA_STATUS2        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS2)
397 #define FLASHC_CM0_STATUS            (((FLASHC_Type *)(FLASHC))->CM0_STATUS)
398 #define FLASHC_CM7_0_STATUS          (((FLASHC_Type *)(FLASHC))->CM7_0_STATUS)
399 #define FLASHC_CM7_1_STATUS          (((FLASHC_Type *)(FLASHC))->CM7_1_STATUS)
400 #define FLASHC_CRYPTO_BUFF_CTL       (((FLASHC_Type *)(FLASHC))->CRYPTO_BUFF_CTL)
401 #define FLASHC_DW0_BUFF_CTL          (((FLASHC_Type *)(FLASHC))->DW0_BUFF_CTL)
402 #define FLASHC_DW1_BUFF_CTL          (((FLASHC_Type *)(FLASHC))->DW1_BUFF_CTL)
403 #define FLASHC_DMAC_BUFF_CTL         (((FLASHC_Type *)(FLASHC))->DMAC_BUFF_CTL)
404 #define FLASHC_SLOW0_MS_BUFF_CTL     (((FLASHC_Type *)(FLASHC))->SLOW0_MS_BUFF_CTL)
405 #define FLASHC_SLOW1_MS_BUFF_CTL     (((FLASHC_Type *)(FLASHC))->SLOW1_MS_BUFF_CTL)
406 
407 /* FLASH Memory  */
408 #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->WORK_FLASH_SAFETY)
409 #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->MAIN_FLASH_SAFETY)
410 #define FLASHC_FM_CTL_ECT_FLASH_STATUS (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->STATUS)
411 
412 /*******************************************************************************
413 *                SFLASH
414 *******************************************************************************/
415 
416 #define SFLASH_DIE_YEAR                     (((SFLASH_V1_Type *) SFLASH)->DIE_YEAR)
417 #define SFLASH_DIE_MINOR                    (((SFLASH_V1_Type *) SFLASH)->DIE_MINOR)
418 #define SFLASH_DIE_SORT                     (((SFLASH_V1_Type *) SFLASH)->DIE_SORT)
419 #define SFLASH_DIE_Y                        (((SFLASH_V1_Type *) SFLASH)->DIE_Y)
420 #define SFLASH_DIE_X                        (((SFLASH_V1_Type *) SFLASH)->DIE_X)
421 #define SFLASH_DIE_WAFER                    (((SFLASH_V1_Type *) SFLASH)->DIE_WAFER)
422 #define SFLASH_DIE_LOT(val)                 (((SFLASH_V1_Type *) SFLASH)->DIE_LOT[(val)])
423 #define SFLASH_FAMILY_ID                    (((SFLASH_V1_Type *) SFLASH)->FAMILY_ID)
424 #define SFLASH_SI_REVISION_ID               (((SFLASH_V1_Type *) SFLASH)->SI_REVISION_ID)
425 #define SFLASH_PWR_TRIM_WAKE_CTL            (((SFLASH_V1_Type *) SFLASH)->PWR_TRIM_WAKE_CTL)
426 #define SFLASH_LDO_0P9V_TRIM                (((SFLASH_V1_Type *) SFLASH)->LDO_0P9V_TRIM)
427 #define SFLASH_LDO_1P1V_TRIM                (((SFLASH_V1_Type *) SFLASH)->LDO_1P1V_TRIM)
428 #define SFLASH_BLE_DEVICE_ADDRESS           (((SFLASH_V1_Type *) SFLASH)->BLE_DEVICE_ADDRESS)
429 #define SFLASH_SILICON_ID                   (((SFLASH_V1_Type *) SFLASH)->SILICON_ID)
430 #define SFLASH_SINGLE_CORE                  (*(volatile uint8_t *) (SFLASH_BASE + 0xBU))
431 
432 
433 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP        (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_LP)
434 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP        (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_LP)
435 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP       (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP)
436 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP       (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP)
437 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP   (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP)
438 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP   (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP)
439 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP  (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP)
440 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP  (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP)
441 
442 
443 #define SFLASH_CSD0_ADC_VREF0_TRIM          (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF0)
444 #define SFLASH_CSD0_ADC_VREF1_TRIM          (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF1)
445 #define SFLASH_CSD0_ADC_VREF2_TRIM          (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF2)
446 
447 
448 /*******************************************************************************
449 *                CPUSS
450 *******************************************************************************/
451 
452 /* ARM core registers */
453 #define SYSTICK_CTRL                        (((SysTick_Type *)SysTick)->CTRL)
454 #define SYSTICK_LOAD                        (((SysTick_Type *)SysTick)->LOAD)
455 #define SYSTICK_VAL                         (((SysTick_Type *)SysTick)->VAL)
456 #define SCB_SCR                             (((SCB_Type *)SCB)->SCR)
457 
458 #define CPUSS_SYSTICK_CTL                (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_CTL)
459 
460 #define UDB_UDBIF_BANK_CTL                  (((UDB_V1_Type *) cy_device->udbBase)->UDBIF.BANK_CTL)
461 #define UDB_BCTL_MDCLK_EN                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN)
462 #define UDB_BCTL_MBCLK_EN                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MBCLK_EN)
463 #define UDB_BCTL_BOTSEL_L                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_L)
464 #define UDB_BCTL_BOTSEL_U                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_U)
465 #define UDB_BCTL_QCLK_EN_0                  (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U])
466 #define UDB_BCTL_QCLK_EN_1                  (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U])
467 #define UDB_BCTL_QCLK_EN_2                  (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U])
468 
469 #define CPUSS_FAST_0_CLOCK_CTL              (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL)
470 #define CPUSS_FAST_1_CLOCK_CTL              (((CPUSS_Type*) CPUSS_BASE)->FAST_1_CLOCK_CTL)
471 #define CPUSS_SLOW_CLOCK_CTL                (((CPUSS_Type*) CPUSS_BASE)->SLOW_CLOCK_CTL)
472 #define CPUSS_MEM_CLOCK_CTL                (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL)
473 #define CPUSS_PERI_CLOCK_CTL                (((CPUSS_Type*) CPUSS_BASE)->PERI_CLOCK_CTL)
474 
475 #define CPUSS_CM0_NMI_CTL(nmi)               (((volatile uint32_t *) (CPUSS->CM0_NMI_CTL))[(nmi)])
476 #define CPUSS_CM7_0_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_0_NMI_CTL))[(nmi)])
477 #define CPUSS_CM7_1_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_1_NMI_CTL))[(nmi)])
478 
479 
480 #define CY_CPUSS_NOT_CONNECTED_IRQN          ((uint32_t)disconnected_IRQn)
481 #define CY_CPUSS_DISCONNECTED_IRQN           ((cy_en_intr_t)CY_CPUSS_NOT_CONNECTED_IRQN)
482 
483 #define CPUSS_CM0_INT_STATUS_BASE            ((volatile const uint32_t *) &(((CPUSS_Type *)(CPUSS))->CM0_INT0_STATUS))
484 #define CY_IS_CM0_CORE   ((_FLD2VAL(CPUSS_IDENTITY_MS, CPUSS_IDENTITY) == ((uint32_t)(CPUSS_MS_ID_CM0))) ? true : false)
485 #define CY_IS_CM7_CORE_0 ((_FLD2VAL(CPUSS_IDENTITY_MS, CPUSS_IDENTITY) == ((uint32_t)(CPUSS_MS_ID_CM7_0))) ? true : false)
486 #define CY_IS_CM7_CORE_1 ((_FLD2VAL(CPUSS_IDENTITY_MS, CPUSS_IDENTITY) == ((uint32_t)(CPUSS_MS_ID_CM7_1))) ? true : false)
487 
488 #define CPUSS_IDENTITY                       ((((CPUSS_Type *)(CPUSS_BASE))->IDENTITY))
489 #define CPUSS_CM7_0_STATUS                   ((((CPUSS_Type *)(CPUSS_BASE))->CM7_0_STATUS))
490 #define CPUSS_FAST_0_CLOCK_CTL               (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL)
491 #define CPUSS_CM7_0_CTL                      (((CPUSS_Type*) CPUSS_BASE)->CM7_0_CTL)
492 #define CPUSS_CM7_0_INT_STATUS               (((CPUSS_Type*) CPUSS_BASE)->CM7_0_INT_STATUS)
493 #define CPUSS_CM7_0_VECTOR_TABLE_BASE        (((CPUSS_Type*) CPUSS_BASE)->CM7_0_VECTOR_TABLE_BASE)
494 #define CPUSS_CM7_0_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_0_NMI_CTL))[(nmi)])
495 #define CPUSS_CM7_1_STATUS                   ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_STATUS))
496 #define CPUSS_FAST_1_CLOCK_CTL               (((CPUSS_Type*) CPUSS_BASE)->FAST_1_CLOCK_CTL)
497 #define CPUSS_CM7_1_CTL                      (((CPUSS_Type*) CPUSS_BASE)->CM7_1_CTL)
498 #define CPUSS_CM7_1_INT_STATUS               ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_INT_STATUS))
499 #define CPUSS_CM7_1_VECTOR_TABLE_BASE        (((CPUSS_Type*) CPUSS_BASE)->CM7_1_VECTOR_TABLE_BASE)
500 #define CPUSS_CM7_1_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_1_NMI_CTL))[(nmi)])
501 #define CPUSS_CM0_CTL                        (((CPUSS_Type*) CPUSS_BASE)->CM0_CTL)
502 #define CPUSS_CM0_STATUS                     (((CPUSS_Type*) CPUSS_BASE)->CM0_STATUS)
503 #define CPUSS_SLOW_CLOCK_CTL                 (((CPUSS_Type*) CPUSS_BASE)->SLOW_CLOCK_CTL)
504 #define CPUSS_PERI_CLOCK_CTL                 (((CPUSS_Type*) CPUSS_BASE)->PERI_CLOCK_CTL)
505 #define CPUSS_MEM_CLOCK_CTL                  (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL)
506 #define CPUSS_CM0_INT0_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT0_STATUS))
507 #define CPUSS_CM0_INT1_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT1_STATUS))
508 #define CPUSS_CM0_INT2_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT2_STATUS))
509 #define CPUSS_CM0_INT3_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT3_STATUS))
510 #define CPUSS_CM0_INT4_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT4_STATUS))
511 #define CPUSS_CM0_INT5_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT5_STATUS))
512 #define CPUSS_CM0_INT6_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT6_STATUS))
513 #define CPUSS_CM0_INT7_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT7_STATUS))
514 #define CPUSS_CM0_NMI_CTL(nmi)               (((volatile uint32_t *) (CPUSS->CM0_NMI_CTL))[(nmi)])
515 #define CPUSS_CM0_VECTOR_TABLE_BASE          ((((CPUSS_Type *)(CPUSS_BASE))->CM0_VECTOR_TABLE_BASE))
516 #define CPUSS_CM7_0_PWR_CTL                  ((((CPUSS_Type *)(CPUSS_BASE))->CM7_0_PWR_CTL))
517 #define CPUSS_CM7_1_PWR_DELAY_CTL            ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_PWR_DELAY_CTL))
518 #define CPUSS_RAM0_CTL0                      ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_CTL0))
519 #define CPUSS_RAM0_STATUS                    ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_STATUS))
520 #define CPUSS_RAM0_PWR_MACRO_CTL(macroIdx)   ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_PWR_MACRO_CTL[(macroIdx)]))
521 #define CPUSS_RAM1_CTL0                      ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_STATUS))
522 #define CPUSS_RAM1_STATUS                    ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_CTL0))
523 #define CPUSS_RAM1_PWR_CTL                   ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_PWR_CTL))
524 #define CPUSS_RAM2_CTL0                      ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_CTL0))
525 #define CPUSS_RAM2_STATUS                    ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_STATUS))
526 #define CPUSS_RAM2_PWR_CTL                   ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_PWR_CTL))
527 #define CPUSS_RAM_PWR_DELAY_CTL              ((((CPUSS_Type *)(CPUSS_BASE))->RAM_PWR_DELAY_CTL))
528 #define CPUSS_ROM_CTL                        ((((CPUSS_Type *)(CPUSS_BASE))->ROM_CTL))
529 #define CPUSS_ECC_CTL                        ((((CPUSS_Type *)(CPUSS_BASE))->ECC_CTL))
530 #define CPUSS_PRODUCT_ID                     ((((CPUSS_Type*) CPUSS_BASE)->PRODUCT_ID))
531 #define CPUSS_CM0_SYSTEM_INT_CTL             (((CPUSS_Type *)(CPUSS_BASE))->CM0_SYSTEM_INT_CTL)
532 #define CPUSS_CM7_0_SYSTEM_INT_CTL           (((CPUSS_Type *)(CPUSS_BASE))->CM7_0_SYSTEM_INT_CTL)
533 #define CPUSS_CM7_1_SYSTEM_INT_CTL           (((CPUSS_Type *)(CPUSS_BASE))->CM7_1_SYSTEM_INT_CTL)
534 
535 #define CPUSS_SRAM_COUNT                    (1u + CPUSS_RAMC1_PRESENT + CPUSS_RAMC2_PRESENT)
536 
537 
538 /*******************************************************************************
539 *                LPCOMP
540 *******************************************************************************/
541 
542 #define LPCOMP_CMP0_CTRL(base)              (((LPCOMP_V1_Type *)(base))->CMP0_CTRL)
543 #define LPCOMP_CMP1_CTRL(base)              (((LPCOMP_V1_Type *)(base))->CMP1_CTRL)
544 #define LPCOMP_CMP0_SW_CLEAR(base)          (((LPCOMP_V1_Type *)(base))->CMP0_SW_CLEAR)
545 #define LPCOMP_CMP1_SW_CLEAR(base)          (((LPCOMP_V1_Type *)(base))->CMP1_SW_CLEAR)
546 #define LPCOMP_CMP0_SW(base)                (((LPCOMP_V1_Type *)(base))->CMP0_SW)
547 #define LPCOMP_CMP1_SW(base)                (((LPCOMP_V1_Type *)(base))->CMP1_SW)
548 #define LPCOMP_STATUS(base)                 (((LPCOMP_V1_Type *)(base))->STATUS)
549 #define LPCOMP_CONFIG(base)                 (((LPCOMP_V1_Type *)(base))->CONFIG)
550 #define LPCOMP_INTR(base)                   (((LPCOMP_V1_Type *)(base))->INTR)
551 #define LPCOMP_INTR_SET(base)               (((LPCOMP_V1_Type *)(base))->INTR_SET)
552 #define LPCOMP_INTR_MASK(base)              (((LPCOMP_V1_Type *)(base))->INTR_MASK)
553 #define LPCOMP_INTR_MASKED(base)            (((LPCOMP_V1_Type *)(base))->INTR_MASKED)
554 
555 
556 /*******************************************************************************
557 *                MCWDT
558 *******************************************************************************/
559 #define MCWDT_CTR_CTL(base, counter)            (((MCWDT_Type *)(base))->CTR[counter].CTL)
560 #define MCWDT_CTR_LOWER_LIMIT(base, counter)    (((MCWDT_Type *)(base))->CTR[counter].LOWER_LIMIT)
561 #define MCWDT_CTR_UPPER_LIMIT(base, counter)    (((MCWDT_Type *)(base))->CTR[counter].UPPER_LIMIT)
562 #define MCWDT_CTR_WARN_LIMIT(base, counter)     (((MCWDT_Type *)(base))->CTR[counter].WARN_LIMIT)
563 #define MCWDT_CTR_CONFIG(base, counter)         (((MCWDT_Type *)(base))->CTR[counter].CONFIG)
564 #define MCWDT_CTR_CNT(base, counter)            (((MCWDT_Type *)(base))->CTR[counter].CNT)
565 
566 #define MCWDT_CPU_SELECT(base)                  (((MCWDT_Type *)(base))->CPU_SELECT)
567 #define MCWDT_CTR2_CTL(base)                    (((MCWDT_Type *)(base))->CTR2_CTL)
568 #define MCWDT_CTR2_CONFIG(base)                 (((MCWDT_Type *)(base))->CTR2_CONFIG)
569 #define MCWDT_CTR2_CNT(base)                    (((MCWDT_Type *)(base))->CTR2_CNT)
570 #define MCWDT_LOCK(base)                        (((MCWDT_Type *)(base))->LOCK)
571 #define MCWDT_SERVICE(base)                     (((MCWDT_Type *)(base))->SERVICE)
572 #define MCWDT_INTR(base)                        (((MCWDT_Type *)(base))->INTR)
573 #define MCWDT_INTR_SET(base)                    (((MCWDT_Type *)(base))->INTR_SET)
574 #define MCWDT_INTR_MASK(base)                   (((MCWDT_Type *)(base))->INTR_MASK)
575 #define MCWDT_INTR_MASKED(base)                 (((MCWDT_Type *)(base))->INTR_MASKED)
576 
577 
578 /*******************************************************************************
579 *                TCPWM
580 *******************************************************************************/
581 
582 #define TCPWM_CTRL_SET(base)                (((TCPWM_Type *)(base))->CTRL_SET)
583 #define TCPWM_CTRL_CLR(base)                (((TCPWM_Type *)(base))->CTRL_CLR)
584 #define TCPWM_CMD_START(base)               (((TCPWM_Type *)(base))->CMD_START)
585 #define TCPWM_CMD_RELOAD(base)              (((TCPWM_Type *)(base))->CMD_RELOAD)
586 #define TCPWM_CMD_STOP(base)                (((TCPWM_Type *)(base))->CMD_STOP)
587 #define TCPWM_CMD_CAPTURE(base)             (((TCPWM_Type *)(base))->CMD_CAPTURE)
588 
589 #define TCPWM_CNT_CTRL(base, cntNum)         (((TCPWM_Type *)(base))->CNT[cntNum].CTRL)
590 #define TCPWM_CNT_CC(base, cntNum)           (((TCPWM_Type *)(base))->CNT[cntNum].CC)
591 #define TCPWM_CNT_CC_BUFF(base, cntNum)      (((TCPWM_Type *)(base))->CNT[cntNum].CC_BUFF)
592 #define TCPWM_CNT_COUNTER(base, cntNum)      (((TCPWM_Type *)(base))->CNT[cntNum].COUNTER)
593 #define TCPWM_CNT_PERIOD(base, cntNum)       (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD)
594 #define TCPWM_CNT_PERIOD_BUFF(base, cntNum)  (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD_BUFF)
595 #define TCPWM_CNT_STATUS(base, cntNum)       (((TCPWM_Type *)(base))->CNT[cntNum].STATUS)
596 #define TCPWM_CNT_INTR(base, cntNum)         (((TCPWM_Type *)(base))->CNT[cntNum].INTR)
597 #define TCPWM_CNT_INTR_SET(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].INTR_SET)
598 #define TCPWM_CNT_INTR_MASK(base, cntNum)    (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASK)
599 #define TCPWM_CNT_INTR_MASKED(base, cntNum)  (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASKED)
600 #define TCPWM_CNT_TR_CTRL0(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL0)
601 #define TCPWM_CNT_TR_CTRL1(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL1)
602 #define TCPWM_CNT_TR_CTRL2(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL2)
603 
604 #if (CY_IP_MXTCPWM_INSTANCES == 1UL)
605 #define TCPWM_GRP_CC1_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))
606 #define TCPWM_GRP_AMC_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))
607 #define TCPWM_GRP_SMC_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))
608 #endif
609 
610 #if (CY_IP_MXTCPWM_INSTANCES == 2UL)
611 #define TCPWM_GRP_CC1_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)))
612 #define TCPWM_GRP_AMC_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)))
613 #define TCPWM_GRP_SMC_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)))
614 #endif
615 
616 #define TCPWM_GRP_CC1(base, grp) ((bool)(((TCPWM_GRP_CC1_PRESENT_STATUS(base)) >> (grp)) & 0x01U))
617 #define TCPWM_GRP_AMC(base, grp) ((bool)(((TCPWM_GRP_AMC_PRESENT_STATUS(base)) >> (grp)) & 0x01U))
618 #define TCPWM_GRP_SMC(base, grp) ((bool)(((TCPWM_GRP_SMC_PRESENT_STATUS(base)) >> (grp)) & 0x01U))
619 
620 #define TCPWM_GRP_CNT_GET_GRP(cntNum)        ((cntNum )/ 256U)
621 
622 #define TCPWM_GRP_CNT_CTRL(base, grp, cntNum)           (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CTRL)
623 #define TCPWM_GRP_CNT_STATUS(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].STATUS)
624 #define TCPWM_GRP_CNT_COUNTER(base, grp, cntNum)        (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].COUNTER)
625 #define TCPWM_GRP_CNT_CC0(base, grp, cntNum)            (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0)
626 #define TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0_BUFF)
627 #define TCPWM_GRP_CNT_CC1(base, grp, cntNum)            (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1)
628 #define TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1_BUFF)
629 #define TCPWM_GRP_CNT_PERIOD(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD)
630 #define TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD_BUFF)
631 #define TCPWM_GRP_CNT_LINE_SEL(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL)
632 #define TCPWM_GRP_CNT_LINE_SEL_BUFF(base, grp, cntNum)  (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL_BUFF)
633 #define TCPWM_GRP_CNT_DT(base, grp, cntNum)             (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT)
634 #define TCPWM_GRP_CNT_TR_CMD(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_CMD)
635 #define TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL0)
636 #define TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL1)
637 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_EDGE_SEL)
638 #define TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_PWM_CTRL)
639 #define TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_OUT_SEL)
640 #define TCPWM_GRP_CNT_INTR(base, grp, cntNum)           (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR)
641 #define TCPWM_GRP_CNT_INTR_SET(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_SET)
642 #define TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum)      (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASK)
643 #define TCPWM_GRP_CNT_INTR_MASKED(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASKED)
644 
645 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos
646 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk
647 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos
648 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk
649 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos
650 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk
651 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos
652 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk
653 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos
654 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk
655 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos
656 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk
657 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos
658 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk
659 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos
660 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk
661 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos  TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos
662 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk  TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk
663 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos
664 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk
665 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos
666 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk
667 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos
668 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk
669 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos  TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos
670 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk  TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk
671 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos      TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos
672 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk      TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk
673 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos
674 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk
675 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos          TCPWM_GRP_CNT_CTRL_MODE_Pos
676 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk          TCPWM_GRP_CNT_CTRL_MODE_Msk
677 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos
678 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk
679 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos       TCPWM_GRP_CNT_CTRL_ENABLED_Pos
680 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk       TCPWM_GRP_CNT_CTRL_ENABLED_Msk
681 /* TCPWM_GRP_CNT.STATUS */
682 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos        TCPWM_GRP_CNT_STATUS_DOWN_Pos
683 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk        TCPWM_GRP_CNT_STATUS_DOWN_Msk
684 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos
685 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk
686 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos    TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos
687 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk    TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk
688 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos   TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos
689 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk   TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk
690 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos     TCPWM_GRP_CNT_STATUS_TR_STOP_Pos
691 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk     TCPWM_GRP_CNT_STATUS_TR_STOP_Msk
692 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos    TCPWM_GRP_CNT_STATUS_TR_START_Pos
693 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk    TCPWM_GRP_CNT_STATUS_TR_START_Msk
694 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos
695 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk
696 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos    TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos
697 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk    TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk
698 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos
699 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk
700 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos     TCPWM_GRP_CNT_STATUS_RUNNING_Pos
701 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk     TCPWM_GRP_CNT_STATUS_RUNNING_Msk
702 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos    TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos
703 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk    TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk
704 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos    TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos
705 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk    TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk
706 /* TCPWM_GRP_CNT.COUNTER */
707 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos    TCPWM_GRP_CNT_COUNTER_COUNTER_Pos
708 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk    TCPWM_GRP_CNT_COUNTER_COUNTER_Msk
709 /* TCPWM_GRP_CNT.CC0 */
710 #define TCPWM_GRP_CNT_V2_CC0_CC_Pos             TCPWM_GRP_CNT_CC0_CC_Pos
711 #define TCPWM_GRP_CNT_V2_CC0_CC_Msk             TCPWM_GRP_CNT_CC0_CC_Msk
712 /* TCPWM_GRP_CNT.CC0_BUFF */
713 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos        TCPWM_GRP_CNT_CC0_BUFF_CC_Pos
714 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk        TCPWM_GRP_CNT_CC0_BUFF_CC_Msk
715 /* TCPWM_GRP_CNT.CC1 */
716 #define TCPWM_GRP_CNT_V2_CC1_CC_Pos             TCPWM_GRP_CNT_CC1_CC_Pos
717 #define TCPWM_GRP_CNT_V2_CC1_CC_Msk             TCPWM_GRP_CNT_CC1_CC_Msk
718 /* TCPWM_GRP_CNT.CC1_BUFF */
719 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos        TCPWM_GRP_CNT_CC1_BUFF_CC_Pos
720 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk        TCPWM_GRP_CNT_CC1_BUFF_CC_Msk
721 /* TCPWM_GRP_CNT.PERIOD */
722 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos      TCPWM_GRP_CNT_PERIOD_PERIOD_Pos
723 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk      TCPWM_GRP_CNT_PERIOD_PERIOD_Msk
724 /* TCPWM_GRP_CNT.PERIOD_BUFF */
725 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos
726 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk
727 /* TCPWM_GRP_CNT.LINE_SEL */
728 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos   TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos
729 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk   TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk
730 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos
731 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk
732 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */
733 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos
734 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk
735 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos
736 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk
737 /* TCPWM_GRP_CNT.DT */
738 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos   TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos
739 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk   TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk
740 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos   TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos
741 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk   TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk
742 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos
743 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk
744 /* TCPWM_GRP_CNT.TR_CMD */
745 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos    TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos
746 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk    TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk
747 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos      TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos
748 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk      TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk
749 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos        TCPWM_GRP_CNT_TR_CMD_STOP_Pos
750 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk        TCPWM_GRP_CNT_TR_CMD_STOP_Msk
751 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos       TCPWM_GRP_CNT_TR_CMD_START_Pos
752 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk       TCPWM_GRP_CNT_TR_CMD_START_Msk
753 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos    TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos
754 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk    TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk
755 /* TCPWM_GRP_CNT.TR_IN_SEL0 */
756 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos
757 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk
758 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos
759 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk
760 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos
761 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk
762 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos
763 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk
764 /* TCPWM_GRP_CNT.TR_IN_SEL1 */
765 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos
766 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk
767 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos
768 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk
769 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */
770 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos
771 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk
772 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos
773 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk
774 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos
775 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk
776 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos
777 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk
778 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos
779 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk
780 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos
781 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk
782 /* TCPWM_GRP_CNT.TR_PWM_CTRL */
783 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos
784 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk
785 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos
786 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk
787 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos
788 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk
789 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos
790 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk
791 /* TCPWM_GRP_CNT.TR_OUT_SEL */
792 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos    TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos
793 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk    TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk
794 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos    TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos
795 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk    TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk
796 /* TCPWM_GRP_CNT.INTR */
797 #define TCPWM_GRP_CNT_V2_INTR_TC_Pos            TCPWM_GRP_CNT_INTR_TC_Pos
798 #define TCPWM_GRP_CNT_V2_INTR_TC_Msk            TCPWM_GRP_CNT_INTR_TC_Msk
799 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos     TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos
800 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk     TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk
801 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos     TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos
802 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk     TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk
803 /* TCPWM_GRP_CNT.INTR_SET */
804 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos        TCPWM_GRP_CNT_INTR_SET_TC_Pos
805 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk        TCPWM_GRP_CNT_INTR_SET_TC_Msk
806 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos
807 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk
808 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos
809 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk
810 /* TCPWM_GRP_CNT.INTR_MASK */
811 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos       TCPWM_GRP_CNT_INTR_MASK_TC_Pos
812 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk       TCPWM_GRP_CNT_INTR_MASK_TC_Msk
813 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos
814 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk
815 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos
816 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk
817 /* TCPWM_GRP_CNT.INTR_MASKED */
818 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos     TCPWM_GRP_CNT_INTR_MASKED_TC_Pos
819 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk     TCPWM_GRP_CNT_INTR_MASKED_TC_Msk
820 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos
821 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk
822 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos
823 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk
824 
825 /* For backward compatibility, we set TCPWM_CNT_STATUS_RUNNING_Pos with TCPWM_GRP_CNT_V2_STATUS_RUNNING
826 we need to define this for version 2 only. */
827 #define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
828 
829 
830 /*******************************************************************************
831 *                SAR
832 *******************************************************************************/
833 
834 #define CY_SAR_INSTANCES                    (2UL)
835 #define CY_SAR0_BASE                        ((SAR_Type*)(cy_device->sar0Base))
836 #define CY_SAR_INSTANCE(base)               ((CY_SAR0_BASE == (base)) ? 0UL : 1UL)
837 
838 #define SAR_SAMPLE_CTRL(base)               (((SAR_V1_Type *)(base))->SAMPLE_CTRL)
839 #define SAR_SAMPLE_TIME01(base)             (((SAR_V1_Type *)(base))->SAMPLE_TIME01)
840 #define SAR_SAMPLE_TIME23(base)             (((SAR_V1_Type *)(base))->SAMPLE_TIME23)
841 
842 #define SAR_RANGE_THRES(base)               (((SAR_V1_Type *)(base))->RANGE_THRES)
843 #define SAR_RANGE_COND(base)                (((SAR_V1_Type *)(base))->RANGE_COND)
844 #define SAR_RANGE_INTR(base)                (((SAR_V1_Type *)(base))->RANGE_INTR)
845 #define SAR_RANGE_INTR_SET(base)            (((SAR_V1_Type *)(base))->RANGE_INTR_SET)
846 
847 #define SAR_RANGE_INTR_MASK(base)           (((SAR_V1_Type *)(base))->RANGE_INTR_MASK)
848 #define SAR_RANGE_INTR_MASKED(base)         (((SAR_V1_Type *)(base))->RANGE_INTR_MASKED)
849 
850 #define SAR_CHAN_EN(base)                   (((SAR_V1_Type *)(base))->CHAN_EN)
851 #define SAR_CHAN_CONFIG(base, chan)         (((SAR_V1_Type *)(base))->CHAN_CONFIG[(chan)])
852 #define SAR_CHAN_RESULT(base, chan )        (((SAR_V1_Type *)(base))->CHAN_RESULT[(chan)])
853 #define SAR_CHAN_RESULT_UPDATED(base)       (((SAR_V1_Type *)(base))->CHAN_RESULT_UPDATED)
854 
855 #define SAR_INTR(base)                      (((SAR_V1_Type *)(base))->INTR)
856 #define SAR_INTR_MASK(base)                 (((SAR_V1_Type *)(base))->INTR_MASK)
857 #define SAR_INTR_MASKED(base)               (((SAR_V1_Type *)(base))->INTR_MASKED)
858 #define SAR_INTR_SET(base)                  (((SAR_V1_Type *)(base))->INTR_SET)
859 #define SAR_INTR_CAUSE(base)                (((SAR_V1_Type *)(base))->INTR_CAUSE)
860 
861 #define SAR_MUX_SWITCH_CLEAR0(base)         (((SAR_V1_Type *)(base))->MUX_SWITCH_CLEAR0)
862 #define SAR_MUX_SWITCH0(base)               (((SAR_V1_Type *)(base))->MUX_SWITCH0)
863 #define SAR_MUX_SWITCH_SQ_CTRL(base)        (((SAR_V1_Type *)(base))->MUX_SWITCH_SQ_CTRL)
864 #define SAR_MUX_SWITCH_DS_CTRL(base)        (((SAR_V1_Type *)(base))->MUX_SWITCH_DS_CTRL)
865 
866 #define SAR_ANA_TRIM0(base)                 (((SAR_V1_Type *)(base))->ANA_TRIM0)
867 #define SAR_CTRL(base)                      (((SAR_V1_Type *)(base))->CTRL)
868 #define SAR_STATUS(base)                    (((SAR_V1_Type *)(base))->STATUS)
869 #define SAR_START_CTRL(base)                (((SAR_V1_Type *)(base))->START_CTRL)
870 
871 #define SAR_SATURATE_INTR(base)             (((SAR_V1_Type *)(base))->SATURATE_INTR)
872 #define SAR_SATURATE_INTR_MASK(base)        (((SAR_V1_Type *)(base))->SATURATE_INTR_MASK)
873 #define SAR_SATURATE_INTR_MASKED(base)      (((SAR_V1_Type *)(base))->SATURATE_INTR_MASKED)
874 #define SAR_SATURATE_INTR_SET(base)         (((SAR_V1_Type *)(base))->SATURATE_INTR_SET)
875 
876 #define SAR_INJ_CHAN_CONFIG(base)           (((SAR_V1_Type *)(base))->INJ_CHAN_CONFIG)
877 #define SAR_INJ_RESULT(base)                (((SAR_V1_Type *)(base))->INJ_RESULT)
878 
879 /*******************************************************************************
880 *                FAULT
881 *******************************************************************************/
882 
883 #define FAULT_CTL(base)                         (((FAULT_STRUCT_Type *)(base))->CTL)
884 #define FAULT_STATUS(base)                      (((FAULT_STRUCT_Type *)(base))->STATUS)
885 #define FAULT_DATA(base)                        (((FAULT_STRUCT_Type *)(base))->DATA)
886 #define FAULT_PENDING0(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING0)
887 #define FAULT_PENDING1(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING1)
888 #define FAULT_PENDING2(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING2)
889 #define FAULT_MASK0(base)                       (((FAULT_STRUCT_Type *)(base))->MASK0)
890 #define FAULT_MASK1(base)                       (((FAULT_STRUCT_Type *)(base))->MASK1)
891 #define FAULT_MASK2(base)                       (((FAULT_STRUCT_Type *)(base))->MASK2)
892 #define FAULT_INTR(base)                        (((FAULT_STRUCT_Type *)(base))->INTR)
893 #define FAULT_INTR_SET(base)                    (((FAULT_STRUCT_Type *)(base))->INTR_SET)
894 #define FAULT_INTR_MASK(base)                   (((FAULT_STRUCT_Type *)(base))->INTR_MASK)
895 #define FAULT_INTR_MASKED(base)                 (((FAULT_STRUCT_Type *)(base))->INTR_MASKED)
896 
897 /*******************************************************************************
898 *                SDHC
899 *******************************************************************************/
900 
901 #define SDHC_WRAP_CTL(base)                     (((SDHC_Type *)(base))->WRAP.CTL)
902 #define SDHC_CORE_SDMASA_R(base)                (((SDHC_Type *)(base))->CORE.SDMASA_R)
903 #define SDHC_CORE_BLOCKSIZE_R(base)             (((SDHC_Type *)(base))->CORE.BLOCKSIZE_R)
904 #define SDHC_CORE_BLOCKCOUNT_R(base)            (((SDHC_Type *)(base))->CORE.BLOCKCOUNT_R)
905 #define SDHC_CORE_ARGUMENT_R(base)              (((SDHC_Type *)(base))->CORE.ARGUMENT_R)
906 #define SDHC_CORE_XFER_MODE_R(base)             (((SDHC_Type *)(base))->CORE.XFER_MODE_R)
907 #define SDHC_CORE_CMD_R(base)                   (((SDHC_Type *)(base))->CORE.CMD_R)
908 #define SDHC_CORE_RESP01_R(base)                (((SDHC_Type *)(base))->CORE.RESP01_R)
909 #define SDHC_CORE_RESP23_R(base)                (((SDHC_Type *)(base))->CORE.RESP23_R)
910 #define SDHC_CORE_RESP45_R(base)                (((SDHC_Type *)(base))->CORE.RESP45_R)
911 #define SDHC_CORE_RESP67_R(base)                (((SDHC_Type *)(base))->CORE.RESP67_R)
912 #define SDHC_CORE_BUF_DATA_R(base)              (((SDHC_Type *)(base))->CORE.BUF_DATA_R)
913 #define SDHC_CORE_PSTATE_REG(base)              (((SDHC_Type *)(base))->CORE.PSTATE_REG)
914 #define SDHC_CORE_HOST_CTRL1_R(base)            (((SDHC_Type *)(base))->CORE.HOST_CTRL1_R)
915 #define SDHC_CORE_PWR_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.PWR_CTRL_R)
916 #define SDHC_CORE_BGAP_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.BGAP_CTRL_R)
917 #define SDHC_CORE_WUP_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.WUP_CTRL_R)
918 #define SDHC_CORE_CLK_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.CLK_CTRL_R)
919 #define SDHC_CORE_TOUT_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.TOUT_CTRL_R)
920 #define SDHC_CORE_SW_RST_R(base)                (((SDHC_Type *)(base))->CORE.SW_RST_R)
921 #define SDHC_CORE_NORMAL_INT_STAT_R(base)       (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_R)
922 #define SDHC_CORE_ERROR_INT_STAT_R(base)        (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_R)
923 #define SDHC_CORE_NORMAL_INT_STAT_EN_R(base)    (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R)
924 #define SDHC_CORE_ERROR_INT_STAT_EN_R(base)     (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_EN_R)
925 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base)  (((SDHC_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R)
926 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base)   (((SDHC_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R)
927 #define SDHC_CORE_AUTO_CMD_STAT_R(base)         (((SDHC_Type *)(base))->CORE.AUTO_CMD_STAT_R)
928 #define SDHC_CORE_HOST_CTRL2_R(base)            (((SDHC_Type *)(base))->CORE.HOST_CTRL2_R)
929 #define SDHC_CORE_CAPABILITIES1_R(base)         (((SDHC_Type *)(base))->CORE.CAPABILITIES1_R)
930 #define SDHC_CORE_CAPABILITIES2_R(base)         (((SDHC_Type *)(base))->CORE.CAPABILITIES2_R)
931 #define SDHC_CORE_CURR_CAPABILITIES1_R(base)    (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES1_R)
932 #define SDHC_CORE_CURR_CAPABILITIES2_R(base)    (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES2_R)
933 #define SDHC_CORE_ADMA_ERR_STAT_R(base)         (((SDHC_Type *)(base))->CORE.ADMA_ERR_STAT_R)
934 #define SDHC_CORE_ADMA_SA_LOW_R(base)           (((SDHC_Type *)(base))->CORE.ADMA_SA_LOW_R)
935 #define SDHC_CORE_ADMA_ID_LOW_R(base)           (((SDHC_Type *)(base))->CORE.ADMA_ID_LOW_R)
936 #define SDHC_CORE_EMMC_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.EMMC_CTRL_R)
937 #define SDHC_CORE_GP_OUT_R(base)                (((SDHC_Type *)(base))->CORE.GP_OUT_R)
938 
939 /*******************************************************************************
940 *                SMARTIO
941 *******************************************************************************/
942 
943 #define SMARTIO_PRT_CTL(base)               (((SMARTIO_PRT_Type *)(base))->CTL)
944 #define SMARTIO_PRT_SYNC_CTL(base)          (((SMARTIO_PRT_Type *)(base))->SYNC_CTL)
945 #define SMARTIO_PRT_LUT_SEL(base, idx)      (((SMARTIO_PRT_Type *)(base))->LUT_SEL[idx])
946 #define SMARTIO_PRT_LUT_CTL(base, idx)      (((SMARTIO_PRT_Type *)(base))->LUT_CTL[idx])
947 #define SMARTIO_PRT_DU_SEL(base)            (((SMARTIO_PRT_Type *)(base))->DU_SEL)
948 #define SMARTIO_PRT_DU_CTL(base)            (((SMARTIO_PRT_Type *)(base))->DU_CTL)
949 #define SMARTIO_PRT_DATA(base)              (((SMARTIO_PRT_Type *)(base))->DATA)
950 
951 
952 /*******************************************************************************
953 *                SMIF
954 *******************************************************************************/
955 
956 #if defined (CY_IP_MXSMIF_VERSION) && (CY_IP_MXSMIF_VERSION >= 4)
957 /* Feature Flags - Start
958  * Few products have very less memory available in BOOT ROM and they do not require
959  * SFDP enumeration of Octal parts. Hence, we introduce feature flags to enable
960  * specific features only where Octal SFDP enumeration and Hyperbus devices are supported
961  * using below feature flags
962  */
963 #define SMIF_OCTAL_SFDP_SUPPORT
964 #define SMIF_HYPERBUS_DEVICE_SUPPORT
965 /* Feature Flags - End */
966 
967 /* Hidden parameter in SAS (SW=No), have to manually create here.  Remove once
968    SAS issue is corrected and this is generated in the MPN. */
969 #if defined (CY_DEVICE_TVIIC2D6M)
970 /* 0: Bridge is not present. Only SMIF0 is present. SMIF_NR must be set to 1. 1:
971    Bridge is present. Both SMIF0 and SMIF1 are present. SMIF_NR must be set to
972    2. */
973 #define SMIF_BRIDGE_PRESENT                          1
974 /* Number of SMIFs present - must be set as described in BRIDGE_PRESENT. */
975 #define SMIF_SMIF_NR                                 2u
976 #endif
977 
978 #define SMIF_DEVICE_CTL_WR_EN_Pos                    SMIF_CORE_DEVICE_CTL_WR_EN_Pos
979 #define SMIF_DEVICE_CTL_CRYPTO_EN_Pos                SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Pos
980 #define SMIF_DEVICE_CTL_MERGE_EN_Pos                 SMIF_CORE_DEVICE_CTL_MERGE_EN_Pos
981 #define SMIF_DEVICE_CTL_MERGE_TIMEOUT_Pos            SMIF_CORE_DEVICE_CTL_MERGE_TIMEOUT_Pos
982 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_Pos            SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_Pos
983 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_EN_Pos         SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_EN_Pos
984 #define SMIF_DEVICE_CTL_ENABLED_Pos                  SMIF_CORE_DEVICE_CTL_ENABLED_Pos
985 #define SMIF_DEVICE_ADDR_ADDR_Pos                    SMIF_CORE_DEVICE_ADDR_ADDR_Pos
986 #define SMIF_DEVICE_ADDR_CTL_SIZE3_Pos               SMIF_CORE_DEVICE_ADDR_CTL_SIZE3_Pos
987 #define SMIF_DEVICE_ADDR_CTL_DIV2_Pos                SMIF_CORE_DEVICE_ADDR_CTL_DIV2_Pos
988 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos              SMIF_CORE_DEVICE_RD_CMD_CTL_CODE_Pos
989 #define SMIF_DEVICE_RD_CMD_CTL_CODEH_Pos             SMIF_CORE_DEVICE_RD_CMD_CTL_CODEH_Pos
990 #define SMIF_DEVICE_RD_CMD_CTL_DDR_MODE_Pos          SMIF_CORE_DEVICE_RD_CMD_CTL_DDR_MODE_Pos
991 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos             SMIF_CORE_DEVICE_RD_CMD_CTL_WIDTH_Pos
992 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT2_Pos          SMIF_CORE_DEVICE_RD_CMD_CTL_PRESENT2_Pos
993 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos            SMIF_CORE_DEVICE_RD_ADDR_CTL_WIDTH_Pos
994 #define SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE_Pos         SMIF_CORE_DEVICE_RD_ADDR_CTL_DDR_MODE_Pos
995 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos             SMIF_CORE_DEVICE_RD_MODE_CTL_CODE_Pos
996 #define SMIF_DEVICE_RD_MODE_CTL_CODEH_Pos            SMIF_CORE_DEVICE_RD_MODE_CTL_CODEH_Pos
997 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos            SMIF_CORE_DEVICE_RD_MODE_CTL_WIDTH_Pos
998 #define SMIF_DEVICE_RD_MODE_CTL_DDR_MODE_Pos         SMIF_CORE_DEVICE_RD_MODE_CTL_DDR_MODE_Pos
999 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT2_Pos         SMIF_CORE_DEVICE_RD_MODE_CTL_PRESENT2_Pos
1000 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos           SMIF_CORE_DEVICE_RD_DUMMY_CTL_SIZE5_Pos
1001 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2_Pos        SMIF_CORE_DEVICE_RD_DUMMY_CTL_PRESENT2_Pos
1002 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos            SMIF_CORE_DEVICE_RD_DATA_CTL_WIDTH_Pos
1003 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Pos         SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Pos
1004 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos              SMIF_CORE_DEVICE_WR_CMD_CTL_CODE_Pos
1005 #define SMIF_DEVICE_WR_CMD_CTL_CODEH_Pos             SMIF_CORE_DEVICE_WR_CMD_CTL_CODEH_Pos
1006 #define SMIF_DEVICE_WR_CMD_CTL_DDR_MODE_Pos          SMIF_CORE_DEVICE_WR_CMD_CTL_DDR_MODE_Pos
1007 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos             SMIF_CORE_DEVICE_WR_CMD_CTL_WIDTH_Pos
1008 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT2_Pos          SMIF_CORE_DEVICE_WR_CMD_CTL_PRESENT2_Pos
1009 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos            SMIF_CORE_DEVICE_WR_ADDR_CTL_WIDTH_Pos
1010 #define SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE_Pos         SMIF_CORE_DEVICE_WR_ADDR_CTL_DDR_MODE_Pos
1011 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos             SMIF_CORE_DEVICE_WR_MODE_CTL_CODE_Pos
1012 #define SMIF_DEVICE_WR_MODE_CTL_CODEH_Pos            SMIF_CORE_DEVICE_WR_MODE_CTL_CODEH_Pos
1013 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos            SMIF_CORE_DEVICE_WR_MODE_CTL_WIDTH_Pos
1014 #define SMIF_DEVICE_WR_MODE_CTL_DDR_MODE_Pos         SMIF_CORE_DEVICE_WR_MODE_CTL_DDR_MODE_Pos
1015 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT2_Pos         SMIF_CORE_DEVICE_WR_MODE_CTL_PRESENT2_Pos
1016 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos           SMIF_CORE_DEVICE_WR_DUMMY_CTL_SIZE5_Pos
1017 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2_Pos        SMIF_CORE_DEVICE_WR_DUMMY_CTL_PRESENT2_Pos
1018 #define SMIF_DEVICE_WR_DUMMY_CTL_RWDS_EN_Pos         SMIF_CORE_DEVICE_WR_DUMMY_CTL_RWDS_EN_Pos
1019 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos            SMIF_CORE_DEVICE_WR_DATA_CTL_WIDTH_Pos
1020 #define SMIF_DEVICE_WR_DATA_CTL_DDR_MODE_Pos         SMIF_CORE_DEVICE_WR_DATA_CTL_DDR_MODE_Pos
1021 #define SMIF_DEVICE_RD_BOUND_CTL_SIZE5_Pos           SMIF_CORE_DEVICE_RD_BOUND_CTL_SIZE5_Pos
1022 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Pos   SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Pos
1023 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Pos     SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Pos
1024 #define SMIF_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Pos SMIF_CORE_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Pos
1025 #define SMIF_DEVICE_RD_BOUND_CTL_PRESENT_Pos         SMIF_CORE_DEVICE_RD_BOUND_CTL_PRESENT_Pos
1026 
1027 #define SMIF_DEVICE_CTL_WR_EN_Msk                  SMIF_CORE_DEVICE_CTL_WR_EN_Msk
1028 #define SMIF_DEVICE_CTL_CRYPTO_EN_Msk              SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Msk
1029 #define SMIF_DEVICE_CTL_MERGE_EN_Msk               SMIF_CORE_DEVICE_CTL_MERGE_EN_Msk
1030 #define SMIF_DEVICE_CTL_MERGE_TIMEOUT_Msk          SMIF_CORE_DEVICE_CTL_MERGE_TIMEOUT_Msk
1031 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_Msk          SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_Msk
1032 #define SMIF_DEVICE_CTL_TOTAL_TIMEOUT_EN_Msk       SMIF_CORE_DEVICE_CTL_TOTAL_TIMEOUT_EN_Msk
1033 #define SMIF_DEVICE_CTL_ENABLED_Msk                SMIF_CORE_DEVICE_CTL_ENABLED_Msk
1034 #define SMIF_DEVICE_ADDR_ADDR_Msk                  SMIF_CORE_DEVICE_ADDR_ADDR_Msk
1035 #define SMIF_DEVICE_ADDR_CTL_SIZE3_Msk             SMIF_CORE_DEVICE_ADDR_CTL_SIZE3_Msk
1036 #define SMIF_DEVICE_ADDR_CTL_DIV2_Msk              SMIF_CORE_DEVICE_ADDR_CTL_DIV2_Msk
1037 #define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk            SMIF_CORE_DEVICE_RD_CMD_CTL_CODE_Msk
1038 #define SMIF_DEVICE_RD_CMD_CTL_CODEH_Msk           SMIF_CORE_DEVICE_RD_CMD_CTL_CODEH_Msk
1039 #define SMIF_DEVICE_RD_CMD_CTL_DDR_MODE_Msk        SMIF_CORE_DEVICE_RD_CMD_CTL_DDR_MODE_Msk
1040 #define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk           SMIF_CORE_DEVICE_RD_CMD_CTL_WIDTH_Msk
1041 #define SMIF_DEVICE_RD_CMD_CTL_PRESENT2_Msk        SMIF_CORE_DEVICE_RD_CMD_CTL_PRESENT2_Msk
1042 #define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk          SMIF_CORE_DEVICE_RD_ADDR_CTL_WIDTH_Msk
1043 #define SMIF_DEVICE_RD_ADDR_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_RD_ADDR_CTL_DDR_MODE_Msk
1044 #define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk           SMIF_CORE_DEVICE_RD_MODE_CTL_CODE_Msk
1045 #define SMIF_DEVICE_RD_MODE_CTL_CODEH_Msk          SMIF_CORE_DEVICE_RD_MODE_CTL_CODEH_Msk
1046 #define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk          SMIF_CORE_DEVICE_RD_MODE_CTL_WIDTH_Msk
1047 #define SMIF_DEVICE_RD_MODE_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_RD_MODE_CTL_DDR_MODE_Msk
1048 #define SMIF_DEVICE_RD_MODE_CTL_PRESENT2_Msk       SMIF_CORE_DEVICE_RD_MODE_CTL_PRESENT2_Msk
1049 #define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk         SMIF_CORE_DEVICE_RD_DUMMY_CTL_SIZE5_Msk
1050 #define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT2_Msk      SMIF_CORE_DEVICE_RD_DUMMY_CTL_PRESENT2_Msk
1051 #define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk          SMIF_CORE_DEVICE_RD_DATA_CTL_WIDTH_Msk
1052 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Msk
1053 #define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk            SMIF_CORE_DEVICE_WR_CMD_CTL_CODE_Msk
1054 #define SMIF_DEVICE_WR_CMD_CTL_CODEH_Msk           SMIF_CORE_DEVICE_WR_CMD_CTL_CODEH_Msk
1055 #define SMIF_DEVICE_WR_CMD_CTL_DDR_MODE_Msk        SMIF_CORE_DEVICE_WR_CMD_CTL_DDR_MODE_Msk
1056 #define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk           SMIF_CORE_DEVICE_WR_CMD_CTL_WIDTH_Msk
1057 #define SMIF_DEVICE_WR_CMD_CTL_PRESENT2_Msk        SMIF_CORE_DEVICE_WR_CMD_CTL_PRESENT2_Msk
1058 #define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk          SMIF_CORE_DEVICE_WR_ADDR_CTL_WIDTH_Msk
1059 #define SMIF_DEVICE_WR_ADDR_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_WR_ADDR_CTL_DDR_MODE_Msk
1060 #define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk           SMIF_CORE_DEVICE_WR_MODE_CTL_CODE_Msk
1061 #define SMIF_DEVICE_WR_MODE_CTL_CODEH_Msk          SMIF_CORE_DEVICE_WR_MODE_CTL_CODEH_Msk
1062 #define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk          SMIF_CORE_DEVICE_WR_MODE_CTL_WIDTH_Msk
1063 #define SMIF_DEVICE_WR_MODE_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_WR_MODE_CTL_DDR_MODE_Msk
1064 #define SMIF_DEVICE_WR_MODE_CTL_PRESENT2_Msk       SMIF_CORE_DEVICE_WR_MODE_CTL_PRESENT2_Msk
1065 #define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk         SMIF_CORE_DEVICE_WR_DUMMY_CTL_SIZE5_Msk
1066 #define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT2_Msk      SMIF_CORE_DEVICE_WR_DUMMY_CTL_PRESENT2_Msk
1067 #define SMIF_DEVICE_WR_DUMMY_CTL_RWDS_EN_Msk       SMIF_CORE_DEVICE_WR_DUMMY_CTL_RWDS_EN_Msk
1068 #define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk          SMIF_CORE_DEVICE_WR_DATA_CTL_WIDTH_Msk
1069 #define SMIF_DEVICE_WR_DATA_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_WR_DATA_CTL_DDR_MODE_Msk
1070 #define SMIF_DEVICE_MASK_MASK_Msk                  SMIF_CORE_DEVICE_MASK_MASK_Msk
1071 
1072 #define SMIF_DEVICE_RD_BOUND_CTL_SIZE5_Msk           SMIF_CORE_DEVICE_RD_BOUND_CTL_SIZE5_Msk
1073 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Msk   SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_SIZE_Msk
1074 #define SMIF_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Msk     SMIF_CORE_DEVICE_RD_BOUND_CTL_SUB_PAGE_NR_Msk
1075 #define SMIF_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Msk SMIF_CORE_DEVICE_RD_BOUND_CTL_SUBSEQ_BOUND_EN_Msk
1076 #define SMIF_DEVICE_RD_BOUND_CTL_PRESENT_Msk         SMIF_CORE_DEVICE_RD_BOUND_CTL_PRESENT_Msk
1077 
1078 #define SMIF_RX_DATA_FIFO_CTL                      SMIF_RX_DATA_MMIO_FIFO_CTL
1079 #define SMIF_RX_DATA_FIFO_RD4                      SMIF_RX_DATA_MMIO_FIFO_RD4
1080 #define SMIF_RX_DATA_FIFO_RD1                      SMIF_RX_DATA_MMIO_FIFO_RD1
1081 #define SMIF_RX_DATA_FIFO_RD2                      SMIF_RX_DATA_MMIO_FIFO_RD2
1082 
1083 #define SMIF_TX_DATA_FIFO_CTL                      SMIF_TX_DATA_MMIO_FIFO_CTL
1084 #define SMIF_TX_DATA_FIFO_WR4                      SMIF_TX_DATA_MMIO_FIFO_WR4
1085 #define SMIF_TX_DATA_FIFO_WR1                      SMIF_TX_DATA_MMIO_FIFO_WR1
1086 #define SMIF_TX_DATA_FIFO_WR2                      SMIF_TX_DATA_MMIO_FIFO_WR2
1087 
1088 #define SMIF_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk     SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk
1089 #define SMIF_TX_CMD_MMIO_FIFO_STATUS_USED4_Pos     SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Pos
1090 
1091 #define SMIF_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk    SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk
1092 #define SMIF_TX_DATA_MMIO_FIFO_STATUS_USED4_Pos    SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Pos
1093 
1094 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk    SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk
1095 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Pos    SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Pos
1096 
1097 #define SMIF_STATUS_BUSY_Msk                       SMIF_CORE_STATUS_BUSY_Msk
1098 #define SMIF_STATUS_BUSY_Pos                       SMIF_CORE_STATUS_BUSY_Pos
1099 #define SMIF_DEVICE_Type                           SMIF_CORE_DEVICE_Type
1100 #define SMIF_Base_Type                             SMIF_STRUCT_Type
1101 #define SMIF_Type                                  SMIF_CORE_Type
1102 #define CY_SMIF_CORE_COUNT                         (2U)
1103 #define CY_SMIF_BRIDGE_REMAP_REGION_COUNT          (8U)
1104 
1105 #if defined (SMIF_FAST_CACHE_PRESENT)
1106 #define SMIF_FAST_CA_CMD_INV_Msk                   SMIF_CORE_FAST_CA_CMD_INV_Msk
1107 #define SMIF_FAST_CA_CTL_PREF_EN_Msk               SMIF_CORE_FAST_CA_CTL_PREF_EN_Msk
1108 #define SMIF_FAST_CA_CTL_ENABLED_Msk               SMIF_CORE_FAST_CA_CTL_ENABLED_Msk
1109 #endif
1110 
1111 #if defined (SMIF_SLOW_CACHE_PRESENT)
1112 #define SMIF_SLOW_CA_CMD_INV_Msk                   SMIF_CORE_SLOW_CA_CMD_INV_Msk
1113 #define SMIF_SLOW_CA_CTL_ENABLED_Msk               SMIF_CORE_SLOW_CA_CTL_ENABLED_Msk
1114 #define SMIF_SLOW_CA_CTL_PREF_EN_Msk               SMIF_CORE_SLOW_CA_CTL_PREF_EN_Msk
1115 #endif
1116 
1117 #define SMIF_SMIF_CRYPTO_CRYPTO_CMD_START_Pos      SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Pos
1118 #define SMIF_SMIF_CRYPTO_CRYPTO_CMD_START_Msk      SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Msk
1119 
1120 #define SMIF_DEVICE_CTL_CRYPTO_EN_Msk              SMIF_CORE_DEVICE_CTL_CRYPTO_EN_Msk
1121 #define SMIF_INTR_TR_TX_REQ_Msk                    SMIF_CORE_INTR_TR_TX_REQ_Msk
1122 #define SMIF_INTR_TR_RX_REQ_Msk                    SMIF_CORE_INTR_TR_RX_REQ_Msk
1123 #define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk          SMIF_CORE_INTR_XIP_ALIGNMENT_ERROR_Msk
1124 #define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk         SMIF_CORE_INTR_TX_CMD_FIFO_OVERFLOW_Msk
1125 #define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk        SMIF_CORE_INTR_TX_DATA_FIFO_OVERFLOW_Msk
1126 #define SMIF_INTR_TR_RX_REQ_Msk                    SMIF_CORE_INTR_TR_RX_REQ_Msk
1127 #define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk       SMIF_CORE_INTR_RX_DATA_MMIO_FIFO_UNDERFLOW_Msk
1128 #define SMIF_STATUS_BUSY_Msk                       SMIF_CORE_STATUS_BUSY_Msk
1129 #define SMIF_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk    SMIF_CORE_RX_DATA_MMIO_FIFO_STATUS_USED4_Msk
1130 #define SMIF_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk    SMIF_CORE_TX_DATA_MMIO_FIFO_STATUS_USED4_Msk
1131 #define SMIF_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk     SMIF_CORE_TX_CMD_MMIO_FIFO_STATUS_USED4_Msk
1132 #define SMIF_CTL_DESELECT_DELAY_Msk                SMIF_CORE_CTL_DESELECT_DELAY_Msk
1133 #define SMIF_CTL_DESELECT_DELAY_Pos                SMIF_CORE_CTL_DESELECT_DELAY_Pos
1134 #define SMIF_DEVICE_RD_DATA_CTL_DDR_MODE_Msk       SMIF_CORE_DEVICE_RD_DATA_CTL_DDR_MODE_Msk
1135 #define SMIF_DEVICE_CTL_DATA_SEL_Msk               SMIF_CORE_DEVICE_CTL_DATA_SEL_Msk
1136 #define SMIF_CTL_ENABLED_Msk                       SMIF_CORE_CTL_ENABLED_Msk
1137 #define SMIF_CTL_ENABLED_Pos                       SMIF_CORE_CTL_ENABLED_Pos
1138 #define SMIF_DEVICE_CTL_DATA_SEL_Msk               SMIF_CORE_DEVICE_CTL_DATA_SEL_Msk
1139 #define SMIF_CTL_XIP_MODE_Pos                      SMIF_CORE_CTL_XIP_MODE_Pos
1140 #define SMIF_CTL_XIP_MODE_Msk                      SMIF_CORE_CTL_XIP_MODE_Msk
1141 #define SMIF_CTL_BLOCK_Pos                         SMIF_CORE_CTL_BLOCK_Pos
1142 #define SMIF_CTL_BLOCK_Msk                         SMIF_CORE_CTL_BLOCK_Msk
1143 #define SMIF_CTL_CLOCK_IF_SEL_Pos                  SMIF_CORE_CTL_CLOCK_IF_SEL_Pos
1144 #define SMIF_CTL_CLOCK_IF_SEL_Msk                  SMIF_CORE_CTL_CLOCK_IF_SEL_Msk
1145 
1146 #define SMIF_DEVICE_CTL_DATA_SEL_Pos               SMIF_CORE_DEVICE_CTL_DATA_SEL_Pos
1147 #define SMIF_CRYPTO_CMD_START_Pos                  SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Pos
1148 #define SMIF_CRYPTO_CMD_START_Msk                  SMIF_CORE_SMIF_CRYPTO_CRYPTO_CMD_START_Msk
1149 
1150 #define SMIF_CRYPTO_CMD(base)            (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_CMD)
1151 #define SMIF_CRYPTO_ADDR(base)           (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_ADDR)
1152 #define SMIF_CRYPTO_MASK(base)           (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_MASK)
1153 #define SMIF_CRYPTO_SUBREGION(base)      (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_SUBREGION)
1154 #define SMIF_CRYPTO_INPUT0(base)         (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT0)
1155 #define SMIF_CRYPTO_INPUT1(base)         (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT1)
1156 #define SMIF_CRYPTO_INPUT2(base)         (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT2)
1157 #define SMIF_CRYPTO_INPUT3(base)         (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT3)
1158 #define SMIF_CRYPTO_KEY0(base)           (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY0)
1159 #define SMIF_CRYPTO_KEY1(base)           (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY1)
1160 #define SMIF_CRYPTO_KEY2(base)           (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY2)
1161 #define SMIF_CRYPTO_KEY3(base)           (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY3)
1162 #define SMIF_CRYPTO_OUTPUT0(base)        (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT0)
1163 #define SMIF_CRYPTO_OUTPUT1(base)        (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT1)
1164 #define SMIF_CRYPTO_OUTPUT2(base)        (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT2)
1165 #define SMIF_CRYPTO_OUTPUT3(base)        (((SMIF_CORE_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT3)
1166 
1167 #define SMIF_CRYPTO_IDX(base, deviceIndex)                 (((SMIF_CORE_Type *)(base))->SMIF_CRYPTO_BLOCK[deviceIndex])
1168 
1169 #define SMIF_CRYPTO_IDX_CMD(base, deviceIndex)             (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_CMD)
1170 #define SMIF_CRYPTO_IDX_ADDR(base, deviceIndex)            (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_ADDR)
1171 #define SMIF_CRYPTO_IDX_MASK(base, deviceIndex)            (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_MASK)
1172 #define SMIF_CRYPTO_IDX_SUBREGION(base, deviceIndex)       (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_SUBREGION)
1173 #define SMIF_CRYPTO_IDX_INPUT0(base, deviceIndex)          (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT0)
1174 #define SMIF_CRYPTO_IDX_INPUT1(base, deviceIndex)          (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT1)
1175 #define SMIF_CRYPTO_IDX_INPUT2(base, deviceIndex)          (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT2)
1176 #define SMIF_CRYPTO_IDX_INPUT3(base, deviceIndex)          (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT3)
1177 #define SMIF_CRYPTO_IDX_KEY0(base, deviceIndex)            (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY0)
1178 #define SMIF_CRYPTO_IDX_KEY1(base, deviceIndex)            (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY1)
1179 #define SMIF_CRYPTO_IDX_KEY2(base, deviceIndex)            (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY2)
1180 #define SMIF_CRYPTO_IDX_KEY3(base, deviceIndex)            (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY3)
1181 #define SMIF_CRYPTO_IDX_OUTPUT0(base, deviceIndex)         (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT0)
1182 #define SMIF_CRYPTO_IDX_OUTPUT1(base, deviceIndex)         (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT1)
1183 #define SMIF_CRYPTO_IDX_OUTPUT2(base, deviceIndex)         (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT2)
1184 
1185 #define SMIF_BRIDGE_CTL(base)                              ((((SMIF_Base_Type *)base)->SMIF_BRIDGE).CTL)
1186 #define SMIF_REMAPREGION_CTL(base, index)                  (((((SMIF_Base_Type *)base)->SMIF_BRIDGE).SMIF_REMAP_REGION[index]).CTL)
1187 #define SMIF_REMAPREGION_ADDR(base, index)                 (((((SMIF_Base_Type *)base)->SMIF_BRIDGE).SMIF_REMAP_REGION[index]).ADDR)
1188 #define SMIF_REMAPREGION_MASK(base, index)                 (((((SMIF_Base_Type *)base)->SMIF_BRIDGE).SMIF_REMAP_REGION[index]).MASK)
1189 #define SMIF_REMAPREGION_SMIF0_REMAP(base, index)          (((((SMIF_Base_Type *)base)->SMIF_BRIDGE).SMIF_REMAP_REGION[index]).SMIF0_REMAP)
1190 #define SMIF_REMAPREGION_SMIF1_REMAP(base, index)          (((((SMIF_Base_Type *)base)->SMIF_BRIDGE).SMIF_REMAP_REGION[index]).SMIF1_REMAP)
1191 
1192 #define SMIF_DEVICE_CTL(base)               (((SMIF_CORE_DEVICE_Type *)(base))->CTL)
1193 #define SMIF_DEVICE_ADDR(base)              (((SMIF_CORE_DEVICE_Type *)(base))->ADDR)
1194 #define SMIF_DEVICE_ADDR_CTL(base)          (((SMIF_CORE_DEVICE_Type *)(base))->ADDR_CTL)
1195 #define SMIF_DEVICE_MASK(base)              (((SMIF_CORE_DEVICE_Type *)(base))->MASK)
1196 #define SMIF_DEVICE_RD_CMD_CTL(base)        (((SMIF_CORE_DEVICE_Type *)(base))->RD_CMD_CTL)
1197 #define SMIF_DEVICE_RD_ADDR_CTL(base)       (((SMIF_CORE_DEVICE_Type *)(base))->RD_ADDR_CTL)
1198 #define SMIF_DEVICE_RD_MODE_CTL(base)       (((SMIF_CORE_DEVICE_Type *)(base))->RD_MODE_CTL)
1199 #define SMIF_DEVICE_RD_DUMMY_CTL(base)      (((SMIF_CORE_DEVICE_Type *)(base))->RD_DUMMY_CTL)
1200 #define SMIF_DEVICE_RD_DATA_CTL(base)       (((SMIF_CORE_DEVICE_Type *)(base))->RD_DATA_CTL)
1201 #define SMIF_DEVICE_RD_BOUND_CTL(base)      (((SMIF_DEVICE_Type *)(base))->RD_BOUND_CTL)
1202 #define SMIF_DEVICE_WR_CMD_CTL(base)        (((SMIF_CORE_DEVICE_Type *)(base))->WR_CMD_CTL)
1203 #define SMIF_DEVICE_WR_ADDR_CTL(base)       (((SMIF_CORE_DEVICE_Type *)(base))->WR_ADDR_CTL)
1204 #define SMIF_DEVICE_WR_MODE_CTL(base)       (((SMIF_CORE_DEVICE_Type *)(base))->WR_MODE_CTL)
1205 #define SMIF_DEVICE_WR_DUMMY_CTL(base)      (((SMIF_CORE_DEVICE_Type *)(base))->WR_DUMMY_CTL)
1206 #define SMIF_DEVICE_WR_DATA_CTL(base)       (((SMIF_CORE_DEVICE_Type *)(base))->WR_DATA_CTL)
1207 #define SMIF_DEVICE_RX_CAPTURE_CONFIG(base) (((SMIF_CORE_DEVICE_Type *)(base))->RX_CAPTURE_CONFIG)
1208 #define SMIF_DEVICE_HB_FW_DEL_TAP_SEL_0(base) (((SMIF_CORE_DEVICE_Type *)(base))->HB_FW_DEL_TAP_SEL_0)
1209 #define SMIF_DEVICE_HB_FW_DEL_TAP_SEL_1(base) (((SMIF_CORE_DEVICE_Type *)(base))->HB_FW_DEL_TAP_SEL_1)
1210 
1211 
1212 #define SMIF_DEVICE_IDX(base, deviceIndex)                 (((SMIF_CORE_Type *)(base))->DEVICE[deviceIndex])
1213 
1214 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex)             (SMIF_DEVICE_IDX(base, deviceIndex).CTL)
1215 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).ADDR)
1216 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex)        (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL)
1217 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).MASK)
1218 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL)
1219 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL)
1220 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL)
1221 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL)
1222 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL)
1223 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL)
1224 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL)
1225 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL)
1226 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL)
1227 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL)
1228 #define SMIF_DEVICE_IDX_RX_CAPTURE_CONFIG(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RX_CAPTURE_CONFIG)
1229 
1230 #define SMIF_CORE_IDX(base, coreIndex)                     (((SMIF_Type *)(base))->CORE[coreIndex])
1231 
1232 #define SMIF_CTL(base)                            (((SMIF_CORE_Type *)(base))->CTL)
1233 #define SMIF_CTL2(base)                           (((SMIF_CORE_Type *)(base))->CTL2)
1234 #define SMIF_STATUS(base)                         (((SMIF_CORE_Type *)(base))->STATUS)
1235 #if defined (CY_MXSMIF) && (CY_MXSMIF_VERSION <= 2)
1236 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0(base)       (((SMIF_CORE_Type *)(base))->INT_CLOCK_DELAY_TAP_SEL0)
1237 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1(base)       (((SMIF_CORE_Type *)(base))->INT_CLOCK_DELAY_TAP_SEL1)
1238 #endif
1239 #if defined (SMIF_DLP_PRESENT) && (SMIF_DLP_PRESENT > 0)
1240 #define SMIF_DLP_DELAY_TAP_SEL0(base)             (((SMIF_CORE_Type *)(base))->DLP_DELAY_TAP_SEL0)
1241 #define SMIF_DLP_DELAY_TAP_SEL1(base)             (((SMIF_CORE_Type *)(base))->DLP_DELAY_TAP_SEL1)
1242 #define SMIF_DLP_CTL(base)                        (((SMIF_CORE_Type *)(base))->DLP_CTL)
1243 #define SMIF_DL_STATUS0(base)                     (((SMIF_CORE_Type *)(base))->DL_STATUS0)
1244 #define SMIF_DL_STATUS1(base)                     (((SMIF_CORE_Type *)(base))->DL_STATUS1)
1245 #endif
1246 #define SMIF_TX_CMD_FIFO_STATUS(base)             (((SMIF_CORE_Type *)(base))->TX_CMD_FIFO_STATUS)
1247 #define SMIF_TX_CMD_MMIO_FIFO_STATUS(base)        (((SMIF_CORE_Type *)(base))->TX_CMD_MMIO_FIFO_STATUS)
1248 #define SMIF_TX_CMD_MMIO_FIFO_WR(base)            (((SMIF_CORE_Type *)(base))->TX_CMD_MMIO_FIFO_WR)
1249 #define SMIF_TX_DATA_MMIO_FIFO_CTL(base)          (((SMIF_CORE_Type *)(base))->TX_DATA_MMIO_FIFO_CTL)
1250 #define SMIF_TX_DATA_FIFO_STATUS(base)            (((SMIF_CORE_Type *)(base))->TX_DATA_FIFO_STATUS)
1251 #define SMIF_TX_DATA_MMIO_FIFO_STATUS(base)       (((SMIF_CORE_Type *)(base))->TX_DATA_MMIO_FIFO_STATUS)
1252 #define SMIF_TX_DATA_MMIO_FIFO_WR1(base)          (((SMIF_CORE_Type *)(base))->TX_DATA_MMIO_FIFO_WR1)
1253 #define SMIF_TX_DATA_MMIO_FIFO_WR2(base)          (((SMIF_CORE_Type *)(base))->TX_DATA_MMIO_FIFO_WR2)
1254 #define SMIF_TX_DATA_MMIO_FIFO_WR4(base)          (((SMIF_CORE_Type *)(base))->TX_DATA_MMIO_FIFO_WR4)
1255 #define SMIF_TX_DATA_MMIO_FIFO_WR1ODD(base)       (((SMIF_CORE_Type *)(base))->TX_DATA_MMIO_FIFO_WR1ODD)
1256 #define SMIF_RX_DATA_MMIO_FIFO_CTL(base)          (((SMIF_CORE_Type *)(base))->RX_DATA_MMIO_FIFO_CTL)
1257 #define SMIF_RX_DATA_MMIO_FIFO_STATUS(base)       (((SMIF_CORE_Type *)(base))->RX_DATA_MMIO_FIFO_STATUS)
1258 #define SMIF_RX_DATA_FIFO_STATUS(base)            (((SMIF_CORE_Type *)(base))->RX_DATA_FIFO_STATUS)
1259 #define SMIF_RX_DATA_MMIO_FIFO_RD1(base)          (((SMIF_CORE_Type *)(base))->RX_DATA_MMIO_FIFO_RD1)
1260 #define SMIF_RX_DATA_MMIO_FIFO_RD2(base)          (((SMIF_CORE_Type *)(base))->RX_DATA_MMIO_FIFO_RD2)
1261 #define SMIF_RX_DATA_MMIO_FIFO_RD4(base)          (((SMIF_CORE_Type *)(base))->RX_DATA_MMIO_FIFO_RD4)
1262 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT(base)   (((SMIF_CORE_Type *)(base))->RX_DATA_MMIO_FIFO_RD1_SILENT)
1263 #if defined (SMIF_SLOW_CACHE_PRESENT)
1264 #define SMIF_SLOW_CA_CTL(base)                    (((SMIF_CORE_Type *)(base))->SLOW_CA_CTL)
1265 #define SMIF_SLOW_CA_CMD(base)                    (((SMIF_CORE_Type *)(base))->SLOW_CA_CMD)
1266 #endif
1267 #if defined (SMIF_FAST_CACHE_PRESENT)
1268 #define SMIF_FAST_CA_CTL(base)                    (((SMIF_CORE_Type *)(base))->FAST_CA_CTL)
1269 #define SMIF_FAST_CA_CMD(base)                    (((SMIF_CORE_Type *)(base))->FAST_CA_CMD)
1270 #endif
1271 #if defined (SMIF_BUS_CRC_PRESENT)
1272 #define SMIF_CRC_CMD(base)                        (((SMIF_CORE_Type *)(base))->CRC_CMD)
1273 #define SMIF_CRC_INPUT0(base)                     (((SMIF_CORE_Type *)(base))->CRC_INPUT0)
1274 #define SMIF_CRC_INPUT1(base)                     (((SMIF_CORE_Type *)(base))->CRC_INPUT1)
1275 #define SMIF_CRC_OUTPUT(base)                     (((SMIF_CORE_Type *)(base))->CRC_OUTPUT)
1276 #endif
1277 #define SMIF_INTR(base)                           (((SMIF_CORE_Type *)(base))->INTR)
1278 #define SMIF_INTR_SET(base)                       (((SMIF_CORE_Type *)(base))->INTR_SET)
1279 #define SMIF_INTR_MASK(base)                      (((SMIF_CORE_Type *)(base))->INTR_MASK)
1280 #define SMIF_INTR_MASKED(base)                    (((SMIF_CORE_Type *)(base))->INTR_MASKED)
1281 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
1282 #define SMIF_CLK_HSIOM(base)                      (((SMIF_CORE_Type *)(base))->SMIF_HSIOM.SMIF_PRT[1].PORT_SEL0)
1283 #define SMIF_RWDS_HSIOM(base)                     (((SMIF_CORE_Type *)(base))->SMIF_HSIOM.SMIF_PRT[2].PORT_SEL0)
1284 #define SMIF_CLK_DRIVEMODE(base)                  (((SMIF_CORE_Type *)(base))->SMIF_GPIO.SMIF_PRT[1].CFG)
1285 #define SMIF_RWDS_DRIVEMODE(base)                 (((SMIF_CORE_Type *)(base))->SMIF_GPIO.SMIF_PRT[2].CFG)
1286 #define SMIF_CLK_DRIVE_STRENGTH(base)             (((SMIF_CORE_Type *)(base))->SMIF_GPIO.SMIF_PRT[1].CFG_DRIVE_EXT0)
1287 #define SMIF_RWDS_DRIVE_STRENGTH(base)            (((SMIF_CORE_Type *)(base))->SMIF_GPIO.SMIF_PRT[2].CFG_DRIVE_EXT0)
1288 #define SMIF_IDAC(base)                           (((SMIF_CORE_Type *)(base))->DLL_IDAC)
1289 #endif
1290 
1291 /* Backward Compatibility - Default SMIF instance pointing to CORE0 */
1292 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 4)
1293 #define SMIF_HW SMIF0_CORE0
1294 #define SMIF_config SMIF_0_CORE_0_config
1295 #endif
1296 
1297 #if !defined (SMIF_DELAY_TAPS_NR)
1298 #define SMIF_DELAY_TAPS_NR 32u
1299 
1300 #define SMIF_CORE0_SS0_PORT           (GPIO_PRT5)
1301 #define SMIF_CORE0_SS0_PIN            (0U)
1302 #define SMIF_CORE0_SS1_PORT           (GPIO_PRT2)
1303 #define SMIF_CORE0_SS1_PIN            (0U)
1304 #define SMIF_CORE0_SS2_PORT           (GPIO_PRT6)
1305 #define SMIF_CORE0_SS2_PIN            (7U)
1306 #define SMIF_CORE0_SS3_PORT           (GPIO_PRT7)
1307 #define SMIF_CORE0_SS3_PIN            (0U)
1308 
1309 #define SMIF_CORE1_SS0_PORT           (GPIO_PRT21)
1310 #define SMIF_CORE1_SS0_PIN            (0U)
1311 #define SMIF_CORE1_SS1_PORT           (GPIO_PRT0)
1312 #define SMIF_CORE1_SS1_PIN            (0U)
1313 #define SMIF_CORE1_SS2_PORT           (GPIO_PRT0)
1314 #define SMIF_CORE1_SS2_PIN            (1U)
1315 #define SMIF_CORE1_SS3_PORT           (GPIO_PRT12)
1316 #define SMIF_CORE1_SS3_PIN            (3U)
1317 
1318 #define SMIF_CORE0_SS_PORT(slaveSelectId)       ((slaveSelectId == CY_SMIF_SLAVE_SELECT_0) ? SMIF_CORE0_SS0_PORT : \
1319                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_1) ? SMIF_CORE0_SS1_PORT : \
1320                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_2) ? SMIF_CORE0_SS2_PORT : SMIF_CORE0_SS3_PORT)))
1321 #define SMIF_CORE1_SS_PORT(slaveSelectId)       ((slaveSelectId == CY_SMIF_SLAVE_SELECT_0) ? SMIF_CORE1_SS0_PORT : \
1322                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_1) ? SMIF_CORE1_SS1_PORT : \
1323                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_2) ? SMIF_CORE1_SS2_PORT : SMIF_CORE1_SS3_PORT)))
1324 
1325 #define SMIF_CORE0_SS_PIN(slaveSelectId)        ((slaveSelectId == CY_SMIF_SLAVE_SELECT_0) ? SMIF_CORE0_SS0_PIN : \
1326                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_1) ? SMIF_CORE0_SS1_PIN : \
1327                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_2) ? SMIF_CORE0_SS2_PIN : SMIF_CORE0_SS2_PIN)))
1328 #define SMIF_CORE1_SS_PIN(slaveSelectId)        ((slaveSelectId == CY_SMIF_SLAVE_SELECT_0) ? SMIF_CORE1_SS0_PIN : \
1329                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_1) ? SMIF_CORE1_SS1_PIN : \
1330                                                 ((slaveSelectId == CY_SMIF_SLAVE_SELECT_2) ? SMIF_CORE1_SS2_PIN : SMIF_CORE1_SS3_PIN)))
1331 
1332 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION == 5)
1333 #define SMIF_SS_PORT(base, salveIndex)  (((base) == SMIF0_CORE0) ? (SMIF_CORE0_SS_PORT((salveIndex))) : (SMIF_CORE1_SS_PORT((salveIndex))))
1334 #define SMIF_SS_PIN(base, salveIndex)   (((base) == SMIF0_CORE0) ? (SMIF_CORE0_SS_PIN((salveIndex))) : (SMIF_CORE1_SS_PIN((salveIndex))))
1335 #define SMIF_DQ0_PORT(base)             (((base) == SMIF0_CORE0) ? ((void *)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0) : ((void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0))
1336 #endif
1337 
1338 #endif /* !defined (SMIF_DELAY_TAPS_NR) */
1339 
1340 #else
1341 /* For other cat1c devices with MXSMIF_VERSION == 2 */
1342 
1343 /* Feature Flags - Start
1344  * Few products have very less memory available in BOOT ROM and they do not require
1345  * SFDP enumeration of Octal parts. Hence, we introduce feature flags to enable
1346  * specific features only where Octal SFDP enumeration and Hyperbus devices are supported
1347  * using below feature flags
1348  */
1349 #define SMIF_OCTAL_SFDP_SUPPORT
1350 #define SMIF_HYPERBUS_DEVICE_SUPPORT
1351 /* Feature Flags - End */
1352 
1353 #define SMIF_DEVICE_CTL(base)               (((SMIF_DEVICE_Type *)(base))->CTL)
1354 #define SMIF_DEVICE_ADDR(base)              (((SMIF_DEVICE_Type *)(base))->ADDR)
1355 #define SMIF_DEVICE_ADDR_CTL(base)          (((SMIF_DEVICE_Type *)(base))->ADDR_CTL)
1356 #define SMIF_DEVICE_MASK(base)              (((SMIF_DEVICE_Type *)(base))->MASK)
1357 #define SMIF_DEVICE_RD_CMD_CTL(base)        (((SMIF_DEVICE_Type *)(base))->RD_CMD_CTL)
1358 #define SMIF_DEVICE_RD_ADDR_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_ADDR_CTL)
1359 #define SMIF_DEVICE_RD_MODE_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_MODE_CTL)
1360 #define SMIF_DEVICE_RD_DUMMY_CTL(base)      (((SMIF_DEVICE_Type *)(base))->RD_DUMMY_CTL)
1361 #define SMIF_DEVICE_RD_DATA_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_DATA_CTL)
1362 #define SMIF_DEVICE_RD_BOUND_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_BOUND_CTL)
1363 #define SMIF_DEVICE_WR_CMD_CTL(base)        (((SMIF_DEVICE_Type *)(base))->WR_CMD_CTL)
1364 #define SMIF_DEVICE_WR_ADDR_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_ADDR_CTL)
1365 #define SMIF_DEVICE_WR_MODE_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_MODE_CTL)
1366 #define SMIF_DEVICE_WR_DUMMY_CTL(base)      (((SMIF_DEVICE_Type *)(base))->WR_DUMMY_CTL)
1367 #define SMIF_DEVICE_WR_DATA_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_DATA_CTL)
1368 
1369 #define SMIF_DEVICE_IDX(base, deviceIndex)                 (((SMIF_Type *)(base))->DEVICE[deviceIndex])
1370 
1371 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex)             (SMIF_DEVICE_IDX(base, deviceIndex).CTL)
1372 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).ADDR)
1373 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex)        (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL)
1374 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).MASK)
1375 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL)
1376 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL)
1377 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL)
1378 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL)
1379 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL)
1380 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL)
1381 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL)
1382 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL)
1383 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL)
1384 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL)
1385 
1386 #define SMIF_CTL(base)                      (((SMIF_Type *)(base))->CTL)
1387 #define SMIF_DELAY_TAP_SEL(base)            (((SMIF_Type *)(base))->DELAY_TAP_SEL)
1388 #define SMIF_STATUS(base)                   (((SMIF_Type *)(base))->STATUS)
1389 #define SMIF_TX_DATA_FIFO_CTL(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_CTL)
1390 #define SMIF_RX_DATA_MMIO_FIFO_CTL(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_CTL)
1391 #define SMIF_TX_DATA_FIFO_WR1(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_WR1)
1392 #define SMIF_TX_DATA_FIFO_WR2(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_WR2)
1393 #define SMIF_TX_DATA_FIFO_WR4(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_WR4)
1394 #define SMIF_TX_DATA_FIFO_WR1ODD(base)      (((SMIF_Type *)(base))->TX_DATA_FIFO_WR1ODD)
1395 #define SMIF_RX_DATA_FIFO_STATUS(base)        (((SMIF_Type *)(base))->RX_DATA_FIFO_STATUS)
1396 #define SMIF_RX_DATA_MMIO_FIFO_STATUS(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_STATUS)
1397 #define SMIF_RX_DATA_MMIO_FIFO_RD1(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1)
1398 #define SMIF_RX_DATA_MMIO_FIFO_RD2(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD2)
1399 #define SMIF_RX_DATA_MMIO_FIFO_RD4(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD4)
1400 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1_SILENT)
1401 #define SMIF_TX_CMD_FIFO_WR(base)           (((SMIF_Type *)(base))->TX_CMD_FIFO_WR)
1402 #define SMIF_TX_CMD_FIFO_STATUS(base)       (((SMIF_Type *)(base))->TX_CMD_FIFO_STATUS)
1403 #define SMIF_TX_DATA_FIFO_STATUS(base)      (((SMIF_Type *)(base))->TX_DATA_FIFO_STATUS)
1404 #define SMIF_INTR(base)                     (((SMIF_Type *)(base))->INTR)
1405 #define SMIF_INTR_SET(base)                 (((SMIF_Type *)(base))->INTR_SET)
1406 #define SMIF_INTR_MASK(base)                (((SMIF_Type *)(base))->INTR_MASK)
1407 #define SMIF_INTR_MASKED(base)              (((SMIF_Type *)(base))->INTR_MASKED)
1408 #define SMIF_CRYPTO_INPUT0(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT0)
1409 #define SMIF_CRYPTO_INPUT1(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT1)
1410 #define SMIF_CRYPTO_INPUT2(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT2)
1411 #define SMIF_CRYPTO_INPUT3(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT3)
1412 #define SMIF_CRYPTO_KEY0(base)              (((SMIF_Type *)(base))->CRYPTO_KEY0)
1413 #define SMIF_CRYPTO_KEY1(base)              (((SMIF_Type *)(base))->CRYPTO_KEY1)
1414 #define SMIF_CRYPTO_KEY2(base)              (((SMIF_Type *)(base))->CRYPTO_KEY2)
1415 #define SMIF_CRYPTO_KEY3(base)              (((SMIF_Type *)(base))->CRYPTO_KEY3)
1416 #define SMIF_CRYPTO_OUTPUT0(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT0)
1417 #define SMIF_CRYPTO_OUTPUT1(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT1)
1418 #define SMIF_CRYPTO_OUTPUT2(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT2)
1419 #define SMIF_CRYPTO_OUTPUT3(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT3)
1420 #define SMIF_CRYPTO_CMD(base)               (((SMIF_Type *)(base))->CRYPTO_CMD)
1421 #define SMIF_SLOW_CA_CTL(base)              (((SMIF_Type *)(base))->SLOW_CA_CTL)
1422 #define SMIF_FAST_CA_CTL(base)              (((SMIF_Type *)(base))->FAST_CA_CTL)
1423 #define SMIF_SLOW_CA_CMD(base)              (((SMIF_Type *)(base))->SLOW_CA_CMD)
1424 #define SMIF_FAST_CA_CMD(base)              (((SMIF_Type *)(base))->FAST_CA_CMD)
1425 
1426 #endif /* MXSMIF_VERSION */
1427 
1428 /* CY_XIP_BASE remaps the native XIP Base address definitions below
1429    in order to match the API of other devices. */
1430 #if defined(CY_IP_MXSMIF_VERSION) && (CY_IP_MXSMIF_VERSION >= 4)
1431 #define CY_XIP_BASE    CY_SMIF_PORT0_BASE
1432 #else
1433 #define CY_XIP_BASE    CY_SMIF_XIP_BASE
1434 #endif
1435 
1436 /*******************************************************************************
1437 *                DW
1438 *******************************************************************************/
1439 
1440 #define CY_DW                               (0UL)
1441 #define CY_DW_CRC                           (1UL)
1442 #define CY_DW0_BASE                         DW0
1443 #define CY_DW1_BASE                         DW1
1444 #define CY_DW0_CH_NR                        CPUSS_DW0_CH_NR
1445 #define CY_DW1_CH_NR                        CPUSS_DW1_CH_NR
1446 
1447 #define CY_DW_CH_CTL_PRIO_Pos               ((uint32_t)(DW_CH_STRUCT_CH_CTL_PRIO_Pos))
1448 #define CY_DW_CH_CTL_PRIO_Msk               ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos))
1449 #define CY_DW_CH_CTL_PREEMPTABLE_Pos        ((uint32_t)(DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos))
1450 #define CY_DW_CH_CTL_PREEMPTABLE_Msk        ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos))
1451 #define CY_DW_STATUS_CH_IDX_Pos             ((uint32_t)(DW_STATUS_CH_IDX_Pos))
1452 #define CY_DW_STATUS_CH_IDX_Msk             (DW_STATUS_CH_IDX_Msk)
1453 
1454 #define DW_CTL(base)                        (((DW_Type*)(base))->CTL)
1455 #define DW_STATUS(base)                     (((DW_Type const*)(base))->STATUS)
1456 #define DW_DESCR_SRC(base)                  (((DW_Type*)(base))->ACT_DESCR_SRC)
1457 #define DW_DESCR_DST(base)                  (((DW_Type*)(base))->ACT_DESCR_DST)
1458 
1459 #define DW_CRC_CTL(base)                    (((DW_Type*)(base))->CRC_CTL)
1460 #define DW_CRC_DATA_CTL(base)               (((DW_Type*)(base))->CRC_DATA_CTL)
1461 #define DW_CRC_REM_CTL(base)                (((DW_Type*)(base))->CRC_REM_CTL)
1462 #define DW_CRC_POL_CTL(base)                (((DW_Type*)(base))->CRC_POL_CTL)
1463 #define DW_CRC_LFSR_CTL(base)               (((DW_Type*)(base))->CRC_LFSR_CTL)
1464 
1465 #define DW_CH_OFFSET                        (uint32_t)(offsetof(DW_Type, CH_STRUCT))
1466 #define DW_CH_SIZE                            (uint32_t)(sizeof(DW_CH_STRUCT_Type))
1467 
1468 #define DW_CH(base, chan)                    ((DW_CH_STRUCT_Type*)((uint32_t)(base) + DW_CH_OFFSET + (chan * DW_CH_SIZE)))
1469 #define DW_CH_CTL(base, chan)               (DW_CH((base), (chan))->CH_CTL)
1470 #define DW_CH_STATUS(base, chan)            (DW_CH((base), (chan))->CH_STATUS)
1471 #define DW_CH_IDX(base, chan)               (DW_CH((base), (chan))->CH_IDX)
1472 #define DW_CH_CURR_PTR(base, chan)          (DW_CH((base), (chan))->CH_CURR_PTR)
1473 
1474 #define DW_CH_INTR(base, chan)              (DW_CH((base), (chan))->INTR)
1475 #define DW_CH_INTR_SET(base, chan)          (DW_CH((base), (chan))->INTR_SET)
1476 #define DW_CH_INTR_MASK(base, chan)         (DW_CH((base), (chan))->INTR_MASK)
1477 #define DW_CH_INTR_MASKED(base, chan)       (DW_CH((base), (chan))->INTR_MASKED)
1478 #define DW_CH_TR_CMD(base, chan)            (DW_CH((base), (chan))->TR_CMD)
1479 
1480 #define DW_V2_CRC_CTL_DATA_REVERSE_Msk DW_CRC_CTL_DATA_REVERSE_Msk
1481 #define DW_V2_CRC_CTL_REM_REVERSE_Msk DW_CRC_CTL_REM_REVERSE_Msk
1482 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Msk DW_CRC_DATA_CTL_DATA_XOR_Msk
1483 #define DW_V2_CRC_REM_CTL_REM_XOR_Msk DW_CRC_REM_CTL_REM_XOR_Msk
1484 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk DW_CRC_POL_CTL_POLYNOMIAL_Msk
1485 #define DW_V2_CRC_LFSR_CTL_LFSR32_Msk DW_CRC_LFSR_CTL_LFSR32_Msk
1486 #define DW_V2_CRC_CTL_DATA_REVERSE_Pos DW_CRC_CTL_DATA_REVERSE_Pos
1487 #define DW_V2_CRC_CTL_REM_REVERSE_Pos DW_CRC_CTL_REM_REVERSE_Pos
1488 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Pos DW_CRC_DATA_CTL_DATA_XOR_Pos
1489 #define DW_V2_CRC_REM_CTL_REM_XOR_Pos DW_CRC_REM_CTL_REM_XOR_Pos
1490 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos DW_CRC_POL_CTL_POLYNOMIAL_Pos
1491 #define DW_V2_CRC_LFSR_CTL_LFSR32_Pos DW_CRC_LFSR_CTL_LFSR32_Pos
1492 
1493 
1494 /*******************************************************************************
1495 *                DMAC
1496 *******************************************************************************/
1497 
1498 #define CY_DMAC_CH_NR                       CPUSS_DMAC_CH_NR
1499 #define DMAC_CTL(base)                      (((DMAC_Type*)(base))->CTL)
1500 #define DMAC_ACTIVE(base)                   (((DMAC_Type const*)(base))->ACTIVE)
1501 #define DMAC_CH(base, chan)                 (&(((DMAC_Type*)(base))->CH[(chan)]))
1502 #define DMAC_CH_CTL(base, chan)             (DMAC_CH(base, chan)->CTL)
1503 #define DMAC_CH_IDX(base, chan)             (DMAC_CH(base, chan)->IDX)
1504 #define DMAC_CH_CURR(base, chan)            (DMAC_CH(base, chan)->CURR)
1505 #define DMAC_CH_DESCR_SRC(base, chan)       (DMAC_CH(base, chan)->DESCR_SRC)
1506 #define DMAC_CH_DESCR_DST(base, chan)       (DMAC_CH(base, chan)->DESCR_DST)
1507 #define DMAC_CH_INTR(base, chan)            (DMAC_CH(base, chan)->INTR)
1508 #define DMAC_CH_INTR_SET(base, chan)        (DMAC_CH(base, chan)->INTR_SET)
1509 #define DMAC_CH_INTR_MASK(base, chan)       (DMAC_CH(base, chan)->INTR_MASK)
1510 #define DMAC_CH_INTR_MASKED(base, chan)     (DMAC_CH(base, chan)->INTR_MASKED)
1511 
1512 #define DMAC_CH_V2_INTR_COMPLETION_Msk DMAC_CH_INTR_COMPLETION_Msk
1513 #define DMAC_CH_V2_INTR_COMPLETION_Pos DMAC_CH_INTR_COMPLETION_Pos
1514 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk DMAC_CH_INTR_SRC_BUS_ERROR_Msk
1515 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos DMAC_CH_INTR_SRC_BUS_ERROR_Pos
1516 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk DMAC_CH_INTR_DST_BUS_ERROR_Msk
1517 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos DMAC_CH_INTR_DST_BUS_ERROR_Pos
1518 #define DMAC_CH_V2_INTR_SRC_MISAL_Msk DMAC_CH_INTR_SRC_MISAL_Msk
1519 #define DMAC_CH_V2_INTR_SRC_MISAL_Pos DMAC_CH_INTR_SRC_MISAL_Pos
1520 #define DMAC_CH_V2_INTR_DST_MISAL_Msk DMAC_CH_INTR_DST_MISAL_Msk
1521 #define DMAC_CH_V2_INTR_DST_MISAL_Pos DMAC_CH_INTR_DST_MISAL_Pos
1522 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk DMAC_CH_INTR_CURR_PTR_NULL_Msk
1523 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos DMAC_CH_INTR_CURR_PTR_NULL_Pos
1524 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk
1525 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos DMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos
1526 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk DMAC_CH_INTR_DESCR_BUS_ERROR_Msk
1527 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos DMAC_CH_INTR_DESCR_BUS_ERROR_Pos
1528 #define DMAC_V2_CTL_ENABLED_Msk DMAC_CTL_ENABLED_Msk
1529 #define DMAC_V2_CTL_ENABLED_Pos DMAC_CTL_ENABLED_Pos
1530 #define DMAC_V2_ACTIVE_ACTIVE_Msk DMAC_ACTIVE_ACTIVE_Msk
1531 #define DMAC_V2_ACTIVE_ACTIVE_Pos DMAC_ACTIVE_ACTIVE_Pos
1532 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk DMAC_CH_DESCR_CTL_INTR_TYPE_Msk
1533 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos DMAC_CH_DESCR_CTL_INTR_TYPE_Pos
1534 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk
1535 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos DMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos
1536 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk
1537 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos
1538 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk DMAC_CH_DESCR_CTL_DATA_SIZE_Msk
1539 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos DMAC_CH_DESCR_CTL_DATA_SIZE_Pos
1540 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Msk
1541 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Pos
1542 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Msk
1543 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Pos
1544 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk
1545 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos
1546 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk DMAC_CH_DESCR_CTL_DESCR_TYPE_Msk
1547 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos DMAC_CH_DESCR_CTL_DESCR_TYPE_Pos
1548 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk DMAC_CH_DESCR_CTL_CH_DISABLE_Msk
1549 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos DMAC_CH_DESCR_CTL_CH_DISABLE_Pos
1550 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk DMAC_CH_DESCR_X_INCR_SRC_X_Msk
1551 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos DMAC_CH_DESCR_X_INCR_SRC_X_Pos
1552 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk DMAC_CH_DESCR_X_INCR_DST_X_Msk
1553 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos DMAC_CH_DESCR_X_INCR_DST_X_Pos
1554 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk
1555 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos
1556 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk DMAC_CH_DESCR_Y_INCR_SRC_Y_Msk
1557 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos DMAC_CH_DESCR_Y_INCR_SRC_Y_Pos
1558 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk DMAC_CH_DESCR_Y_INCR_DST_Y_Msk
1559 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos DMAC_CH_DESCR_Y_INCR_DST_Y_Pos
1560 #define DMAC_CH_V2_CTL_ENABLED_Msk DMAC_CH_CTL_ENABLED_Msk
1561 #define DMAC_CH_V2_CTL_ENABLED_Pos DMAC_CH_CTL_ENABLED_Pos
1562 #define DMAC_CH_V2_CTL_PRIO_Msk DMAC_CH_CTL_PRIO_Msk
1563 #define DMAC_CH_V2_CTL_PRIO_Pos DMAC_CH_CTL_PRIO_Pos
1564 #define DMAC_CH_V2_IDX_X_Msk DMAC_CH_IDX_X_Msk
1565 #define DMAC_CH_V2_IDX_X_Pos DMAC_CH_IDX_X_Pos
1566 #define DMAC_CH_V2_IDX_Y_Msk DMAC_CH_IDX_Y_Msk
1567 #define DMAC_CH_V2_IDX_Y_Pos DMAC_CH_IDX_Y_Pos
1568 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk DMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk
1569 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos DMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos
1570 #define DMAC_CH_V2_CTL_B_Msk DMAC_CH_CTL_B_Msk
1571 #define DMAC_CH_V2_CTL_B_Pos DMAC_CH_CTL_B_Pos
1572 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk DMAC_CH_DESCR_X_SIZE_X_COUNT_Msk
1573 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos DMAC_CH_DESCR_X_SIZE_X_COUNT_Pos
1574 
1575 /*******************************************************************************
1576 *                AXIDMAC
1577 *******************************************************************************/
1578 #if defined (CY_IP_MXAXIDMAC)
1579 #define CY_AXIDMAC_CH_NR                    (AXI_DMAC_CH_NR)
1580 #define AXIDMAC_CTL(base)                   (((AXI_DMAC_Type*)(base))->CTL)
1581 #define AXIDMAC_STATUS(base)                (((AXI_DMAC_Type*)(base))->STATUS)
1582 #define AXIDMAC_ACTIVE_SEC(base)            (((AXI_DMAC_Type const*)(base))->ACTIVE_SEC)
1583 #define AXIDMAC_ACTIVE_NONSEC(base)         (((AXI_DMAC_Type const*)(base))->ACTIVE_NONSEC)
1584 #define AXIDMAC_CH(base, chan)              (&(((AXI_DMAC_Type*)(base))->CH[(chan)]))
1585 #define AXIDMAC_CH_CTL(base, chan)          (AXIDMAC_CH(base, chan)->CTL)
1586 #define AXIDMAC_CH_IDX(base, chan)          (AXIDMAC_CH(base, chan)->IDX)
1587 #define AXIDMAC_CH_CURR(base, chan)         (AXIDMAC_CH(base, chan)->CURR)
1588 #define AXIDMAC_CH_DESCR_SRC(base, chan)    (AXIDMAC_CH(base, chan)->DESCR_SRC)
1589 #define AXIDMAC_CH_DESCR_DST(base, chan)    (AXIDMAC_CH(base, chan)->DESCR_DST)
1590 #define AXIDMAC_CH_INTR(base, chan)         (AXIDMAC_CH(base, chan)->INTR)
1591 #define AXIDMAC_CH_INTR_SET(base, chan)     (AXIDMAC_CH(base, chan)->INTR_SET)
1592 #define AXIDMAC_CH_INTR_MASK(base, chan)    (AXIDMAC_CH(base, chan)->INTR_MASK)
1593 #define AXIDMAC_CH_INTR_MASKED(base, chan)  (AXIDMAC_CH(base, chan)->INTR_MASKED)
1594 #define AXIDMAC_CH_TR_CMD(base, chan)       (AXIDMAC_CH(base, chan)->TR_CMD)
1595 #endif /* CY_IP_MXAXIDMAC */
1596 
1597 /*******************************************************************************
1598 *                PERI
1599 *******************************************************************************/
1600 /*******************************************************************************
1601 *                PERI PCLK
1602 *******************************************************************************/
1603 
1604 #define PERI_INSTANCE_COUNT                    (1U)
1605 
1606 #ifndef PERI0_PCLK_GROUP_NR
1607 #define PERI0_PCLK_GROUP_NR     PERI_PCLK_GROUP_NR
1608 #endif
1609 
1610 #ifndef PERI1_PCLK_GROUP_NR
1611 #define PERI1_PCLK_GROUP_NR     (0U)
1612 #endif
1613 
1614 
1615 #ifndef PERI_PCLK0_BASE
1616 #define PERI_PCLK0_BASE     PERI_PCLK_BASE
1617 #endif
1618 
1619 #ifndef PERI_PCLK1_BASE
1620 #define PERI_PCLK1_BASE     0U
1621 #endif
1622 
1623 #if (PERI_INSTANCE_COUNT == 1U)
1624 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
1625 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
1626 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0U
1627 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0U
1628 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0U
1629 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0U
1630 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0U
1631 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1632 
1633 
1634 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
1635 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
1636 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0U
1637 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0U
1638 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0U
1639 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0U
1640 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0U
1641 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1642 
1643 
1644 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT
1645 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT
1646 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0U
1647 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 0U
1648 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0U
1649 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0U
1650 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0U
1651 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1652 
1653 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT
1654 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
1655 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0U
1656 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0U
1657 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0U
1658 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0U
1659 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0U
1660 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1661 
1662 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 0U
1663 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 0U
1664 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0U
1665 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0U
1666 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0U
1667 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0U
1668 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0U
1669 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1670 
1671 
1672 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 0U
1673 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 0U
1674 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0U
1675 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0U
1676 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0U
1677 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0U
1678 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0U
1679 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1680 
1681 
1682 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0U
1683 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0U
1684 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0U
1685 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 0U
1686 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0U
1687 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0U
1688 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0U
1689 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1690 
1691 
1692 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 0U
1693 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 0U
1694 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0U
1695 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0U
1696 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0U
1697 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0U
1698 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0U
1699 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1700 
1701 #endif
1702 
1703 #define PERI_PCLK_PERI_NUM_Msk                 (0x000000FFU)
1704 #define PERI_PCLK_GR_NUM_Msk                   (0x0000FF00U)
1705 #define PERI_PCLK_GR_NUM_Pos                   (8U)
1706 #define PERI_PCLK_PERIPHERAL_GROUP_NUM         (1UL << PERI_PCLK_GR_NUM_Pos)
1707 #define PERI_PCLK_INST_NUM_Msk                 (0x00FF0000U)
1708 #define PERI_PCLK_INST_NUM_Pos                 (16U)
1709 
1710 #define PERI_PCLK_GR_NUM(instNum)              (((instNum) == 0U)? PERI0_PCLK_GROUP_NR : PERI1_PCLK_GROUP_NR)
1711 
1712 #define PERI_PCLK1_OFFSET                      (PERI_PCLK1_BASE - PERI_PCLK0_BASE)
1713 #define PERI_PCLK_REG_BASE(instNum)            ((PERI_PCLK_Type*)(PERI_PCLK0_BASE + ((instNum) * PERI_PCLK1_OFFSET)))
1714 
1715 #define PERI_DIV_8_CTL(instNum, grNum, divNum)                   ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_8_CTL[divNum]
1716 #define PERI_DIV_16_CTL(instNum, grNum, divNum)                  ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_CTL[divNum]
1717 #define PERI_DIV_16_5_CTL(instNum, grNum, divNum)                ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_5_CTL[divNum]
1718 #define PERI_DIV_24_5_CTL(instNum, grNum, divNum)                ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_24_5_CTL[divNum]
1719 #define PERI_CLOCK_CTL(instNum, grNum, periNum)                  ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL[periNum]
1720 #define PERI_DIV_CMD(instNum, grNum)                             ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_CMD
1721 
1722 #define PERI_PCLK_GR_DIV_8_NR(instNum, grNum)     (((instNum) == 0U) ? \
1723                                                   (((grNum) <= 3U) ? \
1724                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) |      \
1725                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U)         |    \
1726                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U)        |    \
1727                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1728                                                   : \
1729                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) |        \
1730                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U)    |    \
1731                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U)   |    \
1732                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1733                                                   : \
1734                                                   (((grNum) <= 3U) ? \
1735                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) |      \
1736                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U)          |    \
1737                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U)         |    \
1738                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1739                                                   : \
1740                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) |         \
1741                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U)    |    \
1742                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U)   |    \
1743                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1744 
1745 #define PERI_PCLK_GR_DIV_16_NR(instNum, grNum)    (((instNum) == 0U) ? \
1746                                                   (((grNum) <= 3U) ? \
1747                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |      \
1748                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U)         |    \
1749                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U)        |    \
1750                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1751                                                   : \
1752                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) |         \
1753                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U)    |    \
1754                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U)   |    \
1755                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1756                                                   : \
1757                                                   (((grNum) <= 3U) ? \
1758                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |       \
1759                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U)          |    \
1760                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U)         |    \
1761                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1762                                                   : \
1763                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) |         \
1764                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U)    |    \
1765                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U)   |    \
1766                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1767 
1768 #define PERI_PCLK_GR_DIV_16_5_NR(instNum, grNum)  (((instNum) == 0U) ? \
1769                                                   (((grNum) <= 3U) ? \
1770                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) |          \
1771                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U)    |    \
1772                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U)    |    \
1773                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1774                                                   : \
1775                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) |         \
1776                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U)    |    \
1777                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U)   |    \
1778                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1779                                                   : \
1780                                                   (((grNum) <= 3U) ? \
1781                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) |       \
1782                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U)          |    \
1783                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U)         |    \
1784                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1785                                                   : \
1786                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) |         \
1787                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U)    |    \
1788                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U)   |    \
1789                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1790 
1791 #define PERI_PCLK_GR_DIV_24_5_NR(instNum, grNum)  (((instNum) == 0U) ? \
1792                                                   (((grNum) <= 3U) ? \
1793                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT) |      \
1794                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U)         |    \
1795                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U)        |    \
1796                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1797                                                   : \
1798                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) |         \
1799                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U)    |    \
1800                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U)   |    \
1801                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1802                                                   : \
1803                                                   (((grNum) <= 3U) ? \
1804                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT) |       \
1805                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U)          |    \
1806                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U)         |    \
1807                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1808                                                   : \
1809                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) |         \
1810                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U)    |    \
1811                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U)   |    \
1812                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1813 
1814 /* PERI_PCLK_GR.DIV_CMD */
1815 #define CY_PERI_DIV_CMD_DIV_SEL_Pos             PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1816 #define CY_PERI_DIV_CMD_DIV_SEL_Msk             PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1817 #define CY_PERI_DIV_CMD_TYPE_SEL_Pos            PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1818 #define CY_PERI_DIV_CMD_TYPE_SEL_Msk            PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1819 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos          PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1820 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk          PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1821 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos         PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1822 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk         PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1823 #define CY_PERI_DIV_CMD_DISABLE_Pos             PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1824 #define CY_PERI_DIV_CMD_DISABLE_Msk             PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1825 #define CY_PERI_DIV_CMD_ENABLE_Pos              PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1826 #define CY_PERI_DIV_CMD_ENABLE_Msk              PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1827 
1828 
1829 #define PERI_DIV_CMD_DIV_SEL_Pos                PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1830 #define PERI_DIV_CMD_DIV_SEL_Msk                PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1831 #define PERI_DIV_CMD_TYPE_SEL_Pos               PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1832 #define PERI_DIV_CMD_TYPE_SEL_Msk               PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1833 #define PERI_DIV_CMD_PA_DIV_SEL_Pos             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1834 #define PERI_DIV_CMD_PA_DIV_SEL_Msk             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1835 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos            PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1836 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk            PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1837 #define PERI_DIV_CMD_DISABLE_Pos                PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1838 #define PERI_DIV_CMD_DISABLE_Msk                PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1839 #define PERI_DIV_CMD_ENABLE_Pos                 PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1840 #define PERI_DIV_CMD_ENABLE_Msk                 PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1841 
1842 /* PERI_PCLK_GR.CLOCK_CTL */
1843 #define CY_PERI_CLOCK_CTL_DIV_SEL_Pos           PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Pos
1844 #define CY_PERI_CLOCK_CTL_DIV_SEL_Msk           PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Msk
1845 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos          PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos
1846 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk          PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Msk
1847 /* PERI.DIV_8_CTL */
1848 #define PERI_DIV_8_CTL_EN_Pos                   PERI_PCLK_GR_DIV_8_CTL_EN_Pos
1849 #define PERI_DIV_8_CTL_EN_Msk                   PERI_PCLK_GR_DIV_8_CTL_EN_Msk
1850 #define PERI_DIV_8_CTL_INT8_DIV_Pos             PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Pos
1851 #define PERI_DIV_8_CTL_INT8_DIV_Msk             PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Msk
1852 /* PERI.DIV_16_CTL */
1853 #define PERI_DIV_16_CTL_EN_Pos                  PERI_PCLK_GR_DIV_16_CTL_EN_Pos
1854 #define PERI_DIV_16_CTL_EN_Msk                  PERI_PCLK_GR_DIV_16_CTL_EN_Msk
1855 #define PERI_DIV_16_CTL_INT16_DIV_Pos           PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Pos
1856 #define PERI_DIV_16_CTL_INT16_DIV_Msk           PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Msk
1857 /* PERI.DIV_16_5_CTL */
1858 #define PERI_DIV_16_5_CTL_EN_Pos                PERI_PCLK_GR_DIV_16_5_CTL_EN_Pos
1859 #define PERI_DIV_16_5_CTL_EN_Msk                PERI_PCLK_GR_DIV_16_5_CTL_EN_Msk
1860 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos         PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Pos
1861 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk         PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Msk
1862 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos         PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Pos
1863 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk         PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Msk
1864 /* PERI.DIV_24_5_CTL */
1865 #define PERI_DIV_24_5_CTL_EN_Pos                PERI_PCLK_GR_DIV_24_5_CTL_EN_Pos
1866 #define PERI_DIV_24_5_CTL_EN_Msk                PERI_PCLK_GR_DIV_24_5_CTL_EN_Msk
1867 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos         PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos
1868 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk         PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Msk
1869 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos         PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos
1870 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk         PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Msk
1871 
1872 /*******************************************************************************
1873 *                PERI-GROUP
1874 *******************************************************************************/
1875 #define CY_PERI_GROUP_NR                        10
1876 
1877 #ifndef PERI0_BASE
1878 #define PERI0_BASE PERI_BASE
1879 #endif
1880 
1881 #ifndef PERI1_BASE
1882 #define PERI1_BASE 0U
1883 #endif
1884 
1885 
1886 #define PERI_GR_OFFSET                      (PERI1_BASE - PERI0_BASE)
1887 #define PERI_GR_REG_BASE(instNum)           ((PERI_Type*)(PERI0_BASE + ((instNum) * PERI_GR_OFFSET)))
1888 
1889 #define PERI_GR_INST_NUM_Msk                 (0x0000FF00U)
1890 #define PERI_GR_INST_NUM_Pos                 (8U)
1891 
1892 
1893 #define PERI_GR_CLOCK_CTL(instNum, grNum)   ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL
1894 #define PERI_GR_SL_CTL(instNum, grNum)      ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL
1895 #define PERI_GR_SL_CTL2(instNum, grNum)     ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL2
1896 #define PERI_GR_SL_CTL3(instNum, grNum)     ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL3
1897 
1898 
1899 /* CLK_HF* to PERI PCLK Group Mapping */
1900 #define PERI0_PCLK_GR_NUM_0_CLK_HF_NUM              (0U)
1901 #define PERI0_PCLK_GR_NUM_1_CLK_HF_NUM              (2U)
1902 
1903 /*******************************************************************************
1904 *                PERI-TR
1905 *******************************************************************************/
1906 #define PERI_TR_CMD                         (((PERI_Type*) (PERI_BASE))->TR_CMD)
1907 #define PERI_TR_GR_TR_CTL(group, trCtl)     (*(volatile uint32_t*) ((uint32_t)PERI_BASE+ (uint32_t)offsetof(PERI_Type,TR_GR) + \
1908                                             ((group) * (uint32_t)sizeof(PERI_TR_GR_Type)) + \
1909                                             ((trCtl) * (uint32_t)sizeof(uint32_t))))
1910 
1911 #if defined (CY_IP_MXPERI)
1912 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1913 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1914 #define CY_PERI_TR_CTL_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1915 #define CY_PERI_TR_CTL_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1916 #define PERI_V2_TR_CMD_OUT_SEL_Msk PERI_TR_CMD_OUT_SEL_Msk
1917 #define PERI_V2_TR_CMD_OUT_SEL_Pos PERI_TR_CMD_OUT_SEL_Pos
1918 #define PERI_V2_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1919 #define PERI_V2_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1920 #define CY_PERI_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1921 #define CY_PERI_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1922 #define CY_PERI_TR_CTL_SEL PERI_TR_GR_TR_CTL_TR_SEL
1923 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk PERI_TR_GR_TR_CTL_TR_INV_Msk
1924 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos PERI_TR_GR_TR_CTL_TR_INV_Pos
1925 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk PERI_TR_GR_TR_CTL_TR_EDGE_Msk
1926 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos PERI_TR_GR_TR_CTL_TR_EDGE_Pos
1927 #define PERI_V2_TR_CMD_TR_EDGE_Msk PERI_TR_CMD_TR_EDGE_Msk
1928 #define PERI_V2_TR_CMD_TR_EDGE_Pos PERI_TR_CMD_TR_EDGE_Pos
1929 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk
1930 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos
1931 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk
1932 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos
1933 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk
1934 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos
1935 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk
1936 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos
1937 #define CY_PERI_V1 0U
1938 #define PERI_TR_CMD_COUNT_Pos 0UL
1939 #define PERI_TR_CMD_COUNT_Msk 0UL
1940 #endif /* CY_IP_MXPERI */
1941 
1942 #define PERI_MS_PPU_PR_SL_ADDR(base)        (((PERI_MS_PPU_PR_Type *) (base))->SL_ADDR)
1943 #define PERI_MS_PPU_PR_SL_SIZE(base)        (((PERI_MS_PPU_PR_Type *) (base))->SL_SIZE)
1944 #define PERI_MS_PPU_PR_MS_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_PR_Type *)(base))->MS_ATT0))
1945 #define PERI_MS_PPU_PR_SL_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_PR_Type *)(base))->SL_ATT0))
1946 #define PERI_MS_PPU_FX_MS_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_FX_Type *)(base))->MS_ATT0))
1947 #define PERI_MS_PPU_FX_SL_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_FX_Type *)(base))->SL_ATT0))
1948 
1949 
1950 /*******************************************************************************
1951 *                PROT
1952 *******************************************************************************/
1953 #define CY_PROT_BASE                        ((uint32_t)PROT_BASE)
1954 #define CY_PROT_PC_MAX                      (8UL)
1955 #define CY_PROT_BUS_MASTER_MASK             (0xFE7FUL)
1956 #define PROT_MPU_MS_CTL(mpu)                (((PROT_Type*)CY_PROT_BASE)->CYMPU[(mpu)].MS_CTL)
1957 #define PROT_MPU_MPU_STRUCT_ADDR(base)      (((PROT_MPU_MPU_STRUCT_Type *) (base))->ADDR)
1958 #define PROT_MPU_MPU_STRUCT_ATT(base)       (((PROT_MPU_MPU_STRUCT_Type *) (base))->ATT)
1959 #define PROT_SMPU_SMPU_STRUCT_ADDR0(base)   (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR0)
1960 #define PROT_SMPU_SMPU_STRUCT_ADDR1(base)   (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR1)
1961 #define PROT_SMPU_SMPU_STRUCT_ATT0(base)    (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT0)
1962 #define PROT_SMPU_SMPU_STRUCT_ATT1(base)    (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT1)
1963 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx)    (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT0)
1964 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT1(stcIdx)    (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT1)
1965 #define PROT_SMPU_SMPU_STRUCT_IDX(stcIdx)         (((PROT_SMPU_SMPU_STRUCT_Type *) &((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)]))
1966 
1967 
1968 /*******************************************************************************
1969 *                IOSS
1970 *******************************************************************************/
1971 
1972 #define CY_GPIO_BASE                       ((uint32_t)GPIO_BASE)
1973 
1974 #define GPIO_INTR_CAUSE0                   ((GPIO)->INTR_CAUSE0)
1975 #define GPIO_INTR_CAUSE1                   ((GPIO)->INTR_CAUSE1)
1976 #define GPIO_INTR_CAUSE2                   ((GPIO)->INTR_CAUSE2)
1977 #define GPIO_INTR_CAUSE3                   ((GPIO)->INTR_CAUSE3)
1978 
1979 #define GPIO_PRT_OUT(base)                 (((GPIO_PRT_Type*)(base))->OUT)
1980 #define GPIO_PRT_OUT_CLR(base)             (((GPIO_PRT_Type*)(base))->OUT_CLR)
1981 #define GPIO_PRT_OUT_SET(base)             (((GPIO_PRT_Type*)(base))->OUT_SET)
1982 #define GPIO_PRT_OUT_INV(base)             (((GPIO_PRT_Type*)(base))->OUT_INV)
1983 #define GPIO_PRT_IN(base)                  (((GPIO_PRT_Type*)(base))->IN)
1984 #define GPIO_PRT_INTR(base)                (((GPIO_PRT_Type*)(base))->INTR)
1985 #define GPIO_PRT_INTR_MASK(base)           (((GPIO_PRT_Type*)(base))->INTR_MASK)
1986 #define GPIO_PRT_INTR_MASKED(base)         (((GPIO_PRT_Type*)(base))->INTR_MASKED)
1987 #define GPIO_PRT_INTR_SET(base)            (((GPIO_PRT_Type*)(base))->INTR_SET)
1988 #define GPIO_PRT_INTR_CFG(base)            (((GPIO_PRT_Type*)(base))->INTR_CFG)
1989 #define GPIO_PRT_CFG(base)                 (((GPIO_PRT_Type*)(base))->CFG)
1990 #define GPIO_PRT_CFG_IN(base)              (((GPIO_PRT_Type*)(base))->CFG_IN)
1991 #define GPIO_PRT_CFG_OUT(base)             (((GPIO_PRT_Type*)(base))->CFG_OUT)
1992 #define GPIO_PRT_CFG_SIO(base)             (((GPIO_PRT_Type*)(base))->CFG_SIO)
1993 #define GPIO_PRT_CFG_IN_AUTOLVL(base)      (((GPIO_PRT_Type*)(base))->CFG_IN_AUTOLVL)
1994 
1995 #define CY_HSIOM_BASE                      ((uint32_t)HSIOM_BASE)
1996 
1997 #define HSIOM_PRT_PORT_SEL0(base)          (((HSIOM_PRT_Type *)(base))->PORT_SEL0)
1998 #define HSIOM_PRT_PORT_SEL1(base)          (((HSIOM_PRT_Type *)(base))->PORT_SEL1)
1999 
2000 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl)    (((HSIOM_Type *)HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl])
2001 
2002 #define ioss_interrupts_gpio_0_IRQn         ioss_interrupts_gpio_dpslp_0_IRQn
2003 #define ioss_interrupts_gpio_1_IRQn         ioss_interrupts_gpio_dpslp_1_IRQn
2004 #define ioss_interrupts_gpio_2_IRQn         ioss_interrupts_gpio_dpslp_2_IRQn
2005 #define ioss_interrupts_gpio_3_IRQn         ioss_interrupts_gpio_dpslp_3_IRQn
2006 #define ioss_interrupts_gpio_4_IRQn         ioss_interrupts_gpio_dpslp_4_IRQn
2007 #define ioss_interrupts_gpio_5_IRQn         ioss_interrupts_gpio_dpslp_5_IRQn
2008 #define ioss_interrupts_gpio_6_IRQn         ioss_interrupts_gpio_dpslp_6_IRQn
2009 #define ioss_interrupts_gpio_7_IRQn         ioss_interrupts_gpio_dpslp_7_IRQn
2010 #define ioss_interrupts_gpio_8_IRQn         ioss_interrupts_gpio_dpslp_8_IRQn
2011 #define ioss_interrupts_gpio_9_IRQn         ioss_interrupts_gpio_dpslp_9_IRQn
2012 #define ioss_interrupts_gpio_10_IRQn        ioss_interrupts_gpio_dpslp_10_IRQn
2013 #define ioss_interrupts_gpio_11_IRQn        ioss_interrupts_gpio_dpslp_11_IRQn
2014 #define ioss_interrupts_gpio_12_IRQn        ioss_interrupts_gpio_dpslp_12_IRQn
2015 #define ioss_interrupts_gpio_13_IRQn        ioss_interrupts_gpio_dpslp_13_IRQn
2016 #define ioss_interrupts_gpio_14_IRQn        ioss_interrupts_gpio_dpslp_14_IRQn
2017 #define ioss_interrupts_gpio_15_IRQn        ioss_interrupts_gpio_dpslp_15_IRQn
2018 #define ioss_interrupts_gpio_16_IRQn        ioss_interrupts_gpio_dpslp_16_IRQn
2019 #define ioss_interrupts_gpio_17_IRQn        ioss_interrupts_gpio_dpslp_17_IRQn
2020 #define ioss_interrupts_gpio_18_IRQn        ioss_interrupts_gpio_dpslp_18_IRQn
2021 #define ioss_interrupts_gpio_19_IRQn        ioss_interrupts_gpio_dpslp_19_IRQn
2022 #define ioss_interrupts_gpio_20_IRQn        ioss_interrupts_gpio_dpslp_20_IRQn
2023 #define ioss_interrupts_gpio_21_IRQn        ioss_interrupts_gpio_dpslp_21_IRQn
2024 #define ioss_interrupts_gpio_22_IRQn        ioss_interrupts_gpio_dpslp_22_IRQn
2025 #define ioss_interrupts_gpio_23_IRQn        ioss_interrupts_gpio_dpslp_23_IRQn
2026 #define ioss_interrupts_gpio_28_IRQn        ioss_interrupts_gpio_dpslp_28_IRQn
2027 #define ioss_interrupts_gpio_29_IRQn        ioss_interrupts_gpio_dpslp_29_IRQn
2028 #define ioss_interrupts_gpio_30_IRQn        ioss_interrupts_gpio_dpslp_30_IRQn
2029 #define ioss_interrupts_gpio_31_IRQn        ioss_interrupts_gpio_dpslp_31_IRQn
2030 #define ioss_interrupts_gpio_32_IRQn        ioss_interrupts_gpio_dpslp_32_IRQn
2031 #define ioss_interrupts_gpio_24_IRQn        ioss_interrupts_gpio_act_24_IRQn
2032 #define ioss_interrupts_gpio_25_IRQn        ioss_interrupts_gpio_act_25_IRQn
2033 #define ioss_interrupts_gpio_26_IRQn        ioss_interrupts_gpio_act_26_IRQn
2034 #define ioss_interrupts_gpio_27_IRQn        ioss_interrupts_gpio_act_27_IRQn
2035 #define ioss_interrupts_gpio_33_IRQn        ioss_interrupts_gpio_act_33_IRQn
2036 #define ioss_interrupts_gpio_34_IRQn        ioss_interrupts_gpio_act_34_IRQn
2037 
2038 /*******************************************************************************
2039 *                I2S
2040 *******************************************************************************/
2041 #if (defined(AUDIOSS_I2S) || defined(AUDIOSS0_I2S_I2S))
2042 #define AUDIOSS_I2S_PRESENT
2043 #endif
2044 
2045 #define REG_I2S_CTL(base)                   (((I2S_Type*)(base))->CTL)
2046 #define REG_I2S_CMD(base)                   (((I2S_Type*)(base))->CMD)
2047 #define REG_I2S_CLOCK_CTL(base)             (((I2S_Type*)(base))->CLOCK_CTL)
2048 #define REG_I2S_TR_CTL(base)                (((I2S_Type*)(base))->TR_CTL)
2049 #define REG_I2S_TX_CTL(base)                (((I2S_Type*)(base))->TX_CTL)
2050 #define REG_I2S_TX_FIFO_CTL(base)           (((I2S_Type*)(base))->TX_FIFO_CTL)
2051 #define REG_I2S_TX_FIFO_STATUS(base)        (((I2S_Type*)(base))->TX_FIFO_STATUS)
2052 #define REG_I2S_TX_FIFO_WR(base)            (((I2S_Type*)(base))->TX_FIFO_WR)
2053 #define REG_I2S_TX_WATCHDOG(base)           (((I2S_Type*)(base))->TX_WATCHDOG)
2054 #define REG_I2S_RX_CTL(base)                (((I2S_Type*)(base))->RX_CTL)
2055 #define REG_I2S_RX_FIFO_CTL(base)           (((I2S_Type*)(base))->RX_FIFO_CTL)
2056 #define REG_I2S_RX_FIFO_STATUS(base)        (((I2S_Type*)(base))->RX_FIFO_STATUS)
2057 #define REG_I2S_RX_FIFO_RD(base)            (((I2S_Type*)(base))->RX_FIFO_RD)
2058 #define REG_I2S_RX_FIFO_RD_SILENT(base)     (((I2S_Type*)(base))->RX_FIFO_RD_SILENT)
2059 #define REG_I2S_RX_WATCHDOG(base)           (((I2S_Type*)(base))->RX_WATCHDOG)
2060 #define REG_I2S_INTR(base)                  (((I2S_Type*)(base))->INTR)
2061 #define REG_I2S_INTR_SET(base)              (((I2S_Type*)(base))->INTR_SET)
2062 #define REG_I2S_INTR_MASK(base)             (((I2S_Type*)(base))->INTR_MASK)
2063 #define REG_I2S_INTR_MASKED(base)           (((I2S_Type*)(base))->INTR_MASKED)
2064 
2065 
2066 
2067 /*******************************************************************************
2068 *                LCD
2069 *******************************************************************************/
2070 
2071 #define LCD_OCTET_NUM                       (8U) /* LCD_NUMPORTS - number of octets supporting up to 4 COMs */
2072 #define LCD_OCTET_NUM_8                     (8U) /* LCD_NUMPORTS8 - number of octets supporting up to 8 COMs */
2073 #define LCD_OCTET_NUM_16                    (0U) /* LCD_NUMPORTS16 - number of octets supporting up to 16 COMs */
2074 #define LCD_COM_NUM                         (8U) /* LCD_CHIP_TOP_COM_NR - maximum number of commons */
2075 
2076 #define LCD_ID(base)                        (((LCD_V1_Type*)(base))->ID)
2077 #define LCD_CONTROL(base)                   (((LCD_V1_Type*)(base))->CONTROL)
2078 #define LCD_DIVIDER(base)                   (((LCD_V1_Type*)(base))->DIVIDER)
2079 #define LCD_DATA0(base)                     (((LCD_V1_Type*)(base))->DATA0)
2080 #define LCD_DATA1(base)                     (((LCD_V1_Type*)(base))->DATA1)
2081 #define LCD_DATA2(base)                     (((LCD_V1_Type*)(base))->DATA2)
2082 #define LCD_DATA3(base)                     (((LCD_V1_Type*)(base))->DATA3)
2083 
2084 
2085 /*******************************************************************************
2086 *                IPC
2087 *******************************************************************************/
2088 
2089 #define CY_IPC_V1                              (0x20u > cy_device->ipcVersion) /* true if the IPC version is 1.x */
2090 
2091 #define REG_IPC_STRUCT_ACQUIRE(base)           (((IPC_STRUCT_Type*)(base))->ACQUIRE)
2092 #define REG_IPC_STRUCT_RELEASE(base)           (((IPC_STRUCT_Type*)(base))->RELEASE)
2093 #define REG_IPC_STRUCT_NOTIFY(base)            (((IPC_STRUCT_Type*)(base))->NOTIFY)
2094 #define REG_IPC_STRUCT_DATA(base)              (((IPC_STRUCT_Type*)(base))->DATA0)
2095 #define REG_IPC_STRUCT_DATA1(base)             (((IPC_STRUCT_Type*)(base))->DATA1)
2096 #define REG_IPC_STRUCT_LOCK_STATUS(base)       (*(volatile uint32_t*)((uint32_t)(base) + (uint32_t)offsetof(IPC_STRUCT_Type, LOCK_STATUS)))
2097 
2098 #define REG_IPC_INTR_STRUCT_INTR(base)         (((IPC_INTR_STRUCT_Type*)(base))->INTR)
2099 #define REG_IPC_INTR_STRUCT_INTR_SET(base)     (((IPC_INTR_STRUCT_Type*)(base))->INTR_SET)
2100 #define REG_IPC_INTR_STRUCT_INTR_MASK(base)    (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASK)
2101 #define REG_IPC_INTR_STRUCT_INTR_MASKED(base)  (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASKED)
2102 
2103 #define CY_IPC_STRUCT_PTR_FOR_IP(ipcIndex, base)            ((IPC_STRUCT_Type*)((uint32_t)(base) + (sizeof(IPC_STRUCT_Type) * (ipcIndex))))
2104 #define CY_IPC_INTR_STRUCT_PTR_FOR_IP(ipcIntrIndex, base)   (&(((IPC_Type *)(base))->INTR_STRUCT[ipcIntrIndex]))
2105 
2106 #define CY_IPC_INSTANCES                       (1U)
2107 #define CY_IPC_CHANNELS                        CPUSS_IPC_IPC_NR
2108 #define CY_IPC_CHANNELS_PER_INSTANCE           CPUSS_IPC_IPC_NR
2109 #define CY_IPC_INTERRUPTS                      CPUSS_IPC_IPC_IRQ_NR
2110 #define CY_IPC_INTERRUPTS_PER_INSTANCE         CPUSS_IPC_IPC_IRQ_NR
2111 #define CY_IPC_IP0_CH                          CPUSS_IPC_IPC_NR
2112 #define CY_IPC_IP0_INT                         CPUSS_IPC_IPC_IRQ_NR
2113 
2114 extern const uint32_t IPC_CHANNELS_NR[CY_IPC_INSTANCES];
2115 extern const uint32_t IPC_IRQ_NR[CY_IPC_INSTANCES];
2116 extern const uint32_t IPC_BASE_PTR[CY_IPC_INSTANCES];
2117 
2118 #define CY_IPC_STRUCT_PTR(ipcIndex)                            CY_IPC_STRUCT_PTR_FOR_IP(((ipcIndex)%CY_IPC_CHANNELS_PER_INSTANCE), IPC_BASE_PTR[(ipcIndex-((ipcIndex)%CY_IPC_CHANNELS_PER_INSTANCE))/CY_IPC_CHANNELS_PER_INSTANCE])
2119 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex)                   CY_IPC_INTR_STRUCT_PTR_FOR_IP(((ipcIntrIndex)%CY_IPC_INTERRUPTS_PER_INSTANCE), IPC_BASE_PTR[(ipcIntrIndex-((ipcIntrIndex)%CY_IPC_INTERRUPTS_PER_INSTANCE))/CY_IPC_INTERRUPTS_PER_INSTANCE])
2120 /* ipcChannel comprises of total number of channels present in all IPC IP instances */
2121 #define CY_IPC_PIPE_CHANNEL_NUMBER_WITHIN_INSTANCE(ipcChannel) (((ipcChannel)%CY_IPC_CHANNELS_PER_INSTANCE))
2122 #define CY_IPC_PIPE_INTR_NUMBER_WITHIN_INSTANCE(ipcIntr)       (((ipcIntr)%CY_IPC_INTERRUPTS_PER_INSTANCE))
2123 
2124 /* IPC channel definitions  */
2125 #define CY_IPC_CHAN_SYSCALL_CM0             (0UL)  /* System calls for the CM0 processor */
2126 #define CY_IPC_CHAN_SYSCALL_CM7_0           (1UL)  /* System calls for the CM7_0 processor */
2127 #if (CPUSS_CM7_1_PRESENT == 1)
2128 #define CY_IPC_CHAN_SYSCALL_CM7_1           (2UL)  /* System calls for the CM7_1 processor */
2129 #define CY_IPC_CHAN_SYSCALL_DAP             (3UL) /* System calls for the DAP */
2130 #define CY_IPC_CHAN_SEMA                    (4UL) /* IPC data channel for the Semaphores */
2131 #else
2132 #define CY_IPC_CHAN_SYSCALL_CM7_1           (CY_IPC_CHANNELS)  /* This macro should not be used. This is defined only for compilation purpose */
2133 #define CY_IPC_CHAN_SYSCALL_DAP             (2UL) /* System calls for the DAP */
2134 #define CY_IPC_CHAN_SEMA                    (3UL) /* IPC data channel for the Semaphores */
2135 #endif
2136 #define CY_IPC_CHAN_USER                    (CY_IPC_CHAN_SEMA + 1UL)
2137 
2138 /* IPC Notify interrupts definitions */
2139 #define CY_IPC_INTR_SYSCALL1                (0UL)
2140 #define CY_IPC_INTR_USER                    (CY_IPC_INTR_SYSCALL1 + 1UL)
2141 
2142 
2143 /*******************************************************************************
2144 *                CTB
2145 *******************************************************************************/
2146 
2147 #define CTBM_CTB_CTRL(base)                 (((CTBM_V1_Type *) (base))->CTB_CTRL)
2148 #define CTBM_CTB_SW_DS_CTRL(base)           (((CTBM_V1_Type *) (base))->CTB_SW_DS_CTRL)
2149 #define CTBM_CTB_SW_SQ_CTRL(base)           (((CTBM_V1_Type *) (base))->CTB_SW_SQ_CTRL)
2150 #define CTBM_CTD_SW(base)                   (((CTBM_V1_Type *) (base))->CTD_SW)
2151 #define CTBM_CTD_SW_CLEAR(base)             (((CTBM_V1_Type *) (base))->CTD_SW_CLEAR)
2152 #define CTBM_COMP_STAT(base)                (((CTBM_V1_Type *) (base))->COMP_STAT)
2153 #define CTBM_OA0_SW_CLEAR(base)             (((CTBM_V1_Type *) (base))->OA0_SW_CLEAR)
2154 #define CTBM_OA1_SW_CLEAR(base)             (((CTBM_V1_Type *) (base))->OA1_SW_CLEAR)
2155 #define CTBM_OA0_SW(base)                   (((CTBM_V1_Type *) (base))->OA0_SW)
2156 #define CTBM_OA1_SW(base)                   (((CTBM_V1_Type *) (base))->OA1_SW)
2157 #define CTBM_OA_RES0_CTRL(base)             (((CTBM_V1_Type *) (base))->OA_RES0_CTRL)
2158 #define CTBM_OA_RES1_CTRL(base)             (((CTBM_V1_Type *) (base))->OA_RES1_CTRL)
2159 #define CTBM_OA0_COMP_TRIM(base)            (((CTBM_V1_Type *) (base))->OA0_COMP_TRIM)
2160 #define CTBM_OA1_COMP_TRIM(base)            (((CTBM_V1_Type *) (base))->OA1_COMP_TRIM)
2161 #define CTBM_OA0_OFFSET_TRIM(base)          (((CTBM_V1_Type *) (base))->OA0_OFFSET_TRIM)
2162 #define CTBM_OA1_OFFSET_TRIM(base)          (((CTBM_V1_Type *) (base))->OA1_OFFSET_TRIM)
2163 #define CTBM_OA0_SLOPE_OFFSET_TRIM(base)    (((CTBM_V1_Type *) (base))->OA0_SLOPE_OFFSET_TRIM)
2164 #define CTBM_OA1_SLOPE_OFFSET_TRIM(base)    (((CTBM_V1_Type *) (base))->OA1_SLOPE_OFFSET_TRIM)
2165 #define CTBM_INTR(base)                     (((CTBM_V1_Type *) (base))->INTR)
2166 #define CTBM_INTR_SET(base)                 (((CTBM_V1_Type *) (base))->INTR_SET)
2167 #define CTBM_INTR_MASK(base)                (((CTBM_V1_Type *) (base))->INTR_MASK)
2168 #define CTBM_INTR_MASKED(base)              (((CTBM_V1_Type *) (base))->INTR_MASKED)
2169 
2170 
2171 /*******************************************************************************
2172 *                CTDAC
2173 *******************************************************************************/
2174 
2175 #define CTDAC_CTDAC_CTRL(base)              (((CTDAC_V1_Type *) (base))->CTDAC_CTRL)
2176 #define CTDAC_CTDAC_SW(base)                (((CTDAC_V1_Type *) (base))->CTDAC_SW)
2177 #define CTDAC_CTDAC_SW_CLEAR(base)          (((CTDAC_V1_Type *) (base))->CTDAC_SW_CLEAR)
2178 #define CTDAC_CTDAC_VAL(base)               (((CTDAC_V1_Type *) (base))->CTDAC_VAL)
2179 #define CTDAC_CTDAC_VAL_NXT(base)           (((CTDAC_V1_Type *) (base))->CTDAC_VAL_NXT)
2180 #define CTDAC_INTR(base)                    (((CTDAC_V1_Type *) (base))->INTR)
2181 #define CTDAC_INTR_SET(base)                (((CTDAC_V1_Type *) (base))->INTR_SET)
2182 #define CTDAC_INTR_MASK(base)               (((CTDAC_V1_Type *) (base))->INTR_MASK)
2183 #define CTDAC_INTR_MASKED(base)             (((CTDAC_V1_Type *) (base))->INTR_MASKED)
2184 
2185 
2186 /*******************************************************************************
2187 *                SYSANALOG
2188 *******************************************************************************/
2189 
2190 #define CY_PASS_V1                          (0x20U > cy_device->passVersion)
2191 #define CY_PASS_ADDR                        ((PASS_Type*)cy_device->passBase)
2192 #define CY_PASS_V2_ADDR                     ((PASS_V2_Type*)cy_device->passBase)
2193 #define CY_PASS_BASE(sarBase)               ((NULL != (sarBase)) ? ((PASS_V2_Type*) cy_device->passBase) : NULL) /* temporary solution for single pass instance */
2194 
2195 #define PASS_AREF_AREF_CTRL                 (((PASS_V1_Type*) CY_PASS_ADDR)->AREF.AREF_CTRL)
2196 #define PASS_INTR_CAUSE(passBase)           (((PASS_V1_Type*) (passBase))->INTR_CAUSE)
2197 #define PASS_CTBM_CLOCK_SEL(passBase)       (((PASS_V2_Type*) (passBase))->CTBM_CLOCK_SEL)
2198 #define PASS_DPSLP_CLOCK_SEL(passBase)      (((PASS_V2_Type*) (passBase))->DPSLP_CLOCK_SEL)
2199 #define PASS_LPOSC_CTRL(passBase)           (((PASS_V2_Type*) (passBase))->LPOSC.CTRL)
2200 #define PASS_LPOSC_CONFIG(passBase)         (((PASS_V2_Type*) (passBase))->LPOSC.CONFIG)
2201 #define PASS_TIMER_CTRL(passBase)           (((PASS_V2_Type*) (passBase))->TIMER.CTRL)
2202 #define PASS_TIMER_CONFIG(passBase)         (((PASS_V2_Type*) (passBase))->TIMER.CONFIG)
2203 #define PASS_TIMER_PERIOD(passBase)         (((PASS_V2_Type*) (passBase))->TIMER.PERIOD)
2204 
2205 #define PASS_SAR_SIMULT_CTRL(passBase)      (((PASS_V2_Type*) (passBase))->SAR_SIMULT_CTRL)
2206 #define PASS_SAR_TR_SCAN_CNT(passBase)      (((PASS_V2_Type*) (passBase))->SAR_TR_SCAN_CNT)
2207 #define PASS_SAR_OVR_CTRL(passBase)         (((PASS_V2_Type*) (passBase))->SAR_OVR_CTRL)
2208 #define PASS_SAR_SIMULT_FW_START_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_SIMULT_FW_START_CTRL)
2209 #define PASS_ANA_PWR_CFG(passBase)          (((PASS_V2_Type*) (passBase))->ANA_PWR_CFG)
2210 #define PASS_SAR_TR_OUT_CTRL(passBase)      (((PASS_V2_Type*) (passBase))->SAR_TR_OUT_CTRL)
2211 
2212 #define PASS_SAR_DPSLP_CTRL(sarBase)        (((PASS_V2_Type*) cy_device->passBase)->SAR_DPSLP_CTRL[CY_SAR_INSTANCE(sarBase)])
2213 #define PASS_SAR_CLOCK_SEL(sarBase)         (((PASS_V2_Type*) cy_device->passBase)->SAR_CLOCK_SEL[CY_SAR_INSTANCE(sarBase)])
2214 
2215 #define PASS_FIFO_BASE(sarBase)             ((PASS_FIFO_V2_Type*)&(((PASS_V2_Type*)cy_device->passBase)->FIFO[CY_SAR_INSTANCE(sarBase)]))
2216 #define PASS_FIFO_CTRL(sarBase)             (PASS_FIFO_BASE(sarBase)->CTRL)
2217 #define PASS_FIFO_CONFIG(sarBase)           (PASS_FIFO_BASE(sarBase)->CONFIG)
2218 #define PASS_FIFO_LEVEL(sarBase)            (PASS_FIFO_BASE(sarBase)->LEVEL)
2219 #define PASS_FIFO_USED(sarBase)             (PASS_FIFO_BASE(sarBase)->USED)
2220 #define PASS_FIFO_RD_DATA(sarBase)          (PASS_FIFO_BASE(sarBase)->RD_DATA)
2221 #define PASS_FIFO_INTR(sarBase)             (PASS_FIFO_BASE(sarBase)->INTR)
2222 #define PASS_FIFO_INTR_SET(sarBase)         (PASS_FIFO_BASE(sarBase)->INTR_SET)
2223 #define PASS_FIFO_INTR_MASK(sarBase)        (PASS_FIFO_BASE(sarBase)->INTR_MASK)
2224 #define PASS_FIFO_INTR_MASKED(sarBase)      (PASS_FIFO_BASE(sarBase)->INTR_MASKED)
2225 
2226 /*******************************************************************************
2227 *                SCB
2228 *******************************************************************************/
2229 
2230 #define SCB_CTRL(base)                      (((CySCB_Type*) (base))->CTRL)
2231 #define SCB_SPI_CTRL(base)                  (((CySCB_Type*) (base))->SPI_CTRL)
2232 #define SCB_SPI_STATUS(base)                (((CySCB_Type*) (base))->SPI_STATUS)
2233 #define SCB_SPI_TX_CTRL(base)               (((CySCB_Type*) (base))->SPI_TX_CTRL)
2234 #define SCB_SPI_RX_CTRL(base)               (((CySCB_Type*) (base))->SPI_RX_CTRL)
2235 #define SCB_UART_CTRL(base)                 (((CySCB_Type*) (base))->UART_CTRL)
2236 #define SCB_UART_TX_CTRL(base)              (((CySCB_Type*) (base))->UART_TX_CTRL)
2237 #define SCB_UART_RX_CTRL(base)              (((CySCB_Type*) (base))->UART_RX_CTRL)
2238 #define SCB_UART_FLOW_CTRL(base)            (((CySCB_Type*) (base))->UART_FLOW_CTRL)
2239 #define SCB_I2C_CTRL(base)                  (((CySCB_Type*) (base))->I2C_CTRL)
2240 #define SCB_I2C_STATUS(base)                (((CySCB_Type*) (base))->I2C_STATUS)
2241 #define SCB_I2C_M_CMD(base)                 (((CySCB_Type*) (base))->I2C_M_CMD)
2242 #define SCB_I2C_S_CMD(base)                 (((CySCB_Type*) (base))->I2C_S_CMD)
2243 #define SCB_I2C_CFG(base)                   (((CySCB_Type*) (base))->I2C_CFG)
2244 #define SCB_TX_CTRL(base)                   (((CySCB_Type*) (base))->TX_CTRL)
2245 #define SCB_TX_FIFO_CTRL(base)              (((CySCB_Type*) (base))->TX_FIFO_CTRL)
2246 #define SCB_TX_FIFO_STATUS(base)            (((CySCB_Type*) (base))->TX_FIFO_STATUS)
2247 #define SCB_TX_FIFO_WR(base)                (((CySCB_Type*) (base))->TX_FIFO_WR)
2248 #define SCB_RX_CTRL(base)                   (((CySCB_Type*) (base))->RX_CTRL)
2249 #define SCB_RX_FIFO_CTRL(base)              (((CySCB_Type*) (base))->RX_FIFO_CTRL)
2250 #define SCB_RX_FIFO_STATUS(base)            (((CySCB_Type*) (base))->RX_FIFO_STATUS)
2251 #define SCB_RX_MATCH(base)                  (((CySCB_Type*) (base))->RX_MATCH)
2252 #define SCB_RX_FIFO_RD(base)                (((CySCB_Type*) (base))->RX_FIFO_RD)
2253 #define SCB_INTR_CAUSE(base)                (((CySCB_Type*) (base))->INTR_CAUSE)
2254 #define SCB_INTR_I2C_EC(base)               (((CySCB_Type*) (base))->INTR_I2C_EC)
2255 #define SCB_INTR_I2C_EC_MASK(base)          (((CySCB_Type*) (base))->INTR_I2C_EC_MASK)
2256 #define SCB_INTR_I2C_EC_MASKED(base)        (((CySCB_Type*) (base))->INTR_I2C_EC_MASKED)
2257 #define SCB_INTR_SPI_EC(base)               (((CySCB_Type*) (base))->INTR_SPI_EC)
2258 #define SCB_INTR_SPI_EC_MASK(base)          (((CySCB_Type*) (base))->INTR_SPI_EC_MASK)
2259 #define SCB_INTR_SPI_EC_MASKED(base)        (((CySCB_Type*) (base))->INTR_SPI_EC_MASKED)
2260 #define SCB_INTR_M(base)                    (((CySCB_Type*) (base))->INTR_M)
2261 #define SCB_INTR_M_SET(base)                (((CySCB_Type*) (base))->INTR_M_SET)
2262 #define SCB_INTR_M_MASK(base)               (((CySCB_Type*) (base))->INTR_M_MASK)
2263 #define SCB_INTR_M_MASKED(base)             (((CySCB_Type*) (base))->INTR_M_MASKED)
2264 #define SCB_INTR_S(base)                    (((CySCB_Type*) (base))->INTR_S)
2265 #define SCB_INTR_S_SET(base)                (((CySCB_Type*) (base))->INTR_S_SET)
2266 #define SCB_INTR_S_MASK(base)               (((CySCB_Type*) (base))->INTR_S_MASK)
2267 #define SCB_INTR_S_MASKED(base)             (((CySCB_Type*) (base))->INTR_S_MASKED)
2268 #define SCB_INTR_TX(base)                   (((CySCB_Type*) (base))->INTR_TX)
2269 #define SCB_INTR_TX_SET(base)               (((CySCB_Type*) (base))->INTR_TX_SET)
2270 #define SCB_INTR_TX_MASK(base)              (((CySCB_Type*) (base))->INTR_TX_MASK)
2271 #define SCB_INTR_TX_MASKED(base)            (((CySCB_Type*) (base))->INTR_TX_MASKED)
2272 #define SCB_INTR_RX(base)                   (((CySCB_Type*) (base))->INTR_RX)
2273 #define SCB_INTR_RX_SET(base)               (((CySCB_Type*) (base))->INTR_RX_SET)
2274 #define SCB_INTR_RX_MASK(base)              (((CySCB_Type*) (base))->INTR_RX_MASK)
2275 #define SCB_INTR_RX_MASKED(base)            (((CySCB_Type*) (base))->INTR_RX_MASKED)
2276 
2277 
2278 /*******************************************************************************
2279 *                PROFILE
2280 *******************************************************************************/
2281 
2282 #define CY_EP_MONITOR_COUNT                 ((uint32_t)(cy_device->epMonitorNr))
2283 #define CY_EP_CNT_NR                        (8UL)
2284 #define PROFILE_CTL                         (((PROFILE_V1_Type*) PROFILE_BASE)->CTL)
2285 #define PROFILE_STATUS                      (((PROFILE_V1_Type*) PROFILE_BASE)->STATUS)
2286 #define PROFILE_CMD                         (((PROFILE_V1_Type*) PROFILE_BASE)->CMD)
2287 #define PROFILE_INTR                        (((PROFILE_V1_Type*) PROFILE_BASE)->INTR)
2288 #define PROFILE_INTR_MASK                   (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASK)
2289 #define PROFILE_INTR_MASKED                 (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASKED)
2290 #define PROFILE_CNT_STRUCT                  (((PROFILE_V1_Type*) PROFILE_BASE)->CNT_STRUCT)
2291 
2292 /******************************************************************************
2293 *                MXETH
2294 *******************************************************************************/
2295 #define ETH_CTL(base)                       (((ETH_Type*)(base))->CTL)
2296 #define ETH_TX_Q_PTR(base)                  (((ETH_Type*)(base))->TRANSMIT_Q_PTR)
2297 #define ETH_TX_Q1_PTR(base)                 (((ETH_Type*)(base))->TRANSMIT_Q1_PTR)
2298 #define ETH_TX_Q2_PTR(base)                 (((ETH_Type*)(base))->TRANSMIT_Q2_PTR)
2299 #define ETH_RX_Q_PTR(base)                  (((ETH_Type*)(base))->RECEIVE_Q_PTR)
2300 #define ETH_RX_Q1_PTR(base)                 (((ETH_Type*)(base))->RECEIVE_Q1_PTR)
2301 #define ETH_RX_Q2_PTR(base)                 (((ETH_Type*)(base))->RECEIVE_Q2_PTR)
2302 
2303 /*******************************************************************************
2304 *                BLE
2305 *******************************************************************************/
2306 
2307 #define BLE_RCB_INTR                        (((BLE_V1_Type *) BLE_BASE)->RCB.INTR)
2308 #define BLE_RCB_TX_FIFO_WR                  (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR)
2309 #define BLE_RCB_RX_FIFO_RD                  (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD)
2310 #define BLE_RCB_CTRL                        (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL)
2311 #define BLE_RCB_RCBLL_CTRL                  (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL)
2312 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG       (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG)
2313 #define BLE_BLESS_MT_CFG                    (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG)
2314 #define BLE_BLESS_MT_STATUS                 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS)
2315 #define BLE_BLESS_MT_DELAY_CFG              (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG)
2316 #define BLE_BLESS_MT_DELAY_CFG2             (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2)
2317 #define BLE_BLESS_MT_DELAY_CFG3             (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3)
2318 #define BLE_BLESS_MT_VIO_CTRL               (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL)
2319 #define BLE_BLESS_LL_CLK_EN                 (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN)
2320 #define BLE_BLESS_MISC_EN_CTRL              (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL)
2321 #define BLE_BLESS_INTR_STAT                 (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT)
2322 #define BLE_BLELL_EVENT_INTR                (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR)
2323 #define BLE_BLELL_CONN_INTR                 (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR)
2324 #define BLE_BLELL_CONN_EXT_INTR             (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR)
2325 #define BLE_BLELL_SCAN_INTR                 (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR)
2326 #define BLE_BLELL_ADV_INTR                  (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR)
2327 
2328 
2329 /*******************************************************************************
2330 *                USBFS Device
2331 *******************************************************************************/
2332 
2333 #define USBFS_DEV_CR0(base)             (((USBFS_V1_Type *)(base))->USBDEV.CR0)
2334 #define USBFS_DEV_CR1(base)             (((USBFS_V1_Type *)(base))->USBDEV.CR1)
2335 #define USBFS_DEV_USBIO_CR0(base)       (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR0)
2336 #define USBFS_DEV_USBIO_CR2(base)       (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR2)
2337 #define USBFS_DEV_USBIO_CR1(base)       (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR1)
2338 #define USBFS_DEV_USB_CLK_EN(base)      (((USBFS_V1_Type *)(base))->USBDEV.USB_CLK_EN)
2339 #define USBFS_DEV_BUS_RST_CNT(base)     (((USBFS_V1_Type *)(base))->USBDEV.BUS_RST_CNT)
2340 #define USBFS_DEV_OSCLK_DR0(base)       (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE)
2341 #define USBFS_DEV_OSCLK_DR1(base)       (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR0)
2342 #define USBFS_DEV_SOF0(base)            (((USBFS_V1_Type *)(base))->USBDEV.SOF0)
2343 #define USBFS_DEV_SOF1(base)            (((USBFS_V1_Type *)(base))->USBDEV.SOF1)
2344 #define USBFS_DEV_SOF16(base)           (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR1)
2345 #define USBFS_DEV_OSCLK_DR16(base)      (((USBFS_V1_Type *)(base))->USBDEV.SOF16)
2346 #define USBFS_DEV_ARB_CFG(base)         (((USBFS_V1_Type *)(base))->USBDEV.ARB_CFG)
2347 #define USBFS_DEV_DYN_RECONFIG(base)    (((USBFS_V1_Type *)(base))->USBDEV.DYN_RECONFIG)
2348 #define USBFS_DEV_BUF_SIZE(base)        (((USBFS_V1_Type *)(base))->USBDEV.BUF_SIZE)
2349 #define USBFS_DEV_EP_ACTIVE(base)       (((USBFS_V1_Type *)(base))->USBDEV.EP_ACTIVE)
2350 #define USBFS_DEV_EP_TYPE(base)         (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE)
2351 #define USBFS_DEV_CWA16(base)           (((USBFS_V1_Type *)(base))->USBDEV.CWA16)
2352 #define USBFS_DEV_CWA(base)             (((USBFS_V1_Type *)(base))->USBDEV.CWA)
2353 #define USBFS_DEV_CWA_MSB(base)         (((USBFS_V1_Type *)(base))->USBDEV.CWA_MSB)
2354 #define USBFS_DEV_DMA_THRES16(base)     (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES16)
2355 #define USBFS_DEV_DMA_THRES(base)       (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES)
2356 #define USBFS_DEV_DMA_THRES_MSB(base)   (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES_MSB)
2357 
2358 #define USBFS_DEV_SIE_EP_INT_EN(base)   (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_EN)
2359 #define USBFS_DEV_SIE_EP_INT_SR(base)   (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_SR)
2360 #define USBFS_DEV_ARB_INT_EN(base)      (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_EN)
2361 #define USBFS_DEV_ARB_INT_SR(base)      (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_SR)
2362 
2363 #define USBFS_DEV_EP0_CR(base)          (((USBFS_V1_Type *)(base))->USBDEV.EP0_CR)
2364 #define USBFS_DEV_EP0_CNT(base)         (((USBFS_V1_Type *)(base))->USBDEV.EP0_CNT)
2365 #define USBFS_DEV_EP0_DR(base, idx)     (((USBFS_V1_Type *)(base))->USBDEV.EP0_DR[idx])
2366 
2367 #define USBFS_DEV_MEM_DATA(base, idx)   (((USBFS_V1_Type *)(base))->USBDEV.MEM[idx])
2368 
2369 #define USBFS_DEV_SIE_REGS_BASE        (0x30U)
2370 #define USBFS_DEV_SIE_REGS_SIZE        (0x40U)
2371 #define USBFS_DEV_SIE_EP_CNT0_OFFSET   (0x00U)
2372 #define USBFS_DEV_SIE_EP_CNT1_OFFSET   (0x04U)
2373 #define USBFS_DEV_SIE_EP_CR0_OFFSET    (0x08U)
2374 #define USBFS_DEV_SIE_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_SIE_REGS_BASE + ((endpoint) * USBFS_DEV_SIE_REGS_SIZE))
2375 
2376 #define USBFS_DEV_SIE_EP_CNT0(base, endpoint)  (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
2377                                                                         USBFS_DEV_SIE_EP_CNT0_OFFSET))
2378 #define USBFS_DEV_SIE_EP_CNT1(base, endpoint)  (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
2379                                                                         USBFS_DEV_SIE_EP_CNT1_OFFSET))
2380 #define USBFS_DEV_SIE_EP_CR0(base, endpoint)   (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
2381                                                                         USBFS_DEV_SIE_EP_CR0_OFFSET))
2382 
2383 #define USBFS_DEV_ARB_REGS_BASE         (0x200U)
2384 #define USBFS_DEV_ARB_REGS_SIZE         (0x40U)
2385 #define USBFS_DEV_ARB_EP_CFG_OFFSET     (0x00U)
2386 #define USBFS_DEV_ARB_EP_INT_EN_OFFSET  (0x04U)
2387 #define USBFS_DEV_ARB_EP_SR_OFFSET      (0x08U)
2388 #define USBFS_DEV_ARB_RW_WA_OFFSET      (0x10U)
2389 #define USBFS_DEV_ARB_RW_WA_MSB_OFFSET  (0x14U)
2390 #define USBFS_DEV_ARB_RW_RA_OFFSET      (0x18U)
2391 #define USBFS_DEV_ARB_RW_RA_MSB_OFFSET  (0x1CU)
2392 #define USBFS_DEV_ARB_RW_DR_OFFSET      (0x20U)
2393 #define USBFS_DEV_ARB_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS_BASE + ((endpoint) * USBFS_DEV_ARB_REGS_SIZE))
2394 
2395 #define USBFS_DEV_ARB_EP_CFG(base, endpoint)       (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2396                                                                             USBFS_DEV_ARB_EP_CFG_OFFSET))
2397 #define USBFS_DEV_ARB_EP_INT_EN(base, endpoint)    (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2398                                                                             USBFS_DEV_ARB_EP_INT_EN_OFFSET))
2399 #define USBFS_DEV_ARB_EP_SR(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2400                                                                             USBFS_DEV_ARB_EP_SR_OFFSET))
2401 #define USBFS_DEV_ARB_RW_WA(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2402                                                                             USBFS_DEV_ARB_RW_WA_OFFSET))
2403 #define USBFS_DEV_ARB_RW_WA_MSB(base, endpoint)    (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2404                                                                             USBFS_DEV_ARB_RW_WA_MSB_OFFSET))
2405 #define USBFS_DEV_ARB_RW_RA(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2406                                                                             USBFS_DEV_ARB_RW_RA_OFFSET))
2407 #define USBFS_DEV_ARB_RW_RA_MSB(base, endpoint)    (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2408                                                                             USBFS_DEV_ARB_RW_RA_MSB_OFFSET))
2409 #define USBFS_DEV_ARB_RW_DR(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
2410                                                                             USBFS_DEV_ARB_RW_DR_OFFSET))
2411 
2412 #define USBFS_DEV_ARB_REGS16_BASE       (0x1210U)
2413 #define USBFS_DEV_ARB_REGS16_SIZE       (0x40U)
2414 #define USBFS_DEV_ARB_RW_WA16_OFFSET    (0x00U)
2415 #define USBFS_DEV_ARB_RW_RA16_OFFSET    (0x08U)
2416 #define USBFS_DEV_ARB_RW_DR16_OFFSET    (0x10U)
2417 #define USBFS_DEV_ARB_REGS_16(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS16_BASE + ((endpoint) * USBFS_DEV_ARB_REGS16_SIZE))
2418 
2419 #define USBFS_DEV_ARB_RW_WA16(base, endpoint)      (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
2420                                                                             USBFS_DEV_ARB_RW_WA16_OFFSET))
2421 #define USBFS_DEV_ARB_RW_RA16(base, endpoint)      (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
2422                                                                             USBFS_DEV_ARB_RW_RA16_OFFSET))
2423 #define USBFS_DEV_ARB_RW_DR16(base, endpoint)      (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
2424                                                                             USBFS_DEV_ARB_RW_DR16_OFFSET))
2425 
2426 #define USBFS_DEV_LPM_POWER_CTL(base)       (((USBFS_V1_Type *)(base))->USBLPM.POWER_CTL)
2427 #define USBFS_DEV_LPM_USBIO_CTL(base)       (((USBFS_V1_Type *)(base))->USBLPM.USBIO_CTL)
2428 #define USBFS_DEV_LPM_FLOW_CTL(base)        (((USBFS_V1_Type *)(base))->USBLPM.FLOW_CTL)
2429 #define USBFS_DEV_LPM_LPM_CTL(base)         (((USBFS_V1_Type *)(base))->USBLPM.LPM_CTL)
2430 #define USBFS_DEV_LPM_LPM_STAT(base)        (((USBFS_V1_Type const *)(base))->USBLPM.LPM_STAT)
2431 #define USBFS_DEV_LPM_INTR_SIE(base)        (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE)
2432 #define USBFS_DEV_LPM_INTR_SIE_SET(base)    (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_SET)
2433 #define USBFS_DEV_LPM_INTR_SIE_MASK(base)   (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASK)
2434 #define USBFS_DEV_LPM_INTR_SIE_MASKED(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASKED)
2435 #define USBFS_DEV_LPM_INTR_LVL_SEL(base)    (((USBFS_V1_Type *)(base))->USBLPM.INTR_LVL_SEL)
2436 #define USBFS_DEV_LPM_INTR_CAUSE_HI(base)   (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_HI)
2437 #define USBFS_DEV_LPM_INTR_CAUSE_MED(base)  (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_MED)
2438 #define USBFS_DEV_LPM_INTR_CAUSE_LO(base)   (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_LO)
2439 #define USBFS_DEV_LPM_DFT_CTL(base)         (((USBFS_V1_Type *)(base))->USBLPM.DFT_CTL)
2440 
2441 #define USBFS_HOST_CTL0(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL0)
2442 #define USBFS_HOST_CTL1(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL1)
2443 #define USBFS_HOST_CTL2(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL2)
2444 #define USBFS_HOST_ERR(base)                (((USBFS_V1_Type *)(base))->USBHOST.HOST_ERR)
2445 #define USBFS_HOST_STATUS(base)             (((USBFS_V1_Type *)(base))->USBHOST.HOST_STATUS)
2446 #define USBFS_HOST_FCOMP(base)              (((USBFS_V1_Type *)(base))->USBHOST.HOST_FCOMP)
2447 #define USBFS_HOST_RTIMER(base)             (((USBFS_V1_Type *)(base))->USBHOST.HOST_RTIMER)
2448 #define USBFS_HOST_ADDR(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_ADDR)
2449 #define USBFS_HOST_EOF(base)                (((USBFS_V1_Type *)(base))->USBHOST.HOST_EOF)
2450 #define USBFS_HOST_FRAME(base)              (((USBFS_V1_Type *)(base))->USBHOST.HOST_FRAME)
2451 #define USBFS_HOST_TOKEN(base)              (((USBFS_V1_Type *)(base))->USBHOST.HOST_TOKEN)
2452 #define USBFS_HOST_EP1_CTL(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_CTL)
2453 #define USBFS_HOST_EP1_STATUS(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_STATUS)
2454 #define USBFS_HOST_EP1_RW1_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW1_DR)
2455 #define USBFS_HOST_EP1_RW2_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW2_DR)
2456 #define USBFS_HOST_EP2_CTL(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_CTL)
2457 #define USBFS_HOST_EP2_STATUS(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_STATUS)
2458 #define USBFS_HOST_EP2_RW1_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW1_DR)
2459 #define USBFS_HOST_EP2_RW2_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW2_DR)
2460 #define USBFS_HOST_LVL1_SEL(base)           (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL1_SEL)
2461 #define USBFS_HOST_LVL2_SEL(base)           (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL2_SEL)
2462 #define USBFS_INTR_USBHOST_CAUSE_HI(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_HI)
2463 #define USBFS_INTR_USBHOST_CAUSE_MED(base)  (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_MED)
2464 #define USBFS_INTR_USBHOST_CAUSE_LO(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_LO)
2465 #define USBFS_INTR_HOST_EP_CAUSE_HI(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_HI)
2466 #define USBFS_INTR_HOST_EP_CAUSE_MED(base)  (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_MED)
2467 #define USBFS_INTR_HOST_EP_CAUSE_LO(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_LO)
2468 #define USBFS_INTR_USBHOST(base)            (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST)
2469 #define USBFS_INTR_USBHOST_SET(base)        (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_SET)
2470 #define USBFS_INTR_USBHOST_MASK(base)       (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASK)
2471 #define USBFS_INTR_USBHOST_MASKED(base)     (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASKED)
2472 #define USBFS_INTR_HOST_EP(base)            (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP)
2473 #define USBFS_INTR_HOST_EP_SET(base)        (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_SET)
2474 #define USBFS_INTR_HOST_EP_MASK(base)       (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASK)
2475 #define USBFS_INTR_HOST_EP_MASKED(base)     (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASKED)
2476 #define USBFS_HOST_DMA_ENBL(base)           (((USBFS_V1_Type *)(base))->USBHOST.HOST_DMA_ENBL)
2477 #define USBFS_HOST_EP1_BLK(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_BLK)
2478 #define USBFS_HOST_EP2_BLK(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_BLK)
2479 
2480 
2481 /*******************************************************************************
2482 *                LIN
2483 *******************************************************************************/
2484 #if defined (CY_IP_MXLIN)
2485 #define LIN0_CH1                                ((LIN_CH_Type*) &LIN0->CH[1])
2486 #define LIN0_CH2                                ((LIN_CH_Type*) &LIN0->CH[2])
2487 #define LIN0_CH3                                ((LIN_CH_Type*) &LIN0->CH[3])
2488 #define LIN0_CH4                                ((LIN_CH_Type*) &LIN0->CH[4])
2489 #define LIN0_CH5                                ((LIN_CH_Type*) &LIN0->CH[5])
2490 #define LIN0_CH6                                ((LIN_CH_Type*) &LIN0->CH[6])
2491 #define LIN0_CH7                                ((LIN_CH_Type*) &LIN0->CH[7])
2492 #define LIN0_CH8                                ((LIN_CH_Type*) &LIN0->CH[8])
2493 #define LIN0_CH9                                ((LIN_CH_Type*) &LIN0->CH[9])
2494 #define LIN0_CH10                               ((LIN_CH_Type*) &LIN0->CH[10])
2495 #define LIN0_CH11                               ((LIN_CH_Type*) &LIN0->CH[11])
2496 #define LIN0_CH12                               ((LIN_CH_Type*) &LIN0->CH[12])
2497 #define LIN0_CH13                               ((LIN_CH_Type*) &LIN0->CH[13])
2498 #define LIN0_CH14                               ((LIN_CH_Type*) &LIN0->CH[14])
2499 #define LIN0_CH15                               ((LIN_CH_Type*) &LIN0->CH[15])
2500 #define LIN0_CH16                               ((LIN_CH_Type*) &LIN0->CH[16])
2501 #define LIN0_CH17                               ((LIN_CH_Type*) &LIN0->CH[17])
2502 #define LIN0_CH18                               ((LIN_CH_Type*) &LIN0->CH[18])
2503 #define LIN0_CH19                               ((LIN_CH_Type*) &LIN0->CH[19])
2504 #define LIN0_CH20                               ((LIN_CH_Type*) &LIN0->CH[20])
2505 #define LIN0_CH21                               ((LIN_CH_Type*) &LIN0->CH[21])
2506 #define LIN0_CH22                               ((LIN_CH_Type*) &LIN0->CH[22])
2507 #define LIN0_CH23                               ((LIN_CH_Type*) &LIN0->CH[23])
2508 #define LIN0_CH24                               ((LIN_CH_Type*) &LIN0->CH[24])
2509 #define LIN0_CH25                               ((LIN_CH_Type*) &LIN0->CH[25])
2510 #define LIN0_CH26                               ((LIN_CH_Type*) &LIN0->CH[26])
2511 #define LIN0_CH27                               ((LIN_CH_Type*) &LIN0->CH[27])
2512 #define LIN0_CH28                               ((LIN_CH_Type*) &LIN0->CH[28])
2513 #define LIN0_CH29                               ((LIN_CH_Type*) &LIN0->CH[29])
2514 #define LIN0_CH30                               ((LIN_CH_Type*) &LIN0->CH[30])
2515 #define LIN0_CH31                               ((LIN_CH_Type*) &LIN0->CH[31])
2516 
2517 #define LIN_CH_CTL0(base)                       (((LIN_CH_Type *)(base))->CTL0)
2518 #define LIN_CH_CTL1(base)                       (((LIN_CH_Type *)(base))->CTL1)
2519 #define LIN_CH_STATUS(base)                     (((LIN_CH_Type *)(base))->STATUS)
2520 #define LIN_CH_CMD(base)                        (((LIN_CH_Type *)(base))->CMD)
2521 #define LIN_CH_TX_RX_STATUS(base)               (((LIN_CH_Type *)(base))->TX_RX_STATUS)
2522 #define LIN_CH_PID_CHECKSUM(base)               (((LIN_CH_Type *)(base))->PID_CHECKSUM)
2523 #define LIN_CH_DATA0(base)                      (((LIN_CH_Type *)(base))->DATA0)
2524 #define LIN_CH_DATA1(base)                      (((LIN_CH_Type *)(base))->DATA1)
2525 #define LIN_CH_INTR(base)                       (((LIN_CH_Type *)(base))->INTR)
2526 #define LIN_CH_INTR_SET(base)                   (((LIN_CH_Type *)(base))->INTR_SET)
2527 #define LIN_CH_INTR_MASK(base)                  (((LIN_CH_Type *)(base))->INTR_MASK)
2528 #define LIN_CH_INTR_MASKED(base)                (((LIN_CH_Type *)(base))->INTR_MASKED)
2529 
2530 #define LIN_ERROR_CTL(base)                     (((LIN_Type *)(base))->ERROR_CTL)
2531 #define LIN_TEST_CTL(base)                      (((LIN_Type *)(base))->TEST_CTL)
2532 #endif /* CY_IP_MXLIN */
2533 
2534 /*******************************************************************************
2535 *                SAR ADC
2536 *******************************************************************************/
2537 /** Channel TR_CTL register access macro. */
2538 #define SAR2_CH_TR_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].TR_CTL)
2539 
2540 /** Channel SAMPLE_CTL register access macro. */
2541 #define SAR2_CH_SAMPLE_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].SAMPLE_CTL)
2542 
2543 /** Channel POST_CTL register access macro. */
2544 #define SAR2_CH_POST_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].POST_CTL)
2545 
2546 /** Channel RANGE_CTL register access macro. */
2547 #define SAR2_CH_RANGE_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].RANGE_CTL)
2548 
2549 /** Channel INTR register access macro. */
2550 #define SAR2_CH_INTR(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR)
2551 
2552 /** Channel INTR_SET register access macro. */
2553 #define SAR2_CH_INTR_SET(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_SET)
2554 
2555 /** Channel INTR_MASK register access macro. */
2556 #define SAR2_CH_INTR_MASK(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_MASK)
2557 
2558 /** Channel INTR_MASKED register access macro. */
2559 #define SAR2_CH_INTR_MASKED(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_MASKED)
2560 
2561 /** Channel WORK register access macro. */
2562 #define SAR2_CH_WORK(base, channel) (((PASS_SAR_Type *)base)->CH[channel].WORK)
2563 
2564 /** Channel RESULT register access macro. */
2565 #define SAR2_CH_RESULT(base, channel) (((PASS_SAR_Type *)base)->CH[channel].RESULT)
2566 
2567 /** Channel GRP_STAT register access macro. */
2568 #define SAR2_CH_GRP_STAT(base, channel) (((PASS_SAR_Type *)base)->CH[channel].GRP_STAT)
2569 
2570 /** Channel ENABLE register access macro. */
2571 #define SAR2_CH_ENABLE(base, channel) (((PASS_SAR_Type *)base)->CH[channel].ENABLE)
2572 
2573 /** Channel TR_CMD register access macro. */
2574 #define SAR2_CH_TR_CMD(base, channel) (((PASS_SAR_Type *)base)->CH[channel].TR_CMD)
2575 
2576 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
2577 #endif /* CY_DEVICE_H_ */
2578 
2579 /* [] END OF FILE */
2580