1 /***************************************************************************//** 2 * \file cy_device.h 3 * \version 2.30 4 * 5 * This file specifies the structure for core and peripheral block HW base 6 * addresses, versions, and parameters. 7 * 8 ******************************************************************************** 9 * \copyright 10 * Copyright 2018-2022 Cypress Semiconductor Corporation 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 *******************************************************************************/ 25 26 #ifndef CY_DEVICE_H_ 27 #define CY_DEVICE_H_ 28 29 #include <stdint.h> 30 #include <stddef.h> 31 32 #include "cy_device_headers.h" 33 34 /* Use for mutual conditions when code should be included for a TVIIBE512K, TVIIBE1M, TVIIEBE2M, or TVIIBE4M device.*/ 35 #if (defined (CY_DEVICE_SERIES_CYT2B6) || defined (CY_DEVICE_SERIES_CYT2B7) || defined (CY_DEVICE_SERIES_CYT2B9) || defined (CY_DEVICE_SERIES_CYT2BL)) 36 37 /* Use to determine if compiling for a TVIIBE device. */ 38 #define CY_DEVICE_TVIIBE (1UL) 39 40 /* Drivers for some TVIIBE IP require macro names with version fields. This header 41 * remaps macros from CAT1A compatible names that don't contain the version fields. */ 42 #include "tviibe_remaps.h" 43 44 #elif (defined (CY_DEVICE_SERIES_FX3G2) || defined (CY_DEVICE_SERIES_FX2G3)) 45 46 #include "ip/cyip_cpuss.h" 47 #include "ip/cyip_cpuss_v2.h" 48 #include "ip/cyip_flashc.h" 49 #include "ip/cyip_flashc_v2.h" 50 #include "ip/cyip_gpio.h" 51 #include "ip/cyip_gpio_v5.h" 52 #include "ip/cyip_hsiom.h" 53 #include "ip/cyip_hsiom_v5.h" 54 #include "ip/cyip_sflash_fx3g2.h" 55 56 #include "ip/cyip_srss.h" 57 #include "ip/cyip_srss.h" 58 #include "ip/cyip_peri.h" 59 #include "ip/cyip_peri_v2.h" 60 #include "ip/cyip_peri_ms_v2.h" 61 #include "ip/cyip_prot.h" 62 #include "ip/cyip_prot_v2.h" 63 #include "ip/cyip_ipc.h" 64 #include "ip/cyip_ipc_v2.h" 65 #include "ip/cyip_dw.h" 66 #include "ip/cyip_dw_v2.h" 67 #include "ip/cyip_dmac_v2.h" 68 #include "ip/cyip_tdm_v2.h" 69 #include "ip/cyip_mxpdm.h" 70 #include "ip/cyip_canfd.h" 71 #include "ip/cyip_tcpwm.h" 72 #include "ip/cyip_mxs40usbhsdev.h" 73 #include "ip/cyip_main_reg.h" 74 #include "ip/cyip_lvdsss.h" 75 #include "ip/cyip_usb32dev.h" 76 77 #else /* PSoC Devices */ 78 79 #include "ip/cyip_cpuss.h" 80 #include "ip/cyip_cpuss_v2.h" 81 #include "ip/cyip_flashc.h" 82 #include "ip/cyip_flashc_v2.h" 83 #include "ip/cyip_gpio.h" 84 #include "ip/cyip_gpio_v2.h" 85 #include "ip/cyip_hsiom.h" 86 #include "ip/cyip_hsiom_v2.h" 87 88 #if defined (COMPONENT_PSOC6_01) 89 #include "ip/cyip_sflash_psoc6_01.h" 90 #endif 91 92 #if defined (COMPONENT_PSOC6_02) 93 #include "ip/cyip_sflash_psoc6_02.h" 94 #endif 95 96 #if defined (COMPONENT_PSOC6_03) 97 #include "ip/cyip_sflash_psoc6_03.h" 98 #endif 99 100 #if defined (COMPONENT_PSOC6_04) 101 #include "ip/cyip_sflash_psoc6_04.h" 102 #endif 103 104 #include "ip/cyip_srss.h" 105 #include "ip/cyip_backup.h" 106 #include "ip/cyip_peri.h" 107 #include "ip/cyip_peri_v2.h" 108 #include "ip/cyip_peri_ms_v2.h" 109 #include "ip/cyip_profile.h" 110 #include "ip/cyip_prot.h" 111 #include "ip/cyip_prot_v2.h" 112 #include "ip/cyip_ipc.h" 113 #include "ip/cyip_ipc_v2.h" 114 #include "ip/cyip_udb.h" 115 #include "ip/cyip_dw.h" 116 #include "ip/cyip_dw_v2.h" 117 #include "ip/cyip_dmac_v2.h" 118 #include "ip/cyip_i2s.h" 119 #include "ip/cyip_pdm.h" 120 #include "ip/cyip_lcd.h" 121 #include "ip/cyip_lcd_v2.h" 122 #include "ip/cyip_sdhc.h" 123 #include "ip/cyip_canfd.h" 124 #include "ip/cyip_smartio.h" 125 #include "ip/cyip_tcpwm.h" 126 #include "ip/cyip_tcpwm_v2.h" 127 #include "ip/cyip_ctbm.h" 128 #include "ip/cyip_ctbm_v2.h" 129 #include "ip/cyip_ctdac.h" 130 #include "ip/cyip_ctdac_v2.h" 131 #include "ip/cyip_sar.h" 132 #include "ip/cyip_sar_v2.h" 133 #include "ip/cyip_pass.h" 134 #include "ip/cyip_pass_v2.h" 135 136 #endif /* PSoC or TVIIBE device */ 137 138 139 /* Device descriptor type */ 140 typedef struct 141 { 142 /* Base HW addresses */ 143 uint32_t cpussBase; 144 uint32_t flashcBase; 145 uint32_t periBase; 146 uint32_t udbBase; 147 uint32_t protBase; 148 uint32_t hsiomBase; 149 uint32_t gpioBase; 150 uint32_t passBase; 151 uint32_t ipcBase; 152 uint32_t cryptoBase; 153 uint32_t sar0Base; 154 155 /* IP block versions: [7:4] major, [3:0] minor */ 156 uint8_t cpussVersion; 157 uint8_t cryptoVersion; 158 uint8_t dwVersion; 159 uint8_t flashcVersion; 160 uint8_t gpioVersion; 161 uint8_t hsiomVersion; 162 uint8_t ipcVersion; 163 uint8_t periVersion; 164 uint8_t protVersion; 165 uint8_t srssVersion; 166 uint8_t passVersion; 167 168 /* Parameters */ 169 uint8_t cpussIpcNr; 170 uint8_t cpussIpcIrqNr; 171 uint8_t cpussDw0ChNr; 172 uint8_t cpussDw1ChNr; 173 uint8_t cpussFlashPaSize; 174 int16_t cpussIpc0Irq; 175 int16_t cpussFmIrq; 176 int16_t cpussNotConnectedIrq; 177 uint8_t srssNumClkpath; 178 uint8_t srssNumPll; 179 uint8_t srssNumHfroot; 180 uint8_t srssIsPiloPresent; 181 uint8_t periClockNr; 182 uint8_t smifDeviceNr; 183 uint8_t passSarChannels; 184 uint8_t epMonitorNr; 185 uint8_t udbPresent; 186 uint8_t sysPmSimoPresent; 187 uint32_t protBusMasterMask; 188 uint32_t cryptoMemSize; 189 uint8_t flashRwwRequired; 190 uint8_t flashPipeRequired; 191 uint8_t flashWriteDelay; 192 uint8_t flashProgramDelay; 193 uint8_t flashEraseDelay; 194 uint8_t flashCtlMainWs0Freq; 195 uint8_t flashCtlMainWs1Freq; 196 uint8_t flashCtlMainWs2Freq; 197 uint8_t flashCtlMainWs3Freq; 198 uint8_t flashCtlMainWs4Freq; 199 uint8_t tcpwmCC1Present; 200 uint8_t tcpwmAMCPresent; 201 uint8_t tcpwmSMCPrecent; 202 203 /* Peripheral register offsets */ 204 205 /* DW registers */ 206 uint16_t dwChOffset; 207 uint16_t dwChSize; 208 uint8_t dwChCtlPrioPos; 209 uint8_t dwChCtlPreemptablePos; 210 uint8_t dwStatusChIdxPos; 211 uint32_t dwStatusChIdxMsk; 212 213 /* PERI registers */ 214 uint16_t periTrCmdOffset; 215 uint16_t periTrCmdGrSelMsk; 216 uint16_t periTrGrOffset; 217 uint16_t periTrGrSize; 218 219 uint8_t periDivCmdDivSelMsk; 220 uint8_t periDivCmdTypeSelPos; 221 uint8_t periDivCmdPaDivSelPos; 222 uint8_t periDivCmdPaTypeSelPos; 223 224 uint16_t periDiv8CtlOffset; 225 uint16_t periDiv16CtlOffset; 226 uint16_t periDiv16_5CtlOffset; 227 uint16_t periDiv24_5CtlOffset; 228 229 /* GPIO registers */ 230 uint8_t gpioPrtIntrCfgOffset; 231 uint8_t gpioPrtCfgOffset; 232 uint8_t gpioPrtCfgInOffset; 233 uint8_t gpioPrtCfgOutOffset; 234 uint8_t gpioPrtCfgSioOffset; 235 236 /* CPUSS registers */ 237 uint32_t cpussCm0ClockCtlOffset; 238 uint32_t cpussCm4ClockCtlOffset; 239 uint32_t cpussCm4StatusOffset; 240 uint32_t cpussCm0StatusOffset; 241 uint32_t cpussCm4PwrCtlOffset; 242 uint32_t cpussTrimRamCtlOffset; 243 uint32_t cpussTrimRomCtlOffset; 244 uint32_t cpussSysTickCtlOffset; 245 uint16_t cpussCm0NmiCtlOffset; 246 uint16_t cpussCm4NmiCtlOffset; 247 uint16_t cpussRomCtl; 248 uint16_t cpussRam0Ctl0; 249 uint16_t cpussRam1Ctl0; 250 uint16_t cpussRam2Ctl0; 251 uint16_t cpussRam0PwrCtl; 252 uint16_t cpussRam1PwrCtl; 253 uint16_t cpussRam2PwrCtl; 254 255 /* IPC registers */ 256 uint16_t ipcStructSize; 257 uint32_t ipcLockStatusOffset; 258 } cy_stc_device_t; 259 260 /******************************************************************************* 261 * Global Variables 262 *******************************************************************************/ 263 264 #if !(defined(CY_DEVICE_TVIIBE)) 265 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01; 266 #endif 267 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02; 268 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03; 269 extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04; 270 extern const cy_stc_device_t cy_deviceIpBlockCfgTVIIBE4M; 271 extern const cy_stc_device_t cy_deviceIpBlockCfgTVIIBE2M; 272 extern const cy_stc_device_t cy_deviceIpBlockCfgTVIIBE1M; 273 extern const cy_stc_device_t cy_deviceIpBlockCfgFX3G2; 274 extern const cy_stc_device_t * cy_device; 275 276 277 /******************************************************************************* 278 * Function Prototypes 279 *******************************************************************************/ 280 281 void Cy_PDL_Init(const cy_stc_device_t * device); 282 283 /******************************************************************************* 284 * Generic Macro Definitions 285 *******************************************************************************/ 286 #define GET_ALIAS_ADDRESS(addr) (uint32_t)(addr) 287 288 /******************************************************************************* 289 * Register Access Helper Macros 290 *******************************************************************************/ 291 #define CY_DEVICE_CAT1A /* Device Category */ 292 #define CY_CRYPTO_V1 (0x20U > cy_device->cryptoVersion) /* true if the mxcrypto version is 1.x */ 293 294 /* Remapping the CBUS to SAHB address & Vice versa*/ 295 #define CY_REMAP_ADDRESS_CBUS_TO_SAHB(addr) (addr) 296 #define CY_REMAP_ADDRESS_SAHB_TO_CBUS(addr) (addr) 297 298 #define CY_SRSS_V1_3 (0x13U == cy_device->srssVersion) 299 #if (defined (CY_DEVICE_SERIES_FX3G2) || defined (CY_DEVICE_SERIES_FX2G3)) 300 #define CY_SRSS_MFO_PRESENT (0) 301 #else 302 #define CY_SRSS_MFO_PRESENT (CY_SRSS_V1_3) 303 #endif /* CY_DEVICE_SERIES_FX3G2 */ 304 305 #if (defined(CY_DEVICE_TVIIBE)) 306 307 #define CY_SRSS_PILO_PRESENT (0) 308 309 #define CY_SRSS_NUM_CLKPATH (SRSS_NUM_CLKPATH) 310 #define CY_SRSS_NUM_PLL (SRSS_NUM_TOTAL_PLL) 311 #define CY_SRSS_NUM_PLL200M (SRSS_NUM_PLL) 312 #if defined(SRSS_NUM_PLL400M) 313 #define CY_SRSS_NUM_PLL400M (SRSS_NUM_PLL400M) 314 #else 315 #define CY_SRSS_NUM_PLL400M (0) 316 #endif 317 #define CY_SRSS_NUM_HFROOT (SRSS_NUM_HFROOT) 318 #define CY_SRSS_ECO_PRESENT (SRSS_ECO_PRESENT) 319 #define CY_SRSS_FLL_PRESENT (1) 320 #define CY_SRSS_PLL_PRESENT (SRSS_NUM_PLL) 321 #define CY_SRSS_PLL400M_PRESENT (SRSS_NUM_PLL400M) 322 #define CY_SRSS_ALTHF_PRESENT (SRSS_ALTHF_PRESENT) 323 324 #define CY_SRSS_ILO_COUNT 2 325 326 /** HF PATH # used for PERI PCLK */ 327 #define CY_SYSCLK_CLK_PERI_HF_PATH_NUM 0U 328 329 /** HF PATH # used for Both Cores */ 330 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM 0U 331 332 /** HF PATH # used for CLOCK FAST */ 333 #define CY_SYSCLK_CLK_FAST_HF_NUM 0U 334 335 /* HF PATH # Max Allowed Frequencies */ 336 #define CY_SYSCLK_HF_MAX_FREQ(hfNum) (160000000U) 337 338 /** FLL Max Frequency */ 339 #define CY_SYSCLK_FLL_MAX_OUTPUT_FREQ (100000000UL) 340 341 /* Technology Independant Register set */ 342 #define SRSS_CLK_DSI_SELECT (((SRSS_Type *) SRSS)->CLK_DSI_SELECT) 343 #define SRSS_CLK_OUTPUT_FAST (((SRSS_Type *) SRSS)->CLK_OUTPUT_FAST) 344 #define SRSS_CLK_OUTPUT_SLOW (((SRSS_Type *) SRSS)->CLK_OUTPUT_SLOW) 345 #define SRSS_CLK_CAL_CNT1 (((SRSS_Type *) SRSS)->CLK_CAL_CNT1) 346 #define SRSS_CLK_CAL_CNT2 (((SRSS_Type *) SRSS)->CLK_CAL_CNT2) 347 #define SRSS_SRSS_INTR (((SRSS_Type *) SRSS)->SRSS_INTR) 348 #define SRSS_SRSS_INTR_SET (((SRSS_Type *) SRSS)->SRSS_INTR_SET) 349 #define SRSS_SRSS_INTR_MASK (((SRSS_Type *) SRSS)->SRSS_INTR_MASK) 350 #define SRSS_SRSS_INTR_MASKED (((SRSS_Type *) SRSS)->SRSS_INTR_MASKED) 351 #define SRSS_PWR_CTL (((SRSS_Type *) SRSS)->PWR_CTL) 352 #define SRSS_PWR_CTL2 (((SRSS_Type *) SRSS)->PWR_CTL2) 353 #define SRSS_PWR_HIBERNATE (((SRSS_Type *) SRSS)->PWR_HIBERNATE) 354 355 #if (CY_IP_MXS40SRSS_VERSION >= 3) 356 #define SRSS_PWR_BUCK_CTL (((SRSS_Type *) SRSS)->PWR_BUCK_CTL) 357 #define SRSS_PWR_BUCK_CTL2 (((SRSS_Type *) SRSS)->PWR_BUCK_CTL2) 358 #endif 359 360 #define SRSS_PWR_SSV_CTL (((SRSS_Type *) SRSS)->PWR_SSV_CTL) 361 #define SRSS_PWR_SSV_STATUS (((SRSS_Type *) SRSS)->PWR_SSV_STATUS) 362 #define SRSS_PWR_LVD_CTL (((SRSS_Type *) SRSS)->PWR_LVD_CTL) 363 #define SRSS_PWR_LVD_CTL2 (((SRSS_Type *) SRSS)->PWR_LVD_CTL2) 364 365 #if (CY_IP_MXS40SRSS_VERSION >= 3) 366 #define SRSS_PWR_REGHC_CTL (((SRSS_Type *) SRSS)->PWR_REGHC_CTL) 367 #define SRSS_PWR_REGHC_STATUS (((SRSS_Type *) SRSS)->PWR_REGHC_STATUS) 368 #define SRSS_PWR_REGHC_CTL2 (((SRSS_Type *) SRSS)->PWR_REGHC_CTL2) 369 #define SRSS_PWR_REGHC_CTL4 (((SRSS_Type *) SRSS)->PWR_REGHC_CTL4) 370 #endif 371 372 #define SRSS_PWR_HIB_DATA (((SRSS_Type *) SRSS)->PWR_HIB_DATA) 373 374 #if (CY_IP_MXS40SRSS_VERSION >= 3) 375 #define SRSS_PWR_PMIC_CTL (((SRSS_Type *) SRSS)->PWR_PMIC_CTL) 376 #define SRSS_PWR_PMIC_STATUS (((SRSS_Type *) SRSS)->PWR_PMIC_STATUS) 377 #define SRSS_PWR_PMIC_CTL2 (((SRSS_Type *) SRSS)->PWR_PMIC_CTL2) 378 #define SRSS_PWR_PMIC_CTL4 (((SRSS_Type *) SRSS)->PWR_PMIC_CTL4) 379 #endif 380 381 #define SRSS_CLK_PATH_SELECT (((SRSS_Type *) SRSS)->CLK_PATH_SELECT) 382 #define SRSS_CLK_ROOT_SELECT (((SRSS_Type *) SRSS)->CLK_ROOT_SELECT) 383 #define SRSS_CLK_DIRECT_SELECT (((SRSS_Type *) SRSS)->CLK_DIRECT_SELECT) 384 #define SRSS_CLK_ECO_STATUS (((SRSS_Type *) SRSS)->CLK_ECO_STATUS) 385 #define SRSS_CLK_ILO_CONFIG (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG) /* BWC */ 386 #define SRSS_CLK_ILO0_CONFIG (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG) 387 #define SRSS_CLK_ILO1_CONFIG (((SRSS_Type *) SRSS)->CLK_ILO1_CONFIG) 388 389 #define SRSS_CLK_ILO_CONFIG_ENABLE_Msk SRSS_CLK_ILO0_CONFIG_ENABLE_Msk /* BWC */ 390 391 #define SRSS_CLK_TRIM_ILO_CTL (((SRSS_Type *) SRSS)->CLK_TRIM_ILO_CTL) 392 393 #if (CY_IP_MXS40SRSS_VERSION >= 3) 394 #define SRSS_CLK_PILO_CONFIG (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG) 395 #endif 396 397 #define SRSS_CLK_ECO_CONFIG (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG) 398 #define SRSS_CLK_ECO_CONFIG2 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG2) 399 #define SRSS_CLK_MFO_CONFIG (((SRSS_Type *) SRSS)->CLK_MFO_CONFIG) 400 #define SRSS_CLK_IHO_CONFIG (((SRSS_Type *) SRSS)->CLK_IHO_CONFIG) 401 #define SRSS_CLK_ALTHF_CTL (((SRSS_Type *) SRSS)->CLK_ALTHF_CTL) 402 403 #define SRSS_CLK_ILO0_CONFIG (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG) 404 #define SRSS_CLK_ILO1_CONFIG (((SRSS_Type *) SRSS)->CLK_ILO1_CONFIG) 405 406 #define SRSS_CSV_HF (((SRSS_Type *) SRSS)->CSV_HF) 407 #define SRSS_CLK_SELECT (((SRSS_Type *) SRSS)->CLK_SELECT) 408 #define SRSS_CLK_TIMER_CTL (((SRSS_Type *) SRSS)->CLK_TIMER_CTL) 409 #define SRSS_CLK_IMO_CONFIG (((SRSS_Type *) SRSS)->CLK_IMO_CONFIG) 410 #define SRSS_CLK_ECO_PRESCALE (((SRSS_Type *) SRSS)->CLK_ECO_PRESCALE) 411 #define SRSS_CLK_MF_SELECT (((SRSS_Type *) SRSS)->CLK_MF_SELECT) 412 #define SRSS_CSV_REF_SEL (((SRSS_Type *) SRSS)->CSV_REF_SEL) 413 #define SRSS_CSV_REF (((SRSS_Type *) SRSS)->CSV_REF) 414 #define SRSS_CSV_LF (((SRSS_Type *) SRSS)->CSV_LF) 415 #define SRSS_CSV_ILO (((SRSS_Type *) SRSS)->CSV_ILO) 416 #define SRSS_RES_CAUSE (((SRSS_Type *) SRSS)->RES_CAUSE) 417 #define SRSS_RES_CAUSE2 (((SRSS_Type *) SRSS)->RES_CAUSE2) 418 #define SRSS_RES_CAUSE_EXTEND (((SRSS_Type *) SRSS)->RES_CAUSE_EXTEND) 419 #define SRSS_CLK_LP_PLL (((SRSS_Type *) SRSS)->CLK_LP_PLL) 420 #define SRSS_CLK_IHO (((SRSS_Type *) SRSS)->CLK_IHO) 421 #define SRSS_TST_XRES_SECURE (((SRSS_Type *) SRSS)->TST_XRES_SECURE) 422 #define SRSS_RES_PXRES_CTL (((SRSS_Type *) SRSS)->RES_PXRES_CTL) 423 424 #define SRSS_CLK_FLL_CONFIG (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG) 425 #define SRSS_CLK_FLL_CONFIG2 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG2) 426 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3) 427 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4) 428 #define SRSS_CLK_FLL_STATUS (((SRSS_Type *) SRSS)->CLK_FLL_STATUS) 429 430 #define SRSS_PWR_LVD_STATUS (((SRSS_Type *) SRSS)->PWR_LVD_STATUS) 431 #define SRSS_PWR_LVD_STATUS2 (((SRSS_Type *) SRSS)->PWR_LVD_STATUS2) 432 433 #define SRSS_SRSS_INTR_CFG (((SRSS_Type *) SRSS)->SRSS_AINTR_CFG) 434 435 #define SRSS_PWR_HIB_WAKE_CTL (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL) 436 #define SRSS_PWR_HIB_WAKE_CTL2 (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL2) 437 #define SRSS_PWR_HIB_WAKE_CAUSE (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CAUSE) 438 #define SRSS_RES_SOFT_CTL (((SRSS_Type *) SRSS)->RES_SOFT_CTL) 439 440 #define SRSS_CLK_PLL_CONFIG (((SRSS_Type *) SRSS)->CLK_PLL_CONFIG) 441 #define SRSS_CLK_PLL_STATUS (((SRSS_Type *) SRSS)->CLK_PLL_STATUS) 442 443 #define SRSS_FLL_PATH_NUM (0UL) 444 #define SRSS_PLL_200M_0_PATH_NUM (1UL) 445 446 #define SRSS_PLL400M_FRAC_BIT_COUNT (24ULL) 447 448 #if (CY_IP_MXS40SRSS_VERSION >= 3) 449 #define SRSS_CLK_PLL_400M_CONFIG(pllNum) (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG) 450 #define SRSS_CLK_PLL_400M_CONFIG2(pllNum) (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG2) 451 #define SRSS_CLK_PLL_400M_CONFIG3(pllNum) (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG3) 452 #define SRSS_CLK_PLL_400M_STATUS(pllNum) (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].STATUS) 453 #endif 454 455 456 #define SRSS_WDT_CTL (((WDT_Type*) &SRSS->WDT_STRUCT)->CTL) 457 #define SRSS_WDT_LOWER_LIMIT (((WDT_Type*) &SRSS->WDT_STRUCT)->LOWER_LIMIT) 458 #define SRSS_WDT_UPPER_LIMIT (((WDT_Type*) &SRSS->WDT_STRUCT)->UPPER_LIMIT) 459 #define SRSS_WDT_WARN_LIMIT (((WDT_Type*) &SRSS->WDT_STRUCT)->WARN_LIMIT) 460 #define SRSS_WDT_CONFIG (((WDT_Type*) &SRSS->WDT_STRUCT)->CONFIG) 461 #define SRSS_WDT_CNT (((WDT_Type*) &SRSS->WDT_STRUCT)->CNT) 462 #define SRSS_WDT_LOCK (((WDT_Type*) &SRSS->WDT_STRUCT)->LOCK) 463 #define SRSS_WDT_SERVICE (((WDT_Type*) &SRSS->WDT_STRUCT)->SERVICE) 464 #define SRSS_WDT_INTR (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR) 465 #define SRSS_WDT_INTR_SET (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_SET) 466 #define SRSS_WDT_INTR_MASK (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_MASK) 467 #define SRSS_WDT_INTR_MASKED (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_MASKED) 468 469 470 471 #define SRSS_TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40261104U) 472 #define SRSS_TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x40261108U) 473 474 #define SRSS_TST_DDFT_SLOW_CTL_MASK (0x00001F1EU) 475 #define SRSS_TST_DDFT_FAST_CTL_MASK (62U) 476 477 478 #else /* PSoC Devices */ 479 480 #define CY_SRSS_PILO_PRESENT (1U == cy_device->srssIsPiloPresent) 481 482 #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) 483 #define CY_SRSS_NUM_PLL ((uint32_t)(cy_device->srssNumPll)) 484 #define CY_SRSS_NUM_HFROOT ((uint32_t)(cy_device->srssNumHfroot)) 485 #define CY_SRSS_PLL_PRESENT SRSS_NUM_PLL 486 #define CY_SRSS_PLL400M_PRESENT 0 487 #define CY_SRSS_DPLL_LP_PRESENT 0 488 489 #ifndef CY_EM_EEPROM_SIZE 490 #define CY_EM_EEPROM_SIZE 0x00000000UL 491 #endif 492 493 #define SRSS_PWR_CTL (((SRSS_V1_Type *) SRSS)->PWR_CTL) 494 #define SRSS_PWR_HIBERNATE (((SRSS_V1_Type *) SRSS)->PWR_HIBERNATE) 495 #define SRSS_PWR_TRIM_PWRSYS_CTL (((SRSS_V1_Type *) SRSS)->PWR_TRIM_PWRSYS_CTL) 496 #define SRSS_PWR_BUCK_CTL (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL) 497 #define SRSS_PWR_BUCK_CTL2 (((SRSS_V1_Type *) SRSS)->PWR_BUCK_CTL2) 498 #define SRSS_PWR_TRIM_WAKE_CTL (((SRSS_V1_Type *) SRSS)->PWR_TRIM_WAKE_CTL) 499 #define SRSS_PWR_LVD_CTL (((SRSS_V1_Type *) SRSS)->PWR_LVD_CTL) 500 #define SRSS_PWR_LVD_STATUS (((SRSS_V1_Type *) SRSS)->PWR_LVD_STATUS) 501 #define SRSS_WDT_CTL (((SRSS_V1_Type *) SRSS)->WDT_CTL) 502 #define SRSS_WDT_CNT (((SRSS_V1_Type *) SRSS)->WDT_CNT) 503 #define SRSS_WDT_MATCH (((SRSS_V1_Type *) SRSS)->WDT_MATCH) 504 #define SRSS_CLK_DSI_SELECT (((SRSS_V1_Type *) SRSS)->CLK_DSI_SELECT) 505 #define SRSS_CLK_PATH_SELECT (((SRSS_V1_Type *) SRSS)->CLK_PATH_SELECT) 506 #define SRSS_CLK_ROOT_SELECT (((SRSS_V1_Type *) SRSS)->CLK_ROOT_SELECT) 507 #define SRSS_CLK_CSV_HF_LIMIT(clk) (((SRSS_V1_Type *) SRSS)->CLK_CSV[(clk)].HF_LIMIT) 508 #define SRSS_CLK_CSV_HF_CTL(clk) (((SRSS_V1_Type *) SRSS)->CLK_CSV[(clk)].HF_CTL) 509 #define SRSS_CLK_SELECT (((SRSS_V1_Type *) SRSS)->CLK_SELECT) 510 #define SRSS_CLK_TIMER_CTL (((SRSS_V1_Type *) SRSS)->CLK_TIMER_CTL) 511 #define SRSS_CLK_CSV_WCO_CTL (((SRSS_V1_Type *) SRSS)->CLK_CSV_WCO_CTL) 512 #define SRSS_CLK_ILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ILO_CONFIG) 513 #define SRSS_CLK_OUTPUT_SLOW (((SRSS_V1_Type *) SRSS)->CLK_OUTPUT_SLOW) 514 #define SRSS_CLK_OUTPUT_FAST (((SRSS_V1_Type *) SRSS)->CLK_OUTPUT_FAST) 515 #define SRSS_CLK_CAL_CNT1 (((SRSS_V1_Type *) SRSS)->CLK_CAL_CNT1) 516 #define SRSS_CLK_CAL_CNT2 (((SRSS_V1_Type *) SRSS)->CLK_CAL_CNT2) 517 #define SRSS_CLK_ECO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_ECO_CONFIG) 518 #define SRSS_CLK_ECO_STATUS (((SRSS_V1_Type *) SRSS)->CLK_ECO_STATUS) 519 #define SRSS_CLK_PILO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PILO_CONFIG) 520 #define SRSS_CLK_MF_SELECT (((SRSS_V1_Type *) SRSS)->CLK_MF_SELECT) /* for CY_SRSS_V1_3 only */ 521 #define SRSS_CLK_MFO_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_MFO_CONFIG) /* for CY_SRSS_V1_3 only */ 522 #define SRSS_CLK_FLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG) 523 #define SRSS_CLK_FLL_CONFIG2 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG2) 524 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG3) 525 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_V1_Type *) SRSS)->CLK_FLL_CONFIG4) 526 #define SRSS_CLK_FLL_STATUS (((SRSS_V1_Type *) SRSS)->CLK_FLL_STATUS) 527 #define SRSS_CLK_PLL_CONFIG (((SRSS_V1_Type *) SRSS)->CLK_PLL_CONFIG) 528 #define SRSS_CLK_PLL_STATUS (((SRSS_V1_Type *) SRSS)->CLK_PLL_STATUS) 529 #define SRSS_SRSS_INTR (((SRSS_V1_Type *) SRSS)->SRSS_INTR) 530 #define SRSS_SRSS_INTR_SET (((SRSS_V1_Type *) SRSS)->SRSS_INTR_SET) 531 #define SRSS_SRSS_INTR_CFG (((SRSS_V1_Type *) SRSS)->SRSS_INTR_CFG) 532 #define SRSS_SRSS_INTR_MASK (((SRSS_V1_Type *) SRSS)->SRSS_INTR_MASK) 533 #define SRSS_SRSS_INTR_MASKED (((SRSS_V1_Type *) SRSS)->SRSS_INTR_MASKED) 534 #define SRSS_CLK_TRIM_ILO_CTL (((SRSS_V1_Type *) SRSS)->CLK_TRIM_ILO_CTL) 535 #define SRSS_CLK_TRIM_ECO_CTL (((SRSS_V1_Type *) SRSS)->CLK_TRIM_ECO_CTL) 536 537 #define SRSS_RES_CAUSE (((SRSS_V1_Type *) SRSS)->RES_CAUSE) 538 #define SRSS_RES_CAUSE2 (((SRSS_V1_Type *) SRSS)->RES_CAUSE2) 539 540 #define SRSS_TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x40260108U) 541 #define SRSS_TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40260104U) 542 543 #define SRSS_TST_DDFT_SLOW_CTL_MASK (0x00001F1EU) 544 #define SRSS_TST_DDFT_FAST_CTL_MASK (62U) 545 #endif /* (defined(CY_DEVICE_TVIIBE)) */ 546 547 /******************************************************************************* 548 * CRYPTO 549 *******************************************************************************/ 550 551 /* The CRYPTO internal-memory buffer-size in 32-bit words. */ 552 #define CY_CRYPTO_MEM_BUFF_SIZE_U32 (1024U) 553 554 /******************************************************************************* 555 * BACKUP 556 *******************************************************************************/ 557 558 #if (defined(CY_DEVICE_TVIIBE)) 559 560 #define BACKUP_PMIC_CTL (((BACKUP_Type *) BACKUP)->PMIC_CTL) 561 #define BACKUP_CTL (((BACKUP_Type *) BACKUP)->CTL) 562 #define BACKUP_RTC_TIME (((BACKUP_Type *) BACKUP)->RTC_TIME) 563 #define BACKUP_RTC_DATE (((BACKUP_Type *) BACKUP)->RTC_DATE) 564 #define BACKUP_RTC_RW (((BACKUP_Type *) BACKUP)->RTC_RW) 565 #define BACKUP_CAL_CTL (((BACKUP_Type *) BACKUP)->CAL_CTL) 566 #define BACKUP_ALM1_TIME (((BACKUP_Type *) BACKUP)->ALM1_TIME) 567 #define BACKUP_ALM1_DATE (((BACKUP_Type *) BACKUP)->ALM1_DATE) 568 #define BACKUP_ALM2_TIME (((BACKUP_Type *) BACKUP)->ALM2_TIME) 569 #define BACKUP_ALM2_DATE (((BACKUP_Type *) BACKUP)->ALM2_DATE) 570 #define BACKUP_STATUS (((BACKUP_Type *) BACKUP)->STATUS) 571 #define BACKUP_INTR (((BACKUP_Type *) BACKUP)->INTR) 572 #define BACKUP_INTR_SET (((BACKUP_Type *) BACKUP)->INTR_SET) 573 #define BACKUP_INTR_MASK (((BACKUP_Type *) BACKUP)->INTR_MASK) 574 #define BACKUP_INTR_MASKED (((BACKUP_Type *) BACKUP)->INTR_MASKED) 575 #define BACKUP_RESET (((BACKUP_Type *) BACKUP)->RESET) 576 #define BACKUP_BREG (((BACKUP_Type *) BACKUP)->BREG) 577 578 #define CY_SRSS_BACKUP_NUM_BREG SRSS_BACKUP_NUM_BREG 579 580 #else /* PSoC Devices */ 581 582 #define BACKUP_PMIC_CTL (((BACKUP_V1_Type *) BACKUP)->PMIC_CTL) 583 #define BACKUP_CTL (((BACKUP_V1_Type *) BACKUP)->CTL) 584 #define BACKUP_RTC_TIME (((BACKUP_V1_Type *) BACKUP)->RTC_TIME) 585 #define BACKUP_RTC_DATE (((BACKUP_V1_Type *) BACKUP)->RTC_DATE) 586 #define BACKUP_RTC_RW (((BACKUP_V1_Type *) BACKUP)->RTC_RW) 587 #define BACKUP_CAL_CTL (((BACKUP_V1_Type *) BACKUP)->CAL_CTL) 588 #define BACKUP_ALM1_TIME (((BACKUP_V1_Type *) BACKUP)->ALM1_TIME) 589 #define BACKUP_ALM1_DATE (((BACKUP_V1_Type *) BACKUP)->ALM1_DATE) 590 #define BACKUP_ALM2_TIME (((BACKUP_V1_Type *) BACKUP)->ALM2_TIME) 591 #define BACKUP_ALM2_DATE (((BACKUP_V1_Type *) BACKUP)->ALM2_DATE) 592 #define BACKUP_STATUS (((BACKUP_V1_Type *) BACKUP)->STATUS) 593 #define BACKUP_INTR (((BACKUP_V1_Type *) BACKUP)->INTR) 594 #define BACKUP_INTR_SET (((BACKUP_V1_Type *) BACKUP)->INTR_SET) 595 #define BACKUP_INTR_MASK (((BACKUP_V1_Type *) BACKUP)->INTR_MASK) 596 #define BACKUP_INTR_MASKED (((BACKUP_V1_Type *) BACKUP)->INTR_MASKED) 597 #define BACKUP_RESET (((BACKUP_V1_Type *) BACKUP)->RESET) 598 #define BACKUP_TRIM (((BACKUP_V1_Type *) BACKUP)->TRIM) 599 600 #endif /* (defined(CY_DEVICE_TVIIBE)) */ 601 602 603 /******************************************************************************* 604 * CANFD 605 *******************************************************************************/ 606 607 #define CANFD_CTL(base) (((CANFD_V1_Type *)(base))->CTL) 608 #define CANFD_STATUS(base) (((CANFD_V1_Type *)(base))->STATUS) 609 #define CANFD_NBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NBTP) 610 #define CANFD_IR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IR) 611 #define CANFD_IE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.IE) 612 #define CANFD_ILS(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILS) 613 #define CANFD_ILE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.ILE) 614 #define CANFD_CCCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CCCR) 615 #define CANFD_SIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.SIDFC) 616 #define CANFD_XIDFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDFC) 617 #define CANFD_XIDAM(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.XIDAM) 618 #define CANFD_RXESC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXESC) 619 #define CANFD_RXF0C(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0C) 620 #define CANFD_RXF1C(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1C) 621 #define CANFD_RXFTOP_CTL(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP_CTL) 622 #define CANFD_RXBC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXBC) 623 #define CANFD_TXESC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXESC) 624 #define CANFD_TXEFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXEFC) 625 #define CANFD_TXBC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBC) 626 #define CANFD_DBTP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.DBTP) 627 #define CANFD_TDCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TDCR) 628 #define CANFD_GFC(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.GFC) 629 #define CANFD_TXBRP(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBRP) 630 #define CANFD_TXBAR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBAR) 631 #define CANFD_TXBCR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCR) 632 #define CANFD_TXBTO(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBTO) 633 #define CANFD_TXBCF(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCF) 634 #define CANFD_TXBTIE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBTIE) 635 #define CANFD_TXBCIE(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TXBCIE) 636 #define CANFD_NDAT1(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NDAT1) 637 #define CANFD_NDAT2(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.NDAT2) 638 #define CANFD_RXF0S(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0S) 639 #define CANFD_RXFTOP0_DATA(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP0_DATA) 640 #define CANFD_RXFTOP1_DATA(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].RXFTOP1_DATA) 641 #define CANFD_RXF0A(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF0A) 642 #define CANFD_RXF1S(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1S) 643 #define CANFD_RXF1A(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.RXF1A) 644 #define CANFD_PSR(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.PSR) 645 #define CANFD_TEST(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.TEST) 646 #define CANFD_CREL(base, chan) (((CANFD_V1_Type *)(base))->CH[chan].M_TTCAN.CREL) 647 648 #define CY_CANFD_CHANNELS_NUM (0x1UL) 649 650 651 /******************************************************************************* 652 * LIN 653 *******************************************************************************/ 654 #if defined (CY_IP_MXLIN) 655 #define LIN0_CH1 ((LIN_CH_Type*) &LIN0->CH[1]) 656 #define LIN0_CH2 ((LIN_CH_Type*) &LIN0->CH[2]) 657 #define LIN0_CH3 ((LIN_CH_Type*) &LIN0->CH[3]) 658 #define LIN0_CH4 ((LIN_CH_Type*) &LIN0->CH[4]) 659 #define LIN0_CH5 ((LIN_CH_Type*) &LIN0->CH[5]) 660 #define LIN0_CH6 ((LIN_CH_Type*) &LIN0->CH[6]) 661 #define LIN0_CH7 ((LIN_CH_Type*) &LIN0->CH[7]) 662 #define LIN0_CH8 ((LIN_CH_Type*) &LIN0->CH[8]) 663 #define LIN0_CH9 ((LIN_CH_Type*) &LIN0->CH[9]) 664 #define LIN0_CH10 ((LIN_CH_Type*) &LIN0->CH[10]) 665 #define LIN0_CH11 ((LIN_CH_Type*) &LIN0->CH[11]) 666 #define LIN0_CH12 ((LIN_CH_Type*) &LIN0->CH[12]) 667 #define LIN0_CH13 ((LIN_CH_Type*) &LIN0->CH[13]) 668 #define LIN0_CH14 ((LIN_CH_Type*) &LIN0->CH[14]) 669 #define LIN0_CH15 ((LIN_CH_Type*) &LIN0->CH[15]) 670 #define LIN0_CH16 ((LIN_CH_Type*) &LIN0->CH[16]) 671 #define LIN0_CH17 ((LIN_CH_Type*) &LIN0->CH[17]) 672 #define LIN0_CH18 ((LIN_CH_Type*) &LIN0->CH[18]) 673 #define LIN0_CH19 ((LIN_CH_Type*) &LIN0->CH[19]) 674 #define LIN0_CH20 ((LIN_CH_Type*) &LIN0->CH[20]) 675 #define LIN0_CH21 ((LIN_CH_Type*) &LIN0->CH[21]) 676 #define LIN0_CH22 ((LIN_CH_Type*) &LIN0->CH[22]) 677 #define LIN0_CH23 ((LIN_CH_Type*) &LIN0->CH[23]) 678 #define LIN0_CH24 ((LIN_CH_Type*) &LIN0->CH[24]) 679 #define LIN0_CH25 ((LIN_CH_Type*) &LIN0->CH[25]) 680 #define LIN0_CH26 ((LIN_CH_Type*) &LIN0->CH[26]) 681 #define LIN0_CH27 ((LIN_CH_Type*) &LIN0->CH[27]) 682 #define LIN0_CH28 ((LIN_CH_Type*) &LIN0->CH[28]) 683 #define LIN0_CH29 ((LIN_CH_Type*) &LIN0->CH[29]) 684 #define LIN0_CH30 ((LIN_CH_Type*) &LIN0->CH[30]) 685 #define LIN0_CH31 ((LIN_CH_Type*) &LIN0->CH[31]) 686 687 #define LIN_CH_CTL0(base) (((LIN_CH_Type *)(base))->CTL0) 688 #define LIN_CH_CTL1(base) (((LIN_CH_Type *)(base))->CTL1) 689 #define LIN_CH_STATUS(base) (((LIN_CH_Type *)(base))->STATUS) 690 #define LIN_CH_CMD(base) (((LIN_CH_Type *)(base))->CMD) 691 #define LIN_CH_TX_RX_STATUS(base) (((LIN_CH_Type *)(base))->TX_RX_STATUS) 692 #define LIN_CH_PID_CHECKSUM(base) (((LIN_CH_Type *)(base))->PID_CHECKSUM) 693 #define LIN_CH_DATA0(base) (((LIN_CH_Type *)(base))->DATA0) 694 #define LIN_CH_DATA1(base) (((LIN_CH_Type *)(base))->DATA1) 695 #define LIN_CH_INTR(base) (((LIN_CH_Type *)(base))->INTR) 696 #define LIN_CH_INTR_SET(base) (((LIN_CH_Type *)(base))->INTR_SET) 697 #define LIN_CH_INTR_MASK(base) (((LIN_CH_Type *)(base))->INTR_MASK) 698 #define LIN_CH_INTR_MASKED(base) (((LIN_CH_Type *)(base))->INTR_MASKED) 699 700 #define LIN_ERROR_CTL(base) (((LIN_Type *)(base))->ERROR_CTL) 701 #define LIN_TEST_CTL(base) (((LIN_Type *)(base))->TEST_CTL) 702 #endif /* CY_IP_MXLIN */ 703 704 /******************************************************************************* 705 * FLASHC 706 *******************************************************************************/ 707 #if (defined (CPUSS_FLASHC_PRESENT) && (CPUSS_FLASHC_PRESENT == 1)) && (defined (CPUSS_FLASHC_ECT) && (CPUSS_FLASHC_ECT == 1)) 708 #define CY_IP_MXFLASHC_VERSION_ECT 709 #endif 710 711 #if defined (CY_DEVICE_TVIIBE) 712 #define FLASHC_FLASH_CMD (((FLASHC_Type *)(FLASHC))->FLASH_CMD) 713 #define FLASHC_FLASH_CTL (((FLASHC_Type *)(FLASHC))->FLASH_CTL) 714 #define FLASHC_ECC_CTL (((FLASHC_Type *)(FLASHC))->ECC_CTL) 715 716 /* FLASH Memory */ 717 #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->WORK_FLASH_SAFETY) 718 #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY (((FLASHC_FM_CTL_ECT_V2_Type *)(FLASHC_FM_CTL_ECT))->MAIN_FLASH_SAFETY) 719 #define FLASHC_FM_CTL_ECT_FLASH_STATUS (((FLASHC_FM_CTL_ECT_V2_Type *)(FLASHC_FM_CTL_ECT))->STATUS) 720 721 #else 722 #define FLASHC_FM_CTL_ANA_CTL0 (((FLASHC_V1_Type *) cy_device->flashcBase)->FM_CTL.ANA_CTL0) 723 #define FLASHC_FM_CTL_BOOKMARK (((FLASHC_V1_Type *) cy_device->flashcBase)->FM_CTL.BOOKMARK) 724 #define FLASHC_FLASH_CMD (((FLASHC_V1_Type *) cy_device->flashcBase)->FLASH_CMD) 725 #define FLASHC_FLASH_CTL (((FLASHC_V1_Type *) cy_device->flashcBase)->FLASH_CTL) 726 #define FLASHC_BIST_DATA_0 (((FLASHC_V1_Type *) cy_device->flashcBase)->BIST_DATA[0U]) 727 #define FLASHC_BIST_STATUS (((FLASHC_V1_Type *) cy_device->flashcBase)->BIST_STATUS) 728 #endif 729 730 731 /******************************************************************************* 732 * SFLASH 733 *******************************************************************************/ 734 #if !(defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u)) 735 736 #define SFLASH_DIE_YEAR (((SFLASH_V1_Type *) SFLASH)->DIE_YEAR) 737 #define SFLASH_DIE_MINOR (((SFLASH_V1_Type *) SFLASH)->DIE_MINOR) 738 #define SFLASH_DIE_SORT (((SFLASH_V1_Type *) SFLASH)->DIE_SORT) 739 #define SFLASH_DIE_Y (((SFLASH_V1_Type *) SFLASH)->DIE_Y) 740 #define SFLASH_DIE_X (((SFLASH_V1_Type *) SFLASH)->DIE_X) 741 #define SFLASH_DIE_WAFER (((SFLASH_V1_Type *) SFLASH)->DIE_WAFER) 742 #define SFLASH_DIE_LOT(val) (((SFLASH_V1_Type *) SFLASH)->DIE_LOT[(val)]) 743 #define SFLASH_FAMILY_ID (((SFLASH_V1_Type *) SFLASH)->FAMILY_ID) 744 #define SFLASH_SI_REVISION_ID (((SFLASH_V1_Type *) SFLASH)->SI_REVISION_ID) 745 #define SFLASH_PWR_TRIM_WAKE_CTL (((SFLASH_V1_Type *) SFLASH)->PWR_TRIM_WAKE_CTL) 746 #define SFLASH_LDO_0P9V_TRIM (((SFLASH_V1_Type *) SFLASH)->LDO_0P9V_TRIM) 747 #define SFLASH_LDO_1P1V_TRIM (((SFLASH_V1_Type *) SFLASH)->LDO_1P1V_TRIM) 748 #define SFLASH_BLE_DEVICE_ADDRESS (((SFLASH_V1_Type *) SFLASH)->BLE_DEVICE_ADDRESS) 749 #define SFLASH_SILICON_ID (((SFLASH_V1_Type *) SFLASH)->SILICON_ID) 750 #define SFLASH_SINGLE_CORE (*(volatile uint8_t *) (SFLASH_BASE + 0xBU)) 751 752 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_LP) 753 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_LP) 754 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP) 755 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP) 756 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP) 757 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP) 758 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP) 759 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP) 760 761 #define SFLASH_CSD0_ADC_VREF0_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF0) 762 #define SFLASH_CSD0_ADC_VREF1_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF1) 763 #define SFLASH_CSD0_ADC_VREF2_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF2) 764 765 #endif /* defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1u) */ 766 767 768 /******************************************************************************* 769 * CPUSS 770 *******************************************************************************/ 771 772 #define CY_CPUSS_V1 (0x20U > cy_device->cpussVersion) 773 774 #define CY_CPUSS_NOT_CONNECTED_IRQN ((uint32_t)(cy_device->cpussNotConnectedIrq)) 775 #define CY_CPUSS_DISCONNECTED_IRQN ((cy_en_intr_t)CY_CPUSS_NOT_CONNECTED_IRQN) 776 #define CY_CPUSS_UNCONNECTED_IRQN ((IRQn_Type)CY_CPUSS_NOT_CONNECTED_IRQN) 777 778 #define CPUSS_CM0_CLOCK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0ClockCtlOffset)) 779 #define CPUSS_CM4_CLOCK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4ClockCtlOffset)) 780 #define CPUSS_CM4_STATUS (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4StatusOffset)) 781 #define CPUSS_CM0_STATUS (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0StatusOffset)) 782 #define CPUSS_CM4_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4PwrCtlOffset)) 783 #define CPUSS_TRIM_RAM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussTrimRamCtlOffset)) 784 #define CPUSS_TRIM_ROM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussTrimRomCtlOffset)) 785 #define CPUSS_SYSTICK_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussSysTickCtlOffset)) 786 787 #define CPUSS_ROM_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRomCtl)) 788 #define CPUSS_RAM0_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam0Ctl0)) 789 #define CPUSS_RAM0_PWR_MACRO_CTL(macroIdx) ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_PWR_MACRO_CTL[(macroIdx)])) 790 #define CPUSS_RAM1_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam1Ctl0)) 791 #define CPUSS_RAM2_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam2Ctl0)) 792 #define CPUSS_RAM0_PWR_CTL(macroIdx) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam0PwrCtl))[(macroIdx)]) 793 #define CPUSS_RAM1_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam1PwrCtl)) 794 #define CPUSS_RAM2_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussRam2PwrCtl)) 795 796 #define CPUSS_CM0_NMI_CTL(nmi) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm0NmiCtlOffset))[(nmi)]) 797 #define CPUSS_CM4_NMI_CTL(nmi) (((volatile uint32_t *) (cy_device->cpussBase + cy_device->cpussCm4NmiCtlOffset))[(nmi)]) 798 799 /* used in V1 code only */ 800 #define CPUSS_CM0_INT_CTL ((volatile uint32_t *) &(((CPUSS_V1_Type *)(cy_device->cpussBase))->CM0_INT_CTL0)) 801 802 /* used in V2 code only */ 803 #define CPUSS_CM0_SYSTEM_INT_CTL (((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_SYSTEM_INT_CTL) 804 #define CPUSS_CM0_INT_STATUS ((volatile const uint32_t *) &(((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_INT0_STATUS)) 805 #define CPUSS_CM4_SYSTEM_INT_CTL (((CPUSS_V2_Type *)(cy_device->cpussBase))->CM4_SYSTEM_INT_CTL) 806 #define CPUSS_CM4_INT_STATUS ((volatile const uint32_t *) &(((CPUSS_V2_Type *)(cy_device->cpussBase))->CM4_INT0_STATUS)) 807 808 #define CPUSS_SRAM_COUNT (1u + CPUSS_RAMC1_PRESENT + CPUSS_RAMC2_PRESENT) 809 810 #if defined(CY_IP_M4CPUSS_VERSION) && (CY_IP_M4CPUSS_VERSION == 2u) 811 #define CPUSS_PRODUCT_ID (((CPUSS_Type*) CPUSS_BASE)->PRODUCT_ID) 812 #endif 813 814 /* ARM core registers */ 815 #define SYSTICK_CTRL (((SysTick_Type *)SysTick)->CTRL) 816 #define SYSTICK_LOAD (((SysTick_Type *)SysTick)->LOAD) 817 #define SYSTICK_VAL (((SysTick_Type *)SysTick)->VAL) 818 #define SCB_SCR (((SCB_Type *)SCB)->SCR) 819 820 #define UDB_UDBIF_BANK_CTL (((UDB_V1_Type *) cy_device->udbBase)->UDBIF.BANK_CTL) 821 #define UDB_BCTL_MDCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN) 822 #define UDB_BCTL_MBCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MBCLK_EN) 823 #define UDB_BCTL_BOTSEL_L (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_L) 824 #define UDB_BCTL_BOTSEL_U (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_U) 825 #define UDB_BCTL_QCLK_EN_0 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U]) 826 #define UDB_BCTL_QCLK_EN_1 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U]) 827 #define UDB_BCTL_QCLK_EN_2 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U]) 828 829 830 /******************************************************************************* 831 * FAULT 832 *******************************************************************************/ 833 #if defined (CY_DEVICE_TVIIBE) 834 835 #if defined(CPUSS_FAULT_FAULT_NR) && (CPUSS_FAULT_FAULT_NR > 0) 836 #define CY_IP_MXS40FAULT (1u) 837 #endif 838 839 #define FAULT_CTL(base) (((FAULT_STRUCT_Type *)(base))->CTL) 840 #define FAULT_STATUS(base) (((FAULT_STRUCT_Type *)(base))->STATUS) 841 #define FAULT_DATA(base) (((FAULT_STRUCT_Type *)(base))->DATA) 842 #define FAULT_PENDING0(base) (((FAULT_STRUCT_Type *)(base))->PENDING0) 843 #define FAULT_PENDING1(base) (((FAULT_STRUCT_Type *)(base))->PENDING1) 844 #define FAULT_PENDING2(base) (((FAULT_STRUCT_Type *)(base))->PENDING2) 845 #define FAULT_MASK0(base) (((FAULT_STRUCT_Type *)(base))->MASK0) 846 #define FAULT_MASK1(base) (((FAULT_STRUCT_Type *)(base))->MASK1) 847 #define FAULT_MASK2(base) (((FAULT_STRUCT_Type *)(base))->MASK2) 848 #define FAULT_INTR(base) (((FAULT_STRUCT_Type *)(base))->INTR) 849 #define FAULT_INTR_SET(base) (((FAULT_STRUCT_Type *)(base))->INTR_SET) 850 #define FAULT_INTR_MASK(base) (((FAULT_STRUCT_Type *)(base))->INTR_MASK) 851 #define FAULT_INTR_MASKED(base) (((FAULT_STRUCT_Type *)(base))->INTR_MASKED) 852 #endif 853 854 /******************************************************************************* 855 * LPCOMP 856 *******************************************************************************/ 857 858 #define LPCOMP_CMP0_CTRL(base) (((LPCOMP_Type *)(base))->CMP0_CTRL) 859 #define LPCOMP_CMP1_CTRL(base) (((LPCOMP_Type *)(base))->CMP1_CTRL) 860 #define LPCOMP_CMP0_SW_CLEAR(base) (((LPCOMP_Type *)(base))->CMP0_SW_CLEAR) 861 #define LPCOMP_CMP1_SW_CLEAR(base) (((LPCOMP_Type *)(base))->CMP1_SW_CLEAR) 862 #define LPCOMP_CMP0_SW(base) (((LPCOMP_Type *)(base))->CMP0_SW) 863 #define LPCOMP_CMP1_SW(base) (((LPCOMP_Type *)(base))->CMP1_SW) 864 #define LPCOMP_STATUS(base) (((LPCOMP_Type *)(base))->STATUS) 865 #define LPCOMP_CONFIG(base) (((LPCOMP_Type *)(base))->CONFIG) 866 #define LPCOMP_INTR(base) (((LPCOMP_Type *)(base))->INTR) 867 #define LPCOMP_INTR_SET(base) (((LPCOMP_Type *)(base))->INTR_SET) 868 #define LPCOMP_INTR_MASK(base) (((LPCOMP_Type *)(base))->INTR_MASK) 869 #define LPCOMP_INTR_MASKED(base) (((LPCOMP_Type *)(base))->INTR_MASKED) 870 871 872 /******************************************************************************* 873 * MCWDT 874 *******************************************************************************/ 875 876 #if defined (CY_DEVICE_TVIIBE) 877 #define MCWDT_CTR_CTL(base, counter) (((MCWDT_Type *)(base))->CTR[counter].CTL) 878 #define MCWDT_CTR_LOWER_LIMIT(base, counter) (((MCWDT_Type *)(base))->CTR[counter].LOWER_LIMIT) 879 #define MCWDT_CTR_UPPER_LIMIT(base, counter) (((MCWDT_Type *)(base))->CTR[counter].UPPER_LIMIT) 880 #define MCWDT_CTR_WARN_LIMIT(base, counter) (((MCWDT_Type *)(base))->CTR[counter].WARN_LIMIT) 881 #define MCWDT_CTR_CONFIG(base, counter) (((MCWDT_Type *)(base))->CTR[counter].CONFIG) 882 #define MCWDT_CTR_CNT(base, counter) (((MCWDT_Type *)(base))->CTR[counter].CNT) 883 #define MCWDT_CPU_SELECT(base) (((MCWDT_Type *)(base))->CPU_SELECT) 884 #define MCWDT_CTR2_CTL(base) (((MCWDT_Type *)(base))->CTR2_CTL) 885 #define MCWDT_CTR2_CONFIG(base) (((MCWDT_Type *)(base))->CTR2_CONFIG) 886 #define MCWDT_CTR2_CNT(base) (((MCWDT_Type *)(base))->CTR2_CNT) 887 #define MCWDT_LOCK(base) (((MCWDT_Type *)(base))->LOCK) 888 #define MCWDT_SERVICE(base) (((MCWDT_Type *)(base))->SERVICE) 889 #define MCWDT_INTR(base) (((MCWDT_Type *)(base))->INTR) 890 #define MCWDT_INTR_SET(base) (((MCWDT_Type *)(base))->INTR_SET) 891 #define MCWDT_INTR_MASK(base) (((MCWDT_Type *)(base))->INTR_MASK) 892 #define MCWDT_INTR_MASKED(base) (((MCWDT_Type *)(base))->INTR_MASKED) 893 #else 894 #define MCWDT_CNTLOW(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CNTLOW) 895 #define MCWDT_CNTHIGH(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CNTHIGH) 896 #define MCWDT_MATCH(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_MATCH) 897 #define MCWDT_CONFIG(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CONFIG) 898 #define MCWDT_LOCK(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_LOCK) 899 #define MCWDT_CTL(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CTL) 900 #define MCWDT_INTR(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR) 901 #define MCWDT_INTR_SET(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_SET) 902 #define MCWDT_INTR_MASK(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_MASK) 903 #define MCWDT_INTR_MASKED(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_MASKED) 904 #endif 905 906 907 /******************************************************************************* 908 * TCPWM 909 *******************************************************************************/ 910 911 #define TCPWM_CTRL_SET(base) (((TCPWM_V1_Type *)(base))->CTRL_SET) 912 #define TCPWM_CTRL_CLR(base) (((TCPWM_V1_Type *)(base))->CTRL_CLR) 913 #define TCPWM_CMD_START(base) (((TCPWM_V1_Type *)(base))->CMD_START) 914 #define TCPWM_CMD_RELOAD(base) (((TCPWM_V1_Type *)(base))->CMD_RELOAD) 915 #define TCPWM_CMD_STOP(base) (((TCPWM_V1_Type *)(base))->CMD_STOP) 916 #define TCPWM_CMD_CAPTURE(base) (((TCPWM_V1_Type *)(base))->CMD_CAPTURE) 917 918 #define TCPWM_CNT_CTRL(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CTRL) 919 #define TCPWM_CNT_CC(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CC) 920 #define TCPWM_CNT_CC_BUFF(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].CC_BUFF) 921 #define TCPWM_CNT_COUNTER(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].COUNTER) 922 #define TCPWM_CNT_PERIOD(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].PERIOD) 923 #define TCPWM_CNT_PERIOD_BUFF(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].PERIOD_BUFF) 924 #define TCPWM_CNT_STATUS(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].STATUS) 925 #define TCPWM_CNT_INTR(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR) 926 #define TCPWM_CNT_INTR_SET(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_SET) 927 #define TCPWM_CNT_INTR_MASK(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_MASK) 928 #define TCPWM_CNT_INTR_MASKED(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].INTR_MASKED) 929 #define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL0) 930 #define TCPWM_CNT_TR_CTRL1(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL1) 931 #define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_V1_Type *)(base))->CNT[cntNum].TR_CTRL2) 932 933 #if defined (CY_DEVICE_TVIIBE) 934 935 #if (CY_IP_MXTCPWM_INSTANCES == 1UL) 936 #define TCPWM_GRP_CC1_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) 937 #define TCPWM_GRP_AMC_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) 938 #define TCPWM_GRP_SMC_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) 939 #endif 940 941 #if (CY_IP_MXTCPWM_INSTANCES == 2UL) 942 #define TCPWM_GRP_CC1_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))) 943 #define TCPWM_GRP_AMC_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))) 944 #define TCPWM_GRP_SMC_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))) 945 #endif 946 947 #define TCPWM_GRP_CC1(base, grp) ((bool)(((TCPWM_GRP_CC1_PRESENT_STATUS(base)) >> (grp)) & 0x01U)) 948 #define TCPWM_GRP_AMC(base, grp) ((bool)(((TCPWM_GRP_AMC_PRESENT_STATUS(base)) >> (grp)) & 0x01U)) 949 #define TCPWM_GRP_SMC(base, grp) ((bool)(((TCPWM_GRP_SMC_PRESENT_STATUS(base)) >> (grp)) & 0x01U)) 950 951 #else /* PSoC Devices */ 952 953 #define TCPWM_GRP_CC1(base, grp) ((((cy_device->tcpwmCC1Present) >> (grp)) & 0x01U) != 0U) 954 #define TCPWM_GRP_AMC(base, grp) ((((cy_device->tcpwmAMCPresent) >> (grp)) & 0x01U) != 0U) 955 #define TCPWM_GRP_SMC(base, grp) ((((cy_device->tcpwmSMCPrecent) >> (grp)) & 0x01U) != 0U) 956 957 #endif /* defined(CY_DEVICE_TVIIBE) */ 958 959 #define TCPWM_GRP_CNT_GET_GRP(cntNum) ((cntNum )/ 256U) 960 961 #define TCPWM_GRP_CNT_CTRL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CTRL) 962 #define TCPWM_GRP_CNT_STATUS(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].STATUS) 963 #define TCPWM_GRP_CNT_COUNTER(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].COUNTER) 964 #define TCPWM_GRP_CNT_CC0(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0) 965 #define TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0_BUFF) 966 #define TCPWM_GRP_CNT_CC1(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1) 967 #define TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1_BUFF) 968 #define TCPWM_GRP_CNT_PERIOD(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD) 969 #define TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD_BUFF) 970 #define TCPWM_GRP_CNT_LINE_SEL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL) 971 #define TCPWM_GRP_CNT_LINE_SEL_BUFF(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL_BUFF) 972 #define TCPWM_GRP_CNT_DT(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT) 973 #define TCPWM_GRP_CNT_TR_CMD(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_CMD) 974 #define TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL0) 975 #define TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL1) 976 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_EDGE_SEL) 977 #define TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_PWM_CTRL) 978 #define TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_OUT_SEL) 979 #define TCPWM_GRP_CNT_INTR(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR) 980 #define TCPWM_GRP_CNT_INTR_SET(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_SET) 981 #define TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASK) 982 #define TCPWM_GRP_CNT_INTR_MASKED(base, grp, cntNum) (((TCPWM_V2_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASKED) 983 984 #if defined (CY_DEVICE_TVIIBE) 985 /* For backward compatibility, TCPWM_CNT_STATUS_RUNNING_Pos was set to the 986 * value of TCPWM_GRP_CNT_V2_STATUS_RUNNING. This needs to be defined for version 2 only. 987 */ 988 #define TCPWM_CNT_STATUS_RUNNING_Pos (31UL) 989 #endif 990 991 992 /******************************************************************************* 993 * SAR 994 *******************************************************************************/ 995 996 #define CY_SAR_INSTANCES (2UL) 997 #define CY_SAR0_BASE ((SAR_Type*)(cy_device->sar0Base)) 998 #define CY_SAR_INSTANCE(base) ((CY_SAR0_BASE == (base)) ? 0UL : 1UL) 999 1000 #define SAR_SAMPLE_CTRL(base) (((SAR_V1_Type *)(base))->SAMPLE_CTRL) 1001 #define SAR_SAMPLE_TIME01(base) (((SAR_V1_Type *)(base))->SAMPLE_TIME01) 1002 #define SAR_SAMPLE_TIME23(base) (((SAR_V1_Type *)(base))->SAMPLE_TIME23) 1003 1004 #define SAR_RANGE_THRES(base) (((SAR_V1_Type *)(base))->RANGE_THRES) 1005 #define SAR_RANGE_COND(base) (((SAR_V1_Type *)(base))->RANGE_COND) 1006 #define SAR_RANGE_INTR(base) (((SAR_V1_Type *)(base))->RANGE_INTR) 1007 #define SAR_RANGE_INTR_SET(base) (((SAR_V1_Type *)(base))->RANGE_INTR_SET) 1008 1009 #define SAR_RANGE_INTR_MASK(base) (((SAR_V1_Type *)(base))->RANGE_INTR_MASK) 1010 #define SAR_RANGE_INTR_MASKED(base) (((SAR_V1_Type *)(base))->RANGE_INTR_MASKED) 1011 1012 #define SAR_CHAN_EN(base) (((SAR_V1_Type *)(base))->CHAN_EN) 1013 #define SAR_CHAN_CONFIG(base, chan) (((SAR_V1_Type *)(base))->CHAN_CONFIG[(chan)]) 1014 #define SAR_CHAN_RESULT(base, chan ) (((SAR_V1_Type *)(base))->CHAN_RESULT[(chan)]) 1015 #define SAR_CHAN_RESULT_UPDATED(base) (((SAR_V1_Type *)(base))->CHAN_RESULT_UPDATED) 1016 1017 #define SAR_INTR(base) (((SAR_V1_Type *)(base))->INTR) 1018 #define SAR_INTR_MASK(base) (((SAR_V1_Type *)(base))->INTR_MASK) 1019 #define SAR_INTR_MASKED(base) (((SAR_V1_Type *)(base))->INTR_MASKED) 1020 #define SAR_INTR_SET(base) (((SAR_V1_Type *)(base))->INTR_SET) 1021 #define SAR_INTR_CAUSE(base) (((SAR_V1_Type *)(base))->INTR_CAUSE) 1022 1023 #define SAR_MUX_SWITCH_CLEAR0(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_CLEAR0) 1024 #define SAR_MUX_SWITCH0(base) (((SAR_V1_Type *)(base))->MUX_SWITCH0) 1025 #define SAR_MUX_SWITCH_SQ_CTRL(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_SQ_CTRL) 1026 #define SAR_MUX_SWITCH_DS_CTRL(base) (((SAR_V1_Type *)(base))->MUX_SWITCH_DS_CTRL) 1027 1028 #define SAR_ANA_TRIM0(base) (((SAR_V1_Type *)(base))->ANA_TRIM0) 1029 #define SAR_CTRL(base) (((SAR_V1_Type *)(base))->CTRL) 1030 #define SAR_STATUS(base) (((SAR_V1_Type *)(base))->STATUS) 1031 #define SAR_START_CTRL(base) (((SAR_V1_Type *)(base))->START_CTRL) 1032 1033 #define SAR_SATURATE_INTR(base) (((SAR_V1_Type *)(base))->SATURATE_INTR) 1034 #define SAR_SATURATE_INTR_MASK(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_MASK) 1035 #define SAR_SATURATE_INTR_MASKED(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_MASKED) 1036 #define SAR_SATURATE_INTR_SET(base) (((SAR_V1_Type *)(base))->SATURATE_INTR_SET) 1037 1038 #define SAR_INJ_CHAN_CONFIG(base) (((SAR_V1_Type *)(base))->INJ_CHAN_CONFIG) 1039 #define SAR_INJ_RESULT(base) (((SAR_V1_Type *)(base))->INJ_RESULT) 1040 1041 /******************************************************************************* 1042 * SDHC 1043 *******************************************************************************/ 1044 1045 #define SDHC_WRAP_CTL(base) (((SDHC_V1_Type *)(base))->WRAP.CTL) 1046 #define SDHC_CORE_SDMASA_R(base) (((SDHC_V1_Type *)(base))->CORE.SDMASA_R) 1047 #define SDHC_CORE_BLOCKSIZE_R(base) (((SDHC_V1_Type *)(base))->CORE.BLOCKSIZE_R) 1048 #define SDHC_CORE_BLOCKCOUNT_R(base) (((SDHC_V1_Type *)(base))->CORE.BLOCKCOUNT_R) 1049 #define SDHC_CORE_ARGUMENT_R(base) (((SDHC_V1_Type *)(base))->CORE.ARGUMENT_R) 1050 #define SDHC_CORE_XFER_MODE_R(base) (((SDHC_V1_Type *)(base))->CORE.XFER_MODE_R) 1051 #define SDHC_CORE_CMD_R(base) (((SDHC_V1_Type *)(base))->CORE.CMD_R) 1052 #define SDHC_CORE_RESP01_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP01_R) 1053 #define SDHC_CORE_RESP23_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP23_R) 1054 #define SDHC_CORE_RESP45_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP45_R) 1055 #define SDHC_CORE_RESP67_R(base) (((SDHC_V1_Type *)(base))->CORE.RESP67_R) 1056 #define SDHC_CORE_BUF_DATA_R(base) (((SDHC_V1_Type *)(base))->CORE.BUF_DATA_R) 1057 #define SDHC_CORE_PSTATE_REG(base) (((SDHC_V1_Type *)(base))->CORE.PSTATE_REG) 1058 #define SDHC_CORE_HOST_CTRL1_R(base) (((SDHC_V1_Type *)(base))->CORE.HOST_CTRL1_R) 1059 #define SDHC_CORE_PWR_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.PWR_CTRL_R) 1060 #define SDHC_CORE_BGAP_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.BGAP_CTRL_R) 1061 #define SDHC_CORE_WUP_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.WUP_CTRL_R) 1062 #define SDHC_CORE_CLK_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.CLK_CTRL_R) 1063 #define SDHC_CORE_TOUT_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.TOUT_CTRL_R) 1064 #define SDHC_CORE_SW_RST_R(base) (((SDHC_V1_Type *)(base))->CORE.SW_RST_R) 1065 #define SDHC_CORE_NORMAL_INT_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_STAT_R) 1066 #define SDHC_CORE_ERROR_INT_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_STAT_R) 1067 #define SDHC_CORE_NORMAL_INT_STAT_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R) 1068 #define SDHC_CORE_ERROR_INT_STAT_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_STAT_EN_R) 1069 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R) 1070 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base) (((SDHC_V1_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R) 1071 #define SDHC_CORE_AUTO_CMD_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.AUTO_CMD_STAT_R) 1072 #define SDHC_CORE_HOST_CTRL2_R(base) (((SDHC_V1_Type *)(base))->CORE.HOST_CTRL2_R) 1073 #define SDHC_CORE_CAPABILITIES1_R(base) (((SDHC_V1_Type *)(base))->CORE.CAPABILITIES1_R) 1074 #define SDHC_CORE_CAPABILITIES2_R(base) (((SDHC_V1_Type *)(base))->CORE.CAPABILITIES2_R) 1075 #define SDHC_CORE_CURR_CAPABILITIES1_R(base) (((SDHC_V1_Type *)(base))->CORE.CURR_CAPABILITIES1_R) 1076 #define SDHC_CORE_CURR_CAPABILITIES2_R(base) (((SDHC_V1_Type *)(base))->CORE.CURR_CAPABILITIES2_R) 1077 #define SDHC_CORE_ADMA_ERR_STAT_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_ERR_STAT_R) 1078 #define SDHC_CORE_ADMA_SA_LOW_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_SA_LOW_R) 1079 #define SDHC_CORE_ADMA_ID_LOW_R(base) (((SDHC_V1_Type *)(base))->CORE.ADMA_ID_LOW_R) 1080 #define SDHC_CORE_EMMC_CTRL_R(base) (((SDHC_V1_Type *)(base))->CORE.EMMC_CTRL_R) 1081 #define SDHC_CORE_GP_OUT_R(base) (((SDHC_V1_Type *)(base))->CORE.GP_OUT_R) 1082 1083 1084 /******************************************************************************* 1085 * SMARTIO 1086 *******************************************************************************/ 1087 1088 #define SMARTIO_PRT_CTL(base) (((SMARTIO_PRT_Type *)(base))->CTL) 1089 #define SMARTIO_PRT_SYNC_CTL(base) (((SMARTIO_PRT_Type *)(base))->SYNC_CTL) 1090 #define SMARTIO_PRT_LUT_SEL(base, idx) (((SMARTIO_PRT_Type *)(base))->LUT_SEL[idx]) 1091 #define SMARTIO_PRT_LUT_CTL(base, idx) (((SMARTIO_PRT_Type *)(base))->LUT_CTL[idx]) 1092 #define SMARTIO_PRT_DU_SEL(base) (((SMARTIO_PRT_Type *)(base))->DU_SEL) 1093 #define SMARTIO_PRT_DU_CTL(base) (((SMARTIO_PRT_Type *)(base))->DU_CTL) 1094 #define SMARTIO_PRT_DATA(base) (((SMARTIO_PRT_Type *)(base))->DATA) 1095 1096 1097 #if (defined (CY_IP_MXTDM)) 1098 /******************************************************************************* 1099 * TDM 1100 *******************************************************************************/ 1101 1102 #define TDM_STRUCT_Type TDM_TDM_STRUCT_Type 1103 #define TDM_TX_STRUCT_Type TDM_TDM_STRUCT_TDM_TX_STRUCT_Type 1104 #define TDM_RX_STRUCT_Type TDM_TDM_STRUCT_TDM_RX_STRUCT_Type 1105 #define TDM_STRUCT0 TDM0_TDM_STRUCT0 1106 #define TDM_STRUCT1 TDM0_TDM_STRUCT1 1107 #define TDM_STRUCT0_TX TDM0_TDM_STRUCT0_TDM_TX_STRUCT 1108 #define TDM_STRUCT1_TX TDM0_TDM_STRUCT1_TDM_TX_STRUCT 1109 #define TDM_STRUCT0_RX TDM0_TDM_STRUCT0_TDM_RX_STRUCT 1110 #define TDM_STRUCT1_RX TDM0_TDM_STRUCT1_TDM_RX_STRUCT 1111 #define TDM_STRUCT_TX_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_CTL) 1112 #define TDM_STRUCT_TX_IF_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_IF_CTL) 1113 #define TDM_STRUCT_TX_CH_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_CH_CTL) 1114 #define TDM_STRUCT_TX_TEST_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_TEST_CTL) 1115 #define TDM_STRUCT_TX_ROUTE_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_ROUTE_CTL) 1116 #define TDM_STRUCT_TX_FIFO_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_CTL) 1117 #define TDM_STRUCT_TX_FIFO_STATUS(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_STATUS) 1118 #define TDM_STRUCT_TX_FIFO_WR(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_WR) 1119 #define TDM_STRUCT_TX_INTR_TX(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX) 1120 #define TDM_STRUCT_TX_INTR_TX_SET(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_SET) 1121 #define TDM_STRUCT_TX_INTR_TX_MASK(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_MASK) 1122 #define TDM_STRUCT_TX_INTR_TX_MASKED(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_MASKED) 1123 1124 #define TDM_STRUCT_RX_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_CTL) 1125 #define TDM_STRUCT_RX_IF_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_IF_CTL) 1126 #define TDM_STRUCT_RX_CH_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_CH_CTL) 1127 #define TDM_STRUCT_RX_TEST_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_TEST_CTL) 1128 #define TDM_STRUCT_RX_ROUTE_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_ROUTE_CTL) 1129 #define TDM_STRUCT_RX_FIFO_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_CTL) 1130 #define TDM_STRUCT_RX_FIFO_STATUS(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_STATUS) 1131 #define TDM_STRUCT_RX_FIFO_RD(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_RD) 1132 #define TDM_STRUCT_RX_FIFO_RD_SILENT(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_RD_SILENT) 1133 #define TDM_STRUCT_RX_INTR_RX(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX) 1134 #define TDM_STRUCT_RX_INTR_RX_SET(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_SET) 1135 #define TDM_STRUCT_RX_INTR_RX_MASK(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_MASK) 1136 #define TDM_STRUCT_RX_INTR_RX_MASKED(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_MASKED) 1137 #endif /* CY_IP_MXTDM */ 1138 1139 1140 /******************************************************************************* 1141 * SMIF 1142 *******************************************************************************/ 1143 1144 #define SMIF_DEVICE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->CTL) 1145 #define SMIF_DEVICE_ADDR(base) (((SMIF_DEVICE_V1_Type *)(base))->ADDR) 1146 #define SMIF_DEVICE_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->ADDR_CTL) 1147 #define SMIF_DEVICE_MASK(base) (((SMIF_DEVICE_V1_Type *)(base))->MASK) 1148 #define SMIF_DEVICE_RD_CMD_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_CMD_CTL) 1149 #define SMIF_DEVICE_RD_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_ADDR_CTL) 1150 #define SMIF_DEVICE_RD_MODE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_MODE_CTL) 1151 #define SMIF_DEVICE_RD_DUMMY_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_DUMMY_CTL) 1152 #define SMIF_DEVICE_RD_DATA_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->RD_DATA_CTL) 1153 #define SMIF_DEVICE_WR_CMD_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_CMD_CTL) 1154 #define SMIF_DEVICE_WR_ADDR_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_ADDR_CTL) 1155 #define SMIF_DEVICE_WR_MODE_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_MODE_CTL) 1156 #define SMIF_DEVICE_WR_DUMMY_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_DUMMY_CTL) 1157 #define SMIF_DEVICE_WR_DATA_CTL(base) (((SMIF_DEVICE_V1_Type *)(base))->WR_DATA_CTL) 1158 1159 #define SMIF_DEVICE_IDX(base, deviceIndex) (((SMIF_V1_Type *)(base))->DEVICE[deviceIndex]) 1160 1161 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).CTL) 1162 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR) 1163 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL) 1164 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).MASK) 1165 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL) 1166 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL) 1167 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL) 1168 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL) 1169 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL) 1170 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL) 1171 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL) 1172 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL) 1173 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL) 1174 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL) 1175 1176 #define SMIF_CTL(base) (((SMIF_V1_Type *)(base))->CTL) 1177 #define SMIF_STATUS(base) (((SMIF_V1_Type *)(base))->STATUS) 1178 #define SMIF_TX_DATA_FIFO_CTL(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_CTL) 1179 #define SMIF_RX_DATA_FIFO_CTL(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_CTL) 1180 #define SMIF_TX_DATA_FIFO_WR1(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR1) 1181 #define SMIF_TX_DATA_FIFO_WR2(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR2) 1182 #define SMIF_TX_DATA_FIFO_WR4(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_WR4) 1183 #define SMIF_RX_DATA_FIFO_RD1(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD1) 1184 #define SMIF_RX_DATA_FIFO_RD2(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD2) 1185 #define SMIF_RX_DATA_FIFO_RD4(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_RD4) 1186 #define SMIF_TX_CMD_FIFO_WR(base) (((SMIF_V1_Type *)(base))->TX_CMD_FIFO_WR) 1187 #define SMIF_TX_CMD_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->TX_CMD_FIFO_STATUS) 1188 #define SMIF_RX_DATA_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->RX_DATA_FIFO_STATUS) 1189 #define SMIF_TX_DATA_FIFO_STATUS(base) (((SMIF_V1_Type *)(base))->TX_DATA_FIFO_STATUS) 1190 #define SMIF_INTR(base) (((SMIF_V1_Type *)(base))->INTR) 1191 #define SMIF_INTR_SET(base) (((SMIF_V1_Type *)(base))->INTR_SET) 1192 #define SMIF_INTR_MASK(base) (((SMIF_V1_Type *)(base))->INTR_MASK) 1193 #define SMIF_INTR_MASKED(base) (((SMIF_V1_Type *)(base))->INTR_MASKED) 1194 #define SMIF_CRYPTO_INPUT0(base) (((SMIF_V1_Type *)(base))->CRYPTO_INPUT0) 1195 #define SMIF_CRYPTO_INPUT1(base) (((SMIF_V1_Type *)(base))->CRYPTO_INPUT1) 1196 #define SMIF_CRYPTO_INPUT2(base) (((SMIF_V1_Type *)(base))->CRYPTO_INPUT2) 1197 #define SMIF_CRYPTO_INPUT3(base) (((SMIF_V1_Type *)(base))->CRYPTO_INPUT3) 1198 #define SMIF_CRYPTO_KEY0(base) (((SMIF_V1_Type *)(base))->CRYPTO_KEY0) 1199 #define SMIF_CRYPTO_KEY1(base) (((SMIF_V1_Type *)(base))->CRYPTO_KEY1) 1200 #define SMIF_CRYPTO_KEY2(base) (((SMIF_V1_Type *)(base))->CRYPTO_KEY2) 1201 #define SMIF_CRYPTO_KEY3(base) (((SMIF_V1_Type *)(base))->CRYPTO_KEY3) 1202 #define SMIF_CRYPTO_OUTPUT0(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT0) 1203 #define SMIF_CRYPTO_OUTPUT1(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT1) 1204 #define SMIF_CRYPTO_OUTPUT2(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT2) 1205 #define SMIF_CRYPTO_OUTPUT3(base) (((SMIF_V1_Type *)(base))->CRYPTO_OUTPUT3) 1206 #define SMIF_CRYPTO_CMD(base) (((SMIF_V1_Type *)(base))->CRYPTO_CMD) 1207 #define SMIF_SLOW_CA_CTL(base) (((SMIF_V1_Type *)(base))->SLOW_CA_CTL) 1208 #define SMIF_FAST_CA_CTL(base) (((SMIF_V1_Type *)(base))->FAST_CA_CTL) 1209 #define SMIF_SLOW_CA_CMD(base) (((SMIF_V1_Type *)(base))->SLOW_CA_CMD) 1210 #define SMIF_FAST_CA_CMD(base) (((SMIF_V1_Type *)(base))->FAST_CA_CMD) 1211 1212 1213 /******************************************************************************* 1214 * DW 1215 *******************************************************************************/ 1216 #define CY_DW_V1 (0x20U > cy_device->dwVersion) 1217 #define CY_DW_CRC ((uint32_t)(0x20U <= cy_device->dwVersion)) 1218 #define CY_DW0_BASE ((DW_Type*) 0x40280000UL) 1219 #define CY_DW0_CH_NR (cy_device->cpussDw0ChNr) 1220 #define CY_DW1_CH_NR (cy_device->cpussDw1ChNr) 1221 1222 #define CY_DW_CH_CTL_PRIO_Pos ((uint32_t)(cy_device->dwChCtlPrioPos)) 1223 #define CY_DW_CH_CTL_PRIO_Msk ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos)) 1224 #define CY_DW_CH_CTL_PREEMPTABLE_Pos ((uint32_t)(cy_device->dwChCtlPreemptablePos)) 1225 #define CY_DW_CH_CTL_PREEMPTABLE_Msk ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos)) 1226 #define CY_DW_STATUS_CH_IDX_Pos ((uint32_t)(cy_device->dwStatusChIdxPos)) 1227 #define CY_DW_STATUS_CH_IDX_Msk (cy_device->dwStatusChIdxMsk) 1228 1229 #define DW_CTL(base) (((DW_Type*)(base))->CTL) 1230 #define DW_STATUS(base) (((DW_Type const*)(base))->STATUS) 1231 #if (CY_IP_M4CPUSS_DMA_VERSION == 1U) 1232 #define DW_PENDING(base) (((DW_Type*)(base))->PENDING) 1233 #else 1234 #define DW_CH_STRUCT_CH_STATUS_PENDING_Msk DW_CH_STRUCT_V2_CH_STATUS_PENDING_Msk 1235 #define DW_CH_STRUCT_CH_STATUS_PENDING_Pos DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos 1236 #endif 1237 #define DW_DESCR_SRC(base) (((DW_Type*)(base))->ACT_DESCR_SRC) 1238 #define DW_DESCR_DST(base) (((DW_Type*)(base))->ACT_DESCR_DST) 1239 1240 #define DW_CRC_CTL(base) (((DW_V2_Type*)(base))->CRC_CTL) 1241 #define DW_CRC_DATA_CTL(base) (((DW_V2_Type*)(base))->CRC_DATA_CTL) 1242 #define DW_CRC_REM_CTL(base) (((DW_V2_Type*)(base))->CRC_REM_CTL) 1243 #define DW_CRC_POL_CTL(base) (((DW_V2_Type*)(base))->CRC_POL_CTL) 1244 #define DW_CRC_LFSR_CTL(base) (((DW_V2_Type*)(base))->CRC_LFSR_CTL) 1245 1246 #define DW_CH(base, chan) ((DW_CH_STRUCT_V2_Type*)((uint32_t)(base) + cy_device->dwChOffset + ((chan) * cy_device->dwChSize))) 1247 #define DW_CH_CTL(base, chan) (DW_CH(base, chan)->CH_CTL) 1248 #define DW_CH_STATUS(base, chan) (DW_CH(base, chan)->CH_STATUS) 1249 #define DW_CH_IDX(base, chan) (DW_CH(base, chan)->CH_IDX) 1250 #define DW_CH_CURR_PTR(base, chan) (DW_CH(base, chan)->CH_CURR_PTR) 1251 1252 #define DW_CH_INTR(base, chan) (DW_CH(base, chan)->INTR) 1253 #define DW_CH_INTR_SET(base, chan) (DW_CH(base, chan)->INTR_SET) 1254 #define DW_CH_INTR_MASK(base, chan) (DW_CH(base, chan)->INTR_MASK) 1255 #define DW_CH_INTR_MASKED(base, chan) (DW_CH(base, chan)->INTR_MASKED) 1256 #define DW_CH_TR_CMD(base, chan) (DW_CH((base), (chan))->TR_CMD) 1257 1258 #if defined DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Msk 1259 #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Msk DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Msk 1260 #define DW_CH_STRUCT_TR_CMD_ACTIVATE_Pos DW_CH_STRUCT_V2_TR_CMD_ACTIVATE_Pos 1261 #endif 1262 /******************************************************************************* 1263 * DMAC 1264 *******************************************************************************/ 1265 1266 #define CY_DMAC_CH_NR CPUSS_DMAC_CH_NR 1267 #define DMAC_CTL(base) (((DMAC_V2_Type*)(base))->CTL) 1268 #define DMAC_ACTIVE(base) (((DMAC_V2_Type const*)(base))->ACTIVE) 1269 #define DMAC_CH(base, chan) (&(((DMAC_V2_Type*)(base))->CH[(chan)])) 1270 #define DMAC_CH_CTL(base, chan) (DMAC_CH(base, chan)->CTL) 1271 #define DMAC_CH_IDX(base, chan) (DMAC_CH(base, chan)->IDX) 1272 #define DMAC_CH_CURR(base, chan) (DMAC_CH(base, chan)->CURR) 1273 #define DMAC_CH_DESCR_SRC(base, chan) (DMAC_CH(base, chan)->DESCR_SRC) 1274 #define DMAC_CH_DESCR_DST(base, chan) (DMAC_CH(base, chan)->DESCR_DST) 1275 #define DMAC_CH_INTR(base, chan) (DMAC_CH(base, chan)->INTR) 1276 #define DMAC_CH_INTR_SET(base, chan) (DMAC_CH(base, chan)->INTR_SET) 1277 #define DMAC_CH_INTR_MASK(base, chan) (DMAC_CH(base, chan)->INTR_MASK) 1278 #define DMAC_CH_INTR_MASKED(base, chan) (DMAC_CH(base, chan)->INTR_MASKED) 1279 1280 1281 /******************************************************************************* 1282 * PERI 1283 *******************************************************************************/ 1284 #if (defined(CY_DEVICE_TVIIBE) || defined(CY_DEVICE_SERIES_FX3G2) || defined(CY_DEVICE_SERIES_FX2G3)) 1285 #define CY_PERI_BASE ((PERI_Type *) cy_device->periBase) 1286 #else /* (defined(CY_DEVICE_TVIIBE)) */ 1287 #define CY_PERI_BASE ((PERI_V1_Type *) cy_device->periBase) 1288 #endif /* (defined(CY_DEVICE_TVIIBE)) */ 1289 1290 #define CY_PERI_V1 ((uint32_t)(0x20U > cy_device->periVersion)) /* true if the mxperi version is 1.x */ 1291 #define CY_PERI_V2_TR_GR_SIZE (sizeof(PERI_TR_GR_V2_Type)) 1292 #define CY_PERI_TR_CTL_NUM ((uint32_t)cy_device->periTrGrSize / sizeof(uint32_t)) 1293 #define CY_PERI_TR_CTL_SEL_Pos (0UL) 1294 #define CY_PERI_TR_CTL_SEL_Msk ((uint32_t)CY_PERI_TR_CTL_NUM - 1UL) 1295 #define CY_PERI_TR_CMD_GROUP_SEL_Pos (PERI_TR_CMD_GROUP_SEL_Pos) 1296 #define CY_PERI_TR_CMD_GROUP_SEL_Msk ((uint32_t)cy_device->periTrCmdGrSelMsk) 1297 1298 #define PERI_TR_CMD (*(volatile uint32_t*)((uint32_t)cy_device->periBase + \ 1299 (uint32_t)cy_device->periTrCmdOffset)) 1300 #define PERI_TR_GR_TR_CTL(group, trCtl) (*(volatile uint32_t*)((uint32_t)cy_device->periBase + \ 1301 (uint32_t)cy_device->periTrGrOffset + \ 1302 ((group) * (uint32_t)cy_device->periTrGrSize) + \ 1303 ((trCtl) * (uint32_t)sizeof(uint32_t)))) 1304 1305 #define CY_PERI_CLOCK_NR ((uint32_t)(cy_device->periClockNr)) 1306 1307 #define CY_PERI_DIV_CMD_DIV_SEL_Pos (PERI_DIV_CMD_DIV_SEL_Pos) 1308 #define CY_PERI_DIV_CMD_DIV_SEL_Msk ((uint32_t)(cy_device->periDivCmdDivSelMsk)) 1309 #define CY_PERI_DIV_CMD_TYPE_SEL_Pos ((uint32_t)(cy_device->periDivCmdTypeSelPos)) 1310 #define CY_PERI_DIV_CMD_TYPE_SEL_Msk ((uint32_t)(0x3UL << CY_PERI_DIV_CMD_TYPE_SEL_Pos)) 1311 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos ((uint32_t)(cy_device->periDivCmdPaDivSelPos)) 1312 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk ((uint32_t)(CY_PERI_DIV_CMD_DIV_SEL_Msk << CY_PERI_DIV_CMD_PA_DIV_SEL_Pos)) 1313 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos ((uint32_t)(cy_device->periDivCmdPaTypeSelPos)) 1314 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk ((uint32_t)(0x3UL << CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos)) 1315 1316 #define PERI_CLOCK_CTL ((CY_PERI_BASE)->CLOCK_CTL) 1317 1318 #define CY_PERI_CLOCK_CTL_DIV_SEL_Pos (PERI_CLOCK_CTL_DIV_SEL_Pos) 1319 #define CY_PERI_CLOCK_CTL_DIV_SEL_Msk (CY_PERI_DIV_CMD_DIV_SEL_Msk) 1320 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos (CY_PERI_DIV_CMD_TYPE_SEL_Pos) 1321 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk (CY_PERI_DIV_CMD_TYPE_SEL_Msk) 1322 1323 1324 #if defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2) 1325 #define PERI_DIV_8_CTL(instNum, grNum, divNum) (((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv8CtlOffset)))[divNum]) 1326 #define PERI_DIV_16_CTL(instNum, grNum, divNum) (((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16CtlOffset)))[divNum]) 1327 #define PERI_DIV_16_5_CTL(instNum, grNum, divNum) (((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16_5CtlOffset)))[divNum]) 1328 #define PERI_DIV_24_5_CTL(instNum, grNum, divNum) (((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv24_5CtlOffset)))[divNum]) 1329 #define PERI_DIV_CMD(instNum, grNum) ((CY_PERI_BASE)->DIV_CMD) 1330 1331 /* Remap these V1 defines to V2 for compatibility. */ 1332 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk (PERI_TR_GR_TR_CTL_TR_SEL_Msk) 1333 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos (PERI_TR_GR_TR_CTL_TR_SEL_Pos) 1334 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk (PERI_TR_GR_TR_CTL_TR_INV_Msk) 1335 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos (PERI_TR_GR_TR_CTL_TR_EDGE_Pos) 1336 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk (PERI_TR_GR_TR_CTL_TR_EDGE_Msk) 1337 1338 #define PERI_TR_CMD_COUNT_Pos 0UL 1339 #define PERI_TR_CMD_COUNT_Msk 0UL 1340 1341 #define PERI_PCLK_PERI_NUM_Msk (0x000000FFU) 1342 #define PERI_PCLK_GR_NUM_Msk (0x0000FF00U) 1343 #define PERI_PCLK_GR_NUM_Pos (8U) 1344 #define PERI_PCLK_PERIPHERAL_GROUP_NUM (1UL << PERI_PCLK_GR_NUM_Pos) 1345 #define PERI_PCLK_INST_NUM_Msk (0x00FF0000U) 1346 #define PERI_PCLK_INST_NUM_Pos (16U) 1347 1348 #define PERI_PCLK_GR_DIV_8_NR(instNum, grNum) (PERI_DIV_8_NR) 1349 #define PERI_PCLK_GR_DIV_16_NR(instNum, grNum) (PERI_DIV_16_NR) 1350 #define PERI_PCLK_GR_DIV_16_5_NR(instNum, grNum) (PERI_DIV_16_5_NR) 1351 #define PERI_PCLK_GR_DIV_24_5_NR(instNum, grNum) (PERI_DIV_24_5_NR) 1352 #else 1353 #define PERI_DIV_8_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv8CtlOffset))) 1354 #define PERI_DIV_16_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16CtlOffset))) 1355 #define PERI_DIV_16_5_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv16_5CtlOffset))) 1356 #define PERI_DIV_24_5_CTL ((volatile uint32_t *)((uint32_t)(cy_device->periBase) + (uint32_t)(cy_device->periDiv24_5CtlOffset))) 1357 #define PERI_DIV_CMD ((CY_PERI_BASE)->DIV_CMD) 1358 #endif 1359 1360 #define PERI_GR_SL_CTL(udbGroupNr) ((CY_PERI_BASE)->GR[udbGroupNr].SL_CTL) 1361 1362 #define PERI_PPU_PR_ADDR0(base) (((PERI_PPU_PR_V1_Type *) (base))->ADDR0) 1363 #define PERI_PPU_PR_ATT0(base) (((PERI_PPU_PR_V1_Type *) (base))->ATT0) 1364 #define PERI_PPU_PR_ATT1(base) (((PERI_PPU_PR_V1_Type *) (base))->ATT1) 1365 1366 #define PERI_PPU_GR_ADDR0(base) (((PERI_PPU_GR_V1_Type *) (base))->ADDR0) 1367 #define PERI_PPU_GR_ATT0(base) (((PERI_PPU_GR_V1_Type *) (base))->ATT0) 1368 #define PERI_PPU_GR_ATT1(base) (((PERI_PPU_GR_V1_Type *) (base))->ATT1) 1369 1370 #define PERI_GR_PPU_SL_ADDR0(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ADDR0) 1371 #define PERI_GR_PPU_SL_ATT0(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ATT0) 1372 #define PERI_GR_PPU_SL_ATT1(base) (((PERI_GR_PPU_SL_V1_Type *) (base))->ATT1) 1373 1374 #define PERI_GR_PPU_RG_ADDR0(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ADDR0) 1375 #define PERI_GR_PPU_RG_ATT0(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ATT0) 1376 #define PERI_GR_PPU_RG_ATT1(base) (((PERI_GR_PPU_RG_V1_Type *) (base))->ATT1) 1377 1378 #define PERI_MS_PPU_PR_SL_ADDR(base) (((PERI_MS_PPU_PR_V2_Type *) (base))->SL_ADDR) 1379 #define PERI_MS_PPU_PR_SL_SIZE(base) (((PERI_MS_PPU_PR_V2_Type *) (base))->SL_SIZE) 1380 #define PERI_MS_PPU_PR_MS_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_PR_V2_Type *)(base))->MS_ATT0)) 1381 #define PERI_MS_PPU_PR_SL_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_PR_V2_Type *)(base))->SL_ATT0)) 1382 #define PERI_MS_PPU_FX_MS_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_FX_V2_Type *)(base))->MS_ATT0)) 1383 #define PERI_MS_PPU_FX_SL_ATT(base) ((volatile uint32_t *) &(((PERI_MS_PPU_FX_V2_Type *)(base))->SL_ATT0)) 1384 1385 #define PROT_PERI_PPU_PR_STRUCT_IDX_ATT0(stcIdx) ((CY_PERI_BASE)->PPU_PR[(stcIdx)].ATT0) 1386 #define PROT_PERI_PPU_PR_STRUCT_IDX_ATT1(stcIdx) ((CY_PERI_BASE)->PPU_PR[(stcIdx)].ATT1) 1387 1388 #define PROT_PERI_PPU_PR_STRUCT_IDX(stcIdx) ((PERI_PPU_PR_Type*) &(CY_PERI_BASE)->PPU_PR[(stcIdx)]) 1389 1390 1391 /******************************************************************************* 1392 * PROT 1393 *******************************************************************************/ 1394 #define CY_PROT_BASE (cy_device->protBase) 1395 1396 #define CY_PROT_PC_MAX (8UL) 1397 #define CY_PROT_BUS_MASTER_MASK (cy_device->protBusMasterMask) 1398 #define PROT_MPU_MS_CTL(mpu) (((PROT_Type*)CY_PROT_BASE)->CYMPU[(mpu)].MS_CTL) 1399 #define PROT_MPU_MPU_STRUCT_ADDR(base) (((PROT_MPU_MPU_STRUCT_Type *) (base))->ADDR) 1400 #define PROT_MPU_MPU_STRUCT_ATT(base) (((PROT_MPU_MPU_STRUCT_Type *) (base))->ATT) 1401 1402 #define PROT_SMPU_SMPU_STRUCT_ADDR0(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR0) 1403 #define PROT_SMPU_SMPU_STRUCT_ADDR1(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR1) 1404 #define PROT_SMPU_SMPU_STRUCT_ATT0(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT0) 1405 #define PROT_SMPU_SMPU_STRUCT_ATT1(base) (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT1) 1406 1407 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx) (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT0) 1408 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT1(stcIdx) (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT1) 1409 #define PROT_SMPU_SMPU_STRUCT_IDX(stcIdx) (((PROT_SMPU_SMPU_STRUCT_Type *) &((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)])) 1410 1411 1412 /******************************************************************************* 1413 * IOSS 1414 *******************************************************************************/ 1415 1416 #define CY_GPIO_BASE ((uint32_t)(cy_device->gpioBase)) 1417 1418 #if defined (CY_IP_MXS40IOSS_VERSION) && (CY_IP_MXS40IOSS_VERSION == 5) 1419 #define GPIO_INTR_CAUSE0 (((GPIO_V5_Type*)(cy_device->gpioBase))->INTR_CAUSE0) 1420 #define GPIO_INTR_CAUSE1 (((GPIO_V5_Type*)(cy_device->gpioBase))->INTR_CAUSE1) 1421 #define GPIO_INTR_CAUSE2 (((GPIO_V5_Type*)(cy_device->gpioBase))->INTR_CAUSE2) 1422 #define GPIO_INTR_CAUSE3 (((GPIO_V5_Type*)(cy_device->gpioBase))->INTR_CAUSE3) 1423 1424 #define GPIO_PRT_V2_Type GPIO_PRT_V5_Type 1425 #define HSIOM_PRT_V2_Type HSIOM_PRT_V5_Type 1426 1427 #elif defined (CY_IP_MXS40IOSS_VERSION) && (CY_IP_MXS40IOSS_VERSION == 2) 1428 #define GPIO_INTR_CAUSE0 (((GPIO_V2_Type*)(cy_device->gpioBase))->INTR_CAUSE0) 1429 #define GPIO_INTR_CAUSE1 (((GPIO_V2_Type*)(cy_device->gpioBase))->INTR_CAUSE1) 1430 #define GPIO_INTR_CAUSE2 (((GPIO_V2_Type*)(cy_device->gpioBase))->INTR_CAUSE2) 1431 #define GPIO_INTR_CAUSE3 (((GPIO_V2_Type*)(cy_device->gpioBase))->INTR_CAUSE3) 1432 1433 /* The GPIO driver requires the HSIOM_PRT_V1_Type in order to compile, even if the device contains V2 version 1434 * of the HSIOM IP. This should be removed once the GPIO driver is corrected. 1435 */ 1436 #define HSIOM_PRT_V1_Type HSIOM_PRT_V2_Type 1437 #define HSIOM_V1_Type HSIOM_V2_Type 1438 #else /* IOSS_VERSION == 1 */ 1439 #define GPIO_INTR_CAUSE0 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE0) 1440 #define GPIO_INTR_CAUSE1 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE1) 1441 #define GPIO_INTR_CAUSE2 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE2) 1442 #define GPIO_INTR_CAUSE3 (((GPIO_V1_Type*)(cy_device->gpioBase))->INTR_CAUSE3) 1443 #endif 1444 1445 #define GPIO_PRT_OUT(base) (((GPIO_PRT_Type*)(base))->OUT) 1446 #define GPIO_PRT_OUT_CLR(base) (((GPIO_PRT_Type*)(base))->OUT_CLR) 1447 #define GPIO_PRT_OUT_SET(base) (((GPIO_PRT_Type*)(base))->OUT_SET) 1448 #define GPIO_PRT_OUT_INV(base) (((GPIO_PRT_Type*)(base))->OUT_INV) 1449 #define GPIO_PRT_IN(base) (((GPIO_PRT_Type*)(base))->IN) 1450 #define GPIO_PRT_INTR(base) (((GPIO_PRT_Type*)(base))->INTR) 1451 #define GPIO_PRT_INTR_MASK(base) (((GPIO_PRT_Type*)(base))->INTR_MASK) 1452 #define GPIO_PRT_INTR_MASKED(base) (((GPIO_PRT_Type*)(base))->INTR_MASKED) 1453 #define GPIO_PRT_INTR_SET(base) (((GPIO_PRT_Type*)(base))->INTR_SET) 1454 1455 #define GPIO_PRT_INTR_CFG(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtIntrCfgOffset))) 1456 #define GPIO_PRT_CFG(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgOffset))) 1457 #define GPIO_PRT_CFG_IN(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgInOffset))) 1458 #define GPIO_PRT_CFG_OUT(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgOutOffset))) 1459 #define GPIO_PRT_CFG_SIO(base) (*(volatile uint32_t *)((uint32_t)(base) + (uint32_t)(cy_device->gpioPrtCfgSioOffset))) 1460 #define GPIO_PRT_CFG_IN_AUTOLVL(base) (((GPIO_PRT_Type*)(base))->CFG_IN_AUTOLVL) 1461 1462 #define CY_HSIOM_BASE ((uint32_t)(cy_device->hsiomBase)) 1463 1464 #define HSIOM_PRT_PORT_SEL0(base) (((HSIOM_PRT_V1_Type *)(base))->PORT_SEL0) 1465 #define HSIOM_PRT_PORT_SEL1(base) (((HSIOM_PRT_V1_Type *)(base))->PORT_SEL1) 1466 1467 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_Type *) CY_HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl]) 1468 1469 1470 /******************************************************************************* 1471 * I2S 1472 *******************************************************************************/ 1473 #if (defined(AUDIOSS_I2S) || defined(AUDIOSS0_I2S)) 1474 #define AUDIOSS_I2S_PRESENT 1475 #endif 1476 1477 #define REG_I2S_CTL(base) (((I2S_V1_Type*)(base))->CTL) 1478 #define REG_I2S_CMD(base) (((I2S_V1_Type*)(base))->CMD) 1479 #define REG_I2S_CLOCK_CTL(base) (((I2S_V1_Type*)(base))->CLOCK_CTL) 1480 #define REG_I2S_TR_CTL(base) (((I2S_V1_Type*)(base))->TR_CTL) 1481 #define REG_I2S_TX_CTL(base) (((I2S_V1_Type*)(base))->TX_CTL) 1482 #define REG_I2S_TX_FIFO_CTL(base) (((I2S_V1_Type*)(base))->TX_FIFO_CTL) 1483 #define REG_I2S_TX_FIFO_STATUS(base) (((I2S_V1_Type*)(base))->TX_FIFO_STATUS) 1484 #define REG_I2S_TX_FIFO_WR(base) (((I2S_V1_Type*)(base))->TX_FIFO_WR) 1485 #define REG_I2S_TX_WATCHDOG(base) (((I2S_V1_Type*)(base))->TX_WATCHDOG) 1486 #define REG_I2S_RX_CTL(base) (((I2S_V1_Type*)(base))->RX_CTL) 1487 #define REG_I2S_RX_FIFO_CTL(base) (((I2S_V1_Type*)(base))->RX_FIFO_CTL) 1488 #define REG_I2S_RX_FIFO_STATUS(base) (((I2S_V1_Type*)(base))->RX_FIFO_STATUS) 1489 #define REG_I2S_RX_FIFO_RD(base) (((I2S_V1_Type*)(base))->RX_FIFO_RD) 1490 #define REG_I2S_RX_FIFO_RD_SILENT(base) (((I2S_V1_Type*)(base))->RX_FIFO_RD_SILENT) 1491 #define REG_I2S_RX_WATCHDOG(base) (((I2S_V1_Type*)(base))->RX_WATCHDOG) 1492 #define REG_I2S_INTR(base) (((I2S_V1_Type*)(base))->INTR) 1493 #define REG_I2S_INTR_SET(base) (((I2S_V1_Type*)(base))->INTR_SET) 1494 #define REG_I2S_INTR_MASK(base) (((I2S_V1_Type*)(base))->INTR_MASK) 1495 #define REG_I2S_INTR_MASKED(base) (((I2S_V1_Type*)(base))->INTR_MASKED) 1496 1497 1498 /******************************************************************************* 1499 * PDM 1500 *******************************************************************************/ 1501 #if (defined(AUDIOSS_PDM) || defined(AUDIOSS0_PDM)) 1502 #define AUDIOSS_PDM_PRESENT 1503 #endif 1504 1505 #if (defined(CY_IP_MXPDM)) 1506 #define PDM_PCM_CTL(base) (((PDM_Type*)(base))->CTL) 1507 #define PDM_PCM_CTL_CLR(base) (((PDM_Type*)(base))->CTL_CLR) 1508 #define PDM_PCM_CTL_SET(base) (((PDM_Type*)(base))->CTL_SET) 1509 #define PDM_PCM_CLOCK_CTL(base) (((PDM_Type*)(base))->CLOCK_CTL) 1510 #define PDM_PCM_ROUTE_CTL(base) (((PDM_Type*)(base))->ROUTE_CTL) 1511 #define PDM_PCM_TEST_CTL(base) (((PDM_Type*)(base))->TEST_CTL) 1512 #define PDM_PCM_FIR0_COEFF0(base) (((PDM_Type*)(base))->FIR0_COEFF0) 1513 #define PDM_PCM_FIR0_COEFF1(base) (((PDM_Type*)(base))->FIR0_COEFF1) 1514 #define PDM_PCM_FIR0_COEFF2(base) (((PDM_Type*)(base))->FIR0_COEFF2) 1515 #define PDM_PCM_FIR0_COEFF3(base) (((PDM_Type*)(base))->FIR0_COEFF3) 1516 #define PDM_PCM_FIR0_COEFF4(base) (((PDM_Type*)(base))->FIR0_COEFF4) 1517 #define PDM_PCM_FIR0_COEFF5(base) (((PDM_Type*)(base))->FIR0_COEFF5) 1518 #define PDM_PCM_FIR0_COEFF6(base) (((PDM_Type*)(base))->FIR0_COEFF6) 1519 #define PDM_PCM_FIR0_COEFF7(base) (((PDM_Type*)(base))->FIR0_COEFF7) 1520 1521 #define PDM_PCM_FIR1_COEFF0(base) (((PDM_Type*)(base))->FIR1_COEFF0) 1522 #define PDM_PCM_FIR1_COEFF1(base) (((PDM_Type*)(base))->FIR1_COEFF1) 1523 #define PDM_PCM_FIR1_COEFF2(base) (((PDM_Type*)(base))->FIR1_COEFF2) 1524 #define PDM_PCM_FIR1_COEFF3(base) (((PDM_Type*)(base))->FIR1_COEFF3) 1525 #define PDM_PCM_FIR1_COEFF4(base) (((PDM_Type*)(base))->FIR1_COEFF4) 1526 #define PDM_PCM_FIR1_COEFF5(base) (((PDM_Type*)(base))->FIR1_COEFF5) 1527 #define PDM_PCM_FIR1_COEFF6(base) (((PDM_Type*)(base))->FIR1_COEFF6) 1528 #define PDM_PCM_FIR1_COEFF7(base) (((PDM_Type*)(base))->FIR1_COEFF7) 1529 #define PDM_PCM_FIR1_COEFF8(base) (((PDM_Type*)(base))->FIR1_COEFF8) 1530 #define PDM_PCM_FIR1_COEFF9(base) (((PDM_Type*)(base))->FIR1_COEFF9) 1531 #define PDM_PCM_FIR1_COEFF10(base) (((PDM_Type*)(base))->FIR1_COEFF10) 1532 #define PDM_PCM_FIR1_COEFF11(base) (((PDM_Type*)(base))->FIR1_COEFF11) 1533 #define PDM_PCM_FIR1_COEFF12(base) (((PDM_Type*)(base))->FIR1_COEFF12) 1534 #define PDM_PCM_FIR1_COEFF13(base) (((PDM_Type*)(base))->FIR1_COEFF13) 1535 1536 1537 #define PDM_PCM_CH_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].CTL) 1538 #define PDM_PCM_CH_IF_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].IF_CTL) 1539 #define PDM_PCM_CH_CIC_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].CIC_CTL) 1540 #define PDM_PCM_CH_FIR0_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].FIR0_CTL) 1541 #define PDM_PCM_CH_FIR1_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].FIR1_CTL) 1542 #define PDM_PCM_CH_DC_BLOCK_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].DC_BLOCK_CTL) 1543 #define PDM_PCM_INTR_RX_MASK(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX_MASK) 1544 #define PDM_PCM_INTR_RX_MASKED(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX_MASKED) 1545 #define PDM_PCM_INTR_RX(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX) 1546 #define PDM_PCM_INTR_RX_SET(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX_SET) 1547 #define PDM_PCM_RX_FIFO_STATUS(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_STATUS) 1548 #define PDM_PCM_RX_FIFO_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_CTL) 1549 #define PDM_PCM_RX_FIFO_RD(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_RD) 1550 #define PDM_PCM_RX_FIFO_RD_SILENT(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_RD_SILENT) 1551 #else 1552 #define PDM_PCM_CTL(base) (((PDM_V1_Type*)(base))->CTL) 1553 #define PDM_PCM_CMD(base) (((PDM_V1_Type*)(base))->CMD) 1554 #define PDM_PCM_CLOCK_CTL(base) (((PDM_V1_Type*)(base))->CLOCK_CTL) 1555 #define PDM_PCM_MODE_CTL(base) (((PDM_V1_Type*)(base))->MODE_CTL) 1556 #define PDM_PCM_DATA_CTL(base) (((PDM_V1_Type*)(base))->DATA_CTL) 1557 #define PDM_PCM_TR_CTL(base) (((PDM_V1_Type*)(base))->TR_CTL) 1558 #define PDM_PCM_INTR_MASK(base) (((PDM_V1_Type*)(base))->INTR_MASK) 1559 #define PDM_PCM_INTR_MASKED(base) (((PDM_V1_Type*)(base))->INTR_MASKED) 1560 #define PDM_PCM_INTR(base) (((PDM_V1_Type*)(base))->INTR) 1561 #define PDM_PCM_INTR_SET(base) (((PDM_V1_Type*)(base))->INTR_SET) 1562 #define PDM_PCM_RX_FIFO_STATUS(base) (((PDM_V1_Type*)(base))->RX_FIFO_STATUS) 1563 #define PDM_PCM_RX_FIFO_CTL(base) (((PDM_V1_Type*)(base))->RX_FIFO_CTL) 1564 #define PDM_PCM_RX_FIFO_RD(base) (((PDM_V1_Type*)(base))->RX_FIFO_RD) 1565 #define PDM_PCM_RX_FIFO_RD_SILENT(base) (((PDM_V1_Type*)(base))->RX_FIFO_RD_SILENT) 1566 #endif /* CY_IP_MXPDM */ 1567 1568 1569 /******************************************************************************* 1570 * LCD 1571 *******************************************************************************/ 1572 1573 #define LCD_OCTET_NUM (8U) /* LCD_NUMPORTS - number of octets supporting up to 4 COMs */ 1574 #define LCD_OCTET_NUM_8 (8U) /* LCD_NUMPORTS8 - number of octets supporting up to 8 COMs */ 1575 #define LCD_OCTET_NUM_16 (0U) /* LCD_NUMPORTS16 - number of octets supporting up to 16 COMs */ 1576 #define LCD_COM_NUM (8U) /* LCD_CHIP_TOP_COM_NR - maximum number of commons */ 1577 1578 #define LCD_ID(base) (((LCD_V1_Type*)(base))->ID) 1579 #define LCD_CONTROL(base) (((LCD_V1_Type*)(base))->CONTROL) 1580 #define LCD_DIVIDER(base) (((LCD_V1_Type*)(base))->DIVIDER) 1581 #define LCD_DATA0(base) (((LCD_V1_Type*)(base))->DATA0) 1582 #define LCD_DATA1(base) (((LCD_V1_Type*)(base))->DATA1) 1583 #define LCD_DATA2(base) (((LCD_V1_Type*)(base))->DATA2) 1584 #define LCD_DATA3(base) (((LCD_V1_Type*)(base))->DATA3) 1585 1586 1587 /******************************************************************************* 1588 * IPC 1589 *******************************************************************************/ 1590 /* Disable the default IPC configuration. Most CAT1A devices use endpoint IPC channels 1591 * to communicate with the flash & srom drivers, however CAT1C uses ECT flash and the 1592 * syscall IPC channels and doesn't need/isn't compatible with the default CAT1A 1593 * IPC configuration. */ 1594 #if defined (CY_DEVICE_TVIIBE) 1595 #ifndef CY_IPC_DEFAULT_CFG_DISABLE 1596 #define CY_IPC_DEFAULT_CFG_DISABLE 1597 #endif 1598 #endif 1599 1600 #define CY_IPC_V1 (0x20u > cy_device->ipcVersion) /* true if the IPC version is 1.x */ 1601 1602 #define REG_IPC_STRUCT_ACQUIRE(base) (((IPC_STRUCT_Type*)(base))->ACQUIRE) 1603 #define REG_IPC_STRUCT_RELEASE(base) (((IPC_STRUCT_Type*)(base))->RELEASE) 1604 #define REG_IPC_STRUCT_NOTIFY(base) (((IPC_STRUCT_Type*)(base))->NOTIFY) 1605 #if (CY_IP_M4CPUSS_VERSION == 1U) 1606 #define REG_IPC_STRUCT_DATA(base) (((IPC_STRUCT_V1_Type*)(base))->DATA) 1607 #else 1608 #define REG_IPC_STRUCT_DATA(base) (((IPC_STRUCT_V2_Type*)(base))->DATA0) 1609 #endif 1610 #define REG_IPC_STRUCT_DATA1(base) (((IPC_STRUCT_V2_Type*)(base))->DATA1) 1611 #define REG_IPC_STRUCT_LOCK_STATUS(base) (*(volatile uint32_t*)((uint32_t)(base) + cy_device->ipcLockStatusOffset)) 1612 1613 #define REG_IPC_INTR_STRUCT_INTR(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR) 1614 #define REG_IPC_INTR_STRUCT_INTR_SET(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_SET) 1615 #define REG_IPC_INTR_STRUCT_INTR_MASK(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASK) 1616 #define REG_IPC_INTR_STRUCT_INTR_MASKED(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASKED) 1617 1618 #define CY_IPC_STRUCT_PTR(ipcIndex) ((IPC_STRUCT_Type*)(cy_device->ipcBase + (cy_device->ipcStructSize * (ipcIndex)))) 1619 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex) (&(((IPC_Type *)cy_device->ipcBase)->INTR_STRUCT[ipcIntrIndex])) 1620 1621 #define CY_IPC_STRUCT_PTR_FOR_IP(ipcIndex, base) ((IPC_STRUCT_Type*)((uint32_t)(base) + (sizeof(IPC_STRUCT_Type) * (ipcIndex)))) 1622 #define CY_IPC_INTR_STRUCT_PTR_FOR_IP(ipcIntrIndex, base) (&(((IPC_Type *)base)->INTR_STRUCT[ipcIntrIndex])) 1623 1624 #define CY_IPC_INSTANCES (1U) 1625 #define CY_IPC_CHANNELS ((uint32_t)(cy_device->cpussIpcNr)) 1626 #define CY_IPC_INTERRUPTS ((uint32_t)(cy_device->cpussIpcIrqNr)) 1627 #define CY_IPC_CHANNELS_PER_INSTANCE CY_IPC_CHANNELS 1628 #define CY_IPC_INTERRUPTS_PER_INSTANCE CY_IPC_INTERRUPTS 1629 1630 /* ipcChannel comprises of total number of channels present in all IPC IP instances */ 1631 #define CY_IPC_PIPE_CHANNEL_NUMBER_WITHIN_INSTANCE(ipcChannel) (((ipcChannel)%CY_IPC_CHANNELS_PER_INSTANCE)) 1632 #define CY_IPC_PIPE_INTR_NUMBER_WITHIN_INSTANCE(ipcIntr) (((ipcIntr)%CY_IPC_INTERRUPTS_PER_INSTANCE)) 1633 1634 /* IPC channel definitions */ 1635 /* Most Cat1A devices have 16 channels, except TVIIBE Cat1A devices which have 8 channels. */ 1636 #define CY_IPC_CHAN_SYSCALL_CM0 (0U) /* System calls for the CM0 processor */ 1637 #define CY_IPC_CHAN_SYSCALL_CM4 (1U) /* System calls for the 1st non-CM0 processor */ 1638 #define CY_IPC_CHAN_SYSCALL_DAP (2UL) /* System calls for the DAP */ 1639 #define CY_IPC_CHAN_SEMA (3UL) /* IPC data channel for the Semaphores */ 1640 #if defined (CPUSS_IPC_IPC_NR) && (CPUSS_IPC_IPC_NR > 0) && (CPUSS_IPC_IPC_NR <= 8) 1641 #define CY_IPC_CHAN_USER (CY_IPC_CHAN_SEMA + 1u) 1642 #else 1643 #define CY_IPC_CHAN_PRA (4UL) /* IPC data channel for PRA */ 1644 #define CY_IPC_CHAN_CYPIPE_EP0 (5UL) /* IPC data channel for CYPIPE EP0 */ 1645 #define CY_IPC_CHAN_CYPIPE_EP1 (6UL) /* IPC data channel for CYPIPE EP1 */ 1646 #define CY_IPC_CHAN_DDFT (7UL) /* IPC data channel for DDFT */ 1647 #define CY_IPC_CHAN_USER (CY_IPC_CHAN_DDFT + 1) 1648 #endif 1649 1650 /* IPC Notify interrupts definitions */ 1651 /* Most Cat1A devices have 16 channels, except TVIIBE Cat1A devices which have 8 channels. */ 1652 #if defined (CPUSS_IPC_IPC_NR) && (CPUSS_IPC_IPC_NR > 0) && (CPUSS_IPC_IPC_NR <= 8) 1653 /* IPC Notify interrupts definitions */ 1654 #define CY_IPC_INTR_SYSCALL1 (0UL) 1655 #define CY_IPC_INTR_USER (CY_IPC_INTR_SYSCALL1 + 1UL) 1656 #else 1657 #define CY_IPC_INTR_SYSCALL1 (0UL) 1658 #define CY_IPC_INTR_CYPIPE_EP0 (3UL) 1659 #define CY_IPC_INTR_CYPIPE_EP1 (4UL) 1660 #define CY_IPC_INTR_PRA (5UL) 1661 #define CY_IPC_INTR_SPARE (7UL) 1662 /* Endpoint indexes in the pipe array */ 1663 #define CY_IPC_EP_CYPIPE_CM0_ADDR (0UL) 1664 #define CY_IPC_EP_CYPIPE_CM4_ADDR (1UL) 1665 #endif 1666 1667 1668 /******************************************************************************* 1669 * CTB 1670 *******************************************************************************/ 1671 1672 #define CTBM_CTB_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_CTRL) 1673 #define CTBM_CTB_SW_DS_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_SW_DS_CTRL) 1674 #define CTBM_CTB_SW_SQ_CTRL(base) (((CTBM_V1_Type *) (base))->CTB_SW_SQ_CTRL) 1675 #define CTBM_CTD_SW(base) (((CTBM_V1_Type *) (base))->CTD_SW) 1676 #define CTBM_CTD_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->CTD_SW_CLEAR) 1677 #define CTBM_COMP_STAT(base) (((CTBM_V1_Type *) (base))->COMP_STAT) 1678 #define CTBM_OA0_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->OA0_SW_CLEAR) 1679 #define CTBM_OA1_SW_CLEAR(base) (((CTBM_V1_Type *) (base))->OA1_SW_CLEAR) 1680 #define CTBM_OA0_SW(base) (((CTBM_V1_Type *) (base))->OA0_SW) 1681 #define CTBM_OA1_SW(base) (((CTBM_V1_Type *) (base))->OA1_SW) 1682 #define CTBM_OA_RES0_CTRL(base) (((CTBM_V1_Type *) (base))->OA_RES0_CTRL) 1683 #define CTBM_OA_RES1_CTRL(base) (((CTBM_V1_Type *) (base))->OA_RES1_CTRL) 1684 #define CTBM_OA0_COMP_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_COMP_TRIM) 1685 #define CTBM_OA1_COMP_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_COMP_TRIM) 1686 #define CTBM_OA0_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_OFFSET_TRIM) 1687 #define CTBM_OA1_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_OFFSET_TRIM) 1688 #define CTBM_OA0_SLOPE_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA0_SLOPE_OFFSET_TRIM) 1689 #define CTBM_OA1_SLOPE_OFFSET_TRIM(base) (((CTBM_V1_Type *) (base))->OA1_SLOPE_OFFSET_TRIM) 1690 #define CTBM_INTR(base) (((CTBM_V1_Type *) (base))->INTR) 1691 #define CTBM_INTR_SET(base) (((CTBM_V1_Type *) (base))->INTR_SET) 1692 #define CTBM_INTR_MASK(base) (((CTBM_V1_Type *) (base))->INTR_MASK) 1693 #define CTBM_INTR_MASKED(base) (((CTBM_V1_Type *) (base))->INTR_MASKED) 1694 1695 1696 /******************************************************************************* 1697 * CTDAC 1698 *******************************************************************************/ 1699 1700 #define CTDAC_CTDAC_CTRL(base) (((CTDAC_V1_Type *) (base))->CTDAC_CTRL) 1701 #define CTDAC_CTDAC_SW(base) (((CTDAC_V1_Type *) (base))->CTDAC_SW) 1702 #define CTDAC_CTDAC_SW_CLEAR(base) (((CTDAC_V1_Type *) (base))->CTDAC_SW_CLEAR) 1703 #define CTDAC_CTDAC_VAL(base) (((CTDAC_V1_Type *) (base))->CTDAC_VAL) 1704 #define CTDAC_CTDAC_VAL_NXT(base) (((CTDAC_V1_Type *) (base))->CTDAC_VAL_NXT) 1705 #define CTDAC_INTR(base) (((CTDAC_V1_Type *) (base))->INTR) 1706 #define CTDAC_INTR_SET(base) (((CTDAC_V1_Type *) (base))->INTR_SET) 1707 #define CTDAC_INTR_MASK(base) (((CTDAC_V1_Type *) (base))->INTR_MASK) 1708 #define CTDAC_INTR_MASKED(base) (((CTDAC_V1_Type *) (base))->INTR_MASKED) 1709 1710 1711 /******************************************************************************* 1712 * SYSANALOG 1713 *******************************************************************************/ 1714 1715 #define CY_PASS_V1 (0x20U > cy_device->passVersion) 1716 #define CY_PASS_ADDR ((PASS_Type*)cy_device->passBase) 1717 #define CY_PASS_V2_ADDR ((PASS_V2_Type*)cy_device->passBase) 1718 1719 #define CY_SAR_PASS_BASE(sarBase) ((NULL != (sarBase)) ? ((PASS_V2_Type*) cy_device->passBase) : NULL) /* temporary solution for single pass instance */ 1720 #define CY_CTB_PASS_BASE(ctbBase) ((NULL != (ctbBase)) ? ((PASS_V2_Type*) cy_device->passBase) : NULL) /* temporary solution for single ctb instance */ 1721 #define CY_CTB_INST(ctbBase) ((NULL != (ctbBase)) ? 0UL : 0UL) /* temporary solution for single ctb instance */ 1722 1723 #define PASS_AREF_AREF_CTRL (((PASS_V1_Type*) CY_PASS_ADDR)->AREF.AREF_CTRL) 1724 #define PASS_INTR_CAUSE(passBase) (((PASS_V1_Type*) (passBase))->INTR_CAUSE) 1725 1726 #define PASS_CTBM_CLOCK_SEL(ctbBase) (CY_CTB_PASS_BASE(ctbBase)->CTBM_CLOCK_SEL[CY_CTB_INST(ctbBase)]) 1727 1728 #define PASS_DPSLP_CLOCK_SEL(passBase) (((PASS_V2_Type*) (passBase))->DPSLP_CLOCK_SEL) 1729 #define PASS_LPOSC_CTRL(passBase) (((PASS_V2_Type*) (passBase))->LPOSC.CTRL) 1730 #define PASS_LPOSC_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->LPOSC.CONFIG) 1731 #define PASS_TIMER_CTRL(passBase) (((PASS_V2_Type*) (passBase))->TIMER.CTRL) 1732 #define PASS_TIMER_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->TIMER.CONFIG) 1733 #define PASS_TIMER_PERIOD(passBase) (((PASS_V2_Type*) (passBase))->TIMER.PERIOD) 1734 1735 #define PASS_SAR_SIMULT_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_SIMULT_CTRL) 1736 #define PASS_SAR_TR_SCAN_CNT(passBase) (((PASS_V2_Type*) (passBase))->SAR_TR_SCAN_CNT) 1737 #define PASS_SAR_OVR_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_OVR_CTRL) 1738 #define PASS_SAR_SIMULT_FW_START_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_SIMULT_FW_START_CTRL) 1739 #define PASS_ANA_PWR_CFG(passBase) (((PASS_V2_Type*) (passBase))->ANA_PWR_CFG) 1740 #define PASS_SAR_TR_OUT_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_TR_OUT_CTRL) 1741 1742 #define PASS_SAR_DPSLP_CTRL(sarBase) (((PASS_V2_Type*) cy_device->passBase)->SAR_DPSLP_CTRL[CY_SAR_INSTANCE(sarBase)]) 1743 #define PASS_SAR_CLOCK_SEL(sarBase) (((PASS_V2_Type*) cy_device->passBase)->SAR_CLOCK_SEL[CY_SAR_INSTANCE(sarBase)]) 1744 1745 #define PASS_FIFO_BASE(sarBase) ((PASS_FIFO_V2_Type*)&(((PASS_V2_Type*)cy_device->passBase)->FIFO[CY_SAR_INSTANCE(sarBase)])) 1746 #define PASS_FIFO_CTRL(sarBase) (PASS_FIFO_BASE(sarBase)->CTRL) 1747 #define PASS_FIFO_CONFIG(sarBase) (PASS_FIFO_BASE(sarBase)->CONFIG) 1748 #define PASS_FIFO_LEVEL(sarBase) (PASS_FIFO_BASE(sarBase)->LEVEL) 1749 #define PASS_FIFO_USED(sarBase) (PASS_FIFO_BASE(sarBase)->USED) 1750 #define PASS_FIFO_RD_DATA(sarBase) (PASS_FIFO_BASE(sarBase)->RD_DATA) 1751 #define PASS_FIFO_INTR(sarBase) (PASS_FIFO_BASE(sarBase)->INTR) 1752 #define PASS_FIFO_INTR_SET(sarBase) (PASS_FIFO_BASE(sarBase)->INTR_SET) 1753 #define PASS_FIFO_INTR_MASK(sarBase) (PASS_FIFO_BASE(sarBase)->INTR_MASK) 1754 #define PASS_FIFO_INTR_MASKED(sarBase) (PASS_FIFO_BASE(sarBase)->INTR_MASKED) 1755 1756 /******************************************************************************* 1757 * SAR ADC 1758 *******************************************************************************/ 1759 /** Channel TR_CTL register access macro. */ 1760 #define SAR2_CH_TR_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].TR_CTL) 1761 1762 /** Channel SAMPLE_CTL register access macro. */ 1763 #define SAR2_CH_SAMPLE_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].SAMPLE_CTL) 1764 1765 /** Channel POST_CTL register access macro. */ 1766 #define SAR2_CH_POST_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].POST_CTL) 1767 1768 /** Channel RANGE_CTL register access macro. */ 1769 #define SAR2_CH_RANGE_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].RANGE_CTL) 1770 1771 /** Channel INTR register access macro. */ 1772 #define SAR2_CH_INTR(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR) 1773 1774 /** Channel INTR_SET register access macro. */ 1775 #define SAR2_CH_INTR_SET(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_SET) 1776 1777 /** Channel INTR_MASK register access macro. */ 1778 #define SAR2_CH_INTR_MASK(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_MASK) 1779 1780 /** Channel INTR_MASKED register access macro. */ 1781 #define SAR2_CH_INTR_MASKED(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_MASKED) 1782 1783 /** Channel WORK register access macro. */ 1784 #define SAR2_CH_WORK(base, channel) (((PASS_SAR_Type *)base)->CH[channel].WORK) 1785 1786 /** Channel WORK register access macro. */ 1787 #define SAR2_CH_RESULT(base, channel) (((PASS_SAR_Type *)base)->CH[channel].WORK) 1788 1789 /** Channel GRP_STAT register access macro. */ 1790 #define SAR2_CH_GRP_STAT(base, channel) (((PASS_SAR_Type *)base)->CH[channel].GRP_STAT) 1791 1792 /** Channel ENABLE register access macro. */ 1793 #define SAR2_CH_ENABLE(base, channel) (((PASS_SAR_Type *)base)->CH[channel].ENABLE) 1794 1795 /** Channel TR_CMD register access macro. */ 1796 #define SAR2_CH_TR_CMD(base, channel) (((PASS_SAR_Type *)base)->CH[channel].TR_CMD) 1797 1798 /******************************************************************************* 1799 * SCB 1800 *******************************************************************************/ 1801 1802 #if (defined(CY_DEVICE_TVIIBE)) 1803 #define SCB_CTRL(base) (((CySCB_Type*) (base))->CTRL) 1804 #define SCB_SPI_CTRL(base) (((CySCB_Type*) (base))->SPI_CTRL) 1805 #define SCB_SPI_STATUS(base) (((CySCB_Type*) (base))->SPI_STATUS) 1806 #define SCB_SPI_TX_CTRL(base) (((CySCB_Type*) (base))->SPI_TX_CTRL) 1807 #define SCB_SPI_RX_CTRL(base) (((CySCB_Type*) (base))->SPI_RX_CTRL) 1808 #define SCB_UART_CTRL(base) (((CySCB_Type*) (base))->UART_CTRL) 1809 #define SCB_UART_TX_CTRL(base) (((CySCB_Type*) (base))->UART_TX_CTRL) 1810 #define SCB_UART_RX_CTRL(base) (((CySCB_Type*) (base))->UART_RX_CTRL) 1811 #define SCB_UART_FLOW_CTRL(base) (((CySCB_Type*) (base))->UART_FLOW_CTRL) 1812 #define SCB_I2C_CTRL(base) (((CySCB_Type*) (base))->I2C_CTRL) 1813 #define SCB_I2C_STATUS(base) (((CySCB_Type*) (base))->I2C_STATUS) 1814 #define SCB_I2C_M_CMD(base) (((CySCB_Type*) (base))->I2C_M_CMD) 1815 #define SCB_I2C_S_CMD(base) (((CySCB_Type*) (base))->I2C_S_CMD) 1816 #define SCB_I2C_CFG(base) (((CySCB_Type*) (base))->I2C_CFG) 1817 #define SCB_TX_CTRL(base) (((CySCB_Type*) (base))->TX_CTRL) 1818 #define SCB_TX_FIFO_CTRL(base) (((CySCB_Type*) (base))->TX_FIFO_CTRL) 1819 #define SCB_TX_FIFO_STATUS(base) (((CySCB_Type*) (base))->TX_FIFO_STATUS) 1820 #define SCB_TX_FIFO_WR(base) (((CySCB_Type*) (base))->TX_FIFO_WR) 1821 #define SCB_RX_CTRL(base) (((CySCB_Type*) (base))->RX_CTRL) 1822 #define SCB_RX_FIFO_CTRL(base) (((CySCB_Type*) (base))->RX_FIFO_CTRL) 1823 #define SCB_RX_FIFO_STATUS(base) (((CySCB_Type*) (base))->RX_FIFO_STATUS) 1824 #define SCB_RX_MATCH(base) (((CySCB_Type*) (base))->RX_MATCH) 1825 #define SCB_RX_FIFO_RD(base) (((CySCB_Type*) (base))->RX_FIFO_RD) 1826 #define SCB_INTR_CAUSE(base) (((CySCB_Type*) (base))->INTR_CAUSE) 1827 #define SCB_INTR_I2C_EC(base) (((CySCB_Type*) (base))->INTR_I2C_EC) 1828 #define SCB_INTR_I2C_EC_MASK(base) (((CySCB_Type*) (base))->INTR_I2C_EC_MASK) 1829 #define SCB_INTR_I2C_EC_MASKED(base) (((CySCB_Type*) (base))->INTR_I2C_EC_MASKED) 1830 #define SCB_INTR_SPI_EC(base) (((CySCB_Type*) (base))->INTR_SPI_EC) 1831 #define SCB_INTR_SPI_EC_MASK(base) (((CySCB_Type*) (base))->INTR_SPI_EC_MASK) 1832 #define SCB_INTR_SPI_EC_MASKED(base) (((CySCB_Type*) (base))->INTR_SPI_EC_MASKED) 1833 #define SCB_INTR_M(base) (((CySCB_Type*) (base))->INTR_M) 1834 #define SCB_INTR_M_SET(base) (((CySCB_Type*) (base))->INTR_M_SET) 1835 #define SCB_INTR_M_MASK(base) (((CySCB_Type*) (base))->INTR_M_MASK) 1836 #define SCB_INTR_M_MASKED(base) (((CySCB_Type*) (base))->INTR_M_MASKED) 1837 #define SCB_INTR_S(base) (((CySCB_Type*) (base))->INTR_S) 1838 #define SCB_INTR_S_SET(base) (((CySCB_Type*) (base))->INTR_S_SET) 1839 #define SCB_INTR_S_MASK(base) (((CySCB_Type*) (base))->INTR_S_MASK) 1840 #define SCB_INTR_S_MASKED(base) (((CySCB_Type*) (base))->INTR_S_MASKED) 1841 #define SCB_INTR_TX(base) (((CySCB_Type*) (base))->INTR_TX) 1842 #define SCB_INTR_TX_SET(base) (((CySCB_Type*) (base))->INTR_TX_SET) 1843 #define SCB_INTR_TX_MASK(base) (((CySCB_Type*) (base))->INTR_TX_MASK) 1844 #define SCB_INTR_TX_MASKED(base) (((CySCB_Type*) (base))->INTR_TX_MASKED) 1845 #define SCB_INTR_RX(base) (((CySCB_Type*) (base))->INTR_RX) 1846 #define SCB_INTR_RX_SET(base) (((CySCB_Type*) (base))->INTR_RX_SET) 1847 #define SCB_INTR_RX_MASK(base) (((CySCB_Type*) (base))->INTR_RX_MASK) 1848 #define SCB_INTR_RX_MASKED(base) (((CySCB_Type*) (base))->INTR_RX_MASKED) 1849 1850 #else /* PSoC Devices */ 1851 #define SCB_CTRL(base) (((CySCB_V1_Type*) (base))->CTRL) 1852 #define SCB_SPI_CTRL(base) (((CySCB_V1_Type*) (base))->SPI_CTRL) 1853 #define SCB_SPI_STATUS(base) (((CySCB_V1_Type*) (base))->SPI_STATUS) 1854 #define SCB_UART_CTRL(base) (((CySCB_V1_Type*) (base))->UART_CTRL) 1855 #define SCB_UART_TX_CTRL(base) (((CySCB_V1_Type*) (base))->UART_TX_CTRL) 1856 #define SCB_UART_RX_CTRL(base) (((CySCB_V1_Type*) (base))->UART_RX_CTRL) 1857 #define SCB_UART_FLOW_CTRL(base) (((CySCB_V1_Type*) (base))->UART_FLOW_CTRL) 1858 #define SCB_I2C_CTRL(base) (((CySCB_V1_Type*) (base))->I2C_CTRL) 1859 #define SCB_I2C_STATUS(base) (((CySCB_V1_Type*) (base))->I2C_STATUS) 1860 #define SCB_I2C_M_CMD(base) (((CySCB_V1_Type*) (base))->I2C_M_CMD) 1861 #define SCB_I2C_S_CMD(base) (((CySCB_V1_Type*) (base))->I2C_S_CMD) 1862 #define SCB_I2C_CFG(base) (((CySCB_V1_Type*) (base))->I2C_CFG) 1863 #define SCB_TX_CTRL(base) (((CySCB_V1_Type*) (base))->TX_CTRL) 1864 #define SCB_TX_FIFO_CTRL(base) (((CySCB_V1_Type*) (base))->TX_FIFO_CTRL) 1865 #define SCB_TX_FIFO_STATUS(base) (((CySCB_V1_Type*) (base))->TX_FIFO_STATUS) 1866 #define SCB_TX_FIFO_WR(base) (((CySCB_V1_Type*) (base))->TX_FIFO_WR) 1867 #define SCB_RX_CTRL(base) (((CySCB_V1_Type*) (base))->RX_CTRL) 1868 #define SCB_RX_FIFO_CTRL(base) (((CySCB_V1_Type*) (base))->RX_FIFO_CTRL) 1869 #define SCB_RX_FIFO_STATUS(base) (((CySCB_V1_Type*) (base))->RX_FIFO_STATUS) 1870 #define SCB_RX_MATCH(base) (((CySCB_V1_Type*) (base))->RX_MATCH) 1871 #define SCB_RX_FIFO_RD(base) (((CySCB_V1_Type*) (base))->RX_FIFO_RD) 1872 #define SCB_INTR_CAUSE(base) (((CySCB_V1_Type*) (base))->INTR_CAUSE) 1873 #define SCB_INTR_I2C_EC(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC) 1874 #define SCB_INTR_I2C_EC_MASK(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC_MASK) 1875 #define SCB_INTR_I2C_EC_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_I2C_EC_MASKED) 1876 #define SCB_INTR_SPI_EC(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC) 1877 #define SCB_INTR_SPI_EC_MASK(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC_MASK) 1878 #define SCB_INTR_SPI_EC_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_SPI_EC_MASKED) 1879 #define SCB_INTR_M(base) (((CySCB_V1_Type*) (base))->INTR_M) 1880 #define SCB_INTR_M_SET(base) (((CySCB_V1_Type*) (base))->INTR_M_SET) 1881 #define SCB_INTR_M_MASK(base) (((CySCB_V1_Type*) (base))->INTR_M_MASK) 1882 #define SCB_INTR_M_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_M_MASKED) 1883 #define SCB_INTR_S(base) (((CySCB_V1_Type*) (base))->INTR_S) 1884 #define SCB_INTR_S_SET(base) (((CySCB_V1_Type*) (base))->INTR_S_SET) 1885 #define SCB_INTR_S_MASK(base) (((CySCB_V1_Type*) (base))->INTR_S_MASK) 1886 #define SCB_INTR_S_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_S_MASKED) 1887 #define SCB_INTR_TX(base) (((CySCB_V1_Type*) (base))->INTR_TX) 1888 #define SCB_INTR_TX_SET(base) (((CySCB_V1_Type*) (base))->INTR_TX_SET) 1889 #define SCB_INTR_TX_MASK(base) (((CySCB_V1_Type*) (base))->INTR_TX_MASK) 1890 #define SCB_INTR_TX_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_TX_MASKED) 1891 #define SCB_INTR_RX(base) (((CySCB_V1_Type*) (base))->INTR_RX) 1892 #define SCB_INTR_RX_SET(base) (((CySCB_V1_Type*) (base))->INTR_RX_SET) 1893 #define SCB_INTR_RX_MASK(base) (((CySCB_V1_Type*) (base))->INTR_RX_MASK) 1894 #define SCB_INTR_RX_MASKED(base) (((CySCB_V1_Type*) (base))->INTR_RX_MASKED) 1895 #endif /* (defined(CY_DEVICE_TVIIBE)) */ 1896 1897 /******************************************************************************* 1898 * PROFILE 1899 *******************************************************************************/ 1900 1901 #define CY_EP_MONITOR_COUNT ((uint32_t)(cy_device->epMonitorNr)) 1902 #define CY_EP_CNT_NR (8UL) 1903 #define PROFILE_CTL (((PROFILE_V1_Type*) PROFILE_BASE)->CTL) 1904 #define PROFILE_STATUS (((PROFILE_V1_Type*) PROFILE_BASE)->STATUS) 1905 #define PROFILE_CMD (((PROFILE_V1_Type*) PROFILE_BASE)->CMD) 1906 #define PROFILE_INTR (((PROFILE_V1_Type*) PROFILE_BASE)->INTR) 1907 #define PROFILE_INTR_MASK (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASK) 1908 #define PROFILE_INTR_MASKED (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASKED) 1909 #define PROFILE_CNT_STRUCT (((PROFILE_V1_Type*) PROFILE_BASE)->CNT_STRUCT) 1910 1911 1912 /******************************************************************************* 1913 * BLE 1914 *******************************************************************************/ 1915 1916 #define BLE_RCB_INTR (((BLE_V1_Type *) BLE_BASE)->RCB.INTR) 1917 #define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR) 1918 #define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD) 1919 #define BLE_RCB_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL) 1920 #define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL) 1921 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG) 1922 #define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG) 1923 #define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS) 1924 #define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG) 1925 #define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2) 1926 #define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3) 1927 #define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL) 1928 #define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN) 1929 #define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL) 1930 #define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT) 1931 #define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR) 1932 #define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR) 1933 #define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR) 1934 #define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR) 1935 #define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR) 1936 1937 1938 /******************************************************************************* 1939 * USBFS Device 1940 *******************************************************************************/ 1941 1942 #define USBFS_DEV_CR0(base) (((USBFS_V1_Type *)(base))->USBDEV.CR0) 1943 #define USBFS_DEV_CR1(base) (((USBFS_V1_Type *)(base))->USBDEV.CR1) 1944 #define USBFS_DEV_USBIO_CR0(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR0) 1945 #define USBFS_DEV_USBIO_CR2(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR2) 1946 #define USBFS_DEV_USBIO_CR1(base) (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR1) 1947 #define USBFS_DEV_USB_CLK_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.USB_CLK_EN) 1948 #define USBFS_DEV_BUS_RST_CNT(base) (((USBFS_V1_Type *)(base))->USBDEV.BUS_RST_CNT) 1949 #define USBFS_DEV_OSCLK_DR0(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE) 1950 #define USBFS_DEV_OSCLK_DR1(base) (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR0) 1951 #define USBFS_DEV_SOF0(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF0) 1952 #define USBFS_DEV_SOF1(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF1) 1953 #define USBFS_DEV_SOF16(base) (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR1) 1954 #define USBFS_DEV_OSCLK_DR16(base) (((USBFS_V1_Type *)(base))->USBDEV.SOF16) 1955 #define USBFS_DEV_ARB_CFG(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_CFG) 1956 #define USBFS_DEV_DYN_RECONFIG(base) (((USBFS_V1_Type *)(base))->USBDEV.DYN_RECONFIG) 1957 #define USBFS_DEV_BUF_SIZE(base) (((USBFS_V1_Type *)(base))->USBDEV.BUF_SIZE) 1958 #define USBFS_DEV_EP_ACTIVE(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_ACTIVE) 1959 #define USBFS_DEV_EP_TYPE(base) (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE) 1960 #define USBFS_DEV_CWA16(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA16) 1961 #define USBFS_DEV_CWA(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA) 1962 #define USBFS_DEV_CWA_MSB(base) (((USBFS_V1_Type *)(base))->USBDEV.CWA_MSB) 1963 #define USBFS_DEV_DMA_THRES16(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES16) 1964 #define USBFS_DEV_DMA_THRES(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES) 1965 #define USBFS_DEV_DMA_THRES_MSB(base) (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES_MSB) 1966 1967 #define USBFS_DEV_SIE_EP_INT_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_EN) 1968 #define USBFS_DEV_SIE_EP_INT_SR(base) (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_SR) 1969 #define USBFS_DEV_ARB_INT_EN(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_EN) 1970 #define USBFS_DEV_ARB_INT_SR(base) (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_SR) 1971 1972 #define USBFS_DEV_EP0_CR(base) (((USBFS_V1_Type *)(base))->USBDEV.EP0_CR) 1973 #define USBFS_DEV_EP0_CNT(base) (((USBFS_V1_Type *)(base))->USBDEV.EP0_CNT) 1974 #define USBFS_DEV_EP0_DR(base, idx) (((USBFS_V1_Type *)(base))->USBDEV.EP0_DR[idx]) 1975 1976 #define USBFS_DEV_MEM_DATA(base, idx) (((USBFS_V1_Type *)(base))->USBDEV.MEM[idx]) 1977 1978 #define USBFS_DEV_SIE_REGS_BASE (0x30U) 1979 #define USBFS_DEV_SIE_REGS_SIZE (0x40U) 1980 #define USBFS_DEV_SIE_EP_CNT0_OFFSET (0x00U) 1981 #define USBFS_DEV_SIE_EP_CNT1_OFFSET (0x04U) 1982 #define USBFS_DEV_SIE_EP_CR0_OFFSET (0x08U) 1983 #define USBFS_DEV_SIE_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_SIE_REGS_BASE + ((endpoint) * USBFS_DEV_SIE_REGS_SIZE)) 1984 1985 #define USBFS_DEV_SIE_EP_CNT0(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \ 1986 USBFS_DEV_SIE_EP_CNT0_OFFSET)) 1987 #define USBFS_DEV_SIE_EP_CNT1(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \ 1988 USBFS_DEV_SIE_EP_CNT1_OFFSET)) 1989 #define USBFS_DEV_SIE_EP_CR0(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \ 1990 USBFS_DEV_SIE_EP_CR0_OFFSET)) 1991 1992 #define USBFS_DEV_ARB_REGS_BASE (0x200U) 1993 #define USBFS_DEV_ARB_REGS_SIZE (0x40U) 1994 #define USBFS_DEV_ARB_EP_CFG_OFFSET (0x00U) 1995 #define USBFS_DEV_ARB_EP_INT_EN_OFFSET (0x04U) 1996 #define USBFS_DEV_ARB_EP_SR_OFFSET (0x08U) 1997 #define USBFS_DEV_ARB_RW_WA_OFFSET (0x10U) 1998 #define USBFS_DEV_ARB_RW_WA_MSB_OFFSET (0x14U) 1999 #define USBFS_DEV_ARB_RW_RA_OFFSET (0x18U) 2000 #define USBFS_DEV_ARB_RW_RA_MSB_OFFSET (0x1CU) 2001 #define USBFS_DEV_ARB_RW_DR_OFFSET (0x20U) 2002 #define USBFS_DEV_ARB_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS_BASE + ((endpoint) * USBFS_DEV_ARB_REGS_SIZE)) 2003 2004 #define USBFS_DEV_ARB_EP_CFG(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2005 USBFS_DEV_ARB_EP_CFG_OFFSET)) 2006 #define USBFS_DEV_ARB_EP_INT_EN(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2007 USBFS_DEV_ARB_EP_INT_EN_OFFSET)) 2008 #define USBFS_DEV_ARB_EP_SR(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2009 USBFS_DEV_ARB_EP_SR_OFFSET)) 2010 #define USBFS_DEV_ARB_RW_WA(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2011 USBFS_DEV_ARB_RW_WA_OFFSET)) 2012 #define USBFS_DEV_ARB_RW_WA_MSB(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2013 USBFS_DEV_ARB_RW_WA_MSB_OFFSET)) 2014 #define USBFS_DEV_ARB_RW_RA(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2015 USBFS_DEV_ARB_RW_RA_OFFSET)) 2016 #define USBFS_DEV_ARB_RW_RA_MSB(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2017 USBFS_DEV_ARB_RW_RA_MSB_OFFSET)) 2018 #define USBFS_DEV_ARB_RW_DR(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \ 2019 USBFS_DEV_ARB_RW_DR_OFFSET)) 2020 2021 #define USBFS_DEV_ARB_REGS16_BASE (0x1210U) 2022 #define USBFS_DEV_ARB_REGS16_SIZE (0x40U) 2023 #define USBFS_DEV_ARB_RW_WA16_OFFSET (0x00U) 2024 #define USBFS_DEV_ARB_RW_RA16_OFFSET (0x08U) 2025 #define USBFS_DEV_ARB_RW_DR16_OFFSET (0x10U) 2026 #define USBFS_DEV_ARB_REGS_16(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS16_BASE + ((endpoint) * USBFS_DEV_ARB_REGS16_SIZE)) 2027 2028 #define USBFS_DEV_ARB_RW_WA16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \ 2029 USBFS_DEV_ARB_RW_WA16_OFFSET)) 2030 #define USBFS_DEV_ARB_RW_RA16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \ 2031 USBFS_DEV_ARB_RW_RA16_OFFSET)) 2032 #define USBFS_DEV_ARB_RW_DR16(base, endpoint) (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \ 2033 USBFS_DEV_ARB_RW_DR16_OFFSET)) 2034 2035 #define USBFS_DEV_LPM_POWER_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.POWER_CTL) 2036 #define USBFS_DEV_LPM_USBIO_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.USBIO_CTL) 2037 #define USBFS_DEV_LPM_FLOW_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.FLOW_CTL) 2038 #define USBFS_DEV_LPM_LPM_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.LPM_CTL) 2039 #define USBFS_DEV_LPM_LPM_STAT(base) (((USBFS_V1_Type const *)(base))->USBLPM.LPM_STAT) 2040 #define USBFS_DEV_LPM_INTR_SIE(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE) 2041 #define USBFS_DEV_LPM_INTR_SIE_SET(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_SET) 2042 #define USBFS_DEV_LPM_INTR_SIE_MASK(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASK) 2043 #define USBFS_DEV_LPM_INTR_SIE_MASKED(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASKED) 2044 #define USBFS_DEV_LPM_INTR_LVL_SEL(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_LVL_SEL) 2045 #define USBFS_DEV_LPM_INTR_CAUSE_HI(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_HI) 2046 #define USBFS_DEV_LPM_INTR_CAUSE_MED(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_MED) 2047 #define USBFS_DEV_LPM_INTR_CAUSE_LO(base) (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_LO) 2048 #define USBFS_DEV_LPM_DFT_CTL(base) (((USBFS_V1_Type *)(base))->USBLPM.DFT_CTL) 2049 2050 #define USBFS_HOST_CTL0(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL0) 2051 #define USBFS_HOST_CTL1(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL1) 2052 #define USBFS_HOST_CTL2(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL2) 2053 #define USBFS_HOST_ERR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_ERR) 2054 #define USBFS_HOST_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_STATUS) 2055 #define USBFS_HOST_FCOMP(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_FCOMP) 2056 #define USBFS_HOST_RTIMER(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_RTIMER) 2057 #define USBFS_HOST_ADDR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_ADDR) 2058 #define USBFS_HOST_EOF(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EOF) 2059 #define USBFS_HOST_FRAME(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_FRAME) 2060 #define USBFS_HOST_TOKEN(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_TOKEN) 2061 #define USBFS_HOST_EP1_CTL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_CTL) 2062 #define USBFS_HOST_EP1_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_STATUS) 2063 #define USBFS_HOST_EP1_RW1_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW1_DR) 2064 #define USBFS_HOST_EP1_RW2_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW2_DR) 2065 #define USBFS_HOST_EP2_CTL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_CTL) 2066 #define USBFS_HOST_EP2_STATUS(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_STATUS) 2067 #define USBFS_HOST_EP2_RW1_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW1_DR) 2068 #define USBFS_HOST_EP2_RW2_DR(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW2_DR) 2069 #define USBFS_HOST_LVL1_SEL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL1_SEL) 2070 #define USBFS_HOST_LVL2_SEL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL2_SEL) 2071 #define USBFS_INTR_USBHOST_CAUSE_HI(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_HI) 2072 #define USBFS_INTR_USBHOST_CAUSE_MED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_MED) 2073 #define USBFS_INTR_USBHOST_CAUSE_LO(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_LO) 2074 #define USBFS_INTR_HOST_EP_CAUSE_HI(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_HI) 2075 #define USBFS_INTR_HOST_EP_CAUSE_MED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_MED) 2076 #define USBFS_INTR_HOST_EP_CAUSE_LO(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_LO) 2077 #define USBFS_INTR_USBHOST(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST) 2078 #define USBFS_INTR_USBHOST_SET(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_SET) 2079 #define USBFS_INTR_USBHOST_MASK(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASK) 2080 #define USBFS_INTR_USBHOST_MASKED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASKED) 2081 #define USBFS_INTR_HOST_EP(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP) 2082 #define USBFS_INTR_HOST_EP_SET(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_SET) 2083 #define USBFS_INTR_HOST_EP_MASK(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASK) 2084 #define USBFS_INTR_HOST_EP_MASKED(base) (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASKED) 2085 #define USBFS_HOST_DMA_ENBL(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_DMA_ENBL) 2086 #define USBFS_HOST_EP1_BLK(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_BLK) 2087 #define USBFS_HOST_EP2_BLK(base) (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_BLK) 2088 2089 2090 #if (defined (CY_IP_MXS40USBHSDEV)) 2091 /******************************************************************************* 2092 * MXS40USBHSDEV 2093 *******************************************************************************/ 2094 2095 #define USBHSDEV_DEV_PWR_CS_DISCON (1U << USBHSDEV_DEV_PWR_CS_DISCON_Pos) 2096 #define USBHSDEV_DEV_LPM_ATTR_RMT_WAKEUP_ENABLE (1U << USBHSDEV_DEV_LPM_ATTR_RMT_WAKEUP_ENABLE_Pos) 2097 #define USBHSDEV_DEV_LPM_ATTR_L2_SUSP_RMT_WAKEUP_EN (1U << USBHSDEV_DEV_LPM_ATTR_L2_SUSP_RMT_WAKEUP_EN_Pos) 2098 #define USBHSDEV_DEV_PWR_CS_DEV_SUSPEND (1U << USBHSDEV_DEV_PWR_CS_DEV_SUSPEND_Pos) 2099 #define USBHSDEV_DEV_PWR_CS_FORCE_FS (1U << USBHSDEV_DEV_PWR_CS_FORCE_FS_Pos) 2100 #define USBHSDEV_DEV_PWR_CS_SIGRSUME (1U << USBHSDEV_DEV_PWR_CS_SIGRSUME_Pos) 2101 #define USBHSDEV_DEV_PWR_CS_L0_ACTIVE (1U << USBHSDEV_DEV_PWR_CS_L0_ACTIVE_Pos) 2102 #define USBHSDEV_DEV_PWR_CS_L2_SUSPEND (1U << USBHSDEV_DEV_PWR_CS_L2_SUSPEND_Pos) 2103 #define USBHSDEV_DEV_PWR_CS_L1_SLEEP (1U << USBHSDEV_DEV_PWR_CS_L1_SLEEP_Pos) 2104 #define USBHSDEV_DEV_EPI_CS_NAK (1U << USBHSDEV_DEV_EPI_CS_NAK_Pos) 2105 #define USBHSDEV_DEV_EPO_CS_NAK (1U << USBHSDEV_DEV_EPO_CS_NAK_Pos) 2106 #define USBHSDEV_DEV_CS_SETUP_CLR_BUSY (1U << USBHSDEV_DEV_CS_SETUP_CLR_BUSY_Pos) 2107 #define USBHSDEV_DEV_CS_NAKALL (1U << USBHSDEV_DEV_CS_NAKALL_Pos) 2108 #define USBHSDEV_DEV_EPI_CS_STALL (1U << USBHSDEV_DEV_EPI_CS_STALL_Pos) 2109 #define USBHSDEV_DEV_EPO_CS_STALL (1U << USBHSDEV_DEV_EPO_CS_STALL_Pos) 2110 #define USBHSDEV_DEV_TOGGLE_IO (1U << USBHSDEV_DEV_TOGGLE_IO_Pos) 2111 #define USBHSDEV_DEV_TOGGLE_TOGGLE_VALID (1U << USBHSDEV_DEV_TOGGLE_TOGGLE_VALID_Pos) 2112 #define USBHSDEV_DEV_TOGGLE_R (1U << USBHSDEV_DEV_TOGGLE_R_Pos) 2113 #define USBHSDEV_DEV_EPO_CS_VALID (1U << USBHSDEV_DEV_EPO_CS_VALID_Pos) 2114 #define USBHSDEV_DEV_EPI_CS_VALID (1U << USBHSDEV_DEV_EPI_CS_VALID_Pos) 2115 #define USBHSDEV_EEPM_ENDPOINT_EGRS_FLUSH_EP (1U << USBHSDEV_EEPM_ENDPOINT_EGRS_FLUSH_EP_Pos) 2116 #define USBHSDEV_EPM_CS_EGRS_FORCE_FLUSH_ALL (1U << USBHSDEV_EPM_CS_EGRS_FORCE_FLUSH_ALL_Pos) 2117 #define USBHSDEV_EPM_CS_IGRS_FORCE_FLUSH_ALL (1U << USBHSDEV_EPM_CS_IGRS_FORCE_FLUSH_ALL_Pos) 2118 #define USBHSDEV_DEV_EPI_CS_ZERO_MASK (1U << USBHSDEV_DEV_EPI_CS_ZERO_MASK_Pos) 2119 #define USBHSDEV_DEV_CTL_INTR_MASK_SETADDR (1U << USBHSDEV_DEV_CTL_INTR_MASK_SETADDR_Pos) 2120 #define USBHSDEV_DEV_CTL_INTR_MASK_SOF (1U << USBHSDEV_DEV_CTL_INTR_MASK_SOF_Pos) 2121 #define USBHSDEV_DEV_CTL_INTR_MASK_SUSP (1U << USBHSDEV_DEV_CTL_INTR_MASK_SUSP_Pos) 2122 #define USBHSDEV_DEV_CTL_INTR_MASK_URESET (1U << USBHSDEV_DEV_CTL_INTR_MASK_URESET_Pos) 2123 #define USBHSDEV_DEV_CTL_INTR_MASK_HSGRANT (1U << USBHSDEV_DEV_CTL_INTR_MASK_HSGRANT_Pos) 2124 #define USBHSDEV_DEV_CTL_INTR_MASK_SUTOK (1U << USBHSDEV_DEV_CTL_INTR_MASK_SUTOK_Pos) 2125 #define USBHSDEV_DEV_CTL_INTR_MASK_SUDAV (1U << USBHSDEV_DEV_CTL_INTR_MASK_SUDAV_Pos) 2126 #define USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT (1U << USBHSDEV_DEV_CTL_INTR_MASK_ERRLIMIT_Pos) 2127 #define USBHSDEV_DEV_CTL_INTR_MASK_URESUME (1U << USBHSDEV_DEV_CTL_INTR_MASK_URESUME_Pos) 2128 #define USBHSDEV_DEV_CTL_INTR_MASK_STATUS_STAGE (1U << USBHSDEV_DEV_CTL_INTR_MASK_STATUS_STAGE_Pos) 2129 #define USBHSDEV_DEV_CTL_INTR_MASK_L1_SLEEP_REQ (1U << USBHSDEV_DEV_CTL_INTR_MASK_L1_SLEEP_REQ_Pos) 2130 #define USBHSDEV_DEV_CTL_INTR_MASK_L1_URESUME (1U << USBHSDEV_DEV_CTL_INTR_MASK_L1_URESUME_Pos) 2131 #define USBHSDEV_DEV_CTL_INTR_MASK_RESETDONE (1U << USBHSDEV_DEV_CTL_INTR_MASK_RESETDONE_Pos) 2132 #define USBHSDEV_DEV_CTL_INTR_MASK_HOST_URSUME_ARRIVED (1U << USBHSDEV_DEV_CTL_INTR_MASK_HOST_URSUME_ARRIVED_Pos) 2133 #define USBHSDEV_DEV_CTL_INTR_MASK_DPSLP (1U << USBHSDEV_DEV_CTL_INTR_MASK_DPSLP_Pos) 2134 #define USBHSDEV_DEV_CTL_INTR_MASK_PID_MISMATCH_ON_NAK (1U << USBHSDEV_DEV_CTL_INTR_MASK_PID_MISMATCH_ON_NAK_Pos) 2135 #define USBHSDEV_DEV_CTL_INTR_SETADDR (1U << USBHSDEV_DEV_CTL_INTR_SETADDR_Pos) 2136 #define USBHSDEV_DEV_CTL_INTR_SOF (1U << USBHSDEV_DEV_CTL_INTR_SOF_Pos) 2137 #define USBHSDEV_DEV_CTL_INTR_SUSP (1U << USBHSDEV_DEV_CTL_INTR_SUSP_Pos) 2138 #define USBHSDEV_DEV_CTL_INTR_URESET (1U << USBHSDEV_DEV_CTL_INTR_URESET_Pos) 2139 #define USBHSDEV_DEV_CTL_INTR_HSGRANT (1U << USBHSDEV_DEV_CTL_INTR_HSGRANT_Pos) 2140 #define USBHSDEV_DEV_CTL_INTR_SUTOK (1U << USBHSDEV_DEV_CTL_INTR_SUTOK_Pos) 2141 #define USBHSDEV_DEV_CTL_INTR_SUDAV (1U << USBHSDEV_DEV_CTL_INTR_SUDAV_Pos) 2142 #define USBHSDEV_DEV_CTL_INTR_ERRLIMIT (1U << USBHSDEV_DEV_CTL_INTR_ERRLIMIT_Pos) 2143 #define USBHSDEV_DEV_CTL_INTR_URESUME (1U << USBHSDEV_DEV_CTL_INTR_URESUME_Pos) 2144 #define USBHSDEV_DEV_CTL_INTR_STATUS_STAGE (1U << USBHSDEV_DEV_CTL_INTR_STATUS_STAGE_Pos) 2145 #define USBHSDEV_DEV_CTL_INTR_L1_SLEEP_REQ (1U << USBHSDEV_DEV_CTL_INTR_L1_SLEEP_REQ_Pos) 2146 #define USBHSDEV_DEV_CTL_INTR_L1_URESUME (1U << USBHSDEV_DEV_CTL_INTR_L1_URESUME_Pos) 2147 #define USBHSDEV_DEV_CTL_INTR_RESETDONE (1U << USBHSDEV_DEV_CTL_INTR_RESETDONE_Pos) 2148 #define USBHSDEV_DEV_CTL_INTR_HOST_URSUME_ARRIVED (1U << USBHSDEV_DEV_CTL_INTR_HOST_URSUME_ARRIVED_Pos) 2149 #define USBHSDEV_DEV_CTL_INTR_DPSLP (1U << USBHSDEV_DEV_CTL_INTR_DPSLP_Pos) 2150 #define USBHSDEV_DEV_CTL_INTR_PID_MISMATCH_ON_NAK (1U << USBHSDEV_DEV_CTL_INTR_PID_MISMATCH_ON_NAK_Pos) 2151 #define USBHSDEV_DEV_EPI_CS_ZERO (1U << USBHSDEV_DEV_EPI_CS_ZERO_Pos) 2152 #define USBHSDEV_DEV_EPI_CS_COMMIT (1U << USBHSDEV_DEV_EPI_CS_COMMIT_Pos) 2153 #define USBHSPHY_PLL_CONTROL_1_SUPPLY_EN (1U << USBHSPHY_PLL_CONTROL_1_SUPPLY_EN_Pos) 2154 #define USBHSPHY_PLL_CONTROL_1_PLL_EN (1U << USBHSPHY_PLL_CONTROL_1_PLL_EN_Pos) 2155 #define USBHSPHY_CDR_CONTROL_CDR_ENABLE (1U << USBHSPHY_CDR_CONTROL_CDR_ENABLE_Pos) 2156 #define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_HS_VCCD (1U << USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_HS_VCCD_Pos) 2157 #define USBHSPHY_REG_1P1_CONTROL_ENABLE_LV (1U << USBHSPHY_REG_1P1_CONTROL_ENABLE_LV_Pos) 2158 #define USBHSPHY_REG_2P5_CONTROL_BYPASS_MODE (1U << USBHSPHY_REG_2P5_CONTROL_BYPASS_MODE_Pos) 2159 #define USBHSPHY_VREFGEN_CONTROL_ENABLE_LV (1U << USBHSPHY_VREFGEN_CONTROL_ENABLE_LV_Pos) 2160 #define USBHSPHY_IREFGEN_CONTROL_ENABLE_LV (1U << USBHSPHY_IREFGEN_CONTROL_ENABLE_LV_Pos) 2161 #define USBHSPHY_REG_1P1_CONTROL_SWITCH_EN (1U << USBHSPHY_REG_1P1_CONTROL_SWITCH_EN_Pos) 2162 #define USBHSPHY_INTR0_ENABLE_HS_VCCD (1U << USBHSPHY_INTR0_ENABLE_HS_VCCD_Pos) 2163 #define USBHSPHY_INTR0_PLL_LOCK (1U << USBHSPHY_INTR0_PLL_LOCK_Pos) 2164 #define USBHSPHY_REG_2P5_CONTROL_ENABLE_LV (1U << USBHSPHY_REG_2P5_CONTROL_ENABLE_LV_Pos) 2165 #define USBHSPHY_INTR0_ENABLE_VCCD (1U << USBHSPHY_INTR0_ENABLE_VCCD_Pos) 2166 #define USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_VCCD (1U << USBHSPHY_AFE_CONTROL_1_CPU_DELAY_ENABLE_VCCD_Pos) 2167 #define USBHSDEV_POWER_RESETN (1U << USBHSDEV_POWER_RESETN_Pos) 2168 #define USBHSDEV_POWER_VBUS_VALID (1U << USBHSDEV_POWER_VBUS_VALID_Pos) 2169 #define USBHSDEV_POWER_EPM_DCG_ENABLE (1U << USBHSDEV_POWER_EPM_DCG_ENABLE_Pos) 2170 #define USBHSDEV_DEV_LPM_ATTR_NYET (1U << USBHSDEV_DEV_LPM_ATTR_NYET_Pos) 2171 #endif /* CY_IP_MXS40USBHSDEV */ 2172 2173 2174 #endif /* CY_DEVICE_H_ */ 2175 2176 /* [] END OF FILE */ 2177
