1 /***************************************************************************//**
2 * \file cy_gpio.h
3 * \version 1.90
4 *
5 * Provides an API declaration of the GPIO driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_gpio
28 * \{
29 * The GPIO driver provides an API to configure and access device Input/Output pins.
30 *
31 * The functions and other declarations used in this driver are in cy_gpio.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and
36 * their variants.
37 *
38 * Initialization can be performed either at the port level or by configuring the
39 * individual pins. For efficient use of code space, port
40 * configuration should be used in the field. Refer to the product device header files
41 * for the list of supported ports and pins.
42 *
43 * A port is represented by GPIO_PRT_Type and a pin is represented by a number
44 * 0 to 7.
45 *
46 * For PSoC 64 devices the the un-intended protected pins (due to constrain on PPU configuration)
47 * are modified using PRA driver. But the GPIO diver does not modify the intended protected pins .
48 *
49 * - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
50 * (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled
51 * cy_stc_gpio_pin_config_t structure).
52 * - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
53 * cy_stc_gpio_prt_config_t structure. The values in the structure are
54 * bitfields representing the desired value for each pin in the port.
55 * - Pin configuration and management is based on the port address and pin number.
56 * \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port
57 * address from the port number at run-time.
58 * - Each I/O is individually configurable to one of eight drive modes represented
59 * by drivemode of cy_stc_gpio_pin_config_t structure.
60 *
61 * Once the pin/port initialization is complete, each pin can be accessed by
62 * specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
63 * functions.
64 *
65 * \section group_gpio_configuration Configuration Considerations
66 *
67 * 1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection.
68 * This allows the pin to connect to signal sources/sinks throughout the device,
69 * as defined by the pin HSIOM selection options (en_hsiom_sel_t).
70 * 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW
71 * control digital pin only) at Power-On-Reset(POR).
72 * 3. Some API functions perform read-modify-write operations on shared port
73 * registers. These functions are not thread safe and care must be taken when
74 * called by the application.
75 * 4. Digital input buffer provides a high-impedance buffer for the external
76 * digital input. The input buffer is connected to the HSIOM for routing to
77 * the CPU port registers and selected peripheral. Enabling the input
78 * buffer provides possibility to read the pin state via the CPU.
79 * If pin is connected to an analog signal, the input buffer should be
80 * disabled to avoid crowbar currents. For more information refer to device
81 * TRM and the device datasheet.
82 *
83 * Multiple pins on a port can be updated using direct port register writes with an
84 * appropriate port mask. An example is shown below, highlighting the different ways of
85 * configuring Port 1 pins using:
86 *
87 * - Initialize a Pin using cy_stc_gpio_pin_config_t structure
88 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_Init
89 *
90 * - Initialize entire port using cy_stc_gpio_prt_config_t structure
91 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Init
92 *
93 * - Port output data register
94 * - Port output data set register
95 * - Port output data clear register
96 *
97 * \snippet gpio/snippet/main.c Cy_GPIO_Snippet
98 *
99 * \section group_gpio_more_information More Information
100 *
101 * Refer to the technical reference manual (TRM) and the device datasheet.
102 *
103 * \section group_gpio_changelog Changelog
104 * <table class="doxtable">
105 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
106 * <tr>
107 * <td>1.90</td>
108 * <td>Updated APIs \ref Cy_GPIO_Port_Init, \ref Cy_GPIO_Port_Deinit, \ref Cy_GPIO_GetDrivemode.</td>
109 * <td>Fixed coverity defects.</td>
110 * </tr>
111 * <tr>
112 * <td rowspan="2">1.80</td>
113 * <td>Updated \ref Cy_GPIO_SetDrivemode and \ref Cy_GPIO_GetDrivemode APIs.</td>
114 * <td>Updated drive mode configuration for CAT1D devices.</td>
115 * </tr>
116 * <tr>
117 * <td>Fixed MISRA 2012 violations.</td>
118 * <td>MISRA 2012 compliance.</td>
119 * </tr>
120 * <tr>
121 * <td>1.70</td>
122 * <td>Updated driver to support the CAT1D family of devices.</td>
123 * <td>Added new family of devices.</td>
124 * </tr>
125 * <tr>
126 * <td rowspan="2">1.60</td>
127 * <td>Added \ref Cy_GPIO_SetVtripAuto and \ref Cy_GPIO_GetVtripAuto APIs for
128 * configuring GPIO input buffer voltage for automotive compatible or not,
129 * for CAT1C devices.</td>
130 * <td>New APIs support for CAT1C devices.</td>
131 * </tr>
132 * <tr>
133 * <td>Fixed unused variables error.</td>
134 * <td>Minor error fixes.</td>
135 * </tr>
136 * <tr>
137 * <td>1.50.1</td>
138 * <td>Updated doxygen for External clock source to HF0.</td>
139 * <td>Documentation enhancement.</td>
140 * </tr>
141 * <tr>
142 * <td>1.50</td>
143 * <td>Modified \ref Cy_GPIO_Pin_Init, \ref Cy_GPIO_Pin_FastInit, and
144 * \ref Cy_GPIO_SetDrivemode APIs to catch wrong drive modes.</td>
145 * <td>Defect fix.</td>
146 * </tr>
147 * <tr>
148 * <td rowspan="2">1.40</td>
149 * <td>Changes in Support of the new family of devices</td>
150 * <td>Added new family of devices</td>
151 * </tr>
152 * <tr>
153 * <td>Changes in support of Secure pins used for External clocks on Secure devices</td>
154 * <td>Added support for accessing External clocks protected pins</td>
155 * </tr>
156 * <tr>
157 * <td>1.30</td>
158 * <td>Fixed/documented MISRA 2012 violations.</td>
159 * <td>MISRA 2012 compliance.</td>
160 * </tr>
161 * <tr>
162 * <td>1.20.1</td>
163 * <td>Minor documentation updates.</td>
164 * <td>Documentation enhancement.</td>
165 * </tr>
166 * <tr>
167 * <td rowspan="3">1.20</td>
168 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
169 * <td>Driver library directory-structure simplification.</td>
170 * </tr>
171 * <tr>
172 * <td>Added the functions for configuring the AMux bus splitter switch cells:
173 * - \ref Cy_GPIO_SetAmuxSplit
174 * - \ref Cy_GPIO_GetAmuxSplit
175 * </td>
176 * <td>Added a new functionality related to AMux bus.</td>
177 * </tr>
178 * <tr>
179 * <td>Added register access layer. Use register access macros instead
180 * of direct register access using dereferenced pointers.</td>
181 * <td>Makes register access device-independent, so that the PDL does
182 * not need to be recompiled for each supported part number.</td>
183 * </tr>
184 * <tr>
185 * <td>1.10.1</td>
186 * <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
187 * \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked.
188 *
189 * Minor documentation edits.
190 * </td>
191 * <td>Documentation update and clarification</td>
192 * </tr>
193 * <tr>
194 * <td>1.10</td>
195 * <td>Added input parameter validation to the API functions</td>
196 * <td></td>
197 * </tr>
198 * <tr>
199 * <td>1.0</td>
200 * <td>Initial version</td>
201 * <td></td>
202 * </tr>
203 * </table>
204 *
205 * \defgroup group_gpio_macros Macros
206 * \defgroup group_gpio_functions Functions
207 * \{
208 * \defgroup group_gpio_functions_init Initialization Functions
209 * \defgroup group_gpio_functions_gpio GPIO Functions
210 * \defgroup group_gpio_functions_sio SIO Functions
211 * \defgroup group_gpio_functions_interrupt Port Interrupt Functions
212 * \}
213 * \defgroup group_gpio_data_structures Data Structures
214 * \defgroup group_gpio_enums Enumerated Types
215 */
216
217 #if !defined(CY_GPIO_H)
218 #define CY_GPIO_H
219
220 #include "cy_device.h"
221
222 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
223
224 #include <stddef.h>
225 #include "cy_syslib.h"
226
227 #if defined(__cplusplus)
228 extern "C" {
229 #endif
230
231 /** \addtogroup group_gpio_macros
232 * \{
233 */
234
235 /** Driver major version */
236 #define CY_GPIO_DRV_VERSION_MAJOR 1
237
238 /** Driver minor version */
239 #define CY_GPIO_DRV_VERSION_MINOR 90
240
241 /** GPIO driver ID */
242 #define CY_GPIO_ID CY_PDL_DRV_ID(0x16U)
243
244 /** \} group_gpio_macros */
245
246
247 /***************************************
248 * Enumerations
249 ***************************************/
250 /**
251 * \addtogroup group_gpio_enums
252 * \{
253 */
254
255 /** GPIO Driver error codes */
256 typedef enum
257 {
258 CY_GPIO_SUCCESS = 0x00U, /**< Returned successful */
259 CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */
260 } cy_en_gpio_status_t;
261
262 /** AMux switch open/close config */
263 typedef enum
264 {
265 CY_GPIO_AMUX_OPENALL, /**< Open ground switch. Open right switch. Open left switch */
266 CY_GPIO_AMUX_L, /**< Open ground switch. Open right switch. Close left switch */
267 CY_GPIO_AMUX_R, /**< Open ground switch. Close right switch. Open left switch */
268 CY_GPIO_AMUX_LR, /**< Open ground switch. Close right switch. Close left switch */
269 CY_GPIO_AMUX_G, /**< Close ground switch. Open right switch. Open left switch */
270 CY_GPIO_AMUX_GL, /**< Close ground switch. Open right switch. Close left switch */
271 CY_GPIO_AMUX_GR, /**< Close ground switch. Close right switch. Open left switch */
272 CY_GPIO_AMUX_GLR, /**< Close ground switch. Close right switch. Close left switch */
273 }cy_en_gpio_amuxconnect_t;
274
275 /**
276 * AMux Bus selection
277 */
278 typedef enum
279 {
280 CY_GPIO_AMUXBUSA, /**< AMuxBus A */
281 CY_GPIO_AMUXBUSB /**< AMuxBus B */
282 }cy_en_gpio_amuxselect_t;
283
284 /** \} group_gpio_enums */
285
286
287 /***************************************
288 * Configuration Structures
289 ***************************************/
290
291 /**
292 * \addtogroup group_gpio_data_structures
293 * \{
294 */
295
296 /** This structure is used to initialize a port of GPIO pins */
297 typedef struct
298 {
299 uint32_t out; /**< Initial output data for the IO pins in the port */
300 uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */
301 uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */
302 uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */
303 uint32_t cfgIn; /**< Port pin input buffer configuration */
304 uint32_t cfgOut; /**< Port pin output buffer configuration */
305 uint32_t cfgSIO; /**< Port SIO pins configuration */
306 uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */
307 uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */
308 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
309 /**
310 * \note
311 * This parameter is available for the CAT1B and CAT1D devices.
312 **/
313 uint32_t cfgSlew; /**< Port slew rate configuration */
314 /**
315 * \note
316 * This parameter is available for the CAT1B and CAT1D devices.
317 **/
318 uint32_t cfgDriveSel0; /**< Drive strength configuration for pins 0,1,2,3 */
319 /**
320 * \note
321 * This parameter is available for the CAT1B and CAT1D devices.
322 **/
323 uint32_t cfgDriveSel1; /**< Drive strength configuration for pins 4,5,6,7 */
324 /**
325 * \note
326 * This parameter is available for the CAT1B and CAT1D devices.
327 **/
328 uint32_t nonSecMask; /**< HSIOM non secure mask for port pins 0-7 */
329 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
330 #if defined (CY_IP_MXS22IOSS)
331 /**
332 * \note
333 * This parameter is available for the CAT1D devices.
334 **/
335 uint32_t cfgRes; /**< Pull-up resistor configuration for port pins */
336 /**
337 * \note
338 * This parameter is available for the CAT1D devices.
339 **/
340 uint32_t cfgOut3; /**< Port pin extra drive mode \ref CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ */
341 #endif /* CY_IP_MXS22IOSS */
342 } cy_stc_gpio_prt_config_t;
343
344 /** This structure is used to initialize a single GPIO pin */
345 typedef struct
346 {
347 uint32_t outVal; /**< Pin output state */
348 uint32_t driveMode; /**< Drive mode */
349 en_hsiom_sel_t hsiom; /**< HSIOM selection */
350 uint32_t intEdge; /**< Interrupt Edge type */
351 uint32_t intMask; /**< Interrupt enable mask */
352 uint32_t vtrip; /**< Input buffer voltage trip type */
353 uint32_t slewRate; /**< Output buffer slew rate */
354 uint32_t driveSel; /**< Drive strength */
355 uint32_t vregEn; /**< SIO pair output buffer mode */
356 uint32_t ibufMode; /**< SIO pair input buffer mode */
357 uint32_t vtripSel; /**< SIO pair input buffer trip point */
358 uint32_t vrefSel; /**< SIO pair reference voltage for input buffer trip point */
359 uint32_t vohSel; /**< SIO pair regulated voltage output level */
360 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
361 /**
362 * \note
363 * This parameter is available for the CAT1B and CAT1D devices.
364 **/
365 uint32_t nonSec; /**< Secure attribute for each Pin of a port */
366 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
367 #if defined (CY_IP_MXS22IOSS)
368 /**
369 * \note
370 * This parameter is available for the CAT1D devices.
371 **/
372 uint32_t pullUpRes; /**< Pull-up resistor configuration for each pin of a port */
373 #endif /* CY_IP_MXS22IOSS */
374 } cy_stc_gpio_pin_config_t;
375
376 /** \} group_gpio_data_structures */
377
378 /***************************************
379 * Constants
380 ***************************************/
381
382 /** \cond INTERNAL */
383
384 /* General Constants */
385 #define CY_GPIO_PRT_HALF (4UL) /**< Half-way point of a GPIO port */
386 #define CY_GPIO_PRT_DEINIT (0UL) /**< De-init value for port registers */
387 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
388 #define CY_HSIOM_NONSEC_DEINIT (0xFFUL) /**< De-init value for port non sec register */
389 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
390
391 /* GPIO Masks */
392 #define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */
393 #define CY_GPIO_OUT_MASK (0x01UL) /**< Single pin mask for OUT register */
394 #define CY_GPIO_IN_MASK (0x01UL) /**< Single pin mask for IN register */
395 #define CY_GPIO_CFG_DM_MASK (0x0FUL) /**< Single pin mask for drive mode in CFG register */
396 #define CY_GPIO_CFG_DM_WIDTH_MASK (0xFUL) /**< Single pin mask for drive mode width in CFG/CFG_OUT3 register */
397 #define CY_GPIO_CFG_DM_NO_INBUF_MASK (0x07UL) /**< Single pin mask for drive mode ( without input buffer ) in CFG register */
398 #define CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN register */
399 #if (defined(CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION == 3U)) || defined(CY_IP_MXS40SIOSS_VERSION)
400 #define CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN AUTOLVL register */
401 #endif /* CY_IP_MXS40IOSS_VERSION */
402 #define CY_GPIO_CFG_IN_VTRIP_SEL_MASK CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK /**< Single pin mask for VTRIP selection in CFG IN register */
403 #define CY_GPIO_INTR_STATUS_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
404 #define CY_GPIO_INTR_EN_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
405 #define CY_GPIO_INTR_MASKED_MASK (0x01UL) /**< Single pin mask for masked interrupt status in INTR_MASKED register */
406 #define CY_GPIO_INTR_SET_MASK (0x01UL) /**< Single pin mask for setting the interrupt in INTR_MASK register */
407 #define CY_GPIO_INTR_EDGE_MASK (0x03UL) /**< Single pin mask for interrupt edge type in INTR_EDGE register */
408 #define CY_GPIO_INTR_FLT_EDGE_MASK (0x07UL) /**< Single pin mask for setting filtered interrupt */
409 #if defined (CY_IP_MXS40IOSS)
410 #define CY_GPIO_CFG_OUT_SLOW_MASK (0x01UL) /**< Single pin mask for slew rate in CFG OUT register */
411 #define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) /**< Single pin mask for drive strength in CFG OUT register */
412 #else
413 #define CY_GPIO_HSIOM_SEC_MASK (0x01UL) /**< Single pin mask for NONSECURE_MASK register */
414 #define CY_GPIO_CFG_SLEW_EXT_MASK (0x07UL) /**< Single pin mask for slew rate in CFG SLEW EXT register */
415 #define CY_GPIO_CFG_DRIVE_SEL_EXT_MASK (0x1FUL) /**< Single pin mask for drive strength in CFG DRIVE EXT register */
416 #endif /* CY_IP_MXS40IOSS */
417 #if defined (CY_IP_MXS22IOSS)
418 #define CY_GPIO_CFG_RES_PULLUP_MODE_MASK (0x0FUL) /**< Single pin mask for Pull-up mode in CFG_RES register */
419 #endif /* CY_IP_MXS22IOSS */
420
421 /* SIO Masks */
422 #define CY_GPIO_VREG_EN_MASK (0x01UL) /**< Single SIO pin mask for voltage regulation enable */
423 #define CY_GPIO_IBUF_MASK (0x01UL) /**< Single SIO pin mask for input buffer */
424 #define CY_GPIO_IBUF_SHIFT (0x01UL) /**< Single SIO pin shift for input buffer */
425 #define CY_GPIO_VTRIP_SEL_MASK (0x01UL) /**< Single SIO pin mask for the input buffer trip point */
426 #define CY_GPIO_VTRIP_SEL_SHIFT (0x02UL) /**< Single SIO pin shift for the input buffer trip point */
427 #define CY_GPIO_VREF_SEL_MASK (0x03UL) /**< Single SIO pin mask for voltage reference */
428 #define CY_GPIO_VREF_SEL_SHIFT (0x03UL) /**< Single SIO pin shift for voltage reference */
429 #define CY_GPIO_VOH_SEL_MASK (0x07UL) /**< Single SIO pin mask for VOH */
430 #define CY_GPIO_VOH_SEL_SHIFT (0x05UL) /**< Single SIO pin shift for VOH */
431
432 /* Special mask for SIO pin pair setting */
433 #define CY_GPIO_SIO_ODD_PIN_MASK (0x00FEUL) /**< SIO pin pair selection mask */
434 #define CY_GPIO_SIO_PIN_MASK (0x00FFUL) /**< SIO pin pair mask */
435
436 /* Offsets */
437 #define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */
438 #define CY_GPIO_DRIVE_MODE_OFFSET (2UL) /**< Offset for Drive mode */
439 #define CY_GPIO_INBUF_OFFSET (3UL) /**< Offset for input buffer */
440 #define CY_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) /**< Offset for drive strength */
441 #define CY_GPIO_INTR_CFG_OFFSET (1UL) /**< Offset for interrupt config */
442 #define CY_GPIO_INTR_FILT_OFFSET (18UL) /**< Offset for filtered interrupt config */
443 #define CY_GPIO_CFG_SIO_OFFSET (2UL) /**< Offset for SIO config */
444 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
445 #define CY_GPIO_CFG_SLEW_EXT_OFFSET (2UL) /**< Offset for CFG SLEW EXT */
446 #define CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET (3UL) /**< Offset for CFG SLEW EXT */
447 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
448 #if defined (CY_IP_MXS22IOSS)
449 #define CY_GPIO_CFG_RES_PULLUP_MODE_OFFSET (2UL) /**< Offset for Pull-up mode */
450 #endif /* CY_IP_MXS22IOSS */
451
452 /* Parameter validation constants */
453 #define CY_GPIO_PINS_MAX (8UL) /**< Number of pins in the port */
454 #define CY_GPIO_PRT_PINS_MASK (0x0000000FFUL)
455 #define CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK (GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk | \
456 GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk | \
457 GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk | \
458 GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk | \
459 GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \
460 GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \
461 GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \
462 GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
463 #define CY_GPIO_PRT_INTR_CFG_RANGE_MASK (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \
464 GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \
465 GPIO_PRT_INTR_CFG_FLT_SEL_Msk)
466 #define CY_GPIO_PRT_INT_MASK_MASK (0x0000001FFUL)
467 #define CY_GPIO_PRT_SEL_ACTIVE_MASK (0x1FFFFFFFUL)
468 #if defined (CY_IP_MXS22IOSS)
469 #define CY_GPIO_PRT_CFG_RES_MASK (0x77777777UL)
470 #endif /* CY_IP_MXS22IOSS */
471
472 #define GPIO_MAX_SPLIT_CELL_SEGMENTS (9U)
473 #if defined (CY_IP_MXS22IOSS)
474 /* CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ is 0x80UL, but CFG_OUT3 register uses 0x8UL. */
475 /* To correctly configure drive mode value in CFG_OUT3 register, CY_GPIO_EXT_DM_SHIFT is used to shift CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ. */
476 #define CY_GPIO_EXT_DM_SHIFT (0x4UL)
477 #endif /* CY_IP_MXS22IOSS */
478
479 /* Parameter validation macros */
480 #define CY_GPIO_IS_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX > (pinNum))
481 #define CY_GPIO_IS_FILTER_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX >= (pinNum))
482 #define CY_GPIO_IS_VALUE_VALID(outVal) (1UL >= (outVal))
483
484 #if defined(CY_IP_MXS22IOSS)
485 #define CY_GPIO_IS_DM_VALID(driveMode) (((0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK)) ||\
486 ((driveMode) == CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ)) && \
487 ((driveMode) != CY_GPIO_DM_INVALID_IN_OFF) && \
488 ((driveMode) != CY_GPIO_DM_INVALID))
489 #else
490 #define CY_GPIO_IS_DM_VALID(driveMode) ((0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK)) && \
491 ((driveMode) != CY_GPIO_DM_INVALID_IN_OFF) && \
492 ((driveMode) != CY_GPIO_DM_INVALID))
493 #endif /* CY_IP_MXS22IOSS */
494
495 #define CY_GPIO_IS_HSIOM_VALID(hsiom) (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK))
496
497 #define CY_GPIO_IS_INT_EDGE_VALID(intEdge) ((CY_GPIO_INTR_DISABLE == (intEdge)) || \
498 (CY_GPIO_INTR_RISING == (intEdge)) || \
499 (CY_GPIO_INTR_FALLING == (intEdge)) || \
500 (CY_GPIO_INTR_BOTH == (intEdge)))
501
502 #define CY_GPIO_IS_VREF_SEL_VALID(vrefSel) ((CY_SIO_VREF_PINREF == (vrefSel)) || \
503 (CY_SIO_VREF_1_2V == (vrefSel)) || \
504 (CY_SIO_VREF_AMUX_A == (vrefSel)) || \
505 (CY_SIO_VREF_AMUX_B == (vrefSel)))
506
507 #define CY_GPIO_IS_VOH_SEL_VALID(vrefSel) ((CY_SIO_VOH_1_00 == (vrefSel)) || \
508 (CY_SIO_VOH_1_25 == (vrefSel)) || \
509 (CY_SIO_VOH_1_49 == (vrefSel)) || \
510 (CY_SIO_VOH_1_67 == (vrefSel)) || \
511 (CY_SIO_VOH_2_08 == (vrefSel)) || \
512 (CY_SIO_VOH_2_50 == (vrefSel)) || \
513 (CY_SIO_VOH_2_78 == (vrefSel)) || \
514 (CY_SIO_VOH_4_16 == (vrefSel)))
515
516 #if defined (CY_IP_MXS22IOSS)
517 #define CY_GPIO_IS_PULLUP_RES_VALID(PullUp) ((CY_GPIO_PULLUP_RES_DISABLE == (PullUp)) || \
518 (CY_GPIO_PULLUP_RES_570 == (PullUp)) || \
519 (CY_GPIO_PULLUP_RES_720 == (PullUp)) || \
520 (CY_GPIO_PULLUP_RES_840 == (PullUp)) || \
521 (CY_GPIO_PULLUP_RES_1100 == (PullUp)) || \
522 (CY_GPIO_PULLUP_RES_1200 == (PullUp)) || \
523 (CY_GPIO_PULLUP_RES_1800 == (PullUp)) || \
524 (CY_GPIO_PULLUP_RES_2800 == (PullUp)))
525
526 #define CY_GPIO_PRT_IS_PULLUP_RES_VALID(PullUp) (0U == ((PullUp) & (uint32_t)~CY_GPIO_PRT_CFG_RES_MASK))
527 #endif /* CY_IP_MXS22IOSS */
528
529 #define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
530 #define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK))
531 #define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK))
532 #define CY_GPIO_IS_SEL_ACT_VALID(selActive) (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK))
533
534 #define CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl) (((uint32_t) (switchCtrl)) < GPIO_MAX_SPLIT_CELL_SEGMENTS)
535
536 #define CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect) ((CY_GPIO_AMUX_OPENALL == (amuxConnect)) || \
537 (CY_GPIO_AMUX_L == (amuxConnect)) || \
538 (CY_GPIO_AMUX_R == (amuxConnect)) || \
539 (CY_GPIO_AMUX_LR == (amuxConnect)) || \
540 (CY_GPIO_AMUX_G == (amuxConnect)) || \
541 (CY_GPIO_AMUX_GL == (amuxConnect)) || \
542 (CY_GPIO_AMUX_GR == (amuxConnect)) || \
543 (CY_GPIO_AMUX_GLR == (amuxConnect)))
544
545 #define CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus) ((CY_GPIO_AMUXBUSA == (amuxBus)) || \
546 (CY_GPIO_AMUXBUSB == (amuxBus)))
547
548 #if defined (CY_IP_MXS40IOSS)
549 #define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) ((CY_GPIO_DRIVE_FULL == (driveSel)) || \
550 (CY_GPIO_DRIVE_1_2 == (driveSel)) || \
551 (CY_GPIO_DRIVE_1_4 == (driveSel)) || \
552 (CY_GPIO_DRIVE_1_8 == (driveSel)))
553 #else
554 #define CY_GPIO_IS_HSIOM_SEC_VALID(secValue) (0U == ((secValue) & (uint32_t)~CY_GPIO_HSIOM_SEC_MASK))
555 #define CY_GPIO_IS_SLEW_RATE_VALID(slewRate) (0U == ((slewRate) & (uint32_t)~CY_GPIO_CFG_SLEW_EXT_MASK))
556 #define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) (0U == ((driveSel) & (uint32_t)~CY_GPIO_CFG_DRIVE_SEL_EXT_MASK))
557 #endif /* CY_IP_MXS40IOSS */
558
559 /** \endcond */
560
561
562 /***************************************
563 * Function Constants
564 ***************************************/
565
566 /**
567 * \addtogroup group_gpio_macros
568 * \{
569 */
570
571 /**
572 * \defgroup group_gpio_driveModes Pin drive mode
573 * \{
574 * Constants to be used for setting the drive mode of the pin. There are eight
575 * primary drive modes.
576 * Below diagrams are simplified output driver diagrams of the pin view for the
577 * CPU register and UDB/DSI based digital peripherals on each of the eight drive
578 * modes.
579 * \image html gpio_cpu_dm_block_diagram.png
580 *
581 * Below is a simplified output driver diagram that shows the pin view for
582 * fixed-function-based peripherals for each of the eight drive modes.
583 * \image html gpio_periio_dm_block_diagram.png
584 *
585 * - High-Impedance:
586 * This is the standard high-impedance (HI-Z) state recommended for analog and
587 * digital inputs. For digital signals, the input buffer is enabled; for analog
588 * signals, the input buffer is typically disabled to reduce crowbar current
589 * and leakage in low-power designs. To achieve the lowest device current, unused
590 * GPIOs must be configured to the high-impedance drive mode with input buffer
591 * disabled. Highimpedance drive mode with input buffer disabled is also the
592 * default pin reset state.
593 *
594 * - Resistive Pull-Up or Resistive Pull-Down:
595 * Resistive modes provide a series resistance in one of the data states and
596 * strong drive in the other. Pins can be used for either digital input or
597 * digital output in these modes. If resistive pull-up is required, a '1' must be
598 * written to that pin's Data Register bit. If resistive pull-down is required,
599 * a '0' must be written to that pin's Data Register. Interfacing mechanical
600 * switches is a common application of these drive modes. The resistive modes are
601 * also used to interface PSoC with open drain drive lines. Resistive pull-up is
602 * used when the input is open drain low and resistive pull-down is used when the
603 * input is open drain high.
604 *
605 * - Open Drain Drives High and Open Drain Drives Low:
606 * Open drain modes provide high impedance in one of the data states and strong
607 * drive in the other. Pins are useful as digital inputs or outputs in these
608 * modes. Therefore, these modes are widely used in bidirectional digital
609 * communication. Open drain drive high mode is used when the signal is
610 * externally pulled down and open drain drive low is used when the signal is
611 * externally pulled high. A common application for the open drain drives low
612 * mode is driving I2C bus signal lines.
613 *
614 * - Strong Drive:
615 * The strong drive mode is the standard digital output mode for pins; it
616 * provides a strong CMOS output drive in both high and low states. Strong drive
617 * mode pins should not be used as inputs under normal circumstances. This mode
618 * is often used for digital output signals or to drive external devices.
619 *
620 * - Resistive Pull-Up and Resistive Pull-Down:
621 * In the resistive pull-up and pull-down mode, the GPIO will have a series
622 * resistance in both logic 1 and logic 0 output states. The high data state is
623 * pulled up while the low data state is pulled down. This mode is useful when
624 * the pin is driven by other signals that may cause shorts.
625 */
626 #define CY_GPIO_DM_ANALOG (0x00UL) /**< Analog High-Z. Input buffer off */
627 #define CY_GPIO_DM_INVALID_IN_OFF (0x01UL) /**< Invalid mode. It should not be used */
628 #define CY_GPIO_DM_PULLUP_IN_OFF (0x02UL) /**< Resistive Pull-Up. Input buffer off */
629 #define CY_GPIO_DM_PULLDOWN_IN_OFF (0x03UL) /**< Resistive Pull-Down. Input buffer off */
630 #define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF (0x04UL) /**< Open Drain, Drives Low. Input buffer off */
631 #define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) /**< Open Drain, Drives High. Input buffer off */
632 #define CY_GPIO_DM_STRONG_IN_OFF (0x06UL) /**< Strong Drive. Input buffer off */
633 #define CY_GPIO_DM_PULLUP_DOWN_IN_OFF (0x07UL) /**< Resistive Pull-Up/Down. Input buffer off */
634 #define CY_GPIO_DM_HIGHZ (0x08UL) /**< Digital High-Z. Input buffer on */
635 #define CY_GPIO_DM_INVALID (0x09UL) /**< Invalid mode. It should not be used */
636 #define CY_GPIO_DM_PULLUP (0x0AUL) /**< Resistive Pull-Up. Input buffer on */
637 #define CY_GPIO_DM_PULLDOWN (0x0BUL) /**< Resistive Pull-Down. Input buffer on */
638 #define CY_GPIO_DM_OD_DRIVESLOW (0x0CUL) /**< Open Drain, Drives Low. Input buffer on */
639 #define CY_GPIO_DM_OD_DRIVESHIGH (0x0DUL) /**< Open Drain, Drives High. Input buffer on */
640 #define CY_GPIO_DM_STRONG (0x0EUL) /**< Strong Drive. Input buffer on */
641 #define CY_GPIO_DM_PULLUP_DOWN (0x0FUL) /**< Resistive Pull-Up/Down. Input buffer on */
642 #if defined (CY_IP_MXS22IOSS)
643 /**
644 * \note
645 * This drive mode is available for the CAT1D devices.
646 **/
647 #define CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ (0x80UL) /**< Strong Drive/Resistive Pull-Up/High-Z based on data_out_en and data_out signals. It is applicable for I3C */
648 #endif /* CY_IP_MXS22IOSS */
649 /** \} */
650
651 /**
652 * \defgroup group_gpio_vtrip Voltage trip mode
653 * \{
654 * Constants to be used for setting the voltage trip type on the pin.
655 */
656 #define CY_GPIO_VTRIP_CMOS (0x00UL) /**< Input buffer compatible with CMOS and I2C interfaces */
657 #define CY_GPIO_VTRIP_TTL (0x01UL) /**< Input buffer compatible with TTL and MediaLB interfaces */
658 /** \} */
659
660 #if (defined(CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION == 3U)) || defined (CY_DOXYGEN)
661 /**
662 * \defgroup group_gpio_vtrip_auto Voltage trip automotive compatible mode
663 * \{
664 * Constants to be used for setting the input buffer automotive compatible mode (trip points and hysteresis) for GPIO upper bit.
665 *
666 * \note
667 * These macros are available for CAT1B devices.
668 *
669 */
670 #define CY_GPIO_VTRIP_DIS_AUTO (0x00UL) /**< Input buffer is not compatible with automotive and it is compatible with CMOS/TTL interfaces */
671 #define CY_GPIO_VTRIP_SEL_AUTO (0x01UL) /**< Input buffer is compatible with automotive */
672 /** \} */
673 #endif/* CY_IP_MXS40IOSS_VERSION */
674
675 /**
676 * \defgroup group_gpio_slewRate Slew Rate Mode
677 * \{
678 * Constants to be used for setting the slew rate of the pin.
679 */
680 #define CY_GPIO_SLEW_FAST (0x00UL) /**< Fast slew rate */
681 #define CY_GPIO_SLEW_SLOW (0x01UL) /**< Slow slew rate */
682 /** \} */
683
684 /**
685 * \defgroup group_gpio_driveStrength Pin drive strength
686 * \{
687 * Constants to be used for setting the drive strength of the pin.
688 */
689 #define CY_GPIO_DRIVE_FULL (0x00UL) /**< Full drive strength: Max drive current */
690 #define CY_GPIO_DRIVE_1_2 (0x01UL) /**< 1/2 drive strength: 1/2 drive current */
691 #define CY_GPIO_DRIVE_1_4 (0x02UL) /**< 1/4 drive strength: 1/4 drive current */
692 #define CY_GPIO_DRIVE_1_8 (0x03UL) /**< 1/8 drive strength: 1/8 drive current */
693 /** \} */
694
695 /**
696 * \defgroup group_gpio_interruptTrigger Interrupt trigger type
697 * \{
698 * Constants to be used for setting the interrupt trigger type on the pin.
699 */
700 #define CY_GPIO_INTR_DISABLE (0x00UL) /**< Disable the pin interrupt generation */
701 #define CY_GPIO_INTR_RISING (0x01UL) /**< Rising-Edge interrupt */
702 #define CY_GPIO_INTR_FALLING (0x02UL) /**< Falling-Edge interrupt */
703 #define CY_GPIO_INTR_BOTH (0x03UL) /**< Both-Edge interrupt */
704 /** \} */
705
706 /**
707 * \defgroup group_gpio_sioVreg SIO output buffer mode
708 * \{
709 * Constants to be used for setting the SIO output buffer mode on the pin.
710 */
711 #define CY_SIO_VREG_UNREGULATED (0x00UL) /**< Unregulated output buffer */
712 #define CY_SIO_VREG_REGULATED (0x01UL) /**< Regulated output buffer */
713 /** \} */
714
715 /**
716 * \defgroup group_gpio_sioIbuf SIO input buffer mode
717 * \{
718 * Constants to be used for setting the SIO input buffer mode on the pin.
719 */
720 #define CY_SIO_IBUF_SINGLEENDED (0x00UL) /**< Single ended input buffer */
721 #define CY_SIO_IBUF_DIFFERENTIAL (0x01UL) /**< Differential input buffer */
722 /** \} */
723
724 /**
725 * \defgroup group_gpio_sioVtrip SIO input buffer trip-point
726 * \{
727 * Constants to be used for setting the SIO input buffer trip-point of the pin.
728 */
729 #define CY_SIO_VTRIP_CMOS (0x00UL) /**< CMOS input buffer (single-ended) */
730 #define CY_SIO_VTRIP_TTL (0x01UL) /**< TTL input buffer (single-ended) */
731 #define CY_SIO_VTRIP_0_5VDDIO_0_5VOH (0x00UL) /**< 0.5xVddio or 0.5xVoh (differential) */
732 #define CY_SIO_VTRIP_0_4VDDIO_1_0VREF (0x01UL) /**< 0.4xVddio or 0.4xVoh (differential) */
733 /** \} */
734
735 /**
736 * \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point
737 * \{
738 * Constants to be used for setting the reference voltage of SIO input buffer trip-point.
739 */
740 #define CY_SIO_VREF_PINREF (0x00UL) /**< Vref from analog pin */
741 #define CY_SIO_VREF_1_2V (0x01UL) /**< Vref from internal 1.2V reference */
742 #define CY_SIO_VREF_AMUX_A (0x02UL) /**< Vref from AMUXBUS_A */
743 #define CY_SIO_VREF_AMUX_B (0x03UL) /**< Vref from AMUXBUS_B */
744 /** \} */
745
746 /**
747 * \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair
748 * \{
749 * Constants to be used for setting the Voh and input buffer trip-point of an SIO pair
750 */
751 #define CY_SIO_VOH_1_00 (0x00UL) /**< Voh = 1 x Reference */
752 #define CY_SIO_VOH_1_25 (0x01UL) /**< Voh = 1.25 x Reference */
753 #define CY_SIO_VOH_1_49 (0x02UL) /**< Voh = 1.49 x Reference */
754 #define CY_SIO_VOH_1_67 (0x03UL) /**< Voh = 1.67 x Reference */
755 #define CY_SIO_VOH_2_08 (0x04UL) /**< Voh = 2.08 x Reference */
756 #define CY_SIO_VOH_2_50 (0x05UL) /**< Voh = 2.50 x Reference */
757 #define CY_SIO_VOH_2_78 (0x06UL) /**< Voh = 2.78 x Reference */
758 #define CY_SIO_VOH_4_16 (0x07UL) /**< Voh = 4.16 x Reference */
759 /** \} */
760
761 #if defined (CY_IP_MXS22IOSS)
762 /**
763 * \defgroup group_gpio_PullUpMode Pull-up mode
764 * \{
765 * Constants to be used for setting the Pull-up mode on the pin.
766 *
767 * \note
768 * This parameter is available for the CAT1D devices.
769 *
770 */
771 #define CY_GPIO_PULLUP_RES_DISABLE (0x00UL) /**< Disable additional Pull-ups */
772 #define CY_GPIO_PULLUP_RES_570 (0x07UL) /**< Pull-up 570 ohms */
773 #define CY_GPIO_PULLUP_RES_720 (0x06UL) /**< Pull-up 720 ohms */
774 #define CY_GPIO_PULLUP_RES_840 (0x05UL) /**< Pull-up 840 ohms */
775 #define CY_GPIO_PULLUP_RES_1100 (0x03UL) /**< Pull-up 1100 ohms */
776 #define CY_GPIO_PULLUP_RES_1200 (0x04UL) /**< Pull-up 1200 ohms */
777 #define CY_GPIO_PULLUP_RES_1800 (0x02UL) /**< Pull-up 1800 ohms */
778 #define CY_GPIO_PULLUP_RES_2800 (0x01UL) /**< Pull-up 2800 ohms */
779 /** \} */
780 #endif /* CY_IP_MXS22IOSS */
781 /** \} group_gpio_macros */
782
783 /***************************************
784 * Function Prototypes
785 ***************************************/
786
787 /**
788 * \addtogroup group_gpio_functions
789 * \{
790 */
791
792 /**
793 * \addtogroup group_gpio_functions_init
794 * \{
795 */
796
797 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config);
798 cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config);
799 void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
800 void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base);
801 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value);
802 en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum);
803 __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum);
804 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
805 void Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
806 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
807 __STATIC_INLINE uint32_t Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum);
808 #endif /* CY_IP_MXS40SIOSS, IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
809
810 /** \} group_gpio_functions_init */
811
812 /**
813 * \addtogroup group_gpio_functions_gpio
814 * \{
815 */
816
817 void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus);
818 cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus);
819
820 uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum);
821 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
822 uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum);
823 void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum);
824 void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum);
825 void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum);
826 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
827 uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum);
828 void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
829 uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum);
830 #if (defined(CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION == 3U)) || defined(CY_IP_MXS40SIOSS_VERSION) || defined (CY_DOXYGEN)
831 void Cy_GPIO_SetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
832 uint32_t Cy_GPIO_GetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum);
833 #endif /* CY_IP_MXS40IOSS_VERSION */
834 void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
835 uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum);
836 void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
837 uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum);
838
839 #if defined (CY_IP_MXS22IOSS)
840 void Cy_GPIO_SetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
841 uint32_t Cy_GPIO_GetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum);
842 #endif /* CY_IP_MXS22IOSS */
843
844 /** \} group_gpio_functions_gpio */
845
846 /**
847 * \addtogroup group_gpio_functions_sio
848 * \{
849 */
850
851 void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
852 uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum);
853 void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
854 uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum);
855 void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
856 uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum);
857 void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
858 uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum);
859 void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
860 uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum);
861
862 /** \} group_gpio_functions_sio */
863
864 /**
865 * \addtogroup group_gpio_functions_interrupt
866 * \{
867 */
868
869 uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum);
870 void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
871 void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
872 uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum);
873 uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum);
874 void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
875 void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
876 uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum);
877 void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value);
878 uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base);
879
880 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void);
881 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void);
882 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void);
883 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void);
884 #if (defined (CY_IP_MXS40SIOSS) && (CPUSS_CM33_0_SECEXT_PRESENT != 0)) || defined (CY_IP_MXS22IOSS)
885 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause0(void);
886 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause1(void);
887 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause2(void);
888 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause3(void);
889 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
890
891 /** \} group_gpio_functions_interrupt */
892
893 /** \cond INTERNAL */
894 #if defined (CY_IP_MXS40SIOSS) || (defined (CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION > 2)) || defined (CY_IP_MXS22IOSS)
895 #define HSIOM_PRT_V1_Type HSIOM_PRT_Type
896 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
897 /** \endcond */
898
899 /**
900 * \addtogroup group_gpio_functions_init
901 * \{
902 */
903
904 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
905 /*******************************************************************************
906 * Function Name: Cy_GPIO_SetHSIOM_SecPin
907 ****************************************************************************//**
908 *
909 * Configures the pin as secure or non-secure.
910 *
911 *
912 * \param base
913 * Pointer to the pin's port register base address
914 *
915 * \param pinNum
916 * Position of the pin bit-field within the port register
917 *
918 * \param value
919 * Secure HSIOM non-secure mask
920 *
921 * \note
922 * This function modifies a port register in a read-modify-write operation. It is
923 * not thread safe as the resource is shared among multiple pins on a port.
924 * This function should be called from the right protection context to access
925 * HSIOM secure port (HSIOM_SECURE_PRT_Type).
926 *
927 * \note
928 * This API is available for the CAT1B and CAT1D devices.
929 *
930 * \funcusage
931 *
932 *******************************************************************************/
Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)933 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
934 {
935 uint32_t tempReg;
936 uint32_t portNum;
937 HSIOM_SECURE_PRT_Type* portAddrSecHSIOM;
938
939 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
940 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
941
942 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
943 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
944
945 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
946 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
947 {
948 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_SECURE_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_SECURE_PRT0)));
949 }
950 #endif
951
952 tempReg= HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) & ~(CY_GPIO_HSIOM_SEC_MASK << pinNum);
953 HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) = tempReg | ((value & CY_GPIO_HSIOM_SEC_MASK) << pinNum);
954 }
955
956 /*******************************************************************************
957 * Function Name: Cy_GPIO_GetHSIOM_SecPin
958 ****************************************************************************//**
959 *
960 * Returns the current status of secure Pin.
961 *
962 * \param base
963 * Pointer to the pin's port register base address
964 *
965 * \param pinNum
966 * Position of the pin bit-field within the port register
967 *
968 * \return
969 * HSIOM input selection
970 *
971 * \note
972 * This API is available for the CAT1B and CAT1D devices.
973 *
974 * \funcusage
975 *
976 *******************************************************************************/
Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type * base,uint32_t pinNum)977 __STATIC_INLINE uint32_t Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum)
978 {
979 uint32_t portNum;
980 HSIOM_SECURE_PRT_Type* portAddrSecHSIOM;
981
982 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
983
984 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
985 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
986
987 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
988 if ((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) || (base == (GPIO_PRT_Type*)((void*)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0)))
989 {
990 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)((void*)((base == (GPIO_PRT_Type*)((void*)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0)) ? ((void*)SMIF0_CORE0_SMIF_HSIOM_SMIF_SECURE_PRT0) : ((void*)SMIF0_CORE1_SMIF_HSIOM_SMIF_SECURE_PRT0)));
991 }
992 #endif
993
994 return (uint32_t)((HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) >> pinNum) & CY_GPIO_HSIOM_SEC_MASK);
995 }
996 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
997
998 /*******************************************************************************
999 * Function Name: Cy_GPIO_PortToAddr
1000 ****************************************************************************//**
1001 *
1002 * Retrieves the port address based on the given port number.
1003 *
1004 * This is a helper function to calculate the port base address when given a port
1005 * number. It is to be used when pin access needs to be calculated at runtime.
1006 *
1007 * \param portNum
1008 * Port number
1009 *
1010 * \return
1011 * Base address of the port register structure
1012 *
1013 * \funcusage
1014 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_PortToAddr
1015 *
1016 *******************************************************************************/
Cy_GPIO_PortToAddr(uint32_t portNum)1017 __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
1018 {
1019 GPIO_PRT_Type* portBase;
1020
1021 if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR)
1022 {
1023 portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum));
1024 }
1025 else
1026 {
1027 /* Error: Return default base address */
1028 portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE);
1029 }
1030
1031 return (portBase);
1032 }
1033
1034 /** \} group_gpio_functions_init */
1035
1036
1037
1038 /**
1039 * \addtogroup group_gpio_functions_interrupt
1040 * \{
1041 */
1042
1043 /*******************************************************************************
1044 * Function Name: Cy_GPIO_GetInterruptCause0
1045 ****************************************************************************//**
1046 *
1047 * Returns the interrupt status for ports 0 to 31.
1048 *
1049 * \return
1050 * 0 = Interrupt not detected on port
1051 * 1 = Interrupt detected on port
1052 *
1053 * \funcusage
1054 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptCause0
1055 *
1056 *******************************************************************************/
Cy_GPIO_GetInterruptCause0(void)1057 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void)
1058 {
1059 return (GPIO_INTR_CAUSE0);
1060 }
1061
1062
1063 /*******************************************************************************
1064 * Function Name: Cy_GPIO_GetInterruptCause1
1065 ****************************************************************************//**
1066 *
1067 * Returns the interrupt status for ports 32 to 63.
1068 *
1069 * \return
1070 * 0 = Interrupt not detected on port
1071 * 1 = Interrupt detected on port
1072 *
1073 * \funcusage
1074 * Refer to the Cy_GPIO_GetInterruptCause0() example.
1075 *
1076 *******************************************************************************/
Cy_GPIO_GetInterruptCause1(void)1077 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void)
1078 {
1079 return (GPIO_INTR_CAUSE1);
1080 }
1081
1082
1083 /*******************************************************************************
1084 * Function Name: Cy_GPIO_GetInterruptCause2
1085 ****************************************************************************//**
1086 *
1087 * Returns the interrupt status for ports 64 to 95.
1088 *
1089 * \return
1090 * 0 = Interrupt not detected on port
1091 * 1 = Interrupt detected on port
1092 * \funcusage
1093 * Refer to the Cy_GPIO_GetInterruptCause0() example.
1094 *
1095 *******************************************************************************/
Cy_GPIO_GetInterruptCause2(void)1096 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void)
1097 {
1098 return (GPIO_INTR_CAUSE2);
1099 }
1100
1101
1102 /*******************************************************************************
1103 * Function Name: Cy_GPIO_GetInterruptCause3
1104 ****************************************************************************//**
1105 *
1106 * Returns the interrupt status for ports 96 to 127.
1107 *
1108 * \return
1109 * 0 = Interrupt not detected on port
1110 * 1 = Interrupt detected on port
1111 *
1112 * \funcusage
1113 * Refer to the Cy_GPIO_GetInterruptCause0() example.
1114 *
1115 *******************************************************************************/
Cy_GPIO_GetInterruptCause3(void)1116 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void)
1117 {
1118 return (GPIO_INTR_CAUSE3);
1119 }
1120
1121 #if (defined (CY_IP_MXS40SIOSS) && (CPUSS_CM33_0_SECEXT_PRESENT != 0)) || defined (CY_IP_MXS22IOSS)
1122 /*******************************************************************************
1123 * Function Name: Cy_GPIO_GetSecureInterruptCause0
1124 ****************************************************************************//**
1125 *
1126 * Returns the interrupt status for ports 0 to 31.
1127 *
1128 * \return
1129 * 0 = Interrupt not detected on port
1130 * 1 = Interrupt detected on port
1131 *
1132 * \note
1133 * This API is available for the CAT1B and CAT1D devices.
1134 *
1135 * \funcusage
1136 *
1137 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause0(void)1138 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause0(void)
1139 {
1140 return (GPIO_SEC_INTR_CAUSE0);
1141 }
1142
1143
1144 /*******************************************************************************
1145 * Function Name: Cy_GPIO_GetSecureInterruptCause1
1146 ****************************************************************************//**
1147 *
1148 * Returns the interrupt status for ports 32 to 63.
1149 *
1150 * \return
1151 * 0 = Interrupt not detected on port
1152 * 1 = Interrupt detected on port
1153 *
1154 * \note
1155 * This API is available for the CAT1B and CAT1D devices.
1156 *
1157 * \funcusage
1158 *
1159 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause1(void)1160 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause1(void)
1161 {
1162 return (GPIO_SEC_INTR_CAUSE1);
1163 }
1164
1165
1166 /*******************************************************************************
1167 * Function Name: Cy_GPIO_GetSecureInterruptCause2
1168 ****************************************************************************//**
1169 *
1170 * Returns the interrupt status for ports 64 to 95.
1171 *
1172 * \return
1173 * 0 = Interrupt not detected on port
1174 * 1 = Interrupt detected on port
1175 *
1176 * \note
1177 * This API is available for the CAT1B and CAT1D devices.
1178 *
1179 * \funcusage
1180 *
1181 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause2(void)1182 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause2(void)
1183 {
1184 return (GPIO_SEC_INTR_CAUSE2);
1185 }
1186
1187
1188 /*******************************************************************************
1189 * Function Name: Cy_GPIO_GetSecureInterruptCause3
1190 ****************************************************************************//**
1191 *
1192 * Returns the interrupt status for ports 96 to 127.
1193 *
1194 * \return
1195 * 0 = Interrupt not detected on port
1196 * 1 = Interrupt detected on port
1197 *
1198 * \note
1199 * This API is available for the CAT1B and CAT1D devices.
1200 *
1201 * \funcusage
1202 *
1203 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause3(void)1204 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause3(void)
1205 {
1206 return (GPIO_SEC_INTR_CAUSE3);
1207 }
1208 #endif /* CY_IP_MXS40SIOSS, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
1209
1210 /** \} group_gpio_functions_interrupt */
1211
1212 /** \} group_gpio_functions */
1213
1214 #if defined(__cplusplus)
1215 }
1216 #endif
1217
1218 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS40IOSS, CY_IP_MXS22IOSS */
1219
1220 #endif /* CY_GPIO_H */
1221
1222 /** \} group_gpio */
1223
1224 /* [] END OF FILE */
1225
