1 /***************************************************************************//**
2 * \file cy_gpio.h
3 * \version 1.110
4 *
5 * Provides an API declaration of the GPIO driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_gpio
28 * \{
29 * The GPIO driver provides an API to configure and access device Input/Output pins.
30 *
31 * The functions and other declarations used in this driver are in cy_gpio.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and
36 * their variants.
37 *
38 * Initialization can be performed either at the port level or by configuring the
39 * individual pins. For efficient use of code space, port
40 * configuration should be used in the field. Refer to the product device header files
41 * for the list of supported ports and pins.
42 *
43 * A port is represented by GPIO_PRT_Type and a pin is represented by a number
44 * 0 to 7.
45 *
46 * For PSoC 64 devices the the un-intended protected pins (due to constrain on PPU configuration)
47 * are modified using PRA driver. But the GPIO diver does not modify the intended protected pins .
48 *
49 * - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
50 * (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled
51 * cy_stc_gpio_pin_config_t structure).
52 * - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
53 * cy_stc_gpio_prt_config_t structure. The values in the structure are
54 * bitfields representing the desired value for each pin in the port.
55 * - Pin configuration and management is based on the port address and pin number.
56 * \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port
57 * address from the port number at run-time.
58 * - Each I/O is individually configurable to one of eight drive modes represented
59 * by drivemode of cy_stc_gpio_pin_config_t structure.
60 *
61 * Once the pin/port initialization is complete, each pin can be accessed by
62 * specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
63 * functions.
64 *
65 * \section group_gpio_configuration Configuration Considerations
66 *
67 * 1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection.
68 * This allows the pin to connect to signal sources/sinks throughout the device,
69 * as defined by the pin HSIOM selection options (en_hsiom_sel_t).
70 * 2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW
71 * control digital pin only) at Power-On-Reset(POR).
72 * 3. Some API functions perform read-modify-write operations on shared port
73 * registers. These functions are not thread safe and care must be taken when
74 * called by the application.
75 * 4. Digital input buffer provides a high-impedance buffer for the external
76 * digital input. The input buffer is connected to the HSIOM for routing to
77 * the CPU port registers and selected peripheral. Enabling the input
78 * buffer provides possibility to read the pin state via the CPU.
79 * If pin is connected to an analog signal, the input buffer should be
80 * disabled to avoid crowbar currents. For more information refer to device
81 * TRM and the device datasheet.
82 *
83 * Multiple pins on a port can be updated using direct port register writes with an
84 * appropriate port mask. An example is shown below, highlighting the different ways of
85 * configuring Port 1 pins using:
86 *
87 * - Initialize a Pin using cy_stc_gpio_pin_config_t structure
88 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Pin_Init
89 *
90 * - Initialize entire port using cy_stc_gpio_prt_config_t structure
91 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_Port_Init
92 *
93 * - Port output data register
94 * - Port output data set register
95 * - Port output data clear register
96 *
97 * \snippet gpio/snippet/main.c Cy_GPIO_Snippet
98 *
99 * \section group_gpio_more_information More Information
100 *
101 * Refer to the technical reference manual (TRM) and the device datasheet.
102 *
103 * \section group_gpio_changelog Changelog
104 * <table class="doxtable">
105 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
106 * <tr>
107 * <td>1.110</td>
108 * <td>Added support for SMIF GPIO PORT1 and PORT2 and reverted to GPIO inline functions.</td>
109 * <td>Code enhancement and support for new GPIO port for SMIF.</td>
110 * </tr>
111 * <tr>
112 * <td>1.100</td>
113 * <td>Added support for TRAVEO™ II Body Entry devices.<br>
114 * Updated pre-processor checks to check for GPIO auto-leveling capability rather than rely on IOSS version.</td>
115 * <td>Code enhancement and support for new devices.</td>
116 * </tr>
117 * <tr>
118 * <td>1.90</td>
119 * <td>Updated APIs \ref Cy_GPIO_Port_Init, \ref Cy_GPIO_Port_Deinit, \ref Cy_GPIO_GetDrivemode.</td>
120 * <td>Fixed coverity defects.</td>
121 * </tr>
122 * <tr>
123 * <td rowspan="2">1.80</td>
124 * <td>Updated \ref Cy_GPIO_SetDrivemode and \ref Cy_GPIO_GetDrivemode APIs.</td>
125 * <td>Updated drive mode configuration for CAT1D devices.</td>
126 * </tr>
127 * <tr>
128 * <td>Fixed MISRA 2012 violations.</td>
129 * <td>MISRA 2012 compliance.</td>
130 * </tr>
131 * <tr>
132 * <td>1.70</td>
133 * <td>Updated driver to support the CAT1D family of devices.</td>
134 * <td>Added new family of devices.</td>
135 * </tr>
136 * <tr>
137 * <td rowspan="2">1.60</td>
138 * <td>Added \ref Cy_GPIO_SetVtripAuto and \ref Cy_GPIO_GetVtripAuto APIs for
139 * configuring GPIO input buffer voltage for automotive compatible or not,
140 * for CAT1C devices.</td>
141 * <td>New APIs support for CAT1C devices.</td>
142 * </tr>
143 * <tr>
144 * <td>Fixed unused variables error.</td>
145 * <td>Minor error fixes.</td>
146 * </tr>
147 * <tr>
148 * <td>1.50.1</td>
149 * <td>Updated doxygen for External clock source to HF0.</td>
150 * <td>Documentation enhancement.</td>
151 * </tr>
152 * <tr>
153 * <td>1.50</td>
154 * <td>Modified \ref Cy_GPIO_Pin_Init, \ref Cy_GPIO_Pin_FastInit, and
155 * \ref Cy_GPIO_SetDrivemode APIs to catch wrong drive modes.</td>
156 * <td>Defect fix.</td>
157 * </tr>
158 * <tr>
159 * <td rowspan="2">1.40</td>
160 * <td>Changes in Support of the new family of devices</td>
161 * <td>Added new family of devices</td>
162 * </tr>
163 * <tr>
164 * <td>Changes in support of Secure pins used for External clocks on Secure devices</td>
165 * <td>Added support for accessing External clocks protected pins</td>
166 * </tr>
167 * <tr>
168 * <td>1.30</td>
169 * <td>Fixed/documented MISRA 2012 violations.</td>
170 * <td>MISRA 2012 compliance.</td>
171 * </tr>
172 * <tr>
173 * <td>1.20.1</td>
174 * <td>Minor documentation updates.</td>
175 * <td>Documentation enhancement.</td>
176 * </tr>
177 * <tr>
178 * <td rowspan="3">1.20</td>
179 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td>
180 * <td>Driver library directory-structure simplification.</td>
181 * </tr>
182 * <tr>
183 * <td>Added the functions for configuring the AMux bus splitter switch cells:
184 * - \ref Cy_GPIO_SetAmuxSplit
185 * - \ref Cy_GPIO_GetAmuxSplit
186 * </td>
187 * <td>Added a new functionality related to AMux bus.</td>
188 * </tr>
189 * <tr>
190 * <td>Added register access layer. Use register access macros instead
191 * of direct register access using dereferenced pointers.</td>
192 * <td>Makes register access device-independent, so that the PDL does
193 * not need to be recompiled for each supported part number.</td>
194 * </tr>
195 * <tr>
196 * <td>1.10.1</td>
197 * <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
198 * \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked.
199 *
200 * Minor documentation edits.
201 * </td>
202 * <td>Documentation update and clarification</td>
203 * </tr>
204 * <tr>
205 * <td>1.10</td>
206 * <td>Added input parameter validation to the API functions</td>
207 * <td></td>
208 * </tr>
209 * <tr>
210 * <td>1.0</td>
211 * <td>Initial version</td>
212 * <td></td>
213 * </tr>
214 * </table>
215 *
216 * \defgroup group_gpio_macros Macros
217 * \defgroup group_gpio_functions Functions
218 * \{
219 * \defgroup group_gpio_functions_init Initialization Functions
220 * \defgroup group_gpio_functions_gpio GPIO Functions
221 * \defgroup group_gpio_functions_sio SIO Functions
222 * \defgroup group_gpio_functions_interrupt Port Interrupt Functions
223 * \}
224 * \defgroup group_gpio_data_structures Data Structures
225 * \defgroup group_gpio_enums Enumerated Types
226 */
227
228 #if !defined(CY_GPIO_H)
229 #define CY_GPIO_H
230
231 #include "cy_device.h"
232
233 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS40IOSS) || defined (CY_IP_MXS22IOSS)
234
235 #include <stddef.h>
236 #include "cy_syslib.h"
237
238 #if defined(__cplusplus)
239 extern "C" {
240 #endif
241
242 /** \addtogroup group_gpio_macros
243 * \{
244 */
245
246 /** Driver major version */
247 #define CY_GPIO_DRV_VERSION_MAJOR 1
248
249 /** Driver minor version */
250 #define CY_GPIO_DRV_VERSION_MINOR 110
251
252 /** GPIO driver ID */
253 #define CY_GPIO_ID CY_PDL_DRV_ID(0x16U)
254
255 /** \} group_gpio_macros */
256
257
258 /***************************************
259 * Enumerations
260 ***************************************/
261 /**
262 * \addtogroup group_gpio_enums
263 * \{
264 */
265
266 /** GPIO Driver error codes */
267 typedef enum
268 {
269 CY_GPIO_SUCCESS = 0x00U, /**< Returned successful */
270 CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter was passed */
271 } cy_en_gpio_status_t;
272
273 /** AMux switch open/close config */
274 typedef enum
275 {
276 CY_GPIO_AMUX_OPENALL, /**< Open ground switch. Open right switch. Open left switch */
277 CY_GPIO_AMUX_L, /**< Open ground switch. Open right switch. Close left switch */
278 CY_GPIO_AMUX_R, /**< Open ground switch. Close right switch. Open left switch */
279 CY_GPIO_AMUX_LR, /**< Open ground switch. Close right switch. Close left switch */
280 CY_GPIO_AMUX_G, /**< Close ground switch. Open right switch. Open left switch */
281 CY_GPIO_AMUX_GL, /**< Close ground switch. Open right switch. Close left switch */
282 CY_GPIO_AMUX_GR, /**< Close ground switch. Close right switch. Open left switch */
283 CY_GPIO_AMUX_GLR, /**< Close ground switch. Close right switch. Close left switch */
284 }cy_en_gpio_amuxconnect_t;
285
286 /**
287 * AMux Bus selection
288 */
289 typedef enum
290 {
291 CY_GPIO_AMUXBUSA, /**< AMuxBus A */
292 CY_GPIO_AMUXBUSB /**< AMuxBus B */
293 }cy_en_gpio_amuxselect_t;
294
295 /** \} group_gpio_enums */
296
297
298 /***************************************
299 * Configuration Structures
300 ***************************************/
301
302 /**
303 * \addtogroup group_gpio_data_structures
304 * \{
305 */
306
307 /** This structure is used to initialize a port of GPIO pins */
308 typedef struct
309 {
310 uint32_t out; /**< Initial output data for the IO pins in the port */
311 uint32_t intrMask; /**< Interrupt enable mask for the port interrupt */
312 uint32_t intrCfg; /**< Port pin interrupt edge detection configuration */
313 uint32_t cfg; /**< Port pin drive modes and input buffer enable configuration */
314 uint32_t cfgIn; /**< Port pin input buffer configuration */
315 uint32_t cfgOut; /**< Port pin output buffer configuration */
316 uint32_t cfgSIO; /**< Port SIO pins configuration */
317 uint32_t sel0Active; /**< HSIOM selection for port pins 0,1,2,3 */
318 uint32_t sel1Active; /**< HSIOM selection for port pins 4,5,6,7 */
319 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
320 /**
321 * \note
322 * This parameter is available for the CAT1B and CAT1D devices.
323 **/
324 uint32_t cfgSlew; /**< Port slew rate configuration */
325 /**
326 * \note
327 * This parameter is available for the CAT1B and CAT1D devices.
328 **/
329 uint32_t cfgDriveSel0; /**< Drive strength configuration for pins 0,1,2,3 */
330 /**
331 * \note
332 * This parameter is available for the CAT1B and CAT1D devices.
333 **/
334 uint32_t cfgDriveSel1; /**< Drive strength configuration for pins 4,5,6,7 */
335 /**
336 * \note
337 * This parameter is available for the CAT1B and CAT1D devices.
338 **/
339 uint32_t nonSecMask; /**< HSIOM non secure mask for port pins 0-7 */
340 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
341 #if defined (CY_IP_MXS22IOSS)
342 /**
343 * \note
344 * This parameter is available for the CAT1D devices.
345 **/
346 uint32_t cfgRes; /**< Pull-up resistor configuration for port pins */
347 /**
348 * \note
349 * This parameter is available for the CAT1D devices.
350 **/
351 uint32_t cfgOut3; /**< Port pin extra drive mode \ref CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ */
352 #endif /* CY_IP_MXS22IOSS */
353 } cy_stc_gpio_prt_config_t;
354
355 /** This structure is used to initialize a single GPIO pin */
356 typedef struct
357 {
358 uint32_t outVal; /**< Pin output state */
359 uint32_t driveMode; /**< Drive mode */
360 en_hsiom_sel_t hsiom; /**< HSIOM selection */
361 uint32_t intEdge; /**< Interrupt Edge type */
362 uint32_t intMask; /**< Interrupt enable mask */
363 uint32_t vtrip; /**< Input buffer voltage trip type */
364 uint32_t slewRate; /**< Output buffer slew rate */
365 uint32_t driveSel; /**< Drive strength */
366 uint32_t vregEn; /**< SIO pair output buffer mode */
367 uint32_t ibufMode; /**< SIO pair input buffer mode */
368 uint32_t vtripSel; /**< SIO pair input buffer trip point */
369 uint32_t vrefSel; /**< SIO pair reference voltage for input buffer trip point */
370 uint32_t vohSel; /**< SIO pair regulated voltage output level */
371 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
372 /**
373 * \note
374 * This parameter is available for the CAT1B and CAT1D devices.
375 **/
376 uint32_t nonSec; /**< Secure attribute for each Pin of a port */
377 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
378 #if defined (CY_IP_MXS22IOSS)
379 /**
380 * \note
381 * This parameter is available for the CAT1D devices.
382 **/
383 uint32_t pullUpRes; /**< Pull-up resistor configuration for each pin of a port */
384 #endif /* CY_IP_MXS22IOSS */
385 } cy_stc_gpio_pin_config_t;
386
387 /** \} group_gpio_data_structures */
388
389 /***************************************
390 * Constants
391 ***************************************/
392
393 /** \cond INTERNAL */
394
395 /* General Constants */
396 #define CY_GPIO_PRT_HALF (4UL) /**< Half-way point of a GPIO port */
397 #define CY_GPIO_PRT_DEINIT (0UL) /**< De-init value for port registers */
398 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
399 #define CY_HSIOM_NONSEC_DEINIT (0xFFUL) /**< De-init value for port non sec register */
400 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
401
402 /* GPIO Masks */
403 #define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */
404 #define CY_GPIO_OUT_MASK (0x01UL) /**< Single pin mask for OUT register */
405 #define CY_GPIO_IN_MASK (0x01UL) /**< Single pin mask for IN register */
406 #define CY_GPIO_CFG_DM_MASK (0x0FUL) /**< Single pin mask for drive mode in CFG register */
407 #define CY_GPIO_CFG_DM_WIDTH_MASK (0xFUL) /**< Single pin mask for drive mode width in CFG/CFG_OUT3 register */
408 #define CY_GPIO_CFG_DM_NO_INBUF_MASK (0x07UL) /**< Single pin mask for drive mode ( without input buffer ) in CFG register */
409 #define CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN register */
410 #if (defined (CY_IP_MXS40IOSS) && ( \
411 (CY_IP_MXS40IOSS_VERSION == 3U) || \
412 (CY_IP_MXS40IOSS_VERSION == 2U && (defined (SRSS_HT_VARIANT) && (SRSS_HT_VARIANT == 1U)))) || \
413 defined (CY_IP_MXS40SIOSS_VERSION))
414
415 #define GPIO_AUTOLVL_AVAIL (1U) /**< Specifies that the AUTOLVL registers are available on this device>**/
416 #define CY_GPIO_CFG_IN_VTRIP_SEL_1_MASK (0x01UL) /**< Single pin mask for VTRIP selection in CFG IN AUTOLVL register */
417 #endif /* CY_IP_MXS40IOSS_VERSION */
418 #define CY_GPIO_CFG_IN_VTRIP_SEL_MASK CY_GPIO_CFG_IN_VTRIP_SEL_0_MASK /**< Single pin mask for VTRIP selection in CFG IN register */
419 #define CY_GPIO_INTR_STATUS_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
420 #define CY_GPIO_INTR_EN_MASK (0x01UL) /**< Single pin mask for interrupt status in INTR register */
421 #define CY_GPIO_INTR_MASKED_MASK (0x01UL) /**< Single pin mask for masked interrupt status in INTR_MASKED register */
422 #define CY_GPIO_INTR_SET_MASK (0x01UL) /**< Single pin mask for setting the interrupt in INTR_MASK register */
423 #define CY_GPIO_INTR_EDGE_MASK (0x03UL) /**< Single pin mask for interrupt edge type in INTR_EDGE register */
424 #define CY_GPIO_INTR_FLT_EDGE_MASK (0x07UL) /**< Single pin mask for setting filtered interrupt */
425 #if defined (CY_IP_MXS40IOSS)
426 #define CY_GPIO_CFG_OUT_SLOW_MASK (0x01UL) /**< Single pin mask for slew rate in CFG OUT register */
427 #define CY_GPIO_CFG_OUT_DRIVE_SEL_MASK (0x03UL) /**< Single pin mask for drive strength in CFG OUT register */
428 #else
429 #define CY_GPIO_HSIOM_SEC_MASK (0x01UL) /**< Single pin mask for NONSECURE_MASK register */
430 #define CY_GPIO_CFG_SLEW_EXT_MASK (0x07UL) /**< Single pin mask for slew rate in CFG SLEW EXT register */
431 #define CY_GPIO_CFG_DRIVE_SEL_EXT_MASK (0x1FUL) /**< Single pin mask for drive strength in CFG DRIVE EXT register */
432 #endif /* CY_IP_MXS40IOSS */
433 #if defined (CY_IP_MXS22IOSS)
434 #define CY_GPIO_CFG_RES_PULLUP_MODE_MASK (0x0FUL) /**< Single pin mask for Pull-up mode in CFG_RES register */
435 #endif /* CY_IP_MXS22IOSS */
436
437 /* SIO Masks */
438 #define CY_GPIO_VREG_EN_MASK (0x01UL) /**< Single SIO pin mask for voltage regulation enable */
439 #define CY_GPIO_IBUF_MASK (0x01UL) /**< Single SIO pin mask for input buffer */
440 #define CY_GPIO_IBUF_SHIFT (0x01UL) /**< Single SIO pin shift for input buffer */
441 #define CY_GPIO_VTRIP_SEL_MASK (0x01UL) /**< Single SIO pin mask for the input buffer trip point */
442 #define CY_GPIO_VTRIP_SEL_SHIFT (0x02UL) /**< Single SIO pin shift for the input buffer trip point */
443 #define CY_GPIO_VREF_SEL_MASK (0x03UL) /**< Single SIO pin mask for voltage reference */
444 #define CY_GPIO_VREF_SEL_SHIFT (0x03UL) /**< Single SIO pin shift for voltage reference */
445 #define CY_GPIO_VOH_SEL_MASK (0x07UL) /**< Single SIO pin mask for VOH */
446 #define CY_GPIO_VOH_SEL_SHIFT (0x05UL) /**< Single SIO pin shift for VOH */
447
448 /* Special mask for SIO pin pair setting */
449 #define CY_GPIO_SIO_ODD_PIN_MASK (0x00FEUL) /**< SIO pin pair selection mask */
450 #define CY_GPIO_SIO_PIN_MASK (0x00FFUL) /**< SIO pin pair mask */
451
452 /* Offsets */
453 #define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */
454 #define CY_GPIO_DRIVE_MODE_OFFSET (2UL) /**< Offset for Drive mode */
455 #define CY_GPIO_INBUF_OFFSET (3UL) /**< Offset for input buffer */
456 #define CY_GPIO_CFG_OUT_DRIVE_OFFSET (16UL) /**< Offset for drive strength */
457 #define CY_GPIO_INTR_CFG_OFFSET (1UL) /**< Offset for interrupt config */
458 #define CY_GPIO_INTR_FILT_OFFSET (18UL) /**< Offset for filtered interrupt config */
459 #define CY_GPIO_CFG_SIO_OFFSET (2UL) /**< Offset for SIO config */
460 #if defined (CY_IP_MXS40SIOSS) || defined (CY_IP_MXS22IOSS)
461 #define CY_GPIO_CFG_SLEW_EXT_OFFSET (2UL) /**< Offset for CFG SLEW EXT */
462 #define CY_GPIO_CFG_DRIVE_SEL_EXT_OFFSET (3UL) /**< Offset for CFG SLEW EXT */
463 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
464 #if defined (CY_IP_MXS22IOSS)
465 #define CY_GPIO_CFG_RES_PULLUP_MODE_OFFSET (2UL) /**< Offset for Pull-up mode */
466 #endif /* CY_IP_MXS22IOSS */
467
468 /* Parameter validation constants */
469 #define CY_GPIO_PINS_MAX (8UL) /**< Number of pins in the port */
470 #define CY_GPIO_PRT_PINS_MASK (0x0000000FFUL)
471 #define CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK (GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk | \
472 GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk | \
473 GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk | \
474 GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk | \
475 GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \
476 GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \
477 GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \
478 GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
479 #define CY_GPIO_PRT_INTR_CFG_RANGE_MASK (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \
480 GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \
481 GPIO_PRT_INTR_CFG_FLT_SEL_Msk)
482 #define CY_GPIO_PRT_INT_MASK_MASK (0x0000001FFUL)
483 #define CY_GPIO_PRT_SEL_ACTIVE_MASK (0x1FFFFFFFUL)
484 #if defined (CY_IP_MXS22IOSS)
485 #define CY_GPIO_PRT_CFG_RES_MASK (0x77777777UL)
486 #endif /* CY_IP_MXS22IOSS */
487
488 #define GPIO_MAX_SPLIT_CELL_SEGMENTS (9U)
489 #if defined (CY_IP_MXS22IOSS)
490 /* CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ is 0x80UL, but CFG_OUT3 register uses 0x8UL. */
491 /* To correctly configure drive mode value in CFG_OUT3 register, CY_GPIO_EXT_DM_SHIFT is used to shift CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ. */
492 #define CY_GPIO_EXT_DM_SHIFT (0x4UL)
493 #endif /* CY_IP_MXS22IOSS */
494
495 /* Parameter validation macros */
496 #define CY_GPIO_IS_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX > (pinNum))
497 #define CY_GPIO_IS_FILTER_PIN_VALID(pinNum) (CY_GPIO_PINS_MAX >= (pinNum))
498 #define CY_GPIO_IS_VALUE_VALID(outVal) (1UL >= (outVal))
499
500 #if defined(CY_IP_MXS22IOSS)
501 #define CY_GPIO_IS_DM_VALID(driveMode) (((0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK)) ||\
502 ((driveMode) == CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ)) && \
503 ((driveMode) != CY_GPIO_DM_INVALID_IN_OFF) && \
504 ((driveMode) != CY_GPIO_DM_INVALID))
505 #else
506 #define CY_GPIO_IS_DM_VALID(driveMode) ((0U == ((driveMode) & (uint32_t)~CY_GPIO_CFG_DM_MASK)) && \
507 ((driveMode) != CY_GPIO_DM_INVALID_IN_OFF) && \
508 ((driveMode) != CY_GPIO_DM_INVALID))
509 #endif /* CY_IP_MXS22IOSS */
510
511 #define CY_GPIO_IS_HSIOM_VALID(hsiom) (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK))
512
513 #define CY_GPIO_IS_INT_EDGE_VALID(intEdge) ((CY_GPIO_INTR_DISABLE == (intEdge)) || \
514 (CY_GPIO_INTR_RISING == (intEdge)) || \
515 (CY_GPIO_INTR_FALLING == (intEdge)) || \
516 (CY_GPIO_INTR_BOTH == (intEdge)))
517
518 #define CY_GPIO_IS_VREF_SEL_VALID(vrefSel) ((CY_SIO_VREF_PINREF == (vrefSel)) || \
519 (CY_SIO_VREF_1_2V == (vrefSel)) || \
520 (CY_SIO_VREF_AMUX_A == (vrefSel)) || \
521 (CY_SIO_VREF_AMUX_B == (vrefSel)))
522
523 #define CY_GPIO_IS_VOH_SEL_VALID(vrefSel) ((CY_SIO_VOH_1_00 == (vrefSel)) || \
524 (CY_SIO_VOH_1_25 == (vrefSel)) || \
525 (CY_SIO_VOH_1_49 == (vrefSel)) || \
526 (CY_SIO_VOH_1_67 == (vrefSel)) || \
527 (CY_SIO_VOH_2_08 == (vrefSel)) || \
528 (CY_SIO_VOH_2_50 == (vrefSel)) || \
529 (CY_SIO_VOH_2_78 == (vrefSel)) || \
530 (CY_SIO_VOH_4_16 == (vrefSel)))
531
532 #if defined (CY_IP_MXS22IOSS)
533 #define CY_GPIO_IS_PULLUP_RES_VALID(PullUp) ((CY_GPIO_PULLUP_RES_DISABLE == (PullUp)) || \
534 (CY_GPIO_PULLUP_RES_570 == (PullUp)) || \
535 (CY_GPIO_PULLUP_RES_720 == (PullUp)) || \
536 (CY_GPIO_PULLUP_RES_840 == (PullUp)) || \
537 (CY_GPIO_PULLUP_RES_1100 == (PullUp)) || \
538 (CY_GPIO_PULLUP_RES_1200 == (PullUp)) || \
539 (CY_GPIO_PULLUP_RES_1800 == (PullUp)) || \
540 (CY_GPIO_PULLUP_RES_2800 == (PullUp)))
541
542 #define CY_GPIO_PRT_IS_PULLUP_RES_VALID(PullUp) (0U == ((PullUp) & (uint32_t)~CY_GPIO_PRT_CFG_RES_MASK))
543 #endif /* CY_IP_MXS22IOSS */
544
545 #define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
546 #define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK))
547 #define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK))
548 #define CY_GPIO_IS_SEL_ACT_VALID(selActive) (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK))
549
550 #define CY_GPIO_IS_AMUX_SPLIT_VALID(switchCtrl) (((uint32_t) (switchCtrl)) < GPIO_MAX_SPLIT_CELL_SEGMENTS)
551
552 #define CY_GPIO_IS_AMUX_CONNECT_VALID(amuxConnect) ((CY_GPIO_AMUX_OPENALL == (amuxConnect)) || \
553 (CY_GPIO_AMUX_L == (amuxConnect)) || \
554 (CY_GPIO_AMUX_R == (amuxConnect)) || \
555 (CY_GPIO_AMUX_LR == (amuxConnect)) || \
556 (CY_GPIO_AMUX_G == (amuxConnect)) || \
557 (CY_GPIO_AMUX_GL == (amuxConnect)) || \
558 (CY_GPIO_AMUX_GR == (amuxConnect)) || \
559 (CY_GPIO_AMUX_GLR == (amuxConnect)))
560
561 #define CY_GPIO_IS_AMUX_SELECT_VALID(amuxBus) ((CY_GPIO_AMUXBUSA == (amuxBus)) || \
562 (CY_GPIO_AMUXBUSB == (amuxBus)))
563
564 #if defined (CY_IP_MXS40IOSS)
565 #define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) ((CY_GPIO_DRIVE_FULL == (driveSel)) || \
566 (CY_GPIO_DRIVE_1_2 == (driveSel)) || \
567 (CY_GPIO_DRIVE_1_4 == (driveSel)) || \
568 (CY_GPIO_DRIVE_1_8 == (driveSel)))
569 #else
570 #define CY_GPIO_IS_HSIOM_SEC_VALID(secValue) (0U == ((secValue) & (uint32_t)~CY_GPIO_HSIOM_SEC_MASK))
571 #define CY_GPIO_IS_SLEW_RATE_VALID(slewRate) (0U == ((slewRate) & (uint32_t)~CY_GPIO_CFG_SLEW_EXT_MASK))
572 #define CY_GPIO_IS_DRIVE_SEL_VALID(driveSel) (0U == ((driveSel) & (uint32_t)~CY_GPIO_CFG_DRIVE_SEL_EXT_MASK))
573 #endif /* CY_IP_MXS40IOSS */
574
575 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
576 #define CY_GPIO_IS_SMIF_GPIO(baseAddress) (((void *)(baseAddress) == (void *)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT0) || \
577 ((void *)(baseAddress) == (void *)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT1) || \
578 ((void *)(baseAddress) == (void *)SMIF0_CORE0_SMIF_GPIO_SMIF_PRT2) || \
579 ((void *)(baseAddress) == (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0) || \
580 ((void *)(baseAddress) == (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT1) || \
581 ((void *)(baseAddress) == (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT2))
582 #endif
583 /** \endcond */
584
585
586 /***************************************
587 * Function Constants
588 ***************************************/
589
590 /**
591 * \addtogroup group_gpio_macros
592 * \{
593 */
594
595 /**
596 * \defgroup group_gpio_driveModes Pin drive mode
597 * \{
598 * Constants to be used for setting the drive mode of the pin. There are eight
599 * primary drive modes.
600 * Below diagrams are simplified output driver diagrams of the pin view for the
601 * CPU register and UDB/DSI based digital peripherals on each of the eight drive
602 * modes.
603 * \image html gpio_cpu_dm_block_diagram.png
604 *
605 * Below is a simplified output driver diagram that shows the pin view for
606 * fixed-function-based peripherals for each of the eight drive modes.
607 * \image html gpio_periio_dm_block_diagram.png
608 *
609 * - High-Impedance:
610 * This is the standard high-impedance (HI-Z) state recommended for analog and
611 * digital inputs. For digital signals, the input buffer is enabled; for analog
612 * signals, the input buffer is typically disabled to reduce crowbar current
613 * and leakage in low-power designs. To achieve the lowest device current, unused
614 * GPIOs must be configured to the high-impedance drive mode with input buffer
615 * disabled. Highimpedance drive mode with input buffer disabled is also the
616 * default pin reset state.
617 *
618 * - Resistive Pull-Up or Resistive Pull-Down:
619 * Resistive modes provide a series resistance in one of the data states and
620 * strong drive in the other. Pins can be used for either digital input or
621 * digital output in these modes. If resistive pull-up is required, a '1' must be
622 * written to that pin's Data Register bit. If resistive pull-down is required,
623 * a '0' must be written to that pin's Data Register. Interfacing mechanical
624 * switches is a common application of these drive modes. The resistive modes are
625 * also used to interface PSoC with open drain drive lines. Resistive pull-up is
626 * used when the input is open drain low and resistive pull-down is used when the
627 * input is open drain high.
628 *
629 * - Open Drain Drives High and Open Drain Drives Low:
630 * Open drain modes provide high impedance in one of the data states and strong
631 * drive in the other. Pins are useful as digital inputs or outputs in these
632 * modes. Therefore, these modes are widely used in bidirectional digital
633 * communication. Open drain drive high mode is used when the signal is
634 * externally pulled down and open drain drive low is used when the signal is
635 * externally pulled high. A common application for the open drain drives low
636 * mode is driving I2C bus signal lines.
637 *
638 * - Strong Drive:
639 * The strong drive mode is the standard digital output mode for pins; it
640 * provides a strong CMOS output drive in both high and low states. Strong drive
641 * mode pins should not be used as inputs under normal circumstances. This mode
642 * is often used for digital output signals or to drive external devices.
643 *
644 * - Resistive Pull-Up and Resistive Pull-Down:
645 * In the resistive pull-up and pull-down mode, the GPIO will have a series
646 * resistance in both logic 1 and logic 0 output states. The high data state is
647 * pulled up while the low data state is pulled down. This mode is useful when
648 * the pin is driven by other signals that may cause shorts.
649 */
650 #define CY_GPIO_DM_ANALOG (0x00UL) /**< Analog High-Z. Input buffer off */
651 #define CY_GPIO_DM_INVALID_IN_OFF (0x01UL) /**< Invalid mode. It should not be used */
652 #define CY_GPIO_DM_PULLUP_IN_OFF (0x02UL) /**< Resistive Pull-Up. Input buffer off */
653 #define CY_GPIO_DM_PULLDOWN_IN_OFF (0x03UL) /**< Resistive Pull-Down. Input buffer off */
654 #define CY_GPIO_DM_OD_DRIVESLOW_IN_OFF (0x04UL) /**< Open Drain, Drives Low. Input buffer off */
655 #define CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF (0x05UL) /**< Open Drain, Drives High. Input buffer off */
656 #define CY_GPIO_DM_STRONG_IN_OFF (0x06UL) /**< Strong Drive. Input buffer off */
657 #define CY_GPIO_DM_PULLUP_DOWN_IN_OFF (0x07UL) /**< Resistive Pull-Up/Down. Input buffer off */
658 #define CY_GPIO_DM_HIGHZ (0x08UL) /**< Digital High-Z. Input buffer on */
659 #define CY_GPIO_DM_INVALID (0x09UL) /**< Invalid mode. It should not be used */
660 #define CY_GPIO_DM_PULLUP (0x0AUL) /**< Resistive Pull-Up. Input buffer on */
661 #define CY_GPIO_DM_PULLDOWN (0x0BUL) /**< Resistive Pull-Down. Input buffer on */
662 #define CY_GPIO_DM_OD_DRIVESLOW (0x0CUL) /**< Open Drain, Drives Low. Input buffer on */
663 #define CY_GPIO_DM_OD_DRIVESHIGH (0x0DUL) /**< Open Drain, Drives High. Input buffer on */
664 #define CY_GPIO_DM_STRONG (0x0EUL) /**< Strong Drive. Input buffer on */
665 #define CY_GPIO_DM_PULLUP_DOWN (0x0FUL) /**< Resistive Pull-Up/Down. Input buffer on */
666 #if defined (CY_IP_MXS22IOSS)
667 /**
668 * \note
669 * This drive mode is available for the CAT1D devices.
670 **/
671 #define CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ (0x80UL) /**< Strong Drive/Resistive Pull-Up/High-Z based on data_out_en and data_out signals. It is applicable for I3C */
672 #endif /* CY_IP_MXS22IOSS */
673 /** \} */
674
675 /**
676 * \defgroup group_gpio_vtrip Voltage trip mode
677 * \{
678 * Constants to be used for setting the voltage trip type on the pin.
679 */
680 #define CY_GPIO_VTRIP_CMOS (0x00UL) /**< Input buffer compatible with CMOS and I2C interfaces */
681 #define CY_GPIO_VTRIP_TTL (0x01UL) /**< Input buffer compatible with TTL and MediaLB interfaces */
682 /** \} */
683
684 #if (defined(CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION == 3U)) || defined (CY_DOXYGEN)
685 /**
686 * \defgroup group_gpio_vtrip_auto Voltage trip automotive compatible mode
687 * \{
688 * Constants to be used for setting the input buffer automotive compatible mode (trip points and hysteresis) for GPIO upper bit.
689 *
690 * \note
691 * These macros are available for CAT1B devices.
692 *
693 */
694 #define CY_GPIO_VTRIP_DIS_AUTO (0x00UL) /**< Input buffer is not compatible with automotive and it is compatible with CMOS/TTL interfaces */
695 #define CY_GPIO_VTRIP_SEL_AUTO (0x01UL) /**< Input buffer is compatible with automotive */
696 /** \} */
697 #endif/* CY_IP_MXS40IOSS_VERSION */
698
699 /**
700 * \defgroup group_gpio_slewRate Slew Rate Mode
701 * \{
702 * Constants to be used for setting the slew rate of the pin.
703 */
704 #define CY_GPIO_SLEW_FAST (0x00UL) /**< Fast slew rate */
705 #define CY_GPIO_SLEW_SLOW (0x01UL) /**< Slow slew rate */
706 /** \} */
707
708 /**
709 * \defgroup group_gpio_driveStrength Pin drive strength
710 * \{
711 * Constants to be used for setting the drive strength of the pin.
712 */
713 #if defined (CY_IP_MXS22IOSS)
714 #define CY_GPIO_DRIVE_SEL_7 (0x07UL) /**< 7 drive selection: 8mA/16mA drive current (normal/high speed IO)*/
715 #define CY_GPIO_DRIVE_SEL_6 (0x06UL) /**< 6 drive selection: 7mA/14mA drive current (normal/high speed IO)*/
716 #define CY_GPIO_DRIVE_SEL_5 (0x05UL) /**< 5 drive selection: 6mA/12mA drive current (normal/high speed IO)*/
717 #define CY_GPIO_DRIVE_SEL_4 (0x04UL) /**< 4 drive selection: 5mA/10mA drive current (normal/high speed IO)*/
718 #define CY_GPIO_DRIVE_SEL_3 (0x03UL) /**< 3 drive selection: 4mA/8mA drive current (normal/high speed IO)*/
719 #define CY_GPIO_DRIVE_SEL_2 (0x02UL) /**< 2 drive selection: 3mA/6mA drive current (normal/high speed IO)*/
720 #define CY_GPIO_DRIVE_SEL_1 (0x01UL) /**< 1 drive selection: 2mA/4mA drive current (normal/high speed IO)*/
721 #define CY_GPIO_DRIVE_SEL_0 (0x00UL) /**< 0 drive selection: 1mA/2mA drive current (normal/high speed IO)*/
722 /* Backward compatible macros */
723 #define CY_GPIO_DRIVE_FULL (0x07UL) /**< Full drive strength: Max drive current */
724 #define CY_GPIO_DRIVE_1_2 (0x03UL) /**< 1/2 drive strength: 1/2 drive current */
725 #define CY_GPIO_DRIVE_1_4 (0x01UL) /**< 1/4 drive strength: 1/4 drive current */
726 #define CY_GPIO_DRIVE_1_8 (0x00UL) /**< 1/8 drive strength: 1/8 drive current */
727 #else
728 #define CY_GPIO_DRIVE_FULL (0x00UL) /**< Full drive strength: Max drive current */
729 #define CY_GPIO_DRIVE_1_2 (0x01UL) /**< 1/2 drive strength: 1/2 drive current */
730 #define CY_GPIO_DRIVE_1_4 (0x02UL) /**< 1/4 drive strength: 1/4 drive current */
731 #define CY_GPIO_DRIVE_1_8 (0x03UL) /**< 1/8 drive strength: 1/8 drive current */
732 #endif
733 /** \} */
734
735 /**
736 * \defgroup group_gpio_interruptTrigger Interrupt trigger type
737 * \{
738 * Constants to be used for setting the interrupt trigger type on the pin.
739 */
740 #define CY_GPIO_INTR_DISABLE (0x00UL) /**< Disable the pin interrupt generation */
741 #define CY_GPIO_INTR_RISING (0x01UL) /**< Rising-Edge interrupt */
742 #define CY_GPIO_INTR_FALLING (0x02UL) /**< Falling-Edge interrupt */
743 #define CY_GPIO_INTR_BOTH (0x03UL) /**< Both-Edge interrupt */
744 /** \} */
745
746 /**
747 * \defgroup group_gpio_sioVreg SIO output buffer mode
748 * \{
749 * Constants to be used for setting the SIO output buffer mode on the pin.
750 */
751 #define CY_SIO_VREG_UNREGULATED (0x00UL) /**< Unregulated output buffer */
752 #define CY_SIO_VREG_REGULATED (0x01UL) /**< Regulated output buffer */
753 /** \} */
754
755 /**
756 * \defgroup group_gpio_sioIbuf SIO input buffer mode
757 * \{
758 * Constants to be used for setting the SIO input buffer mode on the pin.
759 */
760 #define CY_SIO_IBUF_SINGLEENDED (0x00UL) /**< Single ended input buffer */
761 #define CY_SIO_IBUF_DIFFERENTIAL (0x01UL) /**< Differential input buffer */
762 /** \} */
763
764 /**
765 * \defgroup group_gpio_sioVtrip SIO input buffer trip-point
766 * \{
767 * Constants to be used for setting the SIO input buffer trip-point of the pin.
768 */
769 #define CY_SIO_VTRIP_CMOS (0x00UL) /**< CMOS input buffer (single-ended) */
770 #define CY_SIO_VTRIP_TTL (0x01UL) /**< TTL input buffer (single-ended) */
771 #define CY_SIO_VTRIP_0_5VDDIO_0_5VOH (0x00UL) /**< 0.5xVddio or 0.5xVoh (differential) */
772 #define CY_SIO_VTRIP_0_4VDDIO_1_0VREF (0x01UL) /**< 0.4xVddio or 0.4xVoh (differential) */
773 /** \} */
774
775 /**
776 * \defgroup group_gpio_sioVref SIO reference voltage for input buffer trip-point
777 * \{
778 * Constants to be used for setting the reference voltage of SIO input buffer trip-point.
779 */
780 #define CY_SIO_VREF_PINREF (0x00UL) /**< Vref from analog pin */
781 #define CY_SIO_VREF_1_2V (0x01UL) /**< Vref from internal 1.2V reference */
782 #define CY_SIO_VREF_AMUX_A (0x02UL) /**< Vref from AMUXBUS_A */
783 #define CY_SIO_VREF_AMUX_B (0x03UL) /**< Vref from AMUXBUS_B */
784 /** \} */
785
786 /**
787 * \defgroup group_gpio_sioVoh Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair
788 * \{
789 * Constants to be used for setting the Voh and input buffer trip-point of an SIO pair
790 */
791 #define CY_SIO_VOH_1_00 (0x00UL) /**< Voh = 1 x Reference */
792 #define CY_SIO_VOH_1_25 (0x01UL) /**< Voh = 1.25 x Reference */
793 #define CY_SIO_VOH_1_49 (0x02UL) /**< Voh = 1.49 x Reference */
794 #define CY_SIO_VOH_1_67 (0x03UL) /**< Voh = 1.67 x Reference */
795 #define CY_SIO_VOH_2_08 (0x04UL) /**< Voh = 2.08 x Reference */
796 #define CY_SIO_VOH_2_50 (0x05UL) /**< Voh = 2.50 x Reference */
797 #define CY_SIO_VOH_2_78 (0x06UL) /**< Voh = 2.78 x Reference */
798 #define CY_SIO_VOH_4_16 (0x07UL) /**< Voh = 4.16 x Reference */
799 /** \} */
800
801 #if defined (CY_IP_MXS22IOSS)
802 /**
803 * \defgroup group_gpio_PullUpMode Pull-up mode
804 * \{
805 * Constants to be used for setting the Pull-up mode on the pin.
806 *
807 * \note
808 * This parameter is available for the CAT1D devices.
809 *
810 */
811 #define CY_GPIO_PULLUP_RES_DISABLE (0x00UL) /**< Disable additional Pull-ups */
812 #define CY_GPIO_PULLUP_RES_570 (0x07UL) /**< Pull-up 570 ohms */
813 #define CY_GPIO_PULLUP_RES_720 (0x06UL) /**< Pull-up 720 ohms */
814 #define CY_GPIO_PULLUP_RES_840 (0x05UL) /**< Pull-up 840 ohms */
815 #define CY_GPIO_PULLUP_RES_1100 (0x03UL) /**< Pull-up 1100 ohms */
816 #define CY_GPIO_PULLUP_RES_1200 (0x04UL) /**< Pull-up 1200 ohms */
817 #define CY_GPIO_PULLUP_RES_1800 (0x02UL) /**< Pull-up 1800 ohms */
818 #define CY_GPIO_PULLUP_RES_2800 (0x01UL) /**< Pull-up 2800 ohms */
819 /** \} */
820 #endif /* CY_IP_MXS22IOSS */
821 /** \} group_gpio_macros */
822
823 /***************************************
824 * Function Prototypes
825 ***************************************/
826
827 /**
828 * \addtogroup group_gpio_functions
829 * \{
830 */
831
832 /**
833 * \addtogroup group_gpio_functions_init
834 * \{
835 */
836
837 cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type* base, uint32_t pinNum, const cy_stc_gpio_pin_config_t *config);
838 cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt_config_t *config);
839 void Cy_GPIO_Pin_FastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
840 void Cy_GPIO_Port_Deinit(GPIO_PRT_Type* base);
841 void Cy_GPIO_SetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum, en_hsiom_sel_t value);
842 en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pinNum);
843 __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum);
844 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
845 void Cy_GPIO_Pin_SecFastInit(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t driveMode, uint32_t outVal, en_hsiom_sel_t hsiom);
846 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
847 __STATIC_INLINE uint32_t Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum);
848 #endif /* CY_IP_MXS40SIOSS, IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
849
850 /** \} group_gpio_functions_init */
851
852 /**
853 * \addtogroup group_gpio_functions_gpio
854 * \{
855 */
856
857 void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus);
858 cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus);
859
860 uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum);
861 void Cy_GPIO_Write(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
862 uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum);
863 void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum);
864 void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum);
865 void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum);
866 void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
867 uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum);
868 void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
869 uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum);
870 #if defined(GPIO_AUTOLVL_AVAIL) || defined(CY_DOXYGEN)
871 void Cy_GPIO_SetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
872 uint32_t Cy_GPIO_GetVtripAuto(GPIO_PRT_Type* base, uint32_t pinNum);
873 #endif /* CY_IP_MXS40IOSS_VERSION */
874 void Cy_GPIO_SetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
875 uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNum);
876 void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
877 uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum);
878
879 #if defined (CY_IP_MXS22IOSS)
880 void Cy_GPIO_SetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
881 uint32_t Cy_GPIO_GetPullupResistance(GPIO_PRT_Type* base, uint32_t pinNum);
882 #endif /* CY_IP_MXS22IOSS */
883
884 /** \} group_gpio_functions_gpio */
885
886 /**
887 * \addtogroup group_gpio_functions_sio
888 * \{
889 */
890
891 void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
892 uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum);
893 void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
894 uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum);
895 void Cy_GPIO_SetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
896 uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNum);
897 void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
898 uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum);
899 void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
900 uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum);
901
902 /** \} group_gpio_functions_sio */
903
904 /**
905 * \addtogroup group_gpio_functions_interrupt
906 * \{
907 */
908
909 uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum);
910 void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
911 void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
912 uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum);
913 uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum);
914 void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum);
915 void Cy_GPIO_SetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value);
916 uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t pinNum);
917 void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value);
918 uint32_t Cy_GPIO_GetFilter(GPIO_PRT_Type* base);
919
920 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void);
921 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void);
922 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void);
923 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void);
924 #if (defined (CY_IP_MXS40SIOSS) && (CPUSS_CM33_0_SECEXT_PRESENT != 0)) || defined (CY_IP_MXS22IOSS)
925 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause0(void);
926 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause1(void);
927 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause2(void);
928 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause3(void);
929 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
930
931 /** \} group_gpio_functions_interrupt */
932
933 /** \cond INTERNAL */
934 #if defined (CY_IP_MXS40SIOSS) || (defined (CY_IP_MXS40IOSS) && (CY_IP_MXS40IOSS_VERSION > 2)) || defined (CY_IP_MXS22IOSS)
935 #define HSIOM_PRT_V1_Type HSIOM_PRT_Type
936 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
937 /** \endcond */
938
939 /**
940 * \addtogroup group_gpio_functions_init
941 * \{
942 */
943
944 #if (defined (CY_IP_MXS40SIOSS) && ((IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0))) || defined (CY_IP_MXS22IOSS)
945 /*******************************************************************************
946 * Function Name: Cy_GPIO_SetHSIOM_SecPin
947 ****************************************************************************//**
948 *
949 * Configures the pin as secure or non-secure.
950 *
951 *
952 * \param base
953 * Pointer to the pin's port register base address
954 *
955 * \param pinNum
956 * Position of the pin bit-field within the port register
957 *
958 * \param value
959 * Secure HSIOM non-secure mask
960 *
961 * \note
962 * This function modifies a port register in a read-modify-write operation. It is
963 * not thread safe as the resource is shared among multiple pins on a port.
964 * This function should be called from the right protection context to access
965 * HSIOM secure port (HSIOM_SECURE_PRT_Type).
966 *
967 * \note
968 * This API is available for the CAT1B and CAT1D devices. It should be accessed
969 * from secure domain only.
970 *
971 * \funcusage
972 *
973 *******************************************************************************/
Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type * base,uint32_t pinNum,uint32_t value)974 __STATIC_INLINE void Cy_GPIO_SetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum, uint32_t value)
975 {
976 /* Restrict access to secure API. It should be accessed from secure domain only */
977 #if defined (CY_PDL_TZ_ENABLED)
978 uint32_t tempReg;
979 uint32_t portNum;
980 HSIOM_SECURE_PRT_Type* portAddrSecHSIOM;
981
982 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
983 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(value));
984
985 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
986 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
987
988 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
989 if (CY_GPIO_IS_SMIF_GPIO(base))
990 {
991 uint32_t smif_core_offset = ((void *)base >= (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0) ? SMIF_CORE_SECTION_SIZE : 0U;
992 portNum = ((uint32_t)(base) - CY_SMIF_GPIO_BASE - smif_core_offset) / SMIF_CORE_SMIF_GPIO_SMIF_PRT_SECTION_SIZE;
993 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_SMIF_SECURE_HSIOM_BASE + (SMIF_CORE_SMIF_HSIOM_SMIF_SECURE_PRT_SECTION_SIZE * portNum) + smif_core_offset);
994 }
995 #endif
996
997 tempReg= HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) & ~(CY_GPIO_HSIOM_SEC_MASK << pinNum);
998 HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) = tempReg | ((value & CY_GPIO_HSIOM_SEC_MASK) << pinNum);
999 #else
1000 /* Suppress a compiler warning about unused variables */
1001 (void)base;
1002 (void)pinNum;
1003 (void)value;
1004 #endif /* CY_PDL_TZ_ENABLED */
1005 }
1006
1007 /*******************************************************************************
1008 * Function Name: Cy_GPIO_GetHSIOM_SecPin
1009 ****************************************************************************//**
1010 *
1011 * Returns the current status of secure Pin.
1012 *
1013 * \param base
1014 * Pointer to the pin's port register base address
1015 *
1016 * \param pinNum
1017 * Position of the pin bit-field within the port register
1018 *
1019 * \return
1020 * HSIOM input selection. In case of accessing this API from secure domain, it
1021 * will return 0 ( secure ) or 1 ( non-secure ). Whereas, in case of accessing
1022 * this API from non-secure domain, it will return \ref CY_GPIO_BAD_PARAM.
1023 *
1024 * \note
1025 * This API is available for the CAT1B and CAT1D devices. It should be accessed
1026 * from secure domain only.
1027 *
1028 * \funcusage
1029 *
1030 *******************************************************************************/
Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type * base,uint32_t pinNum)1031 __STATIC_INLINE uint32_t Cy_GPIO_GetHSIOM_SecPin(GPIO_PRT_Type* base, uint32_t pinNum)
1032 {
1033 /* Restrict access to secure API. It should be accessed from secure domain only */
1034 #if defined (CY_PDL_TZ_ENABLED)
1035 uint32_t portNum;
1036 HSIOM_SECURE_PRT_Type* portAddrSecHSIOM;
1037
1038 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
1039
1040 portNum = ((uint32_t)(base) - CY_GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
1041 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_HSIOM_SECURE_BASE + (HSIOM_SECURE_PRT_SECTION_SIZE * portNum));
1042
1043 #if defined (CY_IP_MXSMIF) && (CY_IP_MXSMIF_VERSION >= 5)
1044 if (CY_GPIO_IS_SMIF_GPIO(base))
1045 {
1046 uint32_t smif_core_offset = ((void *)base >= (void *)SMIF0_CORE1_SMIF_GPIO_SMIF_PRT0) ? SMIF_CORE_SECTION_SIZE : 0U;
1047 portNum = ((uint32_t)(base) - CY_SMIF_GPIO_BASE - smif_core_offset) / SMIF_CORE_SMIF_GPIO_SMIF_PRT_SECTION_SIZE;
1048 portAddrSecHSIOM = (HSIOM_SECURE_PRT_Type*)(CY_SMIF_SECURE_HSIOM_BASE + (SMIF_CORE_SMIF_HSIOM_SMIF_SECURE_PRT_SECTION_SIZE * portNum) + smif_core_offset);
1049 }
1050 #endif
1051
1052 return (uint32_t)((HSIOM_SEC_PRT_NONSEC_MASK(portAddrSecHSIOM) >> pinNum) & CY_GPIO_HSIOM_SEC_MASK);
1053 #else
1054 /* Suppress a compiler warning about unused variables */
1055 (void)base;
1056 (void)pinNum;
1057
1058 return (uint32_t)CY_GPIO_BAD_PARAM;
1059 #endif /* CY_PDL_TZ_ENABLED */
1060 }
1061 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS22IOSS */
1062
1063 /*******************************************************************************
1064 * Function Name: Cy_GPIO_PortToAddr
1065 ****************************************************************************//**
1066 *
1067 * Retrieves the port address based on the given port number.
1068 *
1069 * This is a helper function to calculate the port base address when given a port
1070 * number. It is to be used when pin access needs to be calculated at runtime.
1071 *
1072 * \param portNum
1073 * Port number
1074 *
1075 * \return
1076 * Base address of the port register structure
1077 *
1078 * \funcusage
1079 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_PortToAddr
1080 *
1081 *******************************************************************************/
Cy_GPIO_PortToAddr(uint32_t portNum)1082 __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
1083 {
1084 GPIO_PRT_Type* portBase;
1085
1086 if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR)
1087 {
1088 portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum));
1089 }
1090 else
1091 {
1092 /* Error: Return default base address */
1093 portBase = (GPIO_PRT_Type *)(CY_GPIO_BASE);
1094 }
1095
1096 return (portBase);
1097 }
1098
1099 /** \} group_gpio_functions_init */
1100
1101
1102
1103 /**
1104 * \addtogroup group_gpio_functions_interrupt
1105 * \{
1106 */
1107
1108 /*******************************************************************************
1109 * Function Name: Cy_GPIO_GetInterruptCause0
1110 ****************************************************************************//**
1111 *
1112 * Returns the interrupt status for ports 0 to 31.
1113 *
1114 * \return
1115 * 0 = Interrupt not detected on port
1116 * 1 = Interrupt detected on port
1117 *
1118 * \funcusage
1119 * \snippet gpio/snippet/main.c snippet_Cy_GPIO_GetInterruptCause0
1120 *
1121 *******************************************************************************/
Cy_GPIO_GetInterruptCause0(void)1122 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause0(void)
1123 {
1124 return (GPIO_INTR_CAUSE0);
1125 }
1126
1127
1128 /*******************************************************************************
1129 * Function Name: Cy_GPIO_GetInterruptCause1
1130 ****************************************************************************//**
1131 *
1132 * Returns the interrupt status for ports 32 to 63.
1133 *
1134 * \return
1135 * 0 = Interrupt not detected on port
1136 * 1 = Interrupt detected on port
1137 *
1138 * \funcusage
1139 * Refer to the Cy_GPIO_GetInterruptCause0() example.
1140 *
1141 *******************************************************************************/
Cy_GPIO_GetInterruptCause1(void)1142 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause1(void)
1143 {
1144 return (GPIO_INTR_CAUSE1);
1145 }
1146
1147
1148 /*******************************************************************************
1149 * Function Name: Cy_GPIO_GetInterruptCause2
1150 ****************************************************************************//**
1151 *
1152 * Returns the interrupt status for ports 64 to 95.
1153 *
1154 * \return
1155 * 0 = Interrupt not detected on port
1156 * 1 = Interrupt detected on port
1157 * \funcusage
1158 * Refer to the Cy_GPIO_GetInterruptCause0() example.
1159 *
1160 *******************************************************************************/
Cy_GPIO_GetInterruptCause2(void)1161 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause2(void)
1162 {
1163 return (GPIO_INTR_CAUSE2);
1164 }
1165
1166
1167 /*******************************************************************************
1168 * Function Name: Cy_GPIO_GetInterruptCause3
1169 ****************************************************************************//**
1170 *
1171 * Returns the interrupt status for ports 96 to 127.
1172 *
1173 * \return
1174 * 0 = Interrupt not detected on port
1175 * 1 = Interrupt detected on port
1176 *
1177 * \funcusage
1178 * Refer to the Cy_GPIO_GetInterruptCause0() example.
1179 *
1180 *******************************************************************************/
Cy_GPIO_GetInterruptCause3(void)1181 __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void)
1182 {
1183 return (GPIO_INTR_CAUSE3);
1184 }
1185
1186 #if (defined (CY_IP_MXS40SIOSS) && (CPUSS_CM33_0_SECEXT_PRESENT != 0)) || defined (CY_IP_MXS22IOSS)
1187 /*******************************************************************************
1188 * Function Name: Cy_GPIO_GetSecureInterruptCause0
1189 ****************************************************************************//**
1190 *
1191 * Returns the interrupt status for ports 0 to 31.
1192 *
1193 * \return
1194 * 0 = Interrupt not detected on port
1195 * 1 = Interrupt detected on port
1196 *
1197 * \note
1198 * This API is available for the CAT1B and CAT1D devices.
1199 *
1200 * \funcusage
1201 *
1202 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause0(void)1203 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause0(void)
1204 {
1205 return (GPIO_SEC_INTR_CAUSE0);
1206 }
1207
1208
1209 /*******************************************************************************
1210 * Function Name: Cy_GPIO_GetSecureInterruptCause1
1211 ****************************************************************************//**
1212 *
1213 * Returns the interrupt status for ports 32 to 63.
1214 *
1215 * \return
1216 * 0 = Interrupt not detected on port
1217 * 1 = Interrupt detected on port
1218 *
1219 * \note
1220 * This API is available for the CAT1B and CAT1D devices.
1221 *
1222 * \funcusage
1223 *
1224 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause1(void)1225 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause1(void)
1226 {
1227 return (GPIO_SEC_INTR_CAUSE1);
1228 }
1229
1230
1231 /*******************************************************************************
1232 * Function Name: Cy_GPIO_GetSecureInterruptCause2
1233 ****************************************************************************//**
1234 *
1235 * Returns the interrupt status for ports 64 to 95.
1236 *
1237 * \return
1238 * 0 = Interrupt not detected on port
1239 * 1 = Interrupt detected on port
1240 *
1241 * \note
1242 * This API is available for the CAT1B and CAT1D devices.
1243 *
1244 * \funcusage
1245 *
1246 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause2(void)1247 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause2(void)
1248 {
1249 return (GPIO_SEC_INTR_CAUSE2);
1250 }
1251
1252
1253 /*******************************************************************************
1254 * Function Name: Cy_GPIO_GetSecureInterruptCause3
1255 ****************************************************************************//**
1256 *
1257 * Returns the interrupt status for ports 96 to 127.
1258 *
1259 * \return
1260 * 0 = Interrupt not detected on port
1261 * 1 = Interrupt detected on port
1262 *
1263 * \note
1264 * This API is available for the CAT1B and CAT1D devices.
1265 *
1266 * \funcusage
1267 *
1268 *******************************************************************************/
Cy_GPIO_GetSecureInterruptCause3(void)1269 __STATIC_INLINE uint32_t Cy_GPIO_GetSecureInterruptCause3(void)
1270 {
1271 return (GPIO_SEC_INTR_CAUSE3);
1272 }
1273 #endif /* CY_IP_MXS40SIOSS, CPUSS_CM33_0_SECEXT_PRESENT, CY_IP_MXS22IOSS */
1274
1275 /** \} group_gpio_functions_interrupt */
1276
1277 /** \} group_gpio_functions */
1278
1279 #if defined(__cplusplus)
1280 }
1281 #endif
1282
1283 #endif /* CY_IP_MXS40SIOSS, CY_IP_MXS40IOSS, CY_IP_MXS22IOSS */
1284
1285 #endif /* CY_GPIO_H */
1286
1287 /** \} group_gpio */
1288
1289 /* [] END OF FILE */
1290
