1 /***************************************************************************//** 2 * \file cy_flash.h 3 * \version 3.50.1 4 * 5 * Provides the API declarations of the Flash driver. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2016-2020 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 #if !defined (CY_FLASH_H) 26 #define CY_FLASH_H 27 28 /** 29 * \addtogroup group_flash 30 * \{ 31 * Internal flash memory programming 32 * 33 * The functions and other declarations used in this driver are in cy_flash.h. 34 * You can include cy_pdl.h to get access to all functions 35 * and declarations in the PDL. 36 * 37 * Flash memory in PSoC devices provides non-volatile storage for user firmware, 38 * user configuration data, and bulk data storage. 39 * 40 * Flash operations are implemented as system calls. System calls are executed 41 * out of SROM in the privileged mode of operation. Users have no access to read 42 * or modify the SROM code. The driver API requests the system call by acquiring 43 * the Inter-processor communication (IPC) and writing the SROM function opcode 44 * and parameters to its input registers. As a result, an NMI interrupt is invoked 45 * and the requested SROM function is executed. The operation status is returned 46 * to the driver context and a release interrupt is triggered. 47 * 48 * Writing to flash can take up to 20 milliseconds. During this time, 49 * the device should not be reset (including XRES pin, software reset, and 50 * watchdog) or unexpected changes may be made to portions of the flash. 51 * Also, the low-voltage detect circuits should be configured to generate an 52 * interrupt instead of a reset. 53 * 54 * A Read while Write violation occurs when a flash Read operation is initiated 55 * in the same or neighboring (neighboring restriction is applicable just for the 56 * CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or 57 * Program operation is working. This violation may cause a HardFault exception. 58 * To avoid the Read while Write violation, carefully split the 59 * Read and Write operation on flash sectors which are not neighboring, 60 * considering both cores in the multi-processor device. If the flash is divided 61 * into four equal sectors, you may edit the linker script to place the code 62 * into neighboring sectors. For example, use sectors number 0 and 1 for code 63 * and sectors 2 and 3 for data storage. 64 * 65 * \section group_flash_configuration Configuration Considerations 66 * 67 * \subsection group_flash_config_intro Introduction: 68 * The PSoC 6 MCU user-programmable Flash consists of: 69 * - Application flash memory (from 2 to 8 sectors) - 128KB/256KB each. 70 * - EE emulation flash memory - 32KB. 71 * 72 * Write operation may be done as Blocking or Partially Blocking, 73 * defined as follows: 74 * 75 * \subsection group_flash_config_blocking Blocking: 76 * In this case, the entire Flash block is not available for the duration of the 77 * Write (∼16ms). Therefore, no Flash accesses (from any Bus Master) can 78 * occur during that time. CPU execution can be performed from SRAM. All 79 * pre-fetching must be disabled. Code execution from Flash is blocked for the 80 * Flash Write duration for both cores. 81 * 82 * \subsection group_flash_config_block_const Constraints for Blocking Flash operations: 83 * -# During write to flash, the device should not be reset (including XRES pin, 84 * software reset, and watchdog), or unexpected changes may be made to portions 85 * of the flash. 86 * -# The low-voltage detect circuits should be configured to generate an 87 * interrupt instead of a reset. 88 * -# Flash rite operation is allowed only in one of the following CM4 states: 89 * -# CM4 is Active and initialized:<br> 90 * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". 91 * <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time 92 * after calling Cy_SysEnableCM4(). 93 * -# CM4 is Off and disabled:<br> 94 * call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not 95 * supported. 96 * . 97 * -# Flash Write cannot be performed in Ultra Low Power (core voltage 0.9V) mode. 98 * -# Interrupts must be enabled on both active cores. Do not enter a critical 99 * section during flash operation. 100 * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe 101 * interrupts (IPC interrupts 3 and 4) have the highest priority, or 102 * at least that pipe interrupts are not interrupted or in a pending state 103 * for more than 700 µs. 104 * -# User must guarantee that during flash write operation no flash read 105 * operations are performed by bus masters other than CM0+ and CM4 (DMA and 106 * Crypto). 107 * -# For the CY8C6xx6, CY8C6xx7 devices if you do not use the default startup, perform the following steps 108 * before any flash write/erase operations: 109 * \snippet flash/snippet/main.c Flash Initialization 110 * 111 * \subsection group_flash_config_rww Partially Blocking: 112 * This method has a much shorter time window during which Flash accesses are not 113 * allowed. Application code execution from Flash is blocked for only a part of 114 * Flash Write duration, for both cores. Blocking duration depends upon the API 115 * sequence used. 116 * 117 * For API sequence Cy_Flash_StartEraseRow() + Cy_Flash_StartProgram() there are 118 * four block-out regions during which Read is blocked. See <b>Figure 1</b>. 119 * 120 * <center> 121 * <table class="doxtable"> 122 * <caption>Table 1 - Block-out periods (timing values are valid just for the 123 * CY8C6xx6, CY8C6xx7 devices) </caption> 124 * <tr> 125 * <th>Block-out</th> 126 * <th>Phase</th> 127 * <th>Duration</th> 128 * </tr> 129 * <tr> 130 * <td>A</td> 131 * <td>The beginning of the Erase operation</td> 132 * <td>2ms + 9500 SlowClk cycles</td> 133 * </tr> 134 * <tr> 135 * <td>B</td> 136 * <td>The end of the Erase operation</td> 137 * <td>0.13ms + 1000 SlowClk cycles</td> 138 * </tr> 139 * <tr> 140 * <td>C</td> 141 * <td>The beginning of the Program operation</td> 142 * <td>0.8ms + 6000 SlowClk cycles</td> 143 * </tr> 144 * <tr> 145 * <td>D</td> 146 * <td>The end of the Program operation</td> 147 * <td>0.13ms + 1000 SlowClk cycles</td> 148 * </tr> 149 * </table> 150 * </center> 151 * 152 * This allows both cores to execute for about 80% of Flash Write 153 * operation - see <b>Figure 1</b>. 154 * This capability is important for communication protocols that rely on fast 155 * response. 156 * 157 * \image html flash-rww-diagram.png "Figure 1 - Blocking Intervals in Flash Write operation" 158 * 159 * For the Cy_Flash_StartWrite() function, the block-out period is different for 160 * the two cores. The core that initiates Cy_Flash_StartWrite() is blocked for 161 * two periods: 162 * - From start of Erase operation (start of A on Figure 1) till the start of 163 * Program operation (end of C on Figure 1). 164 * - During D period on <b>Figure 1</b>. 165 * 166 * The core that performs read/execute is blocked identically to the previous 167 * scenario - see <b>Figure 1</b>. 168 * 169 * This allows the core that initiates Cy_Flash_StartWrite() to execute for about 170 * 20% of Flash Write operation. The other core executes for about 80% of Flash 171 * Write operation. 172 * 173 * Some constraints must be planned for in the Partially Blocking mode which are 174 * described in detail below. 175 * 176 * \subsection group_flash_config_rww_const Constraints for Partially Blocking Flash operations: 177 * -# During write to flash, the device should not be reset (including XRES pin, 178 * software reset, and watchdog) or unexpected changes may be made to portions 179 * of the flash. 180 * -# The low-voltage detect circuits should be configured to generate an 181 * interrupt instead of a reset. 182 * -# During write to flash, application code should not change the clock 183 * settings. Use Cy_Flash_IsOperationComplete() to ensure flash write 184 * operation is finished. 185 * -# During write to flash, application code should not start the clock 186 * measurements (should not call Cy_SysClk_StartClkMeasurementCounters()). 187 * -# Flash write operation is allowed only in one of the following CM4 states: 188 * -# CM4 is Active and initialized:<br> 189 * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". 190 * <b>Note:</b> If desired user may put CM4 core in Deep Sleep any time 191 * after calling Cy_SysEnableCM4(). 192 * -# CM4 is Off and disabled:<br> 193 * call Cy_SysDisableCM4(). <b>Note:</b> In this state Debug mode is not 194 * supported. 195 * . 196 * -# Use the following rules for split by sectors. (In this context, read means 197 * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) 198 * -# Do not write to and read/execute from the same flash sector at the same 199 * time. This is true for all sectors. 200 * -# Writing rules in application flash (this restriction is applicable just 201 * for CY8C6xx6, CY8C6xx7 devices): 202 * -# Any bus master can read/execute from UFLASH S0 and/or S1, during 203 * flash write to UFLASH S2 or S3. 204 * -# Any bus master can read/execute from UFLASH S2 and/or S3, during 205 * flash write to UFLASH S0 or S1. 206 * 207 * <b>Suggestion:</b> in case of bootloading, it is recommended to place 208 * code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data 209 * to S2 and S3 sections. 210 * . 211 * -# Flash Write cannot be performed in Ultra Low Power mode (core voltage 0.9V). 212 * -# Interrupts must be enabled on both active cores. Do not enter a critical 213 * section during flash operation. 214 * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe 215 * interrupts (IPC interrupts 3 and 4) have the highest priority, or at 216 * least that pipe interrupts are not interrupted or in a pending state 217 * for more than 700 µs. 218 * -# For the CY8C6xx6, CY8C6xx7 devices if you do not use the default startup, perform the following steps 219 * before any flash write/erase operations: 220 * \snippet flash/snippet/main.c Flash Initialization 221 * 222 * \subsection group_flash_config_emeeprom EEPROM section use: 223 * If you plan to use "cy_em_eeprom" section for different purposes for both of 224 * device cores or use <b>Em_EEPROM Middleware</b> together with flash driver 225 * write operations you must modify the linker scripts.<br> 226 * For more information, refer to the <b>Middleware/Cypress Em_EEPROM Middleware 227 * Library</b> section of the PDL documentation. 228 * 229 * \section group_flash_more_information More Information 230 * 231 * See the technical reference manual (TRM) for more information about the Flash 232 * architecture. 233 * 234 * \section group_flash_changelog Changelog 235 * 236 * <table class="doxtable"> 237 * <tr><th>Version</th><th style="width: 52%;">Changes</th><th>Reason for Change</th></tr> 238 * <tr> 239 * <td>3.50.1</td> 240 * <td>Updated documentation to limit devices with the restrictions.</td> 241 * <td>User experience enhancement.</td> 242 * </tr> 243 * <tr> 244 * <td rowspan="2">3.50</td> 245 * <td>Updated attribute usage for the linker section placement.</td> 246 * <td>Enhancement based on usability feedback.</td> 247 * </tr> 248 * <tr> 249 * <td>Fixed/documented MISRA 2012 violations.</td> 250 * <td>MISRA 2012 compliance.</td> 251 * </tr> 252 * <tr> 253 * <td rowspan="1">3.40</td> 254 * <td>Updated Cy_Flash_OperationStatus() to access protected registers.</td> 255 * <td>Added PSoC 64 device support.</td> 256 * </tr> 257 * <tr> 258 * <td rowspan="1">3.30.4</td> 259 * <td>Improved documentation.</td> 260 * <td>User experience enhancement.</td> 261 * </tr> 262 * <tr> 263 * <td rowspan="1">3.30.3</td> 264 * <td>Updated documentation to limit devices with the restrictions. Improved calculation of the CY_FLASH_DELAY_CORRECTIVE macro.</td> 265 * <td>User experience enhancement.</td> 266 * </tr> 267 * <tr> 268 * <td rowspan="1">3.30.2</td> 269 * <td>Updated documentation to limit devices with the neighboring restriction.</td> 270 * <td>User experience enhancement.</td> 271 * </tr> 272 * <tr> 273 * <td rowspan="1">3.30.1</td> 274 * <td>Used the CY_RAMFUNC_BEGIN and CY_RAMFUNC_END macros that allocate the function in RAM instead of using the CY_SECTION(".cy_ramfunc") macros.</td> 275 * <td>Removed the code duplication.</td> 276 * </tr> 277 * <tr> 278 * <td rowspan="3">3.30</td> 279 * <td>Moved ipcWaitMessageStc structure to the RAM section called ".cy_sharedmem".</td> 280 * <td>Support Secure Boot devices.</td> 281 * </tr> 282 * <tr> 283 * <td>Renamed Function Cy_Flash_StartErase() to Cy_Flash_StartEraseRow().</td> 284 * <td>The driver improvements based on the usability feedback.</td> 285 * </tr> 286 * <tr> 287 * <td>Added new API functions \ref Cy_Flash_EraseSector, 288 * \ref Cy_Flash_StartEraseSector, \ref Cy_Flash_EraseSubsector, 289 * \ref Cy_Flash_StartEraseSubsector </td> 290 * <td>The driver improvements based on the usability feedback.</td> 291 * </tr> 292 * <tr> 293 * <td rowspan="3">3.20</td> 294 * <td>Flattened the organization of the driver source code into the single source directory and the single include directory.</td> 295 * <td>Driver library directory-structure simplification.</td> 296 * </tr> 297 * <tr> 298 * <td>Added new API function \ref Cy_Flash_InitExt</td> 299 * <td>The driver improvements based on the usability feedback</td> 300 * </tr> 301 * <tr> 302 * <td>Added register access layer. Use register access macros instead 303 * of direct register access using dereferenced pointers.</td> 304 * <td>Makes register access device-independent, so that the PDL does 305 * not need to be recompiled for each supported part number.</td> 306 * </tr> 307 * <tr> 308 * <td>3.11</td> 309 * <td>Updated driver functionality to correctly use the SysClk measurement 310 * counters while partially blocking flash operations</td> 311 * <td>Added arbiter mechanism for correct usage of the SysClk measurement 312 * counters</td> 313 * </tr> 314 * <tr> 315 * <td>3.10</td> 316 * <td>Updated Cy_Flash_SendCmd() code to support single core devices.</td> 317 * <td>Support new devices</td> 318 * </tr> 319 * <tr> 320 * <td>3.0</td> 321 * <td>New function - Cy_Flash_ProgramRow();<br> 322 * Updated Cy_Flash_RowChecksum(): changed input parameter to take the 323 * <b>row address</b> (rowAddr) instead of the <b>row number</b> 324 * (rowNum);<br> 325 * Renamed macro for disabling RWW support in driver to 326 * <b>CY_FLASH_RWW_DRV_SUPPORT_DISABLED</b>.<br> 327 * Updated \ref group_flash_configuration documentation section with 328 * flash usage constraints.</td> 329 * <td>Improvements made based on usability feedback to use a common 330 * interface</td> 331 * </tr> 332 * <tr> 333 * <td rowspan="3">2.0</td> 334 * <td>Added non-blocking erase function - Cy_Flash_StartErase(). 335 * Removed the clear cache function call.</td> 336 * <td>The clear cache operation is removed from the blocking Write/Erase 337 * function because in this case it is performed by the hardware. 338 * Otherwise it is documented that it is the user's responsibility to 339 * clear the cache after executing the non-blocking Write/Erase flash 340 * operation.</td> 341 * </tr> 342 * <tr> 343 * <td>Added new Cy_Flash_IsOperationComplete() function to check completeness. 344 * Obsoleted Cy_Flash_IsWriteComplete(), Cy_Flash_IsProgramComplete(), 345 * and Cy_Flash_IsEraseComplete() functions.<br> 346 * Added Cy_Flash_GetExternalStatus() function to get unparsed status where 347 * flash driver will be used in security applications with other modules 348 * as SecureImage.<br> 349 * Added Cy_Flash_Init() function to initialize all needed prerequisites 350 * for Erase/Write operations.</td> 351 * <td>Updated driver design to improve user experience.</td> 352 * </tr> 353 * <tr> 354 * <td>Updated driver implementation to remove MISRA rules deviations.</td> 355 * <td>Driver implementation quality improvement.</td> 356 * </tr> 357 * <tr> 358 * <td>1.0</td> 359 * <td>Initial version</td> 360 * <td></td> 361 * </tr> 362 * </table> 363 * 364 * \defgroup group_flash_macros Macros 365 * \{ 366 * \defgroup group_flash_general_macros Flash general parameters 367 * Provides general information about flash 368 * 369 * \defgroup group_flash_config_macros Flash configuration 370 * Specifies the parameter values passed to SROM API 371 * \} 372 * \defgroup group_flash_functions Functions 373 * \defgroup group_flash_enumerated_types Enumerated Types 374 */ 375 376 #include "cy_device.h" 377 378 #if defined (CY_IP_M4CPUSS) 379 380 #include "cy_syslib.h" 381 382 #if defined(__cplusplus) 383 extern "C" { 384 #endif 385 386 /*************************************** 387 * Macro definitions 388 ***************************************/ 389 /** 390 * \addtogroup group_flash_macros 391 * \{ 392 */ 393 394 /** Driver major version */ 395 #define CY_FLASH_DRV_VERSION_MAJOR 3 396 397 /** Driver minor version */ 398 #define CY_FLASH_DRV_VERSION_MINOR 50 399 400 #define CY_FLASH_ID (CY_PDL_DRV_ID(0x14UL)) /**< FLASH PDL ID */ 401 402 #define CY_FLASH_ID_INFO (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_INFO ) /**< Return prefix for FLASH driver function status codes */ 403 #define CY_FLASH_ID_WARNING (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_WARNING) /**< Return prefix for FLASH driver function warning return values */ 404 #define CY_FLASH_ID_ERROR (uint32_t)( CY_FLASH_ID | CY_PDL_STATUS_ERROR) /**< Return prefix for FLASH driver function error return values */ 405 406 /** \} group_flash_macros */ 407 408 409 /** 410 * \addtogroup group_flash_general_macros 411 * \{ 412 */ 413 414 /** Flash row size */ 415 #define CY_FLASH_SIZEOF_ROW (CPUSS_FLASHC_PA_SIZE * 4u) 416 /** Long words flash row size */ 417 #define CY_FLASH_SIZEOF_ROW_LONG_UNITS (CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)) 418 419 /** \} group_flash_general_macros */ 420 421 422 /** 423 * \addtogroup group_flash_enumerated_types 424 * \{ 425 */ 426 427 /** This enum has the return values of the Flash driver */ 428 typedef enum cy_en_flashdrv_status 429 { 430 CY_FLASH_DRV_SUCCESS = 0x00UL, /**< Success */ 431 CY_FLASH_DRV_INV_PROT = ( CY_FLASH_ID_ERROR + 0x0UL), /**< Invalid device protection state */ 432 CY_FLASH_DRV_INVALID_FM_PL = ( CY_FLASH_ID_ERROR + 0x1UL), /**< Invalid flash page latch address */ 433 CY_FLASH_DRV_INVALID_FLASH_ADDR = ( CY_FLASH_ID_ERROR + 0x2UL), /**< Invalid flash address */ 434 CY_FLASH_DRV_ROW_PROTECTED = ( CY_FLASH_ID_ERROR + 0x3UL), /**< Row is write protected */ 435 CY_FLASH_DRV_IPC_BUSY = ( CY_FLASH_ID_ERROR + 0x5UL), /**< IPC structure is already locked by another process */ 436 CY_FLASH_DRV_INVALID_INPUT_PARAMETERS = ( CY_FLASH_ID_ERROR + 0x6UL), /**< Input parameters passed to Flash API are not valid */ 437 CY_FLASH_DRV_PL_ROW_COMP_FA = ( CY_FLASH_ID_ERROR + 0x22UL), /**< Comparison between Page Latches and FM row failed */ 438 CY_FLASH_DRV_ERR_UNC = ( CY_FLASH_ID_ERROR + 0xFFUL), /**< Unknown error code. See \ref Cy_Flash_GetExternalStatus() */ 439 CY_FLASH_DRV_PROGRESS_NO_ERROR = ( CY_FLASH_ID_INFO + 0x0UL), /**< Command in progress; no error */ 440 CY_FLASH_DRV_OPERATION_STARTED = ( CY_FLASH_ID_INFO + 0x1UL), /**< Flash operation is successfully initiated */ 441 CY_FLASH_DRV_OPCODE_BUSY = ( CY_FLASH_ID_INFO + 0x2UL) /**< Flash is under operation */ 442 } cy_en_flashdrv_status_t; 443 444 445 #if !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) 446 /** Flash notification configuration structure */ 447 typedef struct 448 { 449 uint8_t clientID; /**< Client ID */ 450 uint8_t pktType; /**< Message Type */ 451 uint16_t intrRelMask; /**< Mask */ 452 } cy_stc_flash_notify_t; 453 #endif /* !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ 454 455 /** \} group_flash_enumerated_types */ 456 457 /*************************************** 458 * Function Prototypes 459 ***************************************/ 460 461 /** 462 * \addtogroup group_flash_functions 463 * \{ 464 */ 465 void Cy_Flash_Init(void); 466 cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr); 467 cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr); 468 cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr); 469 cy_en_flashdrv_status_t Cy_Flash_StartEraseSector(uint32_t sectorAddr); 470 cy_en_flashdrv_status_t Cy_Flash_EraseSubsector(uint32_t subSectorAddr); 471 cy_en_flashdrv_status_t Cy_Flash_StartEraseSubsector(uint32_t subSectorAddr); 472 cy_en_flashdrv_status_t Cy_Flash_ProgramRow(uint32_t rowAddr, const uint32_t* data); 473 cy_en_flashdrv_status_t Cy_Flash_WriteRow(uint32_t rowAddr, const uint32_t* data); 474 cy_en_flashdrv_status_t Cy_Flash_StartWrite(uint32_t rowAddr, const uint32_t* data); 475 cy_en_flashdrv_status_t Cy_Flash_StartProgram(uint32_t rowAddr, const uint32_t* data); 476 cy_en_flashdrv_status_t Cy_Flash_IsOperationComplete(void); 477 cy_en_flashdrv_status_t Cy_Flash_RowChecksum(uint32_t rowAddr, uint32_t* checksumPtr); 478 cy_en_flashdrv_status_t Cy_Flash_CalculateHash(const uint32_t* data, uint32_t numberOfBytes, uint32_t* hashPtr); 479 uint32_t Cy_Flash_GetExternalStatus(void); 480 481 #if !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) 482 void Cy_Flash_InitExt(cy_stc_flash_notify_t *ipcWaitMessageAddr); 483 #endif /* !defined (CY_FLASH_RWW_DRV_SUPPORT_DISABLED) */ 484 485 /** \} group_flash_functions */ 486 487 /** \cond INTERNAL */ 488 #if (CY_CPU_CORTEX_M4) 489 void Cy_Flash_ResumeIrqHandler(void); 490 #endif 491 492 /******************************************************************************* 493 Backward compatibility macro. The following code is DEPRECATED and must 494 not be used in new projects 495 *******************************************************************************/ 496 #define Cy_Flash_IsWriteComplete(...) Cy_Flash_IsOperationComplete() 497 #define Cy_Flash_IsProgramComplete(...) Cy_Flash_IsOperationComplete() 498 #define Cy_Flash_IsEraseComplete(...) Cy_Flash_IsOperationComplete() 499 #define CY_FLASH_NUMBER_ROWS (CY_FLASH_SIZE / CY_FLASH_SIZEOF_ROW) 500 #define Cy_Flash_StartErase Cy_Flash_StartEraseRow 501 502 /** \endcond */ 503 504 #if defined(__cplusplus) 505 } 506 #endif 507 508 #endif /* CY_IP_M4CPUSS */ 509 510 #endif /* #if !defined (CY_FLASH_H) */ 511 512 /** \} group_flash */ 513 514 515 /* [] END OF FILE */ 516
