1 /***************************************************************************//** 2 * \file cy_crypto_core_hw_v1.h 3 * \version 2.120 4 * 5 * \brief 6 * This file provides constants and function prototypes 7 * for the Vector Unit functions in the Crypto block driver. 8 * 9 ******************************************************************************** 10 * \copyright 11 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or 12 * an affiliate of Cypress Semiconductor Corporation. 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 29 #if !defined (CY_CRYPTO_CORE_HW_V1_H) 30 #define CY_CRYPTO_CORE_HW_V1_H 31 32 #include "cy_crypto_common.h" 33 34 #if defined(CY_IP_MXCRYPTO) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) 35 36 #if defined(__cplusplus) 37 extern "C" { 38 #endif 39 40 #include "cy_crypto_core_hw.h" 41 42 /******************************************************************************/ 43 #define CY_CRYPTO_V1_SET_REG1_OPC (0x40u) 44 #define CY_CRYPTO_V1_SET_REG2_OPC (0x41u) 45 #define CY_CRYPTO_V1_SET_REG3_OPC (0x42u) 46 #define CY_CRYPTO_V1_SET_REG4_OPC (0x43u) 47 48 #define CY_CRYPTO_V1_AES_BLOCK_OPC (0x44u) 49 #define CY_CRYPTO_V1_AES_BLOCK_INV_OPC (0x45u) 50 #define CY_CRYPTO_V1_AES_KEY_OPC (0x46u) 51 #define CY_CRYPTO_V1_AES_KEY_INV_OPC (0x47u) 52 #define CY_CRYPTO_V1_AES_XOR_OPC (0x48u) 53 54 #define CY_CRYPTO_V1_SHA_OPC (0x4cu) 55 56 #define CY_CRYPTO_V1_STR_MEMCPY_OPC (0x50u) 57 #define CY_CRYPTO_V1_STR_MEMSET_OPC (0x51u) 58 #define CY_CRYPTO_V1_STR_MEMCMP_OPC (0x52u) 59 #define CY_CRYPTO_V1_STR_MEMXOR_OPC (0x53u) 60 61 #define CY_CRYPTO_V1_CRC_OPC (0x58u) 62 63 #define CY_CRYPTO_V1_PRNG_OPC (0x5cu) 64 65 #define CY_CRYPTO_V1_TRNG_OPC (0x60u) 66 67 #define CY_CRYPTO_V1_DES_BLOCK_OPC (0x70u) 68 #define CY_CRYPTO_V1_DES_BLOCK_INV_OPC (0x71u) 69 70 #define CY_CRYPTO_V1_TDES_BLOCK_OPC (0x72u) 71 #define CY_CRYPTO_V1_TDES_BLOCK_INV_OPC (0x73u) 72 73 #define CY_CRYPTO_V1_SYNC_OPC (0x7fu) 74 75 76 void Cy_Crypto_SetReg1Instr(CRYPTO_Type *base, uint32_t data0); 77 78 void Cy_Crypto_SetReg2Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1); 79 80 void Cy_Crypto_SetReg3Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, uint32_t data2); 81 82 void Cy_Crypto_SetReg4Instr(CRYPTO_Type *base, uint32_t data0, uint32_t data1, uint32_t data2, uint32_t data3); 83 84 void Cy_Crypto_Run0ParamInstr(CRYPTO_Type *base, uint8_t instr); 85 86 void Cy_Crypto_Run1ParamInstr(CRYPTO_Type *base, uint8_t instr, uint32_t rdst0Shift); 87 88 void Cy_Crypto_Run2ParamInstr(CRYPTO_Type *base, uint8_t instr, uint32_t rdst0Shift, uint32_t rdst1Shift); 89 90 void Cy_Crypto_Run3ParamInstr(CRYPTO_Type *base, uint8_t instr, 91 uint8_t rdst0Shift, uint8_t rdst1Shift, uint8_t rdst2Shift); 92 93 void Cy_Crypto_Run4ParamInstr(CRYPTO_Type *base, uint8_t instr, 94 uint32_t rdst0Shift, uint32_t rdst1Shift, uint32_t rdst2Shift, uint32_t rdst3Shift); 95 96 97 #if defined(__cplusplus) 98 } 99 #endif 100 101 #endif /* defined(CY_IP_MXCRYPTO) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) */ 102 103 #endif /* #if !defined (CY_CRYPTO_CORE_HW_V1_H) */ 104 105 106 /* [] END OF FILE */ 107
