1 /***************************************************************************//** 2 * \file cy_crypto_common.h 3 * \version 2.120 4 * 5 * \brief 6 * This file provides common constants and parameters 7 * for the Crypto driver. 8 * 9 ******************************************************************************** 10 * \copyright 11 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or 12 * an affiliate of Cypress Semiconductor Corporation. 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 29 #if !defined (CY_CRYPTO_COMMON_H) 30 #define CY_CRYPTO_COMMON_H 31 32 #include "cy_device.h" 33 #include "cy_device_headers.h" 34 35 #if defined (CY_IP_MXCRYPTO) 36 37 #include "cy_crypto_config.h" 38 #include "cy_syslib.h" 39 40 #if defined(__cplusplus) 41 extern "C" { 42 #endif 43 44 #include <stddef.h> 45 #include <stdbool.h> 46 #include "cy_sysint.h" 47 48 /** Driver major version */ 49 #define CY_CRYPTO_DRV_VERSION_MAJOR 2 50 51 /** Driver minor version */ 52 #define CY_CRYPTO_DRV_VERSION_MINOR 120 53 54 55 /** Rounds off value to nearest multiple of 32 */ 56 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 57 #define CY_CRYPTO_ALIGN_CACHE_LINE(x) ((uint32_t)(((x) + 31) & ~31)) 58 #else 59 #define CY_CRYPTO_ALIGN_CACHE_LINE(x) ((uint32_t)x) 60 #endif 61 62 63 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 64 #define CRYPTO_MEM_ALIGN CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 65 #else 66 #define CRYPTO_MEM_ALIGN 67 #endif 68 69 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 70 #define CRYPTO_MEM_ALIGN_4 CRYPTO_MEM_ALIGN 71 #else 72 #define CRYPTO_MEM_ALIGN_4 CY_ALIGN(4) 73 #endif 74 75 /* Enable SHA functionality */ 76 #if !defined(CPUSS_CRYPTO_SHA) && (defined(CPUSS_CRYPTO_SHA1) || defined(CPUSS_CRYPTO_SHA2)) 77 #define CPUSS_CRYPTO_SHA (1) 78 79 #if defined(CPUSS_CRYPTO_SHA2) && !defined(CPUSS_CRYPTO_SHA256) 80 #define CPUSS_CRYPTO_SHA256 (1) 81 #endif 82 83 #if defined(CPUSS_CRYPTO_SHA2) && !defined(CPUSS_CRYPTO_SHA512) 84 #define CPUSS_CRYPTO_SHA512 (1) 85 #endif 86 #endif 87 88 #if !defined(CPUSS_CRYPTO_STR) 89 #define CPUSS_CRYPTO_STR (1) 90 #endif 91 92 #if !defined(CPUSS_CRYPTO_CHACHA) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) 93 #define CPUSS_CRYPTO_CHACHA (0) 94 #endif 95 96 #if !defined(CPUSS_CRYPTO_GCM) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) 97 #define CPUSS_CRYPTO_GCM (0) 98 #endif 99 100 #if !defined(CPUSS_CRYPTO_SHA3) && defined(CY_CRYPTO_CFG_HW_V1_ENABLE) 101 #define CPUSS_CRYPTO_SHA3 (0) 102 #endif 103 104 /** \cond INTERNAL */ 105 106 /* The width of the Crypto hardware registers values in bits. */ 107 #define CY_CRYPTO_HW_REGS_WIDTH (32UL) 108 109 /* Calculates the actual size in bytes of the bits value */ 110 #define CY_CRYPTO_BYTE_SIZE_OF_BITS(x) (uint32_t)(((uint32_t)(x) + 7U) >> 3U) 111 112 /* Calculates the actual size in 32-bit words of the bits value */ 113 #define CY_CRYPTO_WORD_SIZE_OF_BITS(x) (uint32_t)(((uint32_t)(x) + 31U) >> 5U) 114 115 /** \endcond */ 116 117 /** 118 * \addtogroup group_crypto_cli_srv_macros 119 * \{ 120 */ 121 122 /** Defines Crypto_Sync blocking execution type parameter */ 123 #define CY_CRYPTO_SYNC_BLOCKING (true) 124 125 /** Defines Crypto_Sync non-blocking execution type parameter */ 126 #define CY_CRYPTO_SYNC_NON_BLOCKING (false) 127 128 /** Defines the Crypto DES block size (in bytes). */ 129 #define CY_CRYPTO_DES_BLOCK_SIZE (8u) 130 131 /** Defines the Crypto DES key size (in bytes) */ 132 #define CY_CRYPTO_DES_KEY_SIZE (CY_CRYPTO_DES_BLOCK_SIZE) 133 134 /** Defines the Crypto TDES key size (in bytes) */ 135 #define CY_CRYPTO_TDES_KEY_SIZE (24u) 136 137 138 #if defined(CY_CRYPTO_CFG_AES_C) 139 140 /** Defines the Crypto AES block size (in bytes) */ 141 #define CY_CRYPTO_AES_BLOCK_SIZE (16u) 142 143 /** Defines the Crypto AES_128 key maximum size (in bytes) */ 144 #define CY_CRYPTO_AES_128_KEY_SIZE (16u) 145 146 /** Defines the Crypto AES_192 key maximum size (in bytes) */ 147 #define CY_CRYPTO_AES_192_KEY_SIZE (24u) 148 149 /** Defines the Crypto AES_256 key maximum size (in bytes) */ 150 #define CY_CRYPTO_AES_256_KEY_SIZE (32u) 151 152 /** Defines the Crypto AES key maximum size (in bytes) */ 153 #define CY_CRYPTO_AES_MAX_KEY_SIZE (CY_CRYPTO_AES_256_KEY_SIZE) 154 155 /** Defines the Crypto AES_256 key maximum size (in four-byte words) */ 156 #define CY_CRYPTO_AES_MAX_KEY_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_MAX_KEY_SIZE / 4UL) 157 158 /** Defines size of the AES block, in four-byte words */ 159 #define CY_CRYPTO_AES_BLOCK_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE / 4UL) 160 161 /** Defines the Crypto AES GCM IV size (in bytes) */ 162 #define CY_CRYPTO_AES_GCM_IV_SIZE (12u) 163 164 #endif /* defined(CY_CRYPTO_CFG_AES_C) */ 165 166 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 167 168 /* Defines for the SHA algorithm */ 169 /** Block size for the SHA256 mode (in bytes) */ 170 #define CY_CRYPTO_SHA256_BLOCK_SIZE (64u) 171 /** Pad size for the SHA256 mode (in bytes) */ 172 #define CY_CRYPTO_SHA256_PAD_SIZE (56uL) 173 174 /** Block size for the SHA512 mode (in bytes) */ 175 #define CY_CRYPTO_SHA512_BLOCK_SIZE (128u) 176 /** Pad size for the SHA512 mode (in bytes) */ 177 #define CY_CRYPTO_SHA512_PAD_SIZE (112uL) 178 179 #if defined(CY_CRYPTO_CFG_SHA3_ENABLED) 180 /** SHA3 state size for the SHA modes (in bytes) */ 181 #define CY_CRYPTO_SHA3_STATE_SIZE (200u) 182 /** Block size for the SHA224 mode (in bytes) */ 183 #define CY_CRYPTO_SHA3_224_BLOCK_SIZE (144u) 184 /** Block size for the SHA256 mode (in bytes) */ 185 #define CY_CRYPTO_SHA3_256_BLOCK_SIZE (136u) 186 /** Block size for the SHA384 mode (in bytes) */ 187 #define CY_CRYPTO_SHA3_384_BLOCK_SIZE (104u) 188 /** Block size for the SHA512 mode (in bytes) */ 189 #define CY_CRYPTO_SHA3_512_BLOCK_SIZE (72u) 190 /** SHA3 maximum digest size (in bytes) */ 191 #define CY_CRYPTO_SHA3_MAX_DIGEST_SIZE (64u) 192 #endif 193 194 /** \cond INTERNAL */ 195 #define CY_REMAP_ADDRESS_FOR_CRYPTO(addr) (CY_REMAP_ADDRESS_CBUS_TO_SAHB(addr)) 196 /** \endcond */ 197 198 /** Pad size for the SHA256 mode (in bytes) */ 199 #define CY_CRYPTO_SHA256_PAD_SIZE (56uL) 200 /** Pad size for the SHA512 mode (in bytes) */ 201 #define CY_CRYPTO_SHA512_PAD_SIZE (112uL) 202 203 #if defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 204 /** Hash size for the SHA384 mode (in bytes) */ 205 #define CY_CRYPTO_SHA384_DIGEST_SIZE (48u) 206 /** Hash size for the SHA512 mode (in bytes) */ 207 #define CY_CRYPTO_SHA512_DIGEST_SIZE (64u) 208 /** Hash size for the SHA512_224 mode (in bytes) */ 209 #define CY_CRYPTO_SHA512_224_DIGEST_SIZE (28u) 210 /** Hash size for the SHA512_256 mode (in bytes) */ 211 #define CY_CRYPTO_SHA512_256_DIGEST_SIZE (32u) 212 213 /** \cond INTERNAL */ 214 /** Internal hash size for the SHA512_256 mode (in bytes) */ 215 #define CY_CRYPTO_SHA512_HASH_SIZE (64u) 216 /** Internal round mem size for the SHA512_256 mode (in bytes) */ 217 #define CY_CRYPTO_SHA512_ROUND_MEM_SIZE (640uL) 218 /** \endcond */ 219 #endif 220 #if defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 221 /** Hash size for the SHA224 mode (in bytes) */ 222 #define CY_CRYPTO_SHA224_DIGEST_SIZE (28u) 223 /** Hash size for the SHA256 mode (in bytes) */ 224 #define CY_CRYPTO_SHA256_DIGEST_SIZE (32u) 225 226 /** \cond INTERNAL */ 227 /** Internal hash size for the SHA256 mode (in bytes) */ 228 #define CY_CRYPTO_SHA256_HASH_SIZE (32u) 229 /** Internal round mem size for the SHA256 mode (in bytes) */ 230 #define CY_CRYPTO_SHA256_ROUND_MEM_SIZE (256uL) 231 /** \endcond */ 232 #endif 233 #if defined(CY_CRYPTO_CFG_SHA1_ENABLED) 234 /** Hash size for the SHA1 mode (in bytes) */ 235 #define CY_CRYPTO_SHA1_DIGEST_SIZE (20u) 236 /** Block size for the SHA1 mode (in bytes) */ 237 #define CY_CRYPTO_SHA1_BLOCK_SIZE (64u) 238 239 /** \cond INTERNAL */ 240 /** Internal hash size for the SHA1 mode (in bytes) */ 241 #define CY_CRYPTO_SHA1_HASH_SIZE (20u) 242 /** Internal round mem size for the SHA1 mode (in bytes) */ 243 #define CY_CRYPTO_SHA1_ROUND_MEM_SIZE (320uL) 244 /** \endcond */ 245 #endif 246 247 /** \cond INTERNAL */ 248 #if defined(CY_CRYPTO_CFG_SHA3_ENABLED) 249 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA3_MAX_DIGEST_SIZE) 250 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA3_STATE_SIZE) 251 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA3_STATE_SIZE) 252 #elif defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 253 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA512_DIGEST_SIZE) 254 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA512_BLOCK_SIZE) 255 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA512_HASH_SIZE) 256 #elif defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 257 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA256_DIGEST_SIZE) 258 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA256_BLOCK_SIZE) 259 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA256_HASH_SIZE) 260 #elif defined(CY_CRYPTO_CFG_SHA1_ENABLED) 261 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (CY_CRYPTO_SHA1_DIGEST_SIZE) 262 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (CY_CRYPTO_SHA1_BLOCK_SIZE) 263 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (CY_CRYPTO_SHA1_HASH_SIZE) 264 #else 265 #define CY_CRYPTO_SHA_MAX_DIGEST_SIZE (0u) 266 #define CY_CRYPTO_SHA_MAX_BLOCK_SIZE (0u) 267 #define CY_CRYPTO_SHA_MAX_HASH_SIZE (0u) 268 #endif 269 270 #if defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 271 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA512_ROUND_MEM_SIZE) 272 #elif defined(CY_CRYPTO_CFG_SHA1_ENABLED) 273 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA1_ROUND_MEM_SIZE) 274 #elif defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 275 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (CY_CRYPTO_SHA256_ROUND_MEM_SIZE) 276 #else 277 #define CY_CRYPTO_SHA_MAX_ROUND_MEM_SIZE (0u) 278 #endif 279 /** \endcond */ 280 281 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 282 283 284 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) 285 286 /** \cond INTERNAL */ 287 /** Processed message size for the RSA 1024Bit mode (in bytes) */ 288 #define CY_CRYPTO_RSA1024_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(1024u) 289 /** Processed message size for the RSA 1536Bit mode (in bytes) */ 290 #define CY_CRYPTO_RSA1536_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(1536u) 291 /** Processed message size for the RSA 2048Bit mode (in bytes) */ 292 #define CY_CRYPTO_RSA2048_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(2048u) 293 /** Processed message size for the RSA 3072Bit mode (in bytes) */ 294 #define CY_CRYPTO_RSA3072_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(3072u) 295 /** Processed message size for the RSA 4096Bit mode (in bytes) */ 296 #define CY_CRYPTO_RSA4096_MESSAGE_SIZE CY_CRYPTO_BYTE_SIZE_OF_BITS(4096u) 297 /** \endcond */ 298 299 /** 300 * \addtogroup group_crypto_data_structures 301 * \{ 302 */ 303 304 /** 305 * All fields for the context structure are internal. Firmware never reads or 306 * writes these values. Firmware allocates the structure and provides the 307 * address of the structure to the driver in the function calls. Firmware must 308 * ensure that the defined instance of this structure remains in scope 309 * while the drive is in use. 310 * 311 * The driver uses this structure to store and manipulate the RSA public key and 312 * additional coefficients to accelerate RSA calculation. 313 * 314 * RSA key contained from two fields: 315 * - n - modulus part of the key 316 * - e - exponent part of the key. 317 * 318 * Other fields are accelerating coefficients and can be calculated by 319 * \ref Cy_Crypto_Rsa_CalcCoefs. 320 * 321 * \note The <b>modulus</b> and <b>exponent</b> values in the 322 * \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.<br> 323 * Use \ref Cy_Crypto_InvertEndianness function to convert to or from 324 * little-endian order. 325 */ 326 typedef struct 327 { 328 /** \cond INTERNAL */ 329 /** The pointer to the modulus part of public key. */ 330 uint8_t *moduloPtr; 331 /** The modulus length, in bits, maximum supported size is 2048Bit */ 332 uint32_t moduloLength; 333 334 /** The pointer to the exponent part of public key */ 335 uint8_t *pubExpPtr; 336 /** The exponent length, in bits, maximum supported size is 256Bit */ 337 uint32_t pubExpLength; 338 339 /** The pointer to the Barrett coefficient. Memory for it should be 340 allocated by user with size moduloLength + 1. */ 341 uint8_t *barretCoefPtr; 342 343 /** The pointer to the binary inverse of the modulo. Memory for it 344 should be allocated by user with size moduloLength. */ 345 uint8_t *inverseModuloPtr; 346 347 /** The pointer to the (2^moduloLength mod modulo). Memory for it should 348 be allocated by user with size moduloLength */ 349 uint8_t *rBarPtr; 350 /** \endcond */ 351 } cy_stc_crypto_rsa_pub_key_t; 352 353 /** \} group_crypto_data_structures */ 354 355 #endif /* (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) */ 356 357 /** Crypto Driver PDL ID */ 358 #define CY_CRYPTO_ID CY_PDL_DRV_ID(0x0Cu) 359 360 /** \} group_crypto_cli_srv_macros */ 361 362 /** 363 * \addtogroup group_crypto_config_structure 364 * \{ 365 The Crypto initialization configuration. 366 * \note Should be the same for the Crypto Server and Crypto Client initialization. 367 */ 368 369 /** The Crypto user callback function type. 370 Callback is called at the end of Crypto calculation. */ 371 typedef void (*cy_crypto_callback_ptr_t)(void); 372 373 /** The Crypto configuration structure. */ 374 typedef struct 375 { 376 /** Defines the IPC channel used for client-server data exchange */ 377 uint32_t ipcChannel; 378 379 /** Specifies the IPC notifier channel (IPC interrupt structure number) 380 to notify server that data for the operation is prepared */ 381 uint32_t acquireNotifierChannel; 382 383 /** Specifies the IPC notifier channel (IPC interrupt structure number) 384 to notify client that operation is complete and data is valid */ 385 uint32_t releaseNotifierChannel; 386 387 /** Specifies the release notifier interrupt configuration. It used for 388 internal purposes and user doesn't fill it. */ 389 cy_stc_sysint_t releaseNotifierConfig; 390 391 /** User callback function. 392 If this field is NOT NULL, it called when Crypto operation 393 is complete. */ 394 cy_crypto_callback_ptr_t userCompleteCallback; 395 396 /** Server-side user IRQ handler function, called when data for the 397 operation is prepared to process. 398 - If this field is NULL, server will use own interrupt handler 399 to get data. 400 - If this field is not NULL, server will call this interrupt handler. 401 This interrupt handler must call the 402 \ref Cy_Crypto_Server_GetDataHandler to get data to process. 403 404 Note: In the second case user should process data separately and 405 clear interrupt by calling \ref Cy_Crypto_Server_Process. 406 This model is used in the 407 multitasking environment. */ 408 cy_israddress userGetDataHandler; 409 410 /** Server-side user IRQ handler function, called when a Crypto hardware 411 error occurs (interrupt was raised). 412 - If this field is NULL - server will use own interrupt handler 413 for error processing. 414 - If this field is not NULL - server will call this interrupt handler. 415 This interrupt handler must call the 416 \ref Cy_Crypto_Server_ErrorHandler to clear the interrupt. */ 417 cy_israddress userErrorHandler; 418 419 /** Specifies the prepared data notifier interrupt configuration. It used 420 for internal purposes and user doesn't fill it. */ 421 cy_stc_sysint_t acquireNotifierConfig; 422 423 /** Specifies the hardware error processing interrupt configuration. It used 424 for internal purposes and user doesn't fill it. */ 425 cy_stc_sysint_t cryptoErrorIntrConfig; 426 427 } cy_stc_crypto_config_t; 428 429 /** \} group_crypto_config_structure */ 430 431 /** 432 * \addtogroup group_crypto_cli_data_structures 433 * \{ 434 */ 435 436 /** Structure for storing a description of a Crypto hardware error */ 437 typedef struct 438 { 439 /** 440 Captures error description information for one of obtained hardware error: 441 - for <b>INSTR_OPC_ERROR</b>: - violating the instruction. 442 - for <b>INSTR_CC_ERROR</b> : - violating the instruction condition code. 443 - for <b>BUS_ERROR</b> : - violating the transfer address. */ 444 uint32_t errorStatus0; 445 446 /** 447 [31] - "1" - Indicates that hardware error has occurred and 448 ERROR_STATUS0 and ERROR_STATUS1 captured valid error-information. 449 [26..24] - The error source: 450 - "0": <b>INSTR_OPC_ERROR</b> - an instruction decoder error. 451 - "1": <b>INSTR_CC_ERROR</b> - an instruction condition code-error. 452 - "2": <b>BUS_ERROR</b> - a bus master interface AHB-Lite bus-error. 453 - [5..4] - violating the transfer, the size attribute 454 - "0": an 8-bit transfer; 455 - "1": 16 bits transfer; 456 - "2": 32-bit transfer. 457 - [0] - violating the transfer, read the attribute 458 - "3": <b>TR_AP_DETECT_ERROR</b> - True Random Generator error. 459 */ 460 uint32_t errorStatus1; 461 } cy_stc_crypto_hw_error_t; 462 463 /** \} group_crypto_cli_data_structures */ 464 465 466 /** The Crypto library functionality level. */ 467 typedef enum 468 { 469 CY_CRYPTO_NO_LIBRARY = 0x00u, 470 CY_CRYPTO_BASE_LIBRARY = 0x01u, 471 CY_CRYPTO_EXTRA_LIBRARY = 0x02u, 472 CY_CRYPTO_FULL_LIBRARY = 0x03u, 473 } cy_en_crypto_lib_info_t; 474 475 476 /** 477 * \addtogroup group_crypto_enums 478 * \{ 479 */ 480 481 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 482 /** The key length options for the AES method. */ 483 typedef enum 484 { 485 CY_CRYPTO_KEY_AES_128 = 0x00u, /**< The AES key size is 128 bits */ 486 CY_CRYPTO_KEY_AES_192 = 0x01u, /**< The AES key size is 192 bits */ 487 CY_CRYPTO_KEY_AES_256 = 0x02u /**< The AES key size is 256 bits */ 488 } cy_en_crypto_aes_key_length_t; 489 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 490 491 /** Defines the direction of the Crypto methods */ 492 typedef enum 493 { 494 /** The forward mode, plain text will be encrypted into cipher text */ 495 CY_CRYPTO_ENCRYPT = 0x00u, 496 /** The reverse mode, cipher text will be decrypted into plain text */ 497 CY_CRYPTO_DECRYPT = 0x01u 498 } cy_en_crypto_dir_mode_t; 499 500 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 501 /** Defines modes of SHA method */ 502 typedef enum 503 { 504 #if (CPUSS_CRYPTO_SHA1 == 1) && defined(CY_CRYPTO_CFG_SHA1_ENABLED) 505 CY_CRYPTO_MODE_SHA1 = 0x00u, /**< Sets the SHA1 mode */ 506 #endif /* (CPUSS_CRYPTO_SHA1 == 1) && defined(CY_CRYPTO_CFG_SHA1_ENABLED) */ 507 508 #if (CPUSS_CRYPTO_SHA256 == 1) && defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) 509 CY_CRYPTO_MODE_SHA224 = 0x01u, /**< Sets the SHA224 mode */ 510 CY_CRYPTO_MODE_SHA256 = 0x02u, /**< Sets the SHA256 mode */ 511 #endif /* (CPUSS_CRYPTO_SHA256 == 1) && defined(CY_CRYPTO_CFG_SHA2_256_ENABLED) */ 512 513 #if (CPUSS_CRYPTO_SHA512 == 1) && defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) 514 CY_CRYPTO_MODE_SHA384 = 0x03u, /**< Sets the SHA384 mode */ 515 CY_CRYPTO_MODE_SHA512 = 0x04u, /**< Sets the SHA512 mode */ 516 CY_CRYPTO_MODE_SHA512_256 = 0x05u, /**< Sets the SHA512/256 mode */ 517 CY_CRYPTO_MODE_SHA512_224 = 0x06u, /**< Sets the SHA512/224 mode */ 518 #endif /* (CPUSS_CRYPTO_SHA512 == 1) && defined(CY_CRYPTO_CFG_SHA2_512_ENABLED) */ 519 CY_CRYPTO_MODE_SHA_NONE = 0x07u, /**< Sets the SHA None mode */ 520 521 #if (CPUSS_CRYPTO_SHA3 == 1) && defined(CY_CRYPTO_CFG_SHA3_ENABLED) 522 CY_CRYPTO_MODE_SHA3_224 = 0x07u, /**< Sets the SHA3-224 mode */ 523 CY_CRYPTO_MODE_SHA3_256 = 0x08u, /**< Sets the SHA3-256 mode */ 524 CY_CRYPTO_MODE_SHA3_384 = 0x09u, /**< Sets the SHA3-384 mode */ 525 CY_CRYPTO_MODE_SHA3_512 = 0x0Au, /**< Sets the SHA3-512 mode */ 526 #endif /* (CPUSS_CRYPTO_SHA3 == 1) */ 527 528 529 } cy_en_crypto_sha_mode_t; 530 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 531 532 #if defined(CY_CRYPTO_CFG_RSA_C) && defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) 533 /** Signature verification status */ 534 typedef enum 535 { 536 CY_CRYPTO_RSA_VERIFY_SUCCESS = 0x00u, /**< PKCS1-v1.5 verify SUCCESS */ 537 CY_CRYPTO_RSA_VERIFY_FAIL = 0x01u /**< PKCS1-v1.5 verify FAILED */ 538 } cy_en_crypto_rsa_ver_result_t; 539 #endif /* defined(CY_CRYPTO_CFG_RSA_C) && defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) */ 540 541 /** Errors of the Crypto block */ 542 typedef enum 543 { 544 /** Operation completed successfully. */ 545 CY_CRYPTO_SUCCESS = 0x00u, 546 547 /** A hardware error occurred, detailed information is in stc_crypto_hw_error_t. */ 548 CY_CRYPTO_HW_ERROR = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x01u, 549 550 /** The size of input data is not multiple of 16. */ 551 CY_CRYPTO_SIZE_NOT_X16 = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x02u, 552 553 /** The key for the DES method is weak. */ 554 CY_CRYPTO_DES_WEAK_KEY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x03u, 555 556 /** Communication between the client and server via IPC is broken. */ 557 CY_CRYPTO_COMM_FAIL = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x04u, 558 559 /** The Crypto server is not started. */ 560 CY_CRYPTO_SERVER_NOT_STARTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x06u, 561 562 /** The Crypto server in process state. */ 563 CY_CRYPTO_SERVER_BUSY = CY_CRYPTO_ID | CY_PDL_STATUS_INFO | 0x07u, 564 565 /** The Crypto driver is not initialized. */ 566 CY_CRYPTO_NOT_INITIALIZED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x08u, 567 568 /** The Crypto hardware is not enabled. */ 569 CY_CRYPTO_HW_NOT_ENABLED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x09u, 570 571 /** The Crypto operation is not supported. */ 572 CY_CRYPTO_NOT_SUPPORTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Au, 573 574 /** The Crypto operation parameters are incorrect. */ 575 CY_CRYPTO_BAD_PARAMS = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Bu, 576 577 /** TRNG generated is not a healthy random number. */ 578 CY_CRYPTO_TRNG_UNHEALTHY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x0Cu, 579 580 /** Memory allocation for Crypto operation failed. */ 581 CY_CRYPTO_MEMORY_ALLOC_FAIL = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Du 582 583 } cy_en_crypto_status_t; 584 585 /** 586 * EDDSA signature operation type. 587 * 588 * It identifies the signature operation type (pure, ctx or prehash). 589 */ 590 typedef enum cy_en_eddsa_sig_type_t 591 { 592 CY_CRYPTO_EDDSA_PURE = 0, /*!< Pure - uses the entire message, without hashing it previously. */ 593 CY_CRYPTO_EDDSA_CTX, /*!< Deterministic context - uses the entire message, without hashing it previously. */ 594 CY_CRYPTO_EDDSA_PREHASH, /*!< Pre-hashed message - uses the already hashed message. */ 595 CY_CRYPTO_EDDSA_NONE /*!< None - not a valid choice. */ 596 } cy_en_eddsa_sig_type_t; 597 598 599 /** \} group_crypto_enums */ 600 601 /** 602 * \addtogroup group_crypto_lld_asymmetric_enums 603 * \{ 604 */ 605 606 #if (CPUSS_CRYPTO_VU == 1) && defined (CY_CRYPTO_CFG_ECP_C) 607 /** List of supported elliptic curve IDs */ 608 typedef enum { 609 CY_CRYPTO_ECC_ECP_NONE = 0, 610 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP192R1_ENABLED) 611 CY_CRYPTO_ECC_ECP_SECP192R1, 612 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP192R1_ENABLED) */ 613 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP224R1_ENABLED) 614 CY_CRYPTO_ECC_ECP_SECP224R1, 615 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP224R1_ENABLED) */ 616 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP256R1_ENABLED) 617 CY_CRYPTO_ECC_ECP_SECP256R1, 618 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP256R1_ENABLED) */ 619 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP384R1_ENABLED) 620 CY_CRYPTO_ECC_ECP_SECP384R1, 621 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP384R1_ENABLED) */ 622 #if defined(CY_CRYPTO_CFG_ECP_DP_SECP521R1_ENABLED) 623 CY_CRYPTO_ECC_ECP_SECP521R1, 624 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_SECP521R1_ENABLED) */ 625 #if defined(CY_CRYPTO_CFG_ECP_DP_ED25519_ENABLED) 626 CY_CRYPTO_ECC_ECP_ED25519, 627 #endif /* defined(CY_CRYPTO_CFG_ECP_DP_ED25519_ENABLED) */ 628 /* Count of supported curves */ 629 CY_CRYPTO_ECC_ECP_CURVES_CNT 630 } cy_en_crypto_ecc_curve_id_t; 631 632 #endif /* (CPUSS_CRYPTO_VU == 1) && defined (CY_CRYPTO_CFG_ECP_C) */ 633 634 /** \} group_crypto_lld_asymmetric_enums */ 635 636 /** \cond INTERNAL */ 637 638 /** Instruction to communicate between Client and Server */ 639 typedef enum 640 { 641 CY_CRYPTO_INSTR_UNKNOWN = 0x00u, 642 CY_CRYPTO_INSTR_ENABLE = 0x01u, 643 CY_CRYPTO_INSTR_DISABLE = 0x02u, 644 645 #if (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) 646 CY_CRYPTO_INSTR_PRNG_INIT = 0x03u, 647 CY_CRYPTO_INSTR_PRNG = 0x04u, 648 #endif /* (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) */ 649 650 #if (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) 651 CY_CRYPTO_INSTR_TRNG_INIT = 0x05u, 652 CY_CRYPTO_INSTR_TRNG = 0x06u, 653 #endif /* (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) */ 654 655 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 656 CY_CRYPTO_INSTR_AES_INIT = 0x07u, 657 CY_CRYPTO_INSTR_AES_ECB = 0x08u, 658 659 #if defined(CY_CRYPTO_CFG_CIPHER_MODE_CBC) 660 CY_CRYPTO_INSTR_AES_CBC = 0x09u, 661 #endif /* defined(CY_CRYPTO_CFG_CIPHER_MODE_CBC) */ 662 #if defined(CY_CRYPTO_CFG_CIPHER_MODE_CFB) 663 CY_CRYPTO_INSTR_AES_CFB = 0x0Au, 664 #endif /* defined(CY_CRYPTO_CFG_CIPHER_MODE_CFB) */ 665 #if defined(CY_CRYPTO_CFG_CIPHER_MODE_CTR) 666 CY_CRYPTO_INSTR_AES_CTR = 0x0Bu, 667 #endif /* defined(CY_CRYPTO_CFG_CIPHER_MODE_CTR) */ 668 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 669 670 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_CMAC_C) 671 CY_CRYPTO_INSTR_CMAC = 0x0Cu, 672 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_CMAC_C) */ 673 674 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 675 CY_CRYPTO_INSTR_SHA = 0x0Du, 676 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 677 678 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) 679 CY_CRYPTO_INSTR_HMAC = 0x0Eu, 680 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) */ 681 682 #if (CPUSS_CRYPTO_STR == 1) 683 CY_CRYPTO_INSTR_MEM_CPY = 0x0Fu, 684 CY_CRYPTO_INSTR_MEM_SET = 0x10u, 685 CY_CRYPTO_INSTR_MEM_CMP = 0x11u, 686 CY_CRYPTO_INSTR_MEM_XOR = 0x12u, 687 #endif /* (CPUSS_CRYPTO_STR == 1) */ 688 689 #if (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) 690 CY_CRYPTO_INSTR_CRC_INIT = 0x13u, 691 CY_CRYPTO_INSTR_CRC = 0x14u, 692 #endif /* (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) */ 693 694 #if (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) 695 CY_CRYPTO_INSTR_DES = 0x15u, 696 CY_CRYPTO_INSTR_3DES = 0x16u, 697 #endif /* (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) */ 698 699 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) 700 CY_CRYPTO_INSTR_RSA_PROC = 0x17u, 701 CY_CRYPTO_INSTR_RSA_COEF = 0x18u, 702 703 #if defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) 704 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 705 CY_CRYPTO_INSTR_RSA_VER = 0x19u, 706 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 707 #endif /* defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) */ 708 709 #endif /* (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_RSA_C) */ 710 711 CY_CRYPTO_INSTR_SRV_INFO = 0x55u, 712 713 #if (CPUSS_CRYPTO_VU == 1) 714 #if defined(CY_CRYPTO_CFG_RSA_C) 715 CY_CRYPTO_INSTR_MEMBUF_SET = 0x56u, 716 CY_CRYPTO_INSTR_MEMBUF_ADDR = 0x57u, 717 CY_CRYPTO_INSTR_MEMBUF_SIZE = 0x58u, 718 #endif /* defined(CY_CRYPTO_CFG_RSA_C) */ 719 720 #if defined(CY_CRYPTO_CFG_ECP_C) 721 CY_CRYPTO_INSTR_ECC_GET_DP = 0x59u, 722 CY_CRYPTO_INSTR_ECC_ECP_MUL = 0x5Au, 723 #endif /* defined(CY_CRYPTO_CFG_ECP_C) */ 724 725 #if defined(CY_CRYPTO_CFG_ECDSA_GENKEY_C) 726 CY_CRYPTO_INSTR_ECP_GEN_PRIK = 0x5Bu, 727 CY_CRYPTO_INSTR_ECP_GEN_PUBK = 0x5Cu, 728 #endif /* defined(CY_CRYPTO_CFG_ECDSA_GENKEY_C) */ 729 730 #if defined(CY_CRYPTO_CFG_ECDSA_SIGN_C) 731 CY_CRYPTO_INSTR_ECDSA_SIGN = 0x5Du, 732 #endif /* defined(CY_CRYPTO_CFG_ECDSA_SIGN_C) */ 733 734 #if defined(CY_CRYPTO_CFG_ECDSA_VERIFY_C) 735 CY_CRYPTO_INSTR_ECDSA_VER = 0x5Eu 736 #endif /* defined(CY_CRYPTO_CFG_ECDSA_VERIFY_C) */ 737 #endif /* (CPUSS_CRYPTO_VU == 1) */ 738 739 } cy_en_crypto_comm_instr_t; 740 741 /** \endcond */ 742 743 /** 744 * \addtogroup group_crypto_data_structures 745 * \{ 746 */ 747 748 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 749 750 /** The structure for storing the AES state. 751 * All fields for this structure are internal. Firmware never reads or 752 * writes these values. Firmware allocates the structure and provides the 753 * address of the structure to the driver in the function calls. Firmware must 754 * ensure that the defined instance of this structure remains in scope 755 * while the drive is in use. 756 */ 757 758 /* The structure to define used memory buffers */ 759 760 CRYPTO_MEM_ALIGN typedef struct 761 { 762 /** \cond INTERNAL */ 763 CRYPTO_MEM_ALIGN uint32_t key[CY_CRYPTO_AES_MAX_KEY_SIZE_U32]; 764 CRYPTO_MEM_ALIGN uint32_t keyInv[CY_CRYPTO_AES_MAX_KEY_SIZE_U32]; 765 CRYPTO_MEM_ALIGN uint32_t block0[CY_CRYPTO_AES_BLOCK_SIZE_U32]; 766 CRYPTO_MEM_ALIGN uint32_t block1[CY_CRYPTO_AES_BLOCK_SIZE_U32]; 767 CRYPTO_MEM_ALIGN uint32_t block2[CY_CRYPTO_AES_BLOCK_SIZE_U32]; 768 CRYPTO_MEM_ALIGN uint8_t unProcessedData[CY_CRYPTO_AES_BLOCK_SIZE]; 769 CRYPTO_MEM_ALIGN uint8_t iv[CY_CRYPTO_AES_BLOCK_SIZE]; 770 CRYPTO_MEM_ALIGN uint8_t dummy[1]; 771 772 /** \endcond */ 773 } cy_stc_crypto_aes_buffers_t; 774 775 776 777 typedef struct 778 { 779 /** \cond INTERNAL */ 780 /** AES key length */ 781 cy_en_crypto_aes_key_length_t keyLength; 782 /** Pointer to AES work buffers */ 783 CRYPTO_MEM_ALIGN cy_stc_crypto_aes_buffers_t *buffers; 784 /** AES processed block index (for CMAC, SHA operations) */ 785 uint32_t blockIdx; 786 /** AES unprocessed message block*/ 787 uint32_t unProcessedBytes; 788 /** AES ivSize*/ 789 uint16_t ivSize; 790 /** AES mode*/ 791 cy_en_crypto_dir_mode_t dirMode; 792 /** \endcond */ 793 } cy_stc_crypto_aes_state_t; 794 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 795 796 797 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_CCM_C) 798 /** The structure for storing the AES CCM state. 799 * All fields for this structure are internal. Firmware never reads or 800 * writes these values. Firmware allocates the structure and provides the 801 * address of the structure to the driver in the function calls. Firmware must 802 * ensure that the defined instance of this structure remains in scope 803 * while the drive is in use. 804 */ 805 806 /* The structure to define used memory buffers */ 807 CRYPTO_MEM_ALIGN typedef struct 808 { 809 /** \cond INTERNAL */ 810 /** AES CBC MAC buffer */ 811 CRYPTO_MEM_ALIGN cy_stc_crypto_aes_buffers_t aesCbcMacBuffer; 812 /** AES CTR buffer */ 813 CRYPTO_MEM_ALIGN cy_stc_crypto_aes_buffers_t aesCtrBuffer; 814 /** temp buffer */ 815 CRYPTO_MEM_ALIGN_4 uint8_t temp_buffer[CY_CRYPTO_AES_BLOCK_SIZE]; 816 /** Counter buffer */ 817 CRYPTO_MEM_ALIGN uint8_t ctr[CY_CRYPTO_AES_BLOCK_SIZE]; 818 /** Y buffer */ 819 CRYPTO_MEM_ALIGN uint8_t y[CY_CRYPTO_AES_BLOCK_SIZE]; 820 /** Dummy */ 821 CRYPTO_MEM_ALIGN uint8_t dummy[1]; 822 /** \endcond */ 823 } cy_stc_crypto_aes_ccm_buffers_t; 824 825 typedef struct 826 { 827 /** \cond INTERNAL */ 828 /** AES state data */ 829 cy_en_crypto_dir_mode_t dirMode; 830 /** Pointer to AES work buffers */ 831 cy_stc_crypto_aes_state_t aesCbcMacState; 832 /** Operation data descriptors */ 833 cy_stc_crypto_aes_state_t aesCtrState; 834 /** pointer to temp buffer */ 835 uint8_t *temp; 836 /** pointer to ctr buffer */ 837 uint8_t *ctr; 838 /** pointer to y buffer */ 839 uint8_t *y; 840 /** Length field Size*/ 841 uint32_t L; 842 /** Total text size*/ 843 uint32_t textLength; 844 /** Total AAD size*/ 845 uint32_t aadLength; 846 /** Total tag size*/ 847 uint8_t tagLength; 848 /** AAD size processed*/ 849 uint32_t aadLengthProcessed; 850 /** AAD processed flag*/ 851 bool isAadProcessed; 852 /** IV set flag*/ 853 bool isIvSet; 854 /** Length Set flag*/ 855 bool isLengthSet; 856 /** \endcond */ 857 } cy_stc_crypto_aes_ccm_state_t; 858 #endif 859 860 #if (CPUSS_CRYPTO_GCM == 1u) && defined(CY_CRYPTO_CFG_GCM_C) 861 862 /** The structure for storing the AES GCM state. 863 * All fields for this structure are internal. Firmware never reads or 864 * writes these values. Firmware allocates the structure and provides the 865 * address of the structure to the driver in the function calls. Firmware must 866 * ensure that the defined instance of this structure remains in scope 867 * while the drive is in use. 868 */ 869 870 /* The structure to define used memory buffers */ 871 872 CRYPTO_MEM_ALIGN typedef struct 873 { 874 /** \cond INTERNAL */ 875 /** AES ECB buffer */ 876 cy_stc_crypto_aes_buffers_t aes_buffer; 877 /** AES GCM Hash Subkey */ 878 uint8_t h[CY_CRYPTO_AES_BLOCK_SIZE]; 879 /** AES GCM Initial Counter BLock*/ 880 uint8_t icb[CY_CRYPTO_AES_BLOCK_SIZE]; 881 /** AES GCM Counter Block */ 882 uint8_t cb[CY_CRYPTO_AES_BLOCK_SIZE]; 883 /** AES GCM Ghash buffer Block */ 884 CRYPTO_MEM_ALIGN uint8_t y[CY_CRYPTO_AES_BLOCK_SIZE]; 885 /** AES GCM temp buffer for AAD data */ 886 CRYPTO_MEM_ALIGN uint8_t temp[CY_CRYPTO_AES_BLOCK_SIZE]; 887 /** AES GCM aes data buffer*/ 888 CRYPTO_MEM_ALIGN uint8_t aes_data[CY_CRYPTO_AES_BLOCK_SIZE]; 889 /** Dummy */ 890 CRYPTO_MEM_ALIGN uint8_t dummy[1]; 891 /** \endcond */ 892 } cy_stc_crypto_aes_gcm_buffers_t; 893 894 CRYPTO_MEM_ALIGN typedef struct cy_stc_crypto_aes_gcm_state 895 { 896 /** \cond INTERNAL */ 897 /** AES GCM hash key pointer */ 898 uint8_t *h; 899 /**AES GCM Initial Counter block */ 900 uint8_t *icb; 901 /** AES GCM Counter block */ 902 uint8_t *cb; 903 /** Pointer to ghash buffer */ 904 uint8_t *y; 905 /** pointer to temp buffer*/ 906 uint8_t *temp; 907 /**Pointer to hold the last AES block*/ 908 uint8_t *aes_data; 909 /** AES GCM total data processed*/ 910 uint32_t data_size; 911 /** AES GCM total AAD data processed*/ 912 uint32_t aad_size; 913 /** AES GCM partial AAD data processed flag*/ 914 bool partial_aad_processed; 915 /**Mode of the AES GCM operation */ 916 cy_en_crypto_dir_mode_t mode; 917 /**Pointer to the AES buffer*/ 918 cy_stc_crypto_aes_buffers_t *aes_buffer; 919 /**AES state*/ 920 CRYPTO_MEM_ALIGN cy_stc_crypto_aes_state_t aesState; 921 /** Dummy */ 922 CRYPTO_MEM_ALIGN uint8_t dummy[1]; 923 /** \endcond */ 924 } cy_stc_crypto_aes_gcm_state_t; 925 926 #endif /* (CPUSS_CRYPTO_GCM == 1) && defined(CY_CRYPTO_CFG_GCM_C)*/ 927 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 928 929 /** The structure for storing the SHA state. 930 * All fields for the context structure are internal. Firmware never reads or 931 * writes these values. Firmware allocates the structure and provides the 932 * address of the structure to the driver in the function calls. Firmware must 933 * ensure that the defined instance of this structure remains in scope 934 * while the drive is in use. 935 */ 936 CRYPTO_MEM_ALIGN typedef struct 937 { 938 /** \cond INTERNAL */ 939 uint32_t mode; 940 uint32_t modeHw; 941 uint8_t *block; 942 uint32_t blockSize; 943 uint8_t *hash; 944 uint32_t hashSize; 945 uint8_t *roundMem; 946 uint32_t roundMemSize; 947 uint64_t messageSize; 948 uint32_t digestSize; 949 uint32_t blockIdx; 950 CRYPTO_MEM_ALIGN uint8_t const *initialHash; 951 /** Dummy */ 952 CRYPTO_MEM_ALIGN uint8_t dummy[1]; 953 /** \endcond */ 954 } cy_stc_crypto_sha_state_t; 955 956 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 957 958 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) 959 960 /** The structure for storing the HMAC state. 961 * All fields for the context structure are internal. Firmware never reads or 962 * writes these values. Firmware allocates the structure and provides the 963 * address of the structure to the driver in the function calls. Firmware must 964 * ensure that the defined instance of this structure remains in scope 965 * while the drive is in use. 966 */ 967 968 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 969 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 970 #endif 971 typedef struct 972 { 973 /** \cond INTERNAL */ 974 /* Pointer to store the ipad */ 975 uint8_t *ipad; 976 977 /* Pointer to store the opad */ 978 uint8_t *opad; 979 980 /* Pointer to store the key */ 981 uint8_t *m0Key; 982 983 /* Pointer to store the sha buffer */ 984 void* sha_buffer; 985 986 /* Hash state*/ 987 cy_stc_crypto_sha_state_t hashState; 988 /** \endcond */ 989 } cy_stc_crypto_hmac_state_t; 990 991 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_HMAC_C) */ 992 993 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_ECP_C) 994 /** A point on a ECC curve */ 995 typedef struct { 996 /** \cond INTERNAL */ 997 /** The x co-ordinate */ 998 void *x; 999 /** The y co-ordinate */ 1000 void *y; 1001 /** \endcond */ 1002 } cy_stc_crypto_ecc_point; 1003 1004 /** An ECC key type */ 1005 typedef enum cy_en_crypto_ecc_key_type { 1006 PK_PUBLIC = 0u, 1007 PK_PRIVATE = 1u 1008 } cy_en_crypto_ecc_key_type_t; 1009 1010 /** An ECC key */ 1011 typedef struct { 1012 /** \cond INTERNAL */ 1013 /** Type of key, PK_PRIVATE or PK_PUBLIC */ 1014 cy_en_crypto_ecc_key_type_t type; 1015 /** See \ref cy_en_crypto_ecc_curve_id_t */ 1016 cy_en_crypto_ecc_curve_id_t curveID; 1017 /** The public key */ 1018 cy_stc_crypto_ecc_point pubkey; 1019 /** The private key */ 1020 void *k; 1021 /** \endcond */ 1022 } cy_stc_crypto_ecc_key; 1023 #endif /* (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_ECP_C) */ 1024 1025 /** \} group_crypto_data_structures */ 1026 1027 /************************************************************* 1028 * Structures used for communication between Client and Server 1029 ***************************************************************/ 1030 1031 /** 1032 * \addtogroup group_crypto_srv_data_structures 1033 * \{ 1034 */ 1035 1036 /** The structure for storing the crypto server context. 1037 * All fields for the context structure are internal. Firmware never reads or 1038 * writes these values. Firmware allocates the structure and provides the 1039 * address of the structure to the driver in the function calls. Firmware must 1040 * ensure that the defined instance of this structure remains in scope 1041 * while the drive is in use. 1042 */ 1043 typedef struct 1044 { 1045 /** \cond INTERNAL */ 1046 /** IPC communication channel number */ 1047 uint32_t ipcChannel; 1048 /** IPC acquire interrupt channel number */ 1049 uint32_t acquireNotifierChannel; 1050 /** IPC release interrupt channel number */ 1051 cy_israddress getDataHandlerPtr; 1052 /** Crypto hardware errors interrupt handler */ 1053 cy_israddress errorHandlerPtr; 1054 /** Acquire notifier interrupt configuration */ 1055 cy_stc_sysint_t acquireNotifierConfig; 1056 /** Crypto hardware errors interrupt configuration */ 1057 cy_stc_sysint_t cryptoErrorIntrConfig; 1058 /** Hardware error occurrence flag */ 1059 bool isHwErrorOccured; 1060 /** Hardware processing errors */ 1061 cy_stc_crypto_hw_error_t hwErrorStatus; 1062 /** \endcond */ 1063 } cy_stc_crypto_server_context_t; 1064 1065 /** \} group_crypto_srv_data_structures */ 1066 1067 /** 1068 * \addtogroup group_crypto_cli_data_structures 1069 * \{ 1070 */ 1071 1072 /** The structure for storing the crypto client context. 1073 * All fields for the context structure are internal. Firmware never reads or 1074 * writes these values. Firmware allocates the structure and provides the 1075 * address of the structure to the driver in the function calls. Firmware must 1076 * ensure that the defined instance of this structure remains in scope 1077 * while the drive is in use. 1078 */ 1079 #if (CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE) 1080 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) typedef struct 1081 #else 1082 typedef struct 1083 #endif 1084 { 1085 /** \cond INTERNAL */ 1086 /** Operation instruction code */ 1087 cy_en_crypto_comm_instr_t instr; 1088 /** Response from executed crypto function */ 1089 cy_en_crypto_status_t resp; 1090 /** Hardware processing errors */ 1091 cy_stc_crypto_hw_error_t hwErrorStatus; 1092 /** IPC communication channel number */ 1093 uint32_t ipcChannel; 1094 /** IPC acquire interrupt channel number */ 1095 uint32_t acquireNotifierChannel; 1096 /** IPC release interrupt channel number */ 1097 uint32_t releaseNotifierChannel; 1098 /** User callback for Crypto HW calculation complete event */ 1099 cy_crypto_callback_ptr_t userCompleteCallback; 1100 /** Release notifier interrupt configuration */ 1101 cy_stc_sysint_t releaseNotifierConfig; 1102 /** Pointer to the crypto function specific context data */ 1103 void *xdata; 1104 /** \endcond */ 1105 } cy_stc_crypto_context_t; 1106 1107 1108 #if (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) 1109 /** The structure for storing the DES context. 1110 * All fields for the context structure are internal. Firmware never reads or 1111 * writes these values. Firmware allocates the structure and provides the 1112 * address of the structure to the driver in the function calls. Firmware must 1113 * ensure that the defined instance of this structure remains in scope 1114 * while the drive is in use. 1115 */ 1116 typedef struct 1117 { 1118 /** \cond INTERNAL */ 1119 /** Operation direction (Encrypt / Decrypt) */ 1120 cy_en_crypto_dir_mode_t dirMode; 1121 /** Pointer to key data */ 1122 uint32_t *key; 1123 /** Pointer to data destination block */ 1124 uint32_t *dst; 1125 /** Pointer to data source block */ 1126 uint32_t *src; 1127 /** \endcond */ 1128 } cy_stc_crypto_context_des_t; 1129 #endif /* (CPUSS_CRYPTO_DES == 1) && defined(CY_CRYPTO_CFG_DES_C) */ 1130 1131 #if (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) 1132 /** The structure for storing the AES context. 1133 * All fields for the context structure are internal. Firmware never reads or 1134 * writes these values. Firmware allocates the structure and provides the 1135 * address of the structure to the driver in the function calls. Firmware must 1136 * ensure that the defined instance of this structure remains in scope 1137 * while the drive is in use. 1138 */ 1139 typedef struct 1140 { 1141 /** \cond INTERNAL */ 1142 /** AES state data */ 1143 cy_stc_crypto_aes_state_t aesState; 1144 /** Operation direction (Encrypt / Decrypt) */ 1145 cy_en_crypto_dir_mode_t dirMode; 1146 /** AES key length */ 1147 cy_en_crypto_aes_key_length_t keyLength; 1148 /** Pointer to AES key */ 1149 uint32_t *key; 1150 /** Operation data size */ 1151 uint32_t srcSize; 1152 /** Size of the last non-complete block (for CTR mode only) */ 1153 uint32_t *srcOffset; 1154 /** Initialization vector, in the CTR mode is used as nonceCounter */ 1155 uint32_t *ivPtr; 1156 /** AES processed block pointer (for CTR mode only) */ 1157 uint32_t *streamBlock; 1158 /** Pointer to data destination block */ 1159 uint32_t *dst; 1160 /** Pointer to data source block */ 1161 uint32_t *src; 1162 /** \endcond */ 1163 } cy_stc_crypto_context_aes_t; 1164 #endif /* (CPUSS_CRYPTO_AES == 1) && defined(CY_CRYPTO_CFG_AES_C) */ 1165 1166 #if (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 1167 /** The structure for storing the SHA context. 1168 * All fields for the context structure are internal. Firmware never reads or 1169 * writes these values. Firmware allocates the structure and provides the 1170 * address of the structure to the driver in the function calls. Firmware must 1171 * ensure that the defined instance of this structure remains in scope 1172 * while the drive is in use. 1173 */ 1174 typedef struct 1175 { 1176 /** \cond INTERNAL */ 1177 /** Pointer to data source block */ 1178 uint32_t *message; 1179 /** Operation data size */ 1180 uint32_t messageSize; 1181 /** Pointer to data destination block */ 1182 uint32_t *dst; 1183 /** SHA mode */ 1184 cy_en_crypto_sha_mode_t mode; 1185 /** Pointer to key data (for HMAC only) */ 1186 uint32_t *key; 1187 /** Key data length (for HMAC only) */ 1188 uint32_t keyLength; 1189 /** \endcond */ 1190 } cy_stc_crypto_context_sha_t; 1191 #endif /* (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 1192 1193 #if (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) 1194 /** The structure for storing the PRNG context. 1195 * All fields for the context structure are internal. Firmware never reads or 1196 * writes these values. Firmware allocates the structure and provides the 1197 * address of the structure to the driver in the function calls. Firmware must 1198 * ensure that the defined instance of this structure remains in scope 1199 * while the drive is in use. 1200 */ 1201 typedef struct 1202 { 1203 /** \cond INTERNAL */ 1204 uint32_t lfsr32InitState; /**< lfsr32 initialization data */ 1205 uint32_t lfsr31InitState; /**< lfsr31 initialization data */ 1206 uint32_t lfsr29InitState; /**< lfsr29 initialization data */ 1207 uint32_t max; /**< Maximum of the generated value */ 1208 uint32_t *prngNum; /**< Pointer to generated value */ 1209 /** \endcond */ 1210 } cy_stc_crypto_context_prng_t; 1211 #endif /* (CPUSS_CRYPTO_PR == 1) && defined(CY_CRYPTO_CFG_PRNG_C) */ 1212 1213 #if (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) 1214 /** \cond INTERNAL */ 1215 #define CY_CRYPTO_TR_RO_ENABLE (1U) 1216 #define CY_CRYPTO_TR_RO_DISABLE (0U) 1217 /** \endcond */ 1218 1219 /** \cond INTERNAL */ 1220 typedef enum 1221 { 1222 /** "Selection of the ring oscillator (RO) source: */ 1223 CY_CRYPTO_TR_SRC_RO11 = 0, /**< "0": fixed RO 11 bit. */ 1224 CY_CRYPTO_TR_SRC_RO15, /**< "1": fixed RO 15 bit. */ 1225 CY_CRYPTO_TR_SRC_GARO15, /**< "2": fixed Galois RO 15 bit. */ 1226 CY_CRYPTO_TR_SRC_GARO31, /**< "3": flexible Galois RO 31 bit. */ 1227 CY_CRYPTO_TR_SRC_FIRO15, /**< "4": fixed Fibonacci RO 15 bit. */ 1228 CY_CRYPTO_TR_SRC_FIRO31 /**< "5": flexible Fibonacci RO 31 bit. */ 1229 } cy_en_crypto_trng_ro_sel_t; 1230 /** \endcond */ 1231 1232 /****************************************** 1233 * Configuration structure 1234 ******************************************/ 1235 /** \cond INTERNAL */ 1236 typedef enum 1237 { 1238 /** "Selection of the bitstream: */ 1239 CY_CRYPTO_TRMON_BS_DAS = 0, /**< "0": DAS bitstream. */ 1240 CY_CRYPTO_TRMON_BS_RED, /**< "1": RED bitstream. */ 1241 CY_CRYPTO_TRMON_BS_TR, /**< "2": TR bitstream. */ 1242 CY_CRYPTO_TRMON_BS_UNDEF /**< "3": Undefined. */ 1243 } cy_en_crypto_trng_bs_sel_t; 1244 /** \endcond */ 1245 1246 /** The structure for storing the TRNG configuration. 1247 */ 1248 typedef struct 1249 { 1250 /** \cond INTERNAL */ 1251 /** 1252 * "Specifies the clock divider that is used to sample oscillator data. 1253 * This clock divider is wrt. "clk_sys". 1254 * "0": sample clock is "clk_sys". 1255 * "1": sample clock is "clk_sys"/2. 1256 * 1257 * "255": sample clock is "clk_sys"/256. */ 1258 uint8_t sampleClockDiv; 1259 /** 1260 * "Specifies the clock divider that is used to produce reduced bits. 1261 * "0": 1 reduced bit is produced for each sample. 1262 * "1": 1 reduced bit is produced for each 2 samples. 1263 * 1264 * "255": 1 reduced bit is produced for each 256 samples. */ 1265 uint8_t reducedClockDiv; 1266 /** 1267 * Specifies an initialization delay: number of removed/dropped samples 1268 * before reduced bits are generated. This field should be programmed 1269 * in the range [1, 255]. After starting the oscillators, 1270 * at least the first 2 samples should be removed/dropped to clear the state 1271 * of internal synchronizers. In addition, it is advised to drop 1272 * at least the second 2 samples from the oscillators (to circumvent 1273 * the semi-predictable oscillator startup behavior). 1274 * 1275 * This result in the default field value of "3". 1276 * Field encoding is as follows: 1277 * "0": 1 sample is dropped. 1278 * "1": 2 samples are dropped. 1279 * 1280 * "255": 256 samples are dropped. 1281 * 1282 * The TR_INITIALIZED interrupt cause is set to '1', when 1283 * the initialization delay is passed. */ 1284 uint8_t initDelay; 1285 /** 1286 * "Specifies if the "von Neumann corrector" is disabled or enabled: 1287 * '0': disabled. 1288 * '1': enabled. 1289 * The "von Neumann corrector" post-processes the reduced bits 1290 * to remove a '0' or '1' bias. The corrector operates on reduced bit pairs 1291 * ("oldest bit, newest bit"): 1292 * "00": no bit is produced. 1293 * "01": '0' bit is produced (oldest bit). 1294 * "10": '1' bit is produced (oldest bit). 1295 * "11": no bit is produced. 1296 * Note that the corrector produces bits at a random pace and at a frequency 1297 * that is 1/4 of the reduced bit frequency (reduced bits are processed 1298 * in pairs, and half of the pairs do NOT produce a bit). */ 1299 bool vnCorrectorEnable; 1300 /** 1301 * Specifies if TRNG functionality is stopped on an adaptive proportion 1302 * test detection (when HW sets INTR.TR_AP_DETECT to '1'): 1303 * '0': Functionality is NOT stopped. 1304 * '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). */ 1305 bool stopOnAPDetect; 1306 /** 1307 * Specifies if TRNG functionality is stopped on a repetition 1308 * count test detection (when HW sets INTR.TR_RC_DETECT to '1'): 1309 * '0': Functionality is NOT stopped. 1310 * '1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). */ 1311 bool stopOnRCDetect; 1312 1313 /** 1314 * FW sets this field to '1' to enable the ring oscillator with 11 inverters. 1315 */ 1316 bool ro11Enable; 1317 /** 1318 * FW sets this field to '1' to enable the ring oscillator with 15 inverters. 1319 */ 1320 bool ro15Enable; 1321 /** 1322 * FW sets this field to '1' to enable the fixed Galois ring oscillator 1323 * with 15 inverters. */ 1324 bool garo15Enable; 1325 /** 1326 * FW sets this field to '1' to enable the programmable Galois ring 1327 * oscillator with up to 31 inverters. The TR_GARO_CTL register specifies 1328 * the programmable polynomial. */ 1329 bool garo31Enable; 1330 /** 1331 * FW sets this field to '1' to enable the fixed Fibonacci ring oscillator 1332 * with 15 inverters. */ 1333 bool firo15Enable; 1334 /** 1335 * FW sets this field to '1' to enable the programmable Fibonacci ring 1336 * oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies 1337 * the programmable polynomial. */ 1338 bool firo31Enable; 1339 1340 /** 1341 * Polynomial for programmable Galois ring oscillator. 1342 * The polynomial is represented WITHOUT 1343 * the high order bit (this bit is always assumed '1'). 1344 * The polynomial should be aligned such that the more 1345 * significant bits (bit 30 and down) contain the polynomial 1346 * and the less significant bits (bit 0 and up) contain padding '0's. */ 1347 uint32_t garo31Poly; 1348 1349 /** 1350 * Polynomial for programmable Fibonacci ring oscillator. 1351 * The polynomial is represented WITHOUT 1352 * the high order bit (this bit is always assumed '1'). 1353 * The polynomial should be aligned such that the more 1354 * significant bits (bit 30 and down) contain the polynomial 1355 * and the less significant bits (bit 0 and up) contain padding '0's. */ 1356 uint32_t firo31Poly; 1357 1358 /** 1359 * Selection of the bitstream: 1360 * "0": DAS bitstream. 1361 * "1": RED bitstream. 1362 * "2": TR bitstream. 1363 * "3": Undefined. */ 1364 cy_en_crypto_trng_bs_sel_t monBitStreamSelect; 1365 1366 /** 1367 * Cutoff count (legal range is [1, 255]): 1368 * "0": Illegal. 1369 * "1": 1 repetition. 1370 * .. 1371 * "255": 255 repetitions. */ 1372 uint8_t monCutoffCount8; 1373 1374 /** 1375 * Cutoff count (legal range is [1, 65535]). 1376 * "0": Illegal. 1377 * "1": 1 occurrence. 1378 * ... 1379 * "65535": 65535 occurrences. */ 1380 uint16_t monCutoffCount16; 1381 /** 1382 * Window size (minus 1) : 1383 * "0": 1 bit. 1384 * ... 1385 * "65535": 65536 bits. */ 1386 uint16_t monWindowSize; 1387 /** \endcond */ 1388 } cy_stc_crypto_trng_config_t; 1389 1390 /** The structure for storing the TRNG context. 1391 * All fields for the context structure are internal. Firmware never reads or 1392 * writes these values. Firmware allocates the structure and provides the 1393 * address of the structure to the driver in the function calls. Firmware must 1394 * ensure that the defined instance of this structure remains in scope 1395 * while the drive is in use. 1396 */ 1397 typedef struct 1398 { 1399 /** \cond INTERNAL */ 1400 /** 1401 The polynomial for the programmable Galois ring oscillator (TR_GARO_CTL). 1402 The polynomial is represented WITHOUT the high order bit (this bit is 1403 always assumed '1'). 1404 The polynomial should be aligned so that more significant bits 1405 (bit 30 and down) contain the polynomial and less significant bits 1406 (bit 0 and up) contain padding '0's. */ 1407 uint32_t GAROPol; 1408 1409 /** 1410 The polynomial for the programmable Fibonacci ring oscillator(TR_FIRO_CTL). 1411 The polynomial is represented WITHOUT the high order bit (this bit is 1412 always assumed '1'). 1413 The polynomial should be aligned so that more significant bits 1414 (bit 30 and down) contain the polynomial and less significant bits 1415 (bit 0 and up) contain padding '0's. */ 1416 uint32_t FIROPol; 1417 /** Maximum of the generated value */ 1418 uint32_t max; 1419 /** Pointer to generated value */ 1420 uint32_t *trngNum; 1421 /** \endcond */ 1422 } cy_stc_crypto_context_trng_t; 1423 #endif /* (CPUSS_CRYPTO_TR == 1) && defined(CY_CRYPTO_CFG_TRNG_C) */ 1424 1425 #if (CPUSS_CRYPTO_STR == 1) 1426 /** The structure for storing the string context. 1427 * All fields for the context structure are internal. Firmware never reads or 1428 * writes these values. Firmware allocates the structure and provides the 1429 * address of the structure to the driver in the function calls. Firmware must 1430 * ensure that the defined instance of this structure remains in scope 1431 * while the drive is in use. 1432 */ 1433 typedef struct 1434 { 1435 /** \cond INTERNAL */ 1436 void const *src0; /**< Pointer to 1-st string source */ 1437 void const *src1; /**< Pointer to 2-nd string source */ 1438 void *dst; /**< Pointer to string destination */ 1439 uint32_t dataSize; /**< Operation data size */ 1440 uint32_t data; /**< Operation data value (for memory setting) */ 1441 /** \endcond */ 1442 } cy_stc_crypto_context_str_t; 1443 #endif /* (CPUSS_CRYPTO_STR == 1) */ 1444 1445 #if (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) 1446 /** The structure for storing the CRC context. 1447 * All fields for the context structure are internal. Firmware never reads or 1448 * writes these values. Firmware allocates the structure and provides the 1449 * address of the structure to the driver in the function calls. Firmware must 1450 * ensure that the defined instance of this structure remains in scope 1451 * while the drive is in use. 1452 */ 1453 typedef struct 1454 { 1455 /** \cond INTERNAL */ 1456 void* data; /**< Pointer to data source block */ 1457 uint32_t dataSize; /**< Operation data size */ 1458 uint32_t *crc; /**< Pointer to CRC destination variable */ 1459 uint32_t polynomial; /**< Polynomial for CRC calculate */ 1460 uint32_t lfsrInitState; /**< CRC calculation initial value */ 1461 uint32_t dataReverse; /**< Input data reverse flag */ 1462 uint32_t dataXor; /**< Input data XOR flag */ 1463 uint32_t remReverse; /**< Output data reverse flag */ 1464 uint32_t remXor; /**< Output data XOR flag */ 1465 /** \endcond */ 1466 } cy_stc_crypto_context_crc_t; 1467 #endif /* (CPUSS_CRYPTO_CRC == 1) && defined(CY_CRYPTO_CFG_CRC_C) */ 1468 1469 #if (CPUSS_CRYPTO_VU == 1) 1470 #if defined(CY_CRYPTO_CFG_RSA_C) 1471 /** The structure for storing the RSA context. 1472 * All fields for the context structure are internal. Firmware never reads or 1473 * writes these values. Firmware allocates the structure and provides the 1474 * address of the structure to the driver in function calls. Firmware must 1475 * ensure that the defined instance of this structure remains in scope 1476 * while the drive is in use. 1477 */ 1478 typedef struct 1479 { 1480 /** \cond INTERNAL */ 1481 /** Pointer to key data */ 1482 cy_stc_crypto_rsa_pub_key_t const *key; 1483 /** Pointer to data source block */ 1484 uint32_t const *message; 1485 /** Operation data size */ 1486 uint32_t messageSize; 1487 /** Pointer to data destination block */ 1488 uint32_t *result; 1489 /** \endcond */ 1490 } cy_stc_crypto_context_rsa_t; 1491 1492 #if defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) && (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) 1493 /** The structure for storing the RSA verification context. 1494 * All fields for the context structure are internal. Firmware never reads or 1495 * writes these values. Firmware allocates the structure and provides the 1496 * address of the structure to the driver in the function calls. Firmware must 1497 * ensure that the defined instance of this structure remains in scope 1498 * while the drive is in use. 1499 */ 1500 typedef struct 1501 { 1502 /** \cond INTERNAL */ 1503 /** Pointer to verification result /ref cy_en_crypto_rsa_ver_result_t */ 1504 cy_en_crypto_rsa_ver_result_t *verResult; 1505 /** SHA digest type, used with SHA calculation of the message */ 1506 cy_en_crypto_sha_mode_t digestType; 1507 /** SHA digest of the message, calculated with digestType */ 1508 uint32_t const *hash; 1509 /** Previously decrypted RSA signature */ 1510 uint32_t const *decryptedSignature; 1511 /** Length of the decrypted RSA signature */ 1512 uint32_t decryptedSignatureLength; 1513 /** \endcond */ 1514 } cy_stc_crypto_context_rsa_ver_t; 1515 #endif /* defined(CY_CRYPTO_CFG_RSA_VERIFY_ENABLED) && (CPUSS_CRYPTO_SHA == 1) && defined(CY_CRYPTO_CFG_SHA_C) */ 1516 #endif /* defined(CY_CRYPTO_CFG_RSA_C) */ 1517 1518 #if defined(CY_CRYPTO_CFG_ECDSA_C) 1519 /** The structure for storing the ECC operations context. 1520 * All fields for the context structure are internal. Firmware never reads or 1521 * writes these values. Firmware allocates the structure and provides the 1522 * address of the structure to the driver in function calls. Firmware must 1523 * ensure that the defined instance of this structure remains in scope 1524 * while the drive is in use. 1525 */ 1526 typedef struct 1527 { 1528 /** \cond INTERNAL */ 1529 /** Elliptic curve ID */ 1530 cy_en_crypto_ecc_curve_id_t curveID; 1531 /** Pointer to key data */ 1532 const cy_stc_crypto_ecc_key *key; 1533 /** Operation data length */ 1534 uint32_t datalen; 1535 /** Pointer to the first source data block */ 1536 const uint8_t *src0; 1537 /** Pointer to the second source data block */ 1538 const uint8_t *src1; 1539 /** Pointer to the third source data block */ 1540 const uint8_t *src2; 1541 /** Pointer to the first destination data block */ 1542 uint8_t *dst0; 1543 /** Pointer to the second destination data block */ 1544 uint8_t *dst1; 1545 /** \endcond */ 1546 } cy_stc_crypto_context_ecc_t; 1547 #endif /* defined(CY_CRYPTO_CFG_ECDSA_C) */ 1548 #endif /* (CPUSS_CRYPTO_VU == 1) */ 1549 1550 1551 #if defined(CY_CRYPTO_CFG_CHACHA_ENABLED) && (CPUSS_CRYPTO_CHACHA == 1) 1552 1553 /** Defines the chacha state size (in bytes) */ 1554 #define CHACHA_STATE_SIZE 64u 1555 1556 /** Defines the chacha key stream size (in bytes) */ 1557 #define CHACHA_KEYSTREAM_SIZE 64u 1558 1559 /** Defines the chacha state block size (in bytes) */ 1560 #define CHACHA_BLOCK_SIZE 64u 1561 1562 /** \cond INTERNAL */ 1563 1564 /** Defines the chacha key size (in bytes) */ 1565 #define CHACHA_KEY_SIZE 32u 1566 1567 /** Defines the chacha nonce size (in bytes) */ 1568 #define CHACHA_NONCE_SIZE 12u 1569 1570 /** Defines the chacha counter size (in bytes) */ 1571 #define CHACHA_COUNTER_SIZE 4u 1572 1573 /** Defines the chacha const size (in bytes) */ 1574 #define CHACHA_CONST_SIZE 16u 1575 /** \endcond */ 1576 1577 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 1578 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 1579 #endif 1580 typedef struct 1581 { 1582 /** \cond INTERNAL */ 1583 1584 /** buffer to store the constant*/ 1585 uint32_t constant[CHACHA_CONST_SIZE/4u]; 1586 1587 /** buffer to store the chacha key*/ 1588 uint8_t key[CHACHA_KEY_SIZE]; 1589 1590 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 1591 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 1592 #endif 1593 /** To store the counter*/ 1594 uint32_t counter; 1595 1596 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 1597 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 1598 #endif 1599 /** buffer to store the nonce*/ 1600 uint8_t nonce[CHACHA_NONCE_SIZE]; 1601 /** \endcond */ 1602 }cy_stc_crypto_v2_chacha_input_buffer; 1603 1604 #if (((CY_CPU_CORTEX_M7) && defined (ENABLE_CM7_DATA_CACHE)) || CY_CPU_CORTEX_M55) 1605 CY_ALIGN(__SCB_DCACHE_LINE_SIZE) 1606 #endif 1607 typedef struct 1608 { 1609 /** \cond INTERNAL */ 1610 /** The pointer to store chacha state */ 1611 cy_stc_crypto_v2_chacha_input_buffer *state; 1612 /** The pointer to chacha key stream */ 1613 uint8_t *key; 1614 /** To store the chacha key bytes used */ 1615 uint8_t keyIndexUsed; 1616 /** To store the rounds for the chacha operation*/ 1617 uint8_t round; 1618 /** \endcond */ 1619 } cy_stc_crypto_chacha_state_t; 1620 1621 #endif 1622 1623 #if defined(CY_CRYPTO_CFG_CCM_C) 1624 /** CCM tag verification status */ 1625 typedef enum 1626 { 1627 /** \cond INTERNAL */ 1628 CY_CRYPTO_CCM_TAG_VALID = 0x05555555u, 1629 CY_CRYPTO_CCM_TAG_INVALID = 0x0AAAAAAAu, 1630 /** \endcond */ 1631 } cy_en_crypto_aesccm_tag_verify_result_t; 1632 #endif 1633 1634 #if (CPUSS_CRYPTO_VU == 1) && defined(CY_CRYPTO_CFG_POLY1305_ENABLED) 1635 1636 /** Defines the poly1305 block size (in bytes) */ 1637 #define CY_CRYPTO_POLY1305_BLOCK_SIZE (16u) 1638 1639 /** Defines the poly1305 key size (in bytes) */ 1640 #define CY_CRYPTO_POLY1305_KEY_SIZE (32u) 1641 1642 /** Defines the poly1305 state size (in bytes) */ 1643 #define CY_CRYPTO_POLY1305_STATE_SIZE (17u) 1644 1645 #endif 1646 1647 /** \} group_crypto_cli_data_structures */ 1648 1649 #if defined(__cplusplus) 1650 } 1651 #endif 1652 1653 #endif /* defined(CY_IP_MXCRYPTO) */ 1654 1655 #endif /* !defined (CY_CRYPTO_COMMON_H) */ 1656 1657 1658 /* [] END OF FILE */ 1659
