1 /***************************************************************************//** 2 * \file cy_crypto_core_trng_config.h 3 * \version 2.120 4 * 5 * \brief 6 * This file provides internal (not public) constants and parameters 7 * for the Crypto TRNG driver. 8 * 9 ******************************************************************************** 10 * \copyright 11 * Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or 12 * an affiliate of Cypress Semiconductor Corporation. 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 29 #if !defined (CY_CRYPTO_CORE_TRNG_CONFIG_H) 30 #define CY_CRYPTO_CORE_TRNG_CONFIG_H 31 32 #include "cy_crypto_common.h" 33 34 #if defined (CY_IP_MXCRYPTO) 35 36 #if defined(__cplusplus) 37 extern "C" { 38 #endif 39 40 #if (CPUSS_CRYPTO_TR == 1) 41 42 43 /** TRNG Configuration default values */ 44 /** 45 * Specifies the clock divider that is used to sample oscillator data. 46 * "0": sample clock is "clk_sys". 47 * "1": sample clock is "clk_sys"/2. 48 * ... 49 * "255": sample clock is "clk_sys"/256. 50 */ 51 #define CY_CRYPTO_DEF_TR_SAMPLE_CLOCK_DIV (0UL) 52 53 /** 54 * Specifies the clock divider used to produce reduced bits. 55 * "0": 1 reduced bit is produced for each sample. 56 * "1": 1 reduced bit is produced for each 2 samples. 57 * ... 58 * "255": 1 reduced bit is produced for each 256 samples. 59 * 60 * The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32. 61 */ 62 #define CY_CRYPTO_DEF_TR_RED_CLOCK_DIV (0UL) 63 64 /** 65 * Specifies an initialization delay: a number of removed/dropped samples before 66 * reduced bits are generated. This field should be programmed in the range [1, 255]. 67 * After starting the oscillators, at least the first 2 samples should be 68 * removed/dropped to clear the state of internal synchronizers. In addition, 69 * it is advised to drop at least the second 2 samples from the oscillators 70 * (to circumvent the semi-predictable oscillator start-up behavior). This results 71 * in the default field value of "3". the field encoding is as follows: 72 * "0": 1 sample is dropped. 73 * "1": 2 samples are dropped. 74 * ... 75 * "255": 256 samples are dropped. 76 * 77 * The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed. 78 */ 79 #define CY_CRYPTO_DEF_TR_INIT_DELAY (3UL) 80 81 /** 82 * Specifies if the "von Neumann corrector" is disabled or enabled: 83 * '0': disabled. 84 * '1': enabled. 85 * The "von Neumann corrector" post-processes the reduced bits to remove a '0' or '1' bias. 86 * The corrector operates on reduced bit pairs ("oldest bit, newest bit"): 87 * "00": no bit is produced. 88 * "01": '0' bit is produced (oldest bit). 89 * "10": '1' bit is produced (oldest bit). 90 * "11": no bit is produced. 91 * NOTE: The corrector produces bits at a random pace and at a frequency that 92 * is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, 93 * and half of the pairs do NOT produce a bit). 94 */ 95 #define CY_CRYPTO_DEF_TR_VON_NEUMANN_CORR (1UL) 96 97 /** 98 * Specifies if the TRNG functionality is stopped on an adaptive proportion test 99 * detection (when HW sets INTR.TR_AP_DETECT to '1'): 100 * '0': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). 101 * '1': Functionality is NOT stopped. 102 */ 103 #define CY_CRYPTO_DEF_TR_STOP_ON_AP_DETECT (1UL) 104 105 /** 106 * Specifies if the TRNG functionality is stopped on a repetition count test detection 107 * (when HW sets INTR.TR_RC_DETECT to '1'): 108 * '0': Functionality is stopped (TR_CTL1 fields are set to '0' by HW). 109 * '1': Functionality is NOT stopped. 110 */ 111 #define CY_CRYPTO_DEF_TR_STOP_ON_RC_DETECT (1UL) 112 113 /** FW sets this field to '1' to enable the ring oscillator with 11 inverters. */ 114 #define CY_CRYPTO_DEF_TR_RO11_EN (1UL) 115 116 /** FW sets this field to '1' to enable the ring oscillator with 15 inverters. */ 117 #define CY_CRYPTO_DEF_TR_RO15_EN (1UL) 118 119 /** 120 * FW sets this field to '1' to enable the fixed Galois ring oscillator 121 * with 15 inverters. 122 */ 123 #define CY_CRYPTO_DEF_TR_GARO15_EN (1UL) 124 125 /** 126 * FW sets this field to '1' to enable the programmable Galois ring oscillator with up 127 * to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial. 128 */ 129 #define CY_CRYPTO_DEF_TR_GARO31_EN (1UL) 130 131 /** FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters. */ 132 #define CY_CRYPTO_DEF_TR_FIRO15_EN (1UL) 133 134 /** 135 * FW sets this field to '1' to enable the programmable Fibonacci ring oscillator 136 * with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial. 137 */ 138 #define CY_CRYPTO_DEF_TR_FIRO31_EN (1UL) 139 140 /** 141 * The polynomial for programmable Galois ring oscillator. The polynomial is represented 142 * WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned 143 * so that the more significant bits (bit 30 and down) contain the polynomial and the less 144 * significant bits (bit 0 and up) contain padding '0's. 145 */ 146 #define CY_CRYPTO_DEF_TR_GARO (0x04c11db7) 147 148 /** 149 * The polynomial for the programmable Fibonacci ring oscillator. The polynomial is represented 150 * WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should 151 * be aligned so that the more significant bits (bit 30 and down) contain the polynomial 152 * and the less significant bits (bit 0 and up) contain padding '0's. 153 */ 154 #define CY_CRYPTO_DEF_TR_FIRO (0x04c11db7) 155 156 /** 157 * Selection of the bit stream: 158 * "0": DAS bit stream. 159 * "1": RED bit stream. 160 * "2": TR bit stream. 161 * "3": Undefined. 162 */ 163 #define CY_CRYPTO_DEF_TR_BITSTREAM_SEL (CY_CRYPTO_TRMON_BS_TR) 164 165 /** 166 * Adaptive proportion (AP) test enable: 167 * '0': Stopped. 168 * '1': Started. 169 * 170 * On AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1. 171 */ 172 #define CY_CRYPTO_DEF_TR_START_AP (0UL) 173 174 /** 175 * Repetition count (RC) test enable: 176 * '0': Disabled. 177 * '1': Enabled. 178 * 179 * On RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1. 180 */ 181 #define CY_CRYPTO_DEF_TR_START_RC (0UL) 182 183 /** 184 * Cut-off count (legal range is [1, 255]): 185 * "0": Illegal. 186 * "1": 1 repetition. 187 * ... 188 * "255": 255 repetitions. 189 */ 190 #define CY_CRYPTO_DEF_TR_CUTOFF_COUNT8 (255UL) 191 192 /** 193 * Cut-off count (legal range is [1, 65535]). 194 * "0": Illegal. 195 * "1": 1 occurrence. 196 * ... 197 * "65535": 65535 occurrences. 198 */ 199 #define CY_CRYPTO_DEF_TR_CUTOFF_COUNT16 (65535UL) 200 201 /** 202 * The window size (minus 1) : 203 * "0": 1 bit. 204 * ... 205 * "65535": 65536 bits. 206 */ 207 208 #define CY_CRYPTO_DEF_TR_WINDOW_SIZE (65535UL) 209 210 211 #endif /* #if (CPUSS_CRYPTO_TR == 1) */ 212 213 #if defined(__cplusplus) 214 } 215 #endif 216 217 #endif /* CY_IP_MXCRYPTO */ 218 219 #endif /* #if !defined (CY_CRYPTO_CORE_TRNG_CONFIG_H) */ 220 221 222 /* [] END OF FILE */ 223
