1 /***************************************************************************//** 2 * \file cyhal_hw_resources.h 3 * 4 * \brief 5 * Provides struct definitions for configuration resources in the PDL. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 /** 28 * \addtogroup group_hal_impl_availability HAL Driver Availability Macros 29 * \ingroup group_hal_impl 30 * \{ 31 */ 32 33 #pragma once 34 35 #include "cy_pdl.h" 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 // Documented in cyhal.h 42 #define CYHAL_API_VERSION (2) 43 44 /** \cond INTERNAL */ 45 #define _CYHAL_DRIVER_AVAILABLE_ADC_SAR ((CY_IP_MXS40PASS_SAR_INSTANCES) > 0) 46 #define _CYHAL_DRIVER_AVAILABLE_ADC_MIC ((CY_IP_MXS40ADCMIC_INSTANCES) > 0) 47 #define _CYHAL_DRIVER_AVAILABLE_DMA_DMAC (((CY_IP_M4CPUSS_DMAC_INSTANCES) > 0) || ((CY_IP_MXAHBDMAC_INSTANCES) > 0)) 48 #define _CYHAL_DRIVER_AVAILABLE_DMA_DW (((CY_IP_M4CPUSS_DMA_INSTANCES) > 0) || ((CY_IP_MXDW_INSTANCES) > 0)) 49 #define _CYHAL_DRIVER_AVAILABLE_COMP_LP ((CY_IP_MXLPCOMP_INSTANCES) > 0) 50 #define _CYHAL_DRIVER_AVAILABLE_COMP_CTB (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTB_INSTANCES) > 0)) 51 #define _CYHAL_DRIVER_AVAILABLE_PASS ((CY_IP_MXS40PASS_INSTANCES) > 0) 52 #define _CYHAL_DRIVER_AVAILABLE_SCB ((CY_IP_MXSCB_INSTANCES) > 0) 53 #define _CYHAL_DRIVER_AVAILABLE_TCPWM ((CY_IP_MXTCPWM_INSTANCES) > 0) 54 #define _CYHAL_DRIVER_AVAILABLE_CRYPTO (((CY_IP_MXCRYPTO_INSTANCES) > 0) || ((CY_IP_MXCRYPTOLITE_INSTANCES) > 0)) 55 #if defined(CYHAL_UDB_SDIO) 56 #define _CYHAL_DRIVER_AVAILABLE_SDIO_UDB (1) 57 #else 58 #define _CYHAL_DRIVER_AVAILABLE_SDIO_UDB (0) 59 #endif 60 #if (!defined(CPUSS_FLASHC_PRESENT) || ((CPUSS_FLASHC_PRESENT) > 0)) 61 #define _CYHAL_DRIVER_AVAILABLE_FLASH (1) 62 #else 63 #define _CYHAL_DRIVER_AVAILABLE_FLASH (0) 64 #endif 65 /** \endcond */ 66 67 // Documented in cyhal.h 68 #define CYHAL_DRIVER_AVAILABLE_ADC ((_CYHAL_DRIVER_AVAILABLE_ADC_SAR) || (_CYHAL_DRIVER_AVAILABLE_ADC_MIC)) 69 #define CYHAL_DRIVER_AVAILABLE_CLOCK (1) 70 #define CYHAL_DRIVER_AVAILABLE_COMP ((_CYHAL_DRIVER_AVAILABLE_COMP_LP) || (_CYHAL_DRIVER_AVAILABLE_COMP_CTB)) 71 #define CYHAL_DRIVER_AVAILABLE_CRC (((CY_IP_MXCRYPTO_INSTANCES) > 0) && (CPUSS_CRYPTO_CRC)) 72 #define CYHAL_DRIVER_AVAILABLE_DAC (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTDAC_INSTANCES) > 0)) 73 #define CYHAL_DRIVER_AVAILABLE_DMA ((_CYHAL_DRIVER_AVAILABLE_DMA_DMAC) || (_CYHAL_DRIVER_AVAILABLE_DMA_DW)) 74 #define CYHAL_DRIVER_AVAILABLE_EZI2C (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_I2C 75 #define CYHAL_DRIVER_AVAILABLE_FLASH (_CYHAL_DRIVER_AVAILABLE_FLASH) 76 #define CYHAL_DRIVER_AVAILABLE_GPIO (1) 77 #define CYHAL_DRIVER_AVAILABLE_HWMGR (1) 78 #define CYHAL_DRIVER_AVAILABLE_I2C (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_I2C 79 #define CYHAL_DRIVER_AVAILABLE_I2S (((CY_IP_MXAUDIOSS_INSTANCES) > 0) || ((CY_IP_MXTDM_INSTANCES) > 0)) //AUDIOSS[x]_I2S 80 #define CYHAL_DRIVER_AVAILABLE_I2S_TX (CYHAL_DRIVER_AVAILABLE_I2S) 81 #define CYHAL_DRIVER_AVAILABLE_I2S_RX (CYHAL_DRIVER_AVAILABLE_I2S) 82 #define CYHAL_DRIVER_AVAILABLE_INTERCONNECT (1) 83 #define CYHAL_DRIVER_AVAILABLE_KEYSCAN ((CY_IP_MXKEYSCAN_INSTANCES) > 0) 84 #define CYHAL_DRIVER_AVAILABLE_LPTIMER ((SRSS_NUM_MCWDT) > 0) 85 #define CYHAL_DRIVER_AVAILABLE_OPAMP (((CY_IP_MXS40PASS_INSTANCES) > 0) && ((CY_IP_MXS40PASS_CTB_INSTANCES) > 0)) 86 #define CYHAL_DRIVER_AVAILABLE_PDMPCM (((CY_IP_MXAUDIOSS_INSTANCES) > 0) || ((CY_IP_MXPDM_INSTANCES) > 0)) //AUDIOSS[x]_PDM 87 #define CYHAL_DRIVER_AVAILABLE_PWM (_CYHAL_DRIVER_AVAILABLE_TCPWM) 88 #define CYHAL_DRIVER_AVAILABLE_QSPI ((CY_IP_MXSMIF_INSTANCES) > 0) 89 #define CYHAL_DRIVER_AVAILABLE_QUADDEC (_CYHAL_DRIVER_AVAILABLE_TCPWM) 90 #define CYHAL_DRIVER_AVAILABLE_RTC ((((CY_IP_MXS40SSRSS_INSTANCES) > 0) || ((CY_IP_MXS40SRSS_INSTANCES) > 0)) && ((SRSS_BACKUP_PRESENT) > 0)) 91 #define CYHAL_DRIVER_AVAILABLE_SDHC ((CY_IP_MXSDHC_INSTANCES) > 0) 92 #define CYHAL_DRIVER_AVAILABLE_SDIO (((CY_IP_MXSDHC_INSTANCES) > 0) || (_CYHAL_DRIVER_AVAILABLE_SDIO_UDB)) 93 #define CYHAL_DRIVER_AVAILABLE_SPI (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_SPI 94 #define CYHAL_DRIVER_AVAILABLE_SYSPM (1) 95 #define CYHAL_DRIVER_AVAILABLE_SYSTEM (1) 96 #define CYHAL_DRIVER_AVAILABLE_TDM (((CY_IP_MXAUDIOSS_INSTANCES) > 0) || ((CY_IP_MXTDM_INSTANCES) > 0)) //AUDIOSS[x]_I2S 97 #define CYHAL_DRIVER_AVAILABLE_TDM_TX (CYHAL_DRIVER_AVAILABLE_TDM) 98 #define CYHAL_DRIVER_AVAILABLE_TDM_RX (CYHAL_DRIVER_AVAILABLE_TDM) 99 #define CYHAL_DRIVER_AVAILABLE_TIMER (_CYHAL_DRIVER_AVAILABLE_TCPWM) 100 #define CYHAL_DRIVER_AVAILABLE_TRNG ((((CY_IP_MXCRYPTO_INSTANCES) > 0) && ((CPUSS_CRYPTO_TR) > 0)) /*|| (((CY_IP_MXCRYPTOLITE_INSTANCES) > 0) && ((CRYPTO_TRNG_PRESENT) > 0))*/) 101 #define CYHAL_DRIVER_AVAILABLE_UART (_CYHAL_DRIVER_AVAILABLE_SCB) //SCB[x]_UART 102 #define CYHAL_DRIVER_AVAILABLE_USB_DEV ((CY_IP_MXUSBFS_INSTANCES) > 0) 103 #define CYHAL_DRIVER_AVAILABLE_WDT (1) 104 105 106 /** \} group_hal_impl_availability */ 107 /** 108 * \addtogroup group_hal_impl_hw_types 109 * \ingroup group_hal_impl 110 * \{ 111 */ 112 113 114 /* NOTE: Any changes made to this enum must also be made to the hardware manager resource tracking */ 115 /** Resource types that the hardware manager supports */ 116 typedef enum 117 { 118 CYHAL_RSC_ADC, /*!< Analog to digital converter */ 119 CYHAL_RSC_ADCMIC, /*!< Analog to digital converter with Analog Mic support */ 120 CYHAL_RSC_BLESS, /*!< Bluetooth communications block */ 121 CYHAL_RSC_CAN, /*!< CAN communication block */ 122 CYHAL_RSC_CLKPATH, /*!< Clock Path. DEPRECATED. */ 123 CYHAL_RSC_CLOCK, /*!< Clock */ 124 CYHAL_RSC_CRYPTO, /*!< Crypto hardware accelerator */ 125 CYHAL_RSC_DAC, /*!< Digital to analog converter */ 126 CYHAL_RSC_DMA, /*!< DMA controller */ 127 CYHAL_RSC_DW, /*!< Datawire DMA controller */ 128 CYHAL_RSC_ETH, /*!< Ethernet communications block */ 129 CYHAL_RSC_GPIO, /*!< General purpose I/O pin */ 130 CYHAL_RSC_I2S, /*!< I2S communications block */ 131 CYHAL_RSC_I3C, /*!< I3C communications block */ 132 CYHAL_RSC_KEYSCAN, /*!< KeyScan block */ 133 CYHAL_RSC_LCD, /*!< Segment LCD controller */ 134 CYHAL_RSC_LIN, /*!< LIN communications block */ 135 CYHAL_RSC_LPCOMP, /*!< Low power comparator */ 136 CYHAL_RSC_LPTIMER, /*!< Low power timer */ 137 CYHAL_RSC_OPAMP, /*!< Opamp */ 138 CYHAL_RSC_PDM, /*!< PCM/PDM communications block */ 139 CYHAL_RSC_SMIF, /*!< Quad-SPI communications block */ 140 CYHAL_RSC_RTC, /*!< Real time clock */ 141 CYHAL_RSC_SCB, /*!< Serial Communications Block */ 142 CYHAL_RSC_SDHC, /*!< SD Host Controller */ 143 CYHAL_RSC_SDIODEV, /*!< SDIO Device Block */ 144 CYHAL_RSC_TCPWM, /*!< Timer/Counter/PWM block */ 145 CYHAL_RSC_TDM, /*!< TDM block */ 146 CYHAL_RSC_UDB, /*!< UDB Array */ 147 CYHAL_RSC_USB, /*!< USB communication block */ 148 CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */ 149 } cyhal_resource_t; 150 151 /** \cond INTERNAL */ 152 /* Extracts the divider from the Peri group block number */ 153 #define _CYHAL_PERIPHERAL_GROUP_GET_DIVIDER_TYPE(block) ((cy_en_divider_types_t)(block & 0x03)) 154 #define _CYHAL_PERIPHERAL_GROUP_GET_GROUP(block) (block >> 2) 155 #if defined(COMPONENT_CAT1B) 156 /* Converts the group/div pair into a unique block number. */ 157 #define _CYHAL_PERIPHERAL_GROUP_ADJUST(group, div) ((group << 2) | div) 158 159 #define _CYHAL_CLOCK_BLOCK_PERI_GROUP(gr) \ 160 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_8BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST(gr, CY_SYSCLK_DIV_8_BIT), /*!< 8bit Peripheral Divider Group 1 */ \ 161 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_16BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST(gr, CY_SYSCLK_DIV_16_BIT), /*!< 16bit Peripheral Divider Group 1 */ \ 162 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_16_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST(gr, CY_SYSCLK_DIV_16_5_BIT), /*!< 16.5bit Peripheral Divider Group 1 */ \ 163 CYHAL_CLOCK_BLOCK_PERIPHERAL##gr##_24_5BIT = _CYHAL_PERIPHERAL_GROUP_ADJUST(gr, CY_SYSCLK_DIV_24_5_BIT) /*!< 24.5bit Peripheral Divider Group 1 */ 164 #endif 165 /** \endcond */ 166 167 /* NOTE: Any changes here must also be made in cyhal_hwmgr.c */ 168 /** Enum for the different types of clocks that exist on the device. */ 169 typedef enum 170 { 171 #if defined(COMPONENT_CAT1A) 172 // The first four items are here for backwards compatability with old clock APIs 173 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< 8bit Peripheral Divider */ 174 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< 16bit Peripheral Divider */ 175 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< 16.5bit Peripheral Divider */ 176 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< 24.5bit Peripheral Divider */ 177 178 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 179 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 180 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 181 CYHAL_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */ 182 CYHAL_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */ 183 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 184 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 185 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 186 CYHAL_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */ 187 188 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 189 190 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 191 CYHAL_CLOCK_BLOCK_PLL, /*!< Phase-Locked Loop Clock */ 192 193 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 194 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 195 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 196 197 CYHAL_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */ 198 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 199 CYHAL_CLOCK_BLOCK_TIMER, /*!< Timer Clock */ 200 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 201 202 CYHAL_CLOCK_BLOCK_FAST, /*!< Fast Clock for CM4 */ 203 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock */ 204 CYHAL_CLOCK_BLOCK_SLOW, /*!< Slow Clock for CM0+ */ 205 #elif defined(COMPONENT_CAT1B) 206 207 CYHAL_CLOCK_BLOCK_PERIPHERAL_8BIT = CY_SYSCLK_DIV_8_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_8_BIT */ 208 CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT = CY_SYSCLK_DIV_16_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_BIT */ 209 CYHAL_CLOCK_BLOCK_PERIPHERAL_16_5BIT = CY_SYSCLK_DIV_16_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_16_5_BIT */ 210 CYHAL_CLOCK_BLOCK_PERIPHERAL_24_5BIT = CY_SYSCLK_DIV_24_5_BIT, /*!< Equivalent to CYHAL_CLOCK_BLOCK_PERIPHERAL0_24_5_BIT */ 211 212 // The first four items are here for backwards compatability with old clock APIs 213 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 1) 214 _CYHAL_CLOCK_BLOCK_PERI_GROUP(0), 215 #endif 216 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 2) 217 _CYHAL_CLOCK_BLOCK_PERI_GROUP(1), 218 #endif 219 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 3) 220 _CYHAL_CLOCK_BLOCK_PERI_GROUP(2), 221 #endif 222 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 4) 223 _CYHAL_CLOCK_BLOCK_PERI_GROUP(3), 224 #endif 225 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 5) 226 _CYHAL_CLOCK_BLOCK_PERI_GROUP(4), 227 #endif 228 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 6) 229 _CYHAL_CLOCK_BLOCK_PERI_GROUP(5), 230 #endif 231 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 7) 232 _CYHAL_CLOCK_BLOCK_PERI_GROUP(6), 233 #endif 234 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 8) 235 _CYHAL_CLOCK_BLOCK_PERI_GROUP(7), 236 #endif 237 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 9) 238 _CYHAL_CLOCK_BLOCK_PERI_GROUP(8), 239 #endif 240 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 10) 241 _CYHAL_CLOCK_BLOCK_PERI_GROUP(9), 242 #endif 243 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 11) 244 _CYHAL_CLOCK_BLOCK_PERI_GROUP(10), 245 #endif 246 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 12) 247 _CYHAL_CLOCK_BLOCK_PERI_GROUP(11), 248 #endif 249 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 13) 250 _CYHAL_CLOCK_BLOCK_PERI_GROUP(12), 251 #endif 252 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 14) 253 _CYHAL_CLOCK_BLOCK_PERI_GROUP(13), 254 #endif 255 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 15) 256 _CYHAL_CLOCK_BLOCK_PERI_GROUP(14), 257 #endif 258 #if (PERI_PERI_PCLK_PCLK_GROUP_NR >= 16) 259 _CYHAL_CLOCK_BLOCK_PERI_GROUP(15), 260 #endif 261 262 CYHAL_CLOCK_BLOCK_IHO, /*!< Internal High Speed Oscillator Input Clock */ 263 CYHAL_CLOCK_BLOCK_IMO, /*!< Internal Main Oscillator Input Clock */ 264 CYHAL_CLOCK_BLOCK_ECO, /*!< External Crystal Oscillator Input Clock */ 265 CYHAL_CLOCK_BLOCK_EXT, /*!< External Input Clock */ 266 CYHAL_CLOCK_BLOCK_ALTHF, /*!< Alternate High Frequency Input Clock */ 267 CYHAL_CLOCK_BLOCK_ALTLF, /*!< Alternate Low Frequency Input Clock */ 268 CYHAL_CLOCK_BLOCK_ILO, /*!< Internal Low Speed Oscillator Input Clock */ 269 CYHAL_CLOCK_BLOCK_PILO, /*!< Precision ILO Input Clock */ 270 CYHAL_CLOCK_BLOCK_WCO, /*!< Watch Crystal Oscillator Input Clock */ 271 CYHAL_CLOCK_BLOCK_MFO, /*!< Medium Frequency Oscillator Clock */ 272 273 CYHAL_CLOCK_BLOCK_PATHMUX, /*!< Path selection mux for input to FLL/PLLs */ 274 275 CYHAL_CLOCK_BLOCK_FLL, /*!< Frequency-Locked Loop Clock */ 276 CYHAL_CLOCK_BLOCK_PLL200, /*!< 200MHz Phase-Locked Loop Clock */ 277 CYHAL_CLOCK_BLOCK_PLL400, /*!< 400MHz Phase-Locked Loop Clock */ 278 CYHAL_CLOCK_BLOCK_ECO_PRESCALER, /*!< ECO Prescaler Divider */ 279 280 CYHAL_CLOCK_BLOCK_LF, /*!< Low Frequency Clock */ 281 CYHAL_CLOCK_BLOCK_MF, /*!< Medium Frequency Clock */ 282 CYHAL_CLOCK_BLOCK_HF, /*!< High Frequency Clock */ 283 284 CYHAL_CLOCK_BLOCK_PUMP, /*!< Analog Pump Clock */ 285 CYHAL_CLOCK_BLOCK_BAK, /*!< Backup Power Domain Clock */ 286 CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, /*!< Alternative SysTick Clock */ 287 CYHAL_CLOCK_BLOCK_PERI, /*!< Peripheral Clock Group */ 288 #endif 289 } cyhal_clock_block_t; 290 291 /** @brief Clock object 292 * Application code should not rely on the specific contents of this struct. 293 * They are considered an implementation detail which is subject to change 294 * between platforms and/or HAL releases. */ 295 typedef struct 296 { 297 cyhal_clock_block_t block; 298 uint8_t channel; 299 bool reserved; 300 const void* funcs; 301 } cyhal_clock_t; 302 303 /** 304 * @brief Represents a particular instance of a resource on the chip. 305 * Application code should not rely on the specific contents of this struct. 306 * They are considered an implementation detail which is subject to change 307 * between platforms and/or HAL releases. 308 */ 309 typedef struct 310 { 311 cyhal_resource_t type; //!< The resource block type 312 uint8_t block_num; //!< The resource block index 313 /** 314 * The channel number, if the resource type defines multiple channels 315 * per block instance. Otherwise, 0 */ 316 uint8_t channel_num; 317 } cyhal_resource_inst_t; 318 319 #if defined(__cplusplus) 320 } 321 #endif /* __cplusplus */ 322 323 /** \} group_hal_impl_hw_types */ 324
