1 /*******************************************************************************
2 * File Name: cyhal_clock.c
3 *
4 * Description:
5 * Provides an implementation for high level interface for interacting with the
6 * Cypress Clocks. This is a wrapper around the lower level PDL API.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
11 * an affiliate of Cypress Semiconductor Corporation
12 *
13 * SPDX-License-Identifier: Apache-2.0
14 *
15 * Licensed under the Apache License, Version 2.0 (the "License");
16 * you may not use this file except in compliance with the License.
17 * You may obtain a copy of the License at
18 *
19 * http://www.apache.org/licenses/LICENSE-2.0
20 *
21 * Unless required by applicable law or agreed to in writing, software
22 * distributed under the License is distributed on an "AS IS" BASIS,
23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 * See the License for the specific language governing permissions and
25 * limitations under the License.
26 *******************************************************************************/
27
28 #include <stdlib.h>
29 #include <string.h>
30 #include "cy_sysclk.h"
31 #include "cy_utils.h"
32 #include "cyhal_clock.h"
33 #include "cyhal_system.h"
34 #include "cyhal_utils.h"
35 #include "cyhal_hwmgr.h"
36
37 #if (CYHAL_DRIVER_AVAILABLE_CLOCK)
38
39 #if defined(__cplusplus)
40 extern "C"
41 {
42 #endif
43
44 #define _CYHAL_CLOCK_FLL_LOCK_TIME (20000UL)
45 #define _CYHAL_CLOCK_PLL_LOCK_TIME (10000UL)
46
47 #if defined(PERI_PCLK_GR_NUM_Pos)
48 #if !defined(COMPONENT_CAT1D)
49 #define _CYHAL_CLOCK_GET_PCLK_GR_NUM(block) ((en_clk_dst_t)(_CYHAL_PERIPHERAL_GROUP_GET_GROUP(block) << PERI_PCLK_GR_NUM_Pos))
50 #else
51 #define _CYHAL_CLOCK_GET_PCLK_GR_NUM(block) ((en_clk_dst_t)((_CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(block) << PERI_PCLK_INST_NUM_Pos) | (_CYHAL_PERIPHERAL_CLOCK_GET_GROUP(block) << PERI_PCLK_GR_NUM_Pos)))
52 #endif
53 #else
54 #define _CYHAL_CLOCK_GET_PCLK_GR_NUM(block) ((en_clk_dst_t)0) /* Value is not used for devices that don't have PCLK groups. */
55 #endif
56
57 /* We can't use the PDL-defined _CYHAL_SRSS_PILO_PRESENT because on CAT1A devices it performs a struct lookup
58 * which won't work in preprocessor expressions */
59 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
60 #define _CYHAL_SRSS_PILO_PRESENT (SRSS_PILO_PRESENT)
61 #elif defined(COMPONENT_CAT1B)
62 #define _CYHAL_SRSS_PILO_PRESENT (SRSS_S40S_PILO_PRESENT)
63 #endif
64
65 /******************************************************************************
66 ****************************** Clock Resources *******************************
67 *****************************************************************************/
68 const cyhal_clock_tolerance_t CYHAL_CLOCK_TOLERANCE_0_P = {CYHAL_TOLERANCE_PERCENT, 0};
69 const cyhal_clock_tolerance_t CYHAL_CLOCK_TOLERANCE_1_P = {CYHAL_TOLERANCE_PERCENT, 1};
70 const cyhal_clock_tolerance_t CYHAL_CLOCK_TOLERANCE_5_P = {CYHAL_TOLERANCE_PERCENT, 5};
71
72 #if !defined(COMPONENT_CAT1D)
73 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_IMO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_IMO, 0 };
74 #endif
75 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_EXT = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_EXT, 0 };
76 #if (_CYHAL_SRSS_ILO_PRESENT)
77 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
78 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ILO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ILO, 0 };
79 #elif defined(COMPONENT_CAT1C)
80 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ILO[_CYHAL_SRSS_NUM_ILO] =
81 {
82 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ILO, 0 },
83 #if (SRSS_HT_VARIANT > 0)
84 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ILO, 1 },
85 #endif
86 };
87 #endif
88 #endif
89 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_LF = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_LF, 0 };
90 /* PUMP clock is only available on CAT1A and CAT1B devices */
91 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
92 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PUMP = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PUMP, 0 };
93 #endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
94 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_BAK = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_BAK, 0 };
95 #if !defined(COMPONENT_CAT1D)
96 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALT_SYS_TICK = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ALT_SYS_TICK, 0 };
97 #endif
98
99 #if defined(COMPONENT_CAT1C)
100 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MEM = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_MEM, 0 };
101 #endif
102
103 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PATHMUX[SRSS_NUM_CLKPATH] =
104 {
105 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 0 },
106 #if (SRSS_NUM_CLKPATH > 1)
107 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 1 },
108 #endif
109 #if (SRSS_NUM_CLKPATH > 2)
110 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 2 },
111 #endif
112 #if (SRSS_NUM_CLKPATH > 3)
113 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 3 },
114 #endif
115 #if (SRSS_NUM_CLKPATH > 4)
116 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 4 },
117 #endif
118 #if (SRSS_NUM_CLKPATH > 5)
119 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 5 },
120 #endif
121 #if (SRSS_NUM_CLKPATH > 6)
122 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 6 },
123 #endif
124 #if (SRSS_NUM_CLKPATH > 7)
125 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 7 },
126 #endif
127 #if (SRSS_NUM_CLKPATH > 8)
128 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 8 },
129 #endif
130 #if (SRSS_NUM_CLKPATH > 9)
131 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 9 },
132 #endif
133 #if (SRSS_NUM_CLKPATH > 10)
134 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 10 },
135 #endif
136 #if (SRSS_NUM_CLKPATH > 11)
137 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 11 },
138 #endif
139 #if (SRSS_NUM_CLKPATH > 12)
140 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 12 },
141 #endif
142 #if (SRSS_NUM_CLKPATH > 13)
143 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 13 },
144 #endif
145 #if (SRSS_NUM_CLKPATH > 14)
146 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 14 },
147 #endif
148 #if (SRSS_NUM_CLKPATH > 15)
149 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PATHMUX, 15 },
150 #endif
151 };
152
153 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_HF[SRSS_NUM_HFROOT] =
154 {
155 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 0 },
156 #if (SRSS_NUM_HFROOT > 1)
157 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 1 },
158 #endif
159 #if (SRSS_NUM_HFROOT > 2)
160 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 2 },
161 #endif
162 #if (SRSS_NUM_HFROOT > 3)
163 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 3 },
164 #endif
165 #if (SRSS_NUM_HFROOT > 4)
166 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 4 },
167 #endif
168 #if (SRSS_NUM_HFROOT > 5)
169 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 5 },
170 #endif
171 #if (SRSS_NUM_HFROOT > 6)
172 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 6 },
173 #endif
174 #if (SRSS_NUM_HFROOT > 7)
175 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 7 },
176 #endif
177 #if (SRSS_NUM_HFROOT > 8)
178 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 8 },
179 #endif
180 #if (SRSS_NUM_HFROOT > 9)
181 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 9 },
182 #endif
183 #if (SRSS_NUM_HFROOT > 10)
184 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 10 },
185 #endif
186 #if (SRSS_NUM_HFROOT > 11)
187 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 11 },
188 #endif
189 #if (SRSS_NUM_HFROOT > 12)
190 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 12 },
191 #endif
192 #if (SRSS_NUM_HFROOT > 13)
193 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 13 },
194 #endif
195 #if (SRSS_NUM_HFROOT > 14)
196 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 14 },
197 #endif
198 #if (SRSS_NUM_HFROOT > 15)
199 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_HF, 15 },
200 #endif
201 };
202
203 #if SRSS_ECO_PRESENT
204 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ECO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ECO, 0 };
205 #endif
206 #if SRSS_ALTHF_PRESENT
207 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALTHF = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ALTHF, 0 };
208 #endif
209 #if SRSS_ALTLF_PRESENT
210 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ALTLF = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ALTLF, 0 };
211 #endif
212 #if _CYHAL_SRSS_PILO_PRESENT
213 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PILO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PILO, 0 };
214 #endif
215 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
216 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_WCO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_WCO, 0 };
217 #endif
218 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
219 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MFO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_MFO, 0 };
220 #endif
221 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT) || defined(CY_IP_MXS22SRSS)
222 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_MF = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_MF, 0 };
223 #endif
224
225 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
226 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FLL = { CYHAL_RSC_CLOCK, CYHAL_CLOCK_BLOCK_FLL, 0 };
227 #endif
228
229 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
230 #if defined(COMPONENT_CAT1A)
231 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FAST = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_FAST, 0 };
232 #else
233 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_FAST[_CYHAL_SRSS_NUM_FAST] =
234 {
235 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_FAST, 0 },
236 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_FAST, 1 },
237 };
238 #endif
239 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_SLOW = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_SLOW, 0 };
240 #endif
241
242 #if defined(COMPONENT_CAT1A)
243 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PERI = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 0 };
244 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_TIMER = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_TIMER, 0 };
245 #if (_CYHAL_SRSS_NUM_PLL > 0)
246 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL[_CYHAL_SRSS_NUM_PLL] =
247 {
248 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 0 },
249 #if (_CYHAL_SRSS_NUM_PLL > 1)
250 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 1 },
251 #endif
252 #if (_CYHAL_SRSS_NUM_PLL > 2)
253 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 2 },
254 #endif
255 #if (_CYHAL_SRSS_NUM_PLL > 3)
256 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 3 },
257 #endif
258 #if (_CYHAL_SRSS_NUM_PLL > 4)
259 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 4 },
260 #endif
261 #if (_CYHAL_SRSS_NUM_PLL > 5)
262 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 5 },
263 #endif
264 #if (_CYHAL_SRSS_NUM_PLL > 6)
265 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 6 },
266 #endif
267 #if (_CYHAL_SRSS_NUM_PLL > 7)
268 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 7 },
269 #endif
270 #if (_CYHAL_SRSS_NUM_PLL > 8)
271 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 8 },
272 #endif
273 #if (_CYHAL_SRSS_NUM_PLL > 9)
274 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 9 },
275 #endif
276 #if (_CYHAL_SRSS_NUM_PLL > 10)
277 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 10 },
278 #endif
279 #if (_CYHAL_SRSS_NUM_PLL > 11)
280 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 11 },
281 #endif
282 #if (_CYHAL_SRSS_NUM_PLL > 12)
283 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 12 },
284 #endif
285 #if (_CYHAL_SRSS_NUM_PLL > 13)
286 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 13 },
287 #endif
288 #if (_CYHAL_SRSS_NUM_PLL > 14)
289 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL, 14 },
290 #endif
291 };
292 #endif
293 #endif
294
295 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
296 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
297 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_IHO = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_IHO, 0 };
298 #if SRSS_ECO_PRESENT
299 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_ECO_PRESCALER = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_ECO_PRESCALER, 0 };
300 #endif
301 #if SRSS_BACKUP_S40E_LPECO_PRESENT
302 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_LPECO_PRESCALER = { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_LPECO_PRESCALER, 0 };
303 #endif
304 #endif
305
306 /* COMPONENT_CAT1C uses a hybrid approach from what was done on CAT1A and CAT1B. Facelift CAT1C supports ClkPeri as well
307 as Peripheral Clock Groups. For CAT1C, ClkPeri is used to source everything in Peripheral Clock Group 0 (HF0) and other
308 Peripheral Clock Groups derive from one of the HFClks and have their own group divider. Thus we declare RSC_PERI Peri array for CAT1C */
309
310 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PERI[CY_PERI_GROUP_NR] =
311 {
312 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 0 },
313 #if (CY_PERI_GROUP_NR > 1)
314 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 1 },
315 #endif
316 #if (CY_PERI_GROUP_NR > 2)
317 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 2 },
318 #endif
319 #if (CY_PERI_GROUP_NR > 3)
320 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 3 },
321 #endif
322 #if (CY_PERI_GROUP_NR > 4)
323 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 4 },
324 #endif
325 #if (CY_PERI_GROUP_NR > 5)
326 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 5 },
327 #endif
328 #if (CY_PERI_GROUP_NR > 6)
329 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 6 },
330 #endif
331 #if (CY_PERI_GROUP_NR > 7)
332 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 7 },
333 #endif
334 #if (CY_PERI_GROUP_NR > 8)
335 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 8 },
336 #endif
337 #if (CY_PERI_GROUP_NR > 9)
338 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 9 },
339 #endif
340 #if (CY_PERI_GROUP_NR > 10)
341 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 10 },
342 #endif
343 #if (CY_PERI_GROUP_NR > 11)
344 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 11 },
345 #endif
346 #if (CY_PERI_GROUP_NR > 12)
347 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 12 },
348 #endif
349 #if (CY_PERI_GROUP_NR > 13)
350 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 13 },
351 #endif
352 #if (CY_PERI_GROUP_NR > 14)
353 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 14 },
354 #endif
355 #if (CY_PERI_GROUP_NR > 15)
356 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PERI, 15 },
357 #endif
358 };
359
360 #if (SRSS_NUM_PLL200M > 0)
361 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL200M[SRSS_NUM_PLL200M] =
362 {
363 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 0 },
364 #if (SRSS_NUM_PLL200M > 1)
365 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 1 },
366 #endif
367 #if (SRSS_NUM_PLL200M > 2)
368 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 2 },
369 #endif
370 #if (SRSS_NUM_PLL200M > 3)
371 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 3 },
372 #endif
373 #if (SRSS_NUM_PLL200M > 4)
374 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 4 },
375 #endif
376 #if (SRSS_NUM_PLL200M > 5)
377 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 5 },
378 #endif
379 #if (SRSS_NUM_PLL200M > 6)
380 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 6 },
381 #endif
382 #if (SRSS_NUM_PLL200M > 7)
383 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 7 },
384 #endif
385 #if (SRSS_NUM_PLL200M > 8)
386 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 8 },
387 #endif
388 #if (SRSS_NUM_PLL200M > 9)
389 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 9 },
390 #endif
391 #if (SRSS_NUM_PLL200M > 10)
392 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 10 },
393 #endif
394 #if (SRSS_NUM_PLL200M > 11)
395 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 11 },
396 #endif
397 #if (SRSS_NUM_PLL200M > 12)
398 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 12 },
399 #endif
400 #if (SRSS_NUM_PLL200M > 13)
401 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 13 },
402 #endif
403 #if (SRSS_NUM_PLL200M > 14)
404 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL200, 14 },
405 #endif
406 };
407 #endif
408
409 #if (SRSS_NUM_PLL400M > 0)
410 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_PLL400M[SRSS_NUM_PLL400M] =
411 {
412 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 0 },
413 #if (SRSS_NUM_PLL400M > 1)
414 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 1 },
415 #endif
416 #if (SRSS_NUM_PLL400M > 2)
417 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 2 },
418 #endif
419 #if (SRSS_NUM_PLL400M > 3)
420 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 3 },
421 #endif
422 #if (SRSS_NUM_PLL400M > 4)
423 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 4 },
424 #endif
425 #if (SRSS_NUM_PLL400M > 5)
426 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 5 },
427 #endif
428 #if (SRSS_NUM_PLL400M > 6)
429 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 6 },
430 #endif
431 #if (SRSS_NUM_PLL400M > 7)
432 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 7 },
433 #endif
434 #if (SRSS_NUM_PLL400M > 8)
435 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 8 },
436 #endif
437 #if (SRSS_NUM_PLL400M > 9)
438 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 9 },
439 #endif
440 #if (SRSS_NUM_PLL400M > 10)
441 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 10 },
442 #endif
443 #if (SRSS_NUM_PLL400M > 11)
444 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 11 },
445 #endif
446 #if (SRSS_NUM_PLL400M > 12)
447 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 12 },
448 #endif
449 #if (SRSS_NUM_PLL400M > 13)
450 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 13 },
451 #endif
452 #if (SRSS_NUM_PLL400M > 14)
453 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_PLL400, 14 },
454 #endif
455 };
456 #endif
457
458 #if (SRSS_NUM_DPLL250M > 0)
459 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_DPLL250M[SRSS_NUM_DPLL250M] =
460 {
461 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 0 },
462 #if (SRSS_NUM_DPLL250M > 1)
463 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 1 },
464 #endif
465 #if (SRSS_NUM_DPLL250M > 2)
466 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 2 },
467 #endif
468 #if (SRSS_NUM_DPLL250M > 3)
469 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 3 },
470 #endif
471 #if (SRSS_NUM_DPLL250M > 4)
472 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 4 },
473 #endif
474 #if (SRSS_NUM_DPLL250M > 5)
475 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 5 },
476 #endif
477 #if (SRSS_NUM_DPLL250M > 6)
478 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 6 },
479 #endif
480 #if (SRSS_NUM_DPLL250M > 7)
481 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 7 },
482 #endif
483 #if (SRSS_NUM_DPLL250M > 8)
484 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 8 },
485 #endif
486 #if (SRSS_NUM_DPLL250M > 9)
487 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 9 },
488 #endif
489 #if (SRSS_NUM_DPLL250M > 10)
490 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 10 },
491 #endif
492 #if (SRSS_NUM_DPLL250M > 11)
493 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 11 },
494 #endif
495 #if (SRSS_NUM_DPLL250M > 12)
496 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 12 },
497 #endif
498 #if (SRSS_NUM_DPLL250M > 13)
499 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 13 },
500 #endif
501 #if (SRSS_NUM_DPLL250M > 14)
502 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL250, 14 },
503 #endif
504 };
505 #endif
506
507 #if (SRSS_NUM_DPLL500M > 0)
508 const cyhal_resource_inst_t CYHAL_CLOCK_RSC_DPLL500M[SRSS_NUM_DPLL500M] =
509 {
510 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 0 },
511 #if (SRSS_NUM_DPLL500M > 1)
512 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 1 },
513 #endif
514 #if (SRSS_NUM_DPLL500M > 2)
515 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 2 },
516 #endif
517 #if (SRSS_NUM_DPLL500M > 3)
518 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 3 },
519 #endif
520 #if (SRSS_NUM_DPLL500M > 4)
521 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 4 },
522 #endif
523 #if (SRSS_NUM_DPLL500M > 5)
524 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 5 },
525 #endif
526 #if (SRSS_NUM_DPLL500M > 6)
527 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 6 },
528 #endif
529 #if (SRSS_NUM_DPLL500M > 7)
530 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 7 },
531 #endif
532 #if (SRSS_NUM_DPLL500M > 8)
533 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 8 },
534 #endif
535 #if (SRSS_NUM_DPLL500M > 9)
536 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 9 },
537 #endif
538 #if (SRSS_NUM_DPLL500M > 10)
539 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 10 },
540 #endif
541 #if (SRSS_NUM_DPLL500M > 11)
542 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 11 },
543 #endif
544 #if (SRSS_NUM_DPLL500M > 12)
545 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 12 },
546 #endif
547 #if (SRSS_NUM_DPLL500M > 13)
548 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 13 },
549 #endif
550 #if (SRSS_NUM_DPLL500M > 14)
551 { CYHAL_RSC_CLOCK, (uint8_t)CYHAL_CLOCK_BLOCK_DPLL500, 14 },
552 #endif
553 };
554 #endif
555
556 #if ((SRSS_NUM_PLL400M > 0) && (SRSS_NUM_PLL200M == 0))
557 #define CYHAL_CLOCK_RSC_PLL CYHAL_CLOCK_RSC_PLL400M
558 #elif ((SRSS_NUM_PLL400M == 0) && (SRSS_NUM_PLL200M > 0))
559 #define CYHAL_CLOCK_RSC_PLL CYHAL_CLOCK_RSC_PLL200M
560 #endif
561 #endif
562
563
564
565 /******************************************************************************
566 ***************************** Support Functions*******************************
567 *****************************************************************************/
568
_cyhal_clock_compute_div(uint64_t input_hz,uint32_t desired_hz,uint32_t divider_bits,const cyhal_clock_tolerance_t * tolerance,uint32_t * div)569 static cy_rslt_t _cyhal_clock_compute_div(uint64_t input_hz, uint32_t desired_hz, uint32_t divider_bits, const cyhal_clock_tolerance_t *tolerance, uint32_t *div)
570 {
571 uint32_t max_div = (1 << divider_bits);
572 *div = (input_hz + (desired_hz / 2)) / desired_hz;
573 if (*div > max_div)
574 *div = max_div;
575
576 uint32_t diff = (tolerance != NULL)
577 ? (uint32_t)abs(_cyhal_utils_calculate_tolerance(tolerance->type, desired_hz, input_hz / *div))
578 : 0;
579
580 return ((tolerance != NULL) && (diff > tolerance->value))
581 ? CYHAL_CLOCK_RSLT_ERR_FREQ
582 : CY_RSLT_SUCCESS;
583 }
584
_cyhal_clock_get_lf_frequency(void)585 static uint32_t _cyhal_clock_get_lf_frequency(void)
586 {
587 cy_en_clklf_in_sources_t source = Cy_SysClk_ClkLfGetSource();
588 switch (source)
589 {
590 case CY_SYSCLK_CLKLF_IN_ILO:
591 #if defined(COMPONENT_CAT1C)
592 case CY_SYSCLK_CLKLF_IN_ILO1:
593 #endif
594 return CY_SYSCLK_ILO_FREQ;
595 #if _CYHAL_SRSS_PILO_PRESENT
596 case CY_SYSCLK_CLKLF_IN_PILO:
597 return CY_SYSCLK_PILO_FREQ;
598 #endif
599 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
600 case CY_SYSCLK_CLKLF_IN_WCO:
601 return CY_SYSCLK_WCO_FREQ;
602 #endif
603 #if SRSS_ALTLF_PRESENT
604 case CY_SYSCLK_CLKLF_IN_ALTLF:
605 return Cy_SysClk_AltLfGetFrequency();
606 #endif
607 #if defined(COMPONENT_CAT1B)
608 #if SRSS_ECO_PRESENT
609 case CY_SYSCLK_CLKLF_IN_ECO_PRESCALER:
610 //return Cy_SysClk_EcoPrescalerGetFrequency();
611 return 0;
612 #endif
613 #if SRSS_BACKUP_S40E_LPECO_PRESENT
614 case CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER:
615 return Cy_SysClk_LpEcoPrescalerGetFrequency();
616 #endif
617 #endif
618 default:
619 CY_ASSERT(false);
620 return 0;
621 }
622 }
623
_cyhal_clock_update_system_state(bool before_change,uint32_t old_sysclk_freq_hz,uint32_t new_sysclk_freq_hz)624 static void _cyhal_clock_update_system_state(bool before_change, uint32_t old_sysclk_freq_hz, uint32_t new_sysclk_freq_hz)
625 {
626 // If increasing the clock frequency we need to update the speeds
627 // before the change. If decreasing the frequency we need to update
628 // after the change.
629 if ((before_change == (bool)(new_sysclk_freq_hz > old_sysclk_freq_hz)) ||
630 (!before_change == (new_sysclk_freq_hz < old_sysclk_freq_hz)))
631 {
632 #if defined(COMPONENT_CAT1A)
633 bool is_ulp = Cy_SysPm_IsSystemUlp();
634 #elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
635 bool is_ulp = true;
636 #elif defined(COMPONENT_CAT1C)
637 bool is_ulp = false;
638 #endif
639 Cy_SysLib_SetWaitStates(is_ulp, new_sysclk_freq_hz / 1000000);
640 }
641
642 // If after the change, update the clock
643 if (!before_change)
644 SystemCoreClockUpdate();
645 }
646
647
_cyhal_clock_set_enabled_unsupported(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)648 static cy_rslt_t _cyhal_clock_set_enabled_unsupported(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
649 {
650 CY_UNUSED_PARAMETER(clock);
651 CY_UNUSED_PARAMETER(enabled);
652 CY_UNUSED_PARAMETER(wait_for_lock);
653 CY_ASSERT(false); // Unhandled clock
654 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
655 }
_cyhal_clock_set_frequency_unsupported(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)656 static cy_rslt_t _cyhal_clock_set_frequency_unsupported(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
657 {
658 CY_UNUSED_PARAMETER(clock);
659 CY_UNUSED_PARAMETER(hz);
660 CY_UNUSED_PARAMETER(tolerance);
661 CY_ASSERT(false); // Unhandled clock
662 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
663 }
_cyhal_clock_set_divider_unsupported(cyhal_clock_t * clock,uint32_t divider)664 static cy_rslt_t _cyhal_clock_set_divider_unsupported(cyhal_clock_t *clock, uint32_t divider)
665 {
666 CY_UNUSED_PARAMETER(clock);
667 CY_UNUSED_PARAMETER(divider);
668 CY_ASSERT(false); // Unhandled clock
669 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
670 }
_cyhal_clock_set_source_unsupported(cyhal_clock_t * clock,const cyhal_clock_t * source)671 static cy_rslt_t _cyhal_clock_set_source_unsupported(cyhal_clock_t *clock, const cyhal_clock_t *source)
672 {
673 CY_UNUSED_PARAMETER(clock);
674 CY_UNUSED_PARAMETER(source);
675 CY_ASSERT(false); // Unhandled clock
676 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
677 }
_cyhal_clock_is_enabled_true(const cyhal_clock_t * clock)678 static bool _cyhal_clock_is_enabled_true(const cyhal_clock_t *clock)
679 {
680 CY_UNUSED_PARAMETER(clock);
681 return true;
682 }
_cyhal_clock_get_sources_none(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)683 static cy_rslt_t _cyhal_clock_get_sources_none(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
684 {
685 CY_UNUSED_PARAMETER(clock);
686 CY_UNUSED_PARAMETER(sources);
687 *count = 0;
688 return CY_RSLT_SUCCESS;
689 }
690
691
692 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_HF[] =
693 {
694 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
695 &CYHAL_CLOCK_RSC_FLL,
696 #endif
697 #if defined(COMPONENT_CAT1A)
698 #if (_CYHAL_SRSS_NUM_PLL > 0)
699 &CYHAL_CLOCK_RSC_PLL[0],
700 #endif
701 #if (_CYHAL_SRSS_NUM_PLL > 1)
702 &CYHAL_CLOCK_RSC_PLL[1],
703 #endif
704 #if (_CYHAL_SRSS_NUM_PLL > 2)
705 &CYHAL_CLOCK_RSC_PLL[2],
706 #endif
707 #if (_CYHAL_SRSS_NUM_PLL > 3)
708 &CYHAL_CLOCK_RSC_PLL[3],
709 #endif
710 #if (_CYHAL_SRSS_NUM_PLL > 4)
711 &CYHAL_CLOCK_RSC_PLL[4],
712 #endif
713 #if (_CYHAL_SRSS_NUM_PLL > 5)
714 &CYHAL_CLOCK_RSC_PLL[5],
715 #endif
716 #if (_CYHAL_SRSS_NUM_PLL > 6)
717 &CYHAL_CLOCK_RSC_PLL[6],
718 #endif
719 #if (_CYHAL_SRSS_NUM_PLL > 7)
720 &CYHAL_CLOCK_RSC_PLL[7],
721 #endif
722 #if (_CYHAL_SRSS_NUM_PLL > 8)
723 &CYHAL_CLOCK_RSC_PLL[8],
724 #endif
725 #if (_CYHAL_SRSS_NUM_PLL > 9)
726 &CYHAL_CLOCK_RSC_PLL[9],
727 #endif
728 #if (_CYHAL_SRSS_NUM_PLL > 10)
729 &CYHAL_CLOCK_RSC_PLL[10],
730 #endif
731 #if (_CYHAL_SRSS_NUM_PLL > 11)
732 &CYHAL_CLOCK_RSC_PLL[11],
733 #endif
734 #if (_CYHAL_SRSS_NUM_PLL > 12)
735 &CYHAL_CLOCK_RSC_PLL[12],
736 #endif
737 #if (_CYHAL_SRSS_NUM_PLL > 13)
738 &CYHAL_CLOCK_RSC_PLL[13],
739 #endif
740 #elif defined(COMPONENT_CAT1C)
741 #if (SRSS_NUM_PLL200M > 0)
742 &CYHAL_CLOCK_RSC_PLL200M[0],
743 #endif
744 #if (SRSS_NUM_PLL200M > 1)
745 &CYHAL_CLOCK_RSC_PLL200M[1],
746 #endif
747 #if (SRSS_NUM_PLL200M > 2)
748 &CYHAL_CLOCK_RSC_PLL200M[2],
749 #endif
750 #if (SRSS_NUM_PLL200M > 3)
751 &CYHAL_CLOCK_RSC_PLL200M[3],
752 #endif
753 #if (SRSS_NUM_PLL200M > 4)
754 &CYHAL_CLOCK_RSC_PLL200M[4],
755 #endif
756 #if (SRSS_NUM_PLL200M > 5)
757 &CYHAL_CLOCK_RSC_PLL200M[5],
758 #endif
759 #if (SRSS_NUM_PLL200M > 6)
760 &CYHAL_CLOCK_RSC_PLL200M[6],
761 #endif
762 #if (SRSS_NUM_PLL200M > 7)
763 &CYHAL_CLOCK_RSC_PLL200M[7],
764 #endif
765 #if (SRSS_NUM_PLL200M > 8)
766 &CYHAL_CLOCK_RSC_PLL200M[8],
767 #endif
768 #if (SRSS_NUM_PLL200M > 9)
769 &CYHAL_CLOCK_RSC_PLL200M[9],
770 #endif
771 #if (SRSS_NUM_PLL200M > 10)
772 &CYHAL_CLOCK_RSC_PLL200M[10],
773 #endif
774 #if (SRSS_NUM_PLL200M > 11)
775 &CYHAL_CLOCK_RSC_PLL200M[11],
776 #endif
777 #if (SRSS_NUM_PLL200M > 12)
778 &CYHAL_CLOCK_RSC_PLL200M[12],
779 #endif
780 #if (SRSS_NUM_PLL200M > 13)
781 &CYHAL_CLOCK_RSC_PLL200M[13],
782 #endif
783 #if (SRSS_NUM_PLL200M > 14)
784 &CYHAL_CLOCK_RSC_PLL200M[14],
785 #endif
786 #if (SRSS_NUM_PLL200M > 15)
787 &CYHAL_CLOCK_RSC_PLL200M[15],
788 #endif
789 #if (SRSS_NUM_PLL400M > 0)
790 &CYHAL_CLOCK_RSC_PLL400M[0],
791 #endif
792 #if (SRSS_NUM_PLL400M > 1)
793 &CYHAL_CLOCK_RSC_PLL400M[1],
794 #endif
795 #if (SRSS_NUM_PLL400M > 2)
796 &CYHAL_CLOCK_RSC_PLL400M[2],
797 #endif
798 #if (SRSS_NUM_PLL400M > 3)
799 &CYHAL_CLOCK_RSC_PLL400M[3],
800 #endif
801 #if (SRSS_NUM_PLL400M > 4)
802 &CYHAL_CLOCK_RSC_PLL400M[4],
803 #endif
804 #if (SRSS_NUM_PLL400M > 5)
805 &CYHAL_CLOCK_RSC_PLL400M[5],
806 #endif
807 #if (SRSS_NUM_PLL400M > 6)
808 &CYHAL_CLOCK_RSC_PLL400M[6],
809 #endif
810 #if (SRSS_NUM_PLL400M > 7)
811 &CYHAL_CLOCK_RSC_PLL400M[7],
812 #endif
813 #if (SRSS_NUM_PLL400M > 8)
814 &CYHAL_CLOCK_RSC_PLL400M[8],
815 #endif
816 #if (SRSS_NUM_PLL400M > 9)
817 &CYHAL_CLOCK_RSC_PLL400M[9],
818 #endif
819 #if (SRSS_NUM_PLL400M > 10)
820 &CYHAL_CLOCK_RSC_PLL400M[10],
821 #endif
822 #if (SRSS_NUM_PLL400M > 11)
823 &CYHAL_CLOCK_RSC_PLL400M[11],
824 #endif
825 #if (SRSS_NUM_PLL400M > 12)
826 &CYHAL_CLOCK_RSC_PLL400M[12],
827 #endif
828 #if (SRSS_NUM_PLL400M > 13)
829 &CYHAL_CLOCK_RSC_PLL400M[13],
830 #endif
831 #if (SRSS_NUM_PLL400M > 14)
832 &CYHAL_CLOCK_RSC_PLL400M[14],
833 #endif
834 #if (SRSS_NUM_PLL400M > 15)
835 &CYHAL_CLOCK_RSC_PLL400M[15],
836 #endif
837 #elif defined(COMPONENT_CAT1D)
838 #if (SRSS_NUM_DPLL250M > 0)
839 &CYHAL_CLOCK_RSC_DPLL250M[0],
840 #endif
841 #if (SRSS_NUM_DPLL250M > 1)
842 &CYHAL_CLOCK_RSC_DPLL250M[1],
843 #endif
844 #if (SRSS_NUM_DPLL250M > 2)
845 &CYHAL_CLOCK_RSC_DPLL250M[2],
846 #endif
847 #if (SRSS_NUM_DPLL250M > 3)
848 &CYHAL_CLOCK_RSC_DPLL250M[3],
849 #endif
850 #if (SRSS_NUM_DPLL250M > 4)
851 &CYHAL_CLOCK_RSC_DPLL250M[4],
852 #endif
853 #if (SRSS_NUM_DPLL250M > 5)
854 &CYHAL_CLOCK_RSC_DPLL250M[5],
855 #endif
856 #if (SRSS_NUM_DPLL250M > 6)
857 &CYHAL_CLOCK_RSC_DPLL250M[6],
858 #endif
859 #if (SRSS_NUM_DPLL250M > 7)
860 &CYHAL_CLOCK_RSC_DPLL250M[7],
861 #endif
862 #if (SRSS_NUM_DPLL250M > 8)
863 &CYHAL_CLOCK_RSC_DPLL250M[8],
864 #endif
865 #if (SRSS_NUM_DPLL250M > 9)
866 &CYHAL_CLOCK_RSC_DPLL250M[9],
867 #endif
868 #if (SRSS_NUM_DPLL250M > 10)
869 &CYHAL_CLOCK_RSC_DPLL250M[10],
870 #endif
871 #if (SRSS_NUM_DPLL250M > 11)
872 &CYHAL_CLOCK_RSC_DPLL250M[11],
873 #endif
874 #if (SRSS_NUM_DPLL250M > 12)
875 &CYHAL_CLOCK_RSC_DPLL250M[12],
876 #endif
877 #if (SRSS_NUM_DPLL250M > 13)
878 &CYHAL_CLOCK_RSC_DPLL250M[13],
879 #endif
880 #if (SRSS_NUM_DPLL250M > 14)
881 &CYHAL_CLOCK_RSC_DPLL250M[14],
882 #endif
883 #if (SRSS_NUM_DPLL250M > 15)
884 &CYHAL_CLOCK_RSC_DPLL250M[15],
885 #endif
886 #if (SRSS_NUM_DPLL500M > 0)
887 &CYHAL_CLOCK_RSC_DPLL500M[0],
888 #endif
889 #if (SRSS_NUM_DPLL500M > 1)
890 &CYHAL_CLOCK_RSC_DPLL500M[1],
891 #endif
892 #if (SRSS_NUM_DPLL500M > 2)
893 &CYHAL_CLOCK_RSC_DPLL500M[2],
894 #endif
895 #if (SRSS_NUM_DPLL500M > 3)
896 &CYHAL_CLOCK_RSC_DPLL500M[3],
897 #endif
898 #if (SRSS_NUM_DPLL500M > 4)
899 &CYHAL_CLOCK_RSC_DPLL500M[4],
900 #endif
901 #if (SRSS_NUM_DPLL500M > 5)
902 &CYHAL_CLOCK_RSC_DPLL500M[5],
903 #endif
904 #if (SRSS_NUM_DPLL500M > 6)
905 &CYHAL_CLOCK_RSC_DPLL500M[6],
906 #endif
907 #if (SRSS_NUM_DPLL500M > 7)
908 &CYHAL_CLOCK_RSC_DPLL500M[7],
909 #endif
910 #if (SRSS_NUM_DPLL500M > 8)
911 &CYHAL_CLOCK_RSC_DPLL500M[8],
912 #endif
913 #if (SRSS_NUM_DPLL500M > 9)
914 &CYHAL_CLOCK_RSC_DPLL500M[9],
915 #endif
916 #if (SRSS_NUM_DPLL500M > 10)
917 &CYHAL_CLOCK_RSC_DPLL500M[10],
918 #endif
919 #if (SRSS_NUM_DPLL500M > 11)
920 &CYHAL_CLOCK_RSC_DPLL500M[11],
921 #endif
922 #if (SRSS_NUM_DPLL500M > 12)
923 &CYHAL_CLOCK_RSC_DPLL500M[12],
924 #endif
925 #if (SRSS_NUM_DPLL500M > 13)
926 &CYHAL_CLOCK_RSC_DPLL500M[13],
927 #endif
928 #if (SRSS_NUM_DPLL500M > 14)
929 &CYHAL_CLOCK_RSC_DPLL500M[14],
930 #endif
931 #if (SRSS_NUM_DPLL500M > 15)
932 &CYHAL_CLOCK_RSC_DPLL500M[15],
933 #endif
934 #endif
935 &CYHAL_CLOCK_RSC_PATHMUX[0],
936 #if (SRSS_NUM_CLKPATH > 1)
937 &CYHAL_CLOCK_RSC_PATHMUX[1],
938 #endif
939 #if (SRSS_NUM_CLKPATH > 2)
940 &CYHAL_CLOCK_RSC_PATHMUX[2],
941 #endif
942 #if (SRSS_NUM_CLKPATH > 3)
943 &CYHAL_CLOCK_RSC_PATHMUX[3],
944 #endif
945 #if (SRSS_NUM_CLKPATH > 4)
946 &CYHAL_CLOCK_RSC_PATHMUX[4],
947 #endif
948 #if (SRSS_NUM_CLKPATH > 5)
949 &CYHAL_CLOCK_RSC_PATHMUX[5],
950 #endif
951 #if (SRSS_NUM_CLKPATH > 6)
952 &CYHAL_CLOCK_RSC_PATHMUX[6],
953 #endif
954 #if (SRSS_NUM_CLKPATH > 7)
955 &CYHAL_CLOCK_RSC_PATHMUX[7],
956 #endif
957 #if (SRSS_NUM_CLKPATH > 8)
958 &CYHAL_CLOCK_RSC_PATHMUX[8],
959 #endif
960 #if (SRSS_NUM_CLKPATH > 9)
961 &CYHAL_CLOCK_RSC_PATHMUX[9],
962 #endif
963 #if (SRSS_NUM_CLKPATH > 10)
964 &CYHAL_CLOCK_RSC_PATHMUX[10],
965 #endif
966 #if (SRSS_NUM_CLKPATH > 11)
967 &CYHAL_CLOCK_RSC_PATHMUX[11],
968 #endif
969 #if (SRSS_NUM_CLKPATH > 12)
970 &CYHAL_CLOCK_RSC_PATHMUX[12],
971 #endif
972 #if (SRSS_NUM_CLKPATH > 13)
973 &CYHAL_CLOCK_RSC_PATHMUX[13],
974 #endif
975 #if (SRSS_NUM_CLKPATH > 14)
976 &CYHAL_CLOCK_RSC_PATHMUX[14],
977 #endif
978 #if (SRSS_NUM_CLKPATH > 15)
979 &CYHAL_CLOCK_RSC_PATHMUX[15],
980 #endif
981 };
982
983 #if defined (COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
_cyhal_clock_get_sources_peri_peripheral(uint8_t idx,const cyhal_resource_inst_t ** sources[],uint32_t * count)984 static cy_rslt_t _cyhal_clock_get_sources_peri_peripheral(uint8_t idx, const cyhal_resource_inst_t **sources[], uint32_t *count)
985 {
986 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_PERI[SRSS_NUM_HFROOT] =
987 {
988 &CYHAL_CLOCK_RSC_HF[0],
989 #if (SRSS_NUM_HFROOT > 1)
990 &CYHAL_CLOCK_RSC_HF[1],
991 #endif
992 #if (SRSS_NUM_HFROOT > 2)
993 &CYHAL_CLOCK_RSC_HF[2],
994 #endif
995 #if (SRSS_NUM_HFROOT > 3)
996 &CYHAL_CLOCK_RSC_HF[3],
997 #endif
998 #if (SRSS_NUM_HFROOT > 4)
999 &CYHAL_CLOCK_RSC_HF[4],
1000 #endif
1001 #if (SRSS_NUM_HFROOT > 5)
1002 &CYHAL_CLOCK_RSC_HF[5],
1003 #endif
1004 #if (SRSS_NUM_HFROOT > 6)
1005 &CYHAL_CLOCK_RSC_HF[6],
1006 #endif
1007 #if (SRSS_NUM_HFROOT > 7)
1008 &CYHAL_CLOCK_RSC_HF[7],
1009 #endif
1010 #if (SRSS_NUM_HFROOT > 8)
1011 &CYHAL_CLOCK_RSC_HF[8],
1012 #endif
1013 #if (SRSS_NUM_HFROOT > 9)
1014 &CYHAL_CLOCK_RSC_HF[9],
1015 #endif
1016 #if (SRSS_NUM_HFROOT > 10)
1017 &CYHAL_CLOCK_RSC_HF[10],
1018 #endif
1019 #if (SRSS_NUM_HFROOT > 11)
1020 &CYHAL_CLOCK_RSC_HF[11],
1021 #endif
1022 #if (SRSS_NUM_HFROOT > 12)
1023 &CYHAL_CLOCK_RSC_HF[12],
1024 #endif
1025 #if (SRSS_NUM_HFROOT > 13)
1026 &CYHAL_CLOCK_RSC_HF[13],
1027 #endif
1028 #if (SRSS_NUM_HFROOT > 14)
1029 &CYHAL_CLOCK_RSC_HF[14],
1030 #endif
1031 #if (SRSS_NUM_HFROOT > 15)
1032 &CYHAL_CLOCK_RSC_HF[15],
1033 #endif
1034 };
1035
1036 *sources = &(_CYHAL_CLOCK_SOURCE_PERI[idx]);
1037 *count = 1;
1038 return CY_RSLT_SUCCESS;
1039 }
1040 #endif
1041
1042
1043 // IMO
1044 #if !defined(COMPONENT_CAT1D)
_cyhal_clock_get_frequency_imo(const cyhal_clock_t * clock)1045 static uint32_t _cyhal_clock_get_frequency_imo(const cyhal_clock_t *clock)
1046 {
1047 CY_UNUSED_PARAMETER(clock);
1048 return CY_SYSCLK_IMO_FREQ;
1049 }
1050 #endif
1051
1052
1053 // ECO
1054 #if SRSS_ECO_PRESENT
_cyhal_clock_is_enabled_eco(const cyhal_clock_t * clock)1055 static bool _cyhal_clock_is_enabled_eco(const cyhal_clock_t *clock)
1056 {
1057 CY_UNUSED_PARAMETER(clock);
1058 return 0u != (SRSS_CLK_ECO_CONFIG & SRSS_CLK_ECO_CONFIG_ECO_EN_Msk);
1059 }
_cyhal_clock_set_enabled_eco(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1060 static cy_rslt_t _cyhal_clock_set_enabled_eco(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1061 {
1062 CY_UNUSED_PARAMETER(clock);
1063
1064 if (enabled)
1065 {
1066 if (0u != (SRSS_CLK_ECO_CONFIG & SRSS_CLK_ECO_CONFIG_ECO_EN_Msk))
1067 {
1068 // Already enabled
1069 if (wait_for_lock)
1070 {
1071 for (int t = 0; t < 3 && Cy_SysClk_EcoGetStatus() != CY_SYSCLK_ECOSTAT_STABLE; ++t)
1072 {
1073 cyhal_system_delay_us(1000UL);
1074 }
1075 return Cy_SysClk_EcoGetStatus() == CY_SYSCLK_ECOSTAT_STABLE
1076 ? CY_RSLT_SUCCESS
1077 : CY_SYSCLK_TIMEOUT;
1078 }
1079 return CY_RSLT_SUCCESS;
1080 }
1081 else
1082 {
1083 return Cy_SysClk_EcoEnable(wait_for_lock ? 3000UL : 0UL);
1084 }
1085 }
1086 else
1087 {
1088 Cy_SysClk_EcoDisable();
1089 return CY_RSLT_SUCCESS;
1090 }
1091 }
_cyhal_clock_get_frequency_eco(const cyhal_clock_t * clock)1092 static uint32_t _cyhal_clock_get_frequency_eco(const cyhal_clock_t *clock)
1093 {
1094 CY_UNUSED_PARAMETER(clock);
1095 return Cy_SysClk_EcoGetFrequency();
1096 }
1097 #endif
1098
1099 // EXT
_cyhal_clock_is_enabled_ext(const cyhal_clock_t * clock)1100 static bool _cyhal_clock_is_enabled_ext(const cyhal_clock_t *clock)
1101 {
1102 CY_UNUSED_PARAMETER(clock);
1103 return (Cy_SysClk_ExtClkGetFrequency() > 0);
1104 }
_cyhal_clock_get_frequency_ext(const cyhal_clock_t * clock)1105 static uint32_t _cyhal_clock_get_frequency_ext(const cyhal_clock_t *clock)
1106 {
1107 CY_UNUSED_PARAMETER(clock);
1108 return Cy_SysClk_ExtClkGetFrequency();
1109 }
_cyhal_clock_set_frequency_ext(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)1110 static cy_rslt_t _cyhal_clock_set_frequency_ext(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
1111 {
1112 CY_UNUSED_PARAMETER(clock);
1113 CY_UNUSED_PARAMETER(tolerance);
1114
1115 Cy_SysClk_ExtClkSetFrequency(hz);
1116 return CY_RSLT_SUCCESS;
1117 }
1118
1119 // ALTHF
1120 #if SRSS_ALTHF_PRESENT
_cyhal_clock_is_enabled_althf(const cyhal_clock_t * clock)1121 static bool _cyhal_clock_is_enabled_althf(const cyhal_clock_t *clock)
1122 {
1123 CY_UNUSED_PARAMETER(clock);
1124 return (Cy_SysClk_AltHfGetFrequency() > 0);
1125 }
_cyhal_clock_get_frequency_althf(const cyhal_clock_t * clock)1126 static uint32_t _cyhal_clock_get_frequency_althf(const cyhal_clock_t *clock)
1127 {
1128 CY_UNUSED_PARAMETER(clock);
1129 return Cy_SysClk_AltHfGetFrequency();
1130 }
1131 #endif
1132
1133 // ALTLF
1134 #if SRSS_ALTLF_PRESENT
_cyhal_clock_is_enabled_altlf(const cyhal_clock_t * clock)1135 static bool _cyhal_clock_is_enabled_altlf(const cyhal_clock_t *clock)
1136 {
1137 CY_UNUSED_PARAMETER(clock);
1138 return Cy_SysClk_AltLfIsEnabled();
1139 }
_cyhal_clock_get_frequency_altlf(const cyhal_clock_t * clock)1140 static uint32_t _cyhal_clock_get_frequency_altlf(const cyhal_clock_t *clock)
1141 {
1142 CY_UNUSED_PARAMETER(clock);
1143 return Cy_SysClk_AltLfGetFrequency();
1144 }
1145 #endif
1146
1147 // IHO
1148 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
_cyhal_clock_is_enabled_iho(const cyhal_clock_t * clock)1149 static bool _cyhal_clock_is_enabled_iho(const cyhal_clock_t *clock)
1150 {
1151 CY_UNUSED_PARAMETER(clock);
1152 return Cy_SysClk_IhoIsEnabled();
1153 }
_cyhal_clock_set_enabled_iho(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1154 static cy_rslt_t _cyhal_clock_set_enabled_iho(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1155 {
1156 CY_UNUSED_PARAMETER(clock);
1157 CY_UNUSED_PARAMETER(wait_for_lock);
1158
1159 if (enabled)
1160 Cy_SysClk_IhoEnable();
1161 else
1162 Cy_SysClk_IhoDisable();
1163 return CY_RSLT_SUCCESS;
1164 }
_cyhal_clock_get_frequency_iho(const cyhal_clock_t * clock)1165 static uint32_t _cyhal_clock_get_frequency_iho(const cyhal_clock_t *clock)
1166 {
1167 CY_UNUSED_PARAMETER(clock);
1168 return CY_SYSCLK_IHO_FREQ;
1169 }
1170 #endif
1171
1172 // ILO
1173 #if _CYHAL_SRSS_ILO_PRESENT
_cyhal_clock_is_enabled_ilo(const cyhal_clock_t * clock)1174 static bool _cyhal_clock_is_enabled_ilo(const cyhal_clock_t *clock)
1175 {
1176 CY_UNUSED_PARAMETER(clock);
1177 #if defined(COMPONENT_CAT1C)
1178 return Cy_SysClk_IloSrcIsEnabled(clock->channel);
1179 #else
1180 return Cy_SysClk_IloIsEnabled();
1181 #endif
1182 }
_cyhal_clock_set_enabled_ilo(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1183 static cy_rslt_t _cyhal_clock_set_enabled_ilo(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1184 {
1185 CY_UNUSED_PARAMETER(clock);
1186 CY_UNUSED_PARAMETER(wait_for_lock);
1187 #if defined(COMPONENT_CAT1C)
1188 if (enabled)
1189 {
1190 Cy_SysPm_BgRefCtrl(true);
1191 Cy_WDT_Unlock();
1192 Cy_SysClk_IloSrcEnable(clock->channel);
1193 Cy_WDT_Lock();
1194 }
1195 else
1196 {
1197 Cy_SysPm_BgRefCtrl(false);
1198 Cy_WDT_Unlock();
1199 Cy_SysClk_IloSrcDisable(clock->channel);
1200 Cy_WDT_Lock();
1201 }
1202 #else
1203 if (enabled)
1204 Cy_SysClk_IloEnable();
1205 else
1206 Cy_SysClk_IloDisable();
1207 #endif
1208 return CY_RSLT_SUCCESS;
1209 }
_cyhal_clock_get_frequency_ilo(const cyhal_clock_t * clock)1210 static uint32_t _cyhal_clock_get_frequency_ilo(const cyhal_clock_t *clock)
1211 {
1212 CY_UNUSED_PARAMETER(clock);
1213 return CY_SYSCLK_ILO_FREQ;
1214 }
1215 #endif
1216
1217 // PILO
1218 #if _CYHAL_SRSS_PILO_PRESENT
_cyhal_clock_is_enabled_pilo(const cyhal_clock_t * clock)1219 static bool _cyhal_clock_is_enabled_pilo(const cyhal_clock_t *clock)
1220 {
1221 CY_UNUSED_PARAMETER(clock);
1222 return Cy_SysClk_PiloIsEnabled();
1223 }
_cyhal_clock_set_enabled_pilo(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1224 static cy_rslt_t _cyhal_clock_set_enabled_pilo(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1225 {
1226 CY_UNUSED_PARAMETER(clock);
1227 CY_UNUSED_PARAMETER(wait_for_lock);
1228
1229 if (enabled)
1230 Cy_SysClk_PiloEnable();
1231 else
1232 Cy_SysClk_PiloDisable();
1233 return CY_RSLT_SUCCESS;
1234 }
_cyhal_clock_get_frequency_pilo(const cyhal_clock_t * clock)1235 static uint32_t _cyhal_clock_get_frequency_pilo(const cyhal_clock_t *clock)
1236 {
1237 CY_UNUSED_PARAMETER(clock);
1238 return CY_SYSCLK_PILO_FREQ;
1239 }
1240 #endif
1241
1242 // WCO
1243 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
_cyhal_clock_is_enabled_wco(const cyhal_clock_t * clock)1244 static bool _cyhal_clock_is_enabled_wco(const cyhal_clock_t *clock)
1245 {
1246 CY_UNUSED_PARAMETER(clock);
1247 #if defined(CY_IP_MXS28SRSS)
1248 return 0u != (BACKUP_CTL & BACKUP_WCO_CTL_WCO_EN_Msk);
1249 #elif defined (CY_IP_MXS22SRSS)
1250 return 0u != (BACKUP_CTL & SRSS_CLK_WCO_CONFIG_WCO_EN_Msk);
1251 #else
1252 return 0u != (BACKUP_CTL & BACKUP_CTL_WCO_EN_Msk);
1253 #endif
1254 }
_cyhal_clock_set_enabled_wco(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1255 static cy_rslt_t _cyhal_clock_set_enabled_wco(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1256 {
1257 CY_UNUSED_PARAMETER(clock);
1258
1259 if (enabled)
1260 {
1261 cy_rslt_t rslt = Cy_SysClk_WcoEnable(wait_for_lock ? 1000000UL : 0UL);
1262 // Ignore CY_SYSCLK_TIMEOUT unless wait_for_lock is true
1263 return wait_for_lock ? rslt : CY_RSLT_SUCCESS;
1264 }
1265 else
1266 {
1267 Cy_SysClk_WcoDisable();
1268 return CY_RSLT_SUCCESS;
1269 }
1270 }
_cyhal_clock_get_frequency_wco(const cyhal_clock_t * clock)1271 static uint32_t _cyhal_clock_get_frequency_wco(const cyhal_clock_t *clock)
1272 {
1273 CY_UNUSED_PARAMETER(clock);
1274 return CY_SYSCLK_WCO_FREQ;
1275 }
1276 #endif
1277
1278 // MFO
1279 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
_cyhal_clock_is_enabled_mfo(const cyhal_clock_t * clock)1280 static bool _cyhal_clock_is_enabled_mfo(const cyhal_clock_t *clock)
1281 {
1282 CY_UNUSED_PARAMETER(clock);
1283 return Cy_SysClk_MfoIsEnabled();
1284 }
_cyhal_clock_set_enabled_mfo(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1285 static cy_rslt_t _cyhal_clock_set_enabled_mfo(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1286 {
1287 CY_UNUSED_PARAMETER(clock);
1288 CY_UNUSED_PARAMETER(wait_for_lock);
1289
1290 if (enabled)
1291 // Enable the MFO but turn it off during deepsleep to reduce power consumption
1292 Cy_SysClk_MfoEnable(false);
1293 else
1294 Cy_SysClk_MfoDisable();
1295 return CY_RSLT_SUCCESS;
1296 }
_cyhal_clock_get_frequency_mfo(const cyhal_clock_t * clock)1297 static uint32_t _cyhal_clock_get_frequency_mfo(const cyhal_clock_t *clock)
1298 {
1299 CY_UNUSED_PARAMETER(clock);
1300 return CY_SYSCLK_MFO_FREQ;
1301 }
_cyhal_clock_get_sources_mfo(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)1302 static cy_rslt_t _cyhal_clock_get_sources_mfo(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
1303 {
1304 CY_UNUSED_PARAMETER(clock);
1305
1306 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_MFO[] =
1307 {
1308 &CYHAL_CLOCK_RSC_IMO,
1309 };
1310
1311 *sources = _CYHAL_CLOCK_SOURCE_MFO;
1312 *count = sizeof(_CYHAL_CLOCK_SOURCE_MFO) / sizeof(_CYHAL_CLOCK_SOURCE_MFO[0]);
1313 return CY_RSLT_SUCCESS;
1314 }
1315 #endif
1316
1317 // PathMux
_cyhal_clock_get_frequency_pathmux(const cyhal_clock_t * clock)1318 static uint32_t _cyhal_clock_get_frequency_pathmux(const cyhal_clock_t *clock)
1319 {
1320 return Cy_SysClk_ClkPathMuxGetFrequency(clock->channel);
1321 }
_cyhal_clock_get_sources_pathmux(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)1322 static cy_rslt_t _cyhal_clock_get_sources_pathmux(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
1323 {
1324 CY_UNUSED_PARAMETER(clock);
1325
1326 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_PATHMUX[] =
1327 {
1328 #if !defined(COMPONENT_CAT1D)
1329 &CYHAL_CLOCK_RSC_IMO,
1330 #endif
1331 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
1332 &CYHAL_CLOCK_RSC_IHO,
1333 #endif
1334 #if SRSS_ECO_PRESENT
1335 &CYHAL_CLOCK_RSC_ECO,
1336 #endif
1337 &CYHAL_CLOCK_RSC_EXT,
1338 #if SRSS_ALTHF_PRESENT
1339 &CYHAL_CLOCK_RSC_ALTHF,
1340 #endif
1341 #if (_CYHAL_SRSS_ILO_PRESENT)
1342 #if defined(COMPONENT_CAT1C)
1343 &CYHAL_CLOCK_RSC_ILO[0],
1344 #if (SRSS_HT_VARIANT > 0)
1345 &CYHAL_CLOCK_RSC_ILO[1],
1346 #endif
1347 #elif !defined(COMPONENT_CAT1D)
1348 &CYHAL_CLOCK_RSC_ILO,
1349 #endif
1350 #endif
1351 #if _CYHAL_SRSS_PILO_PRESENT
1352 &CYHAL_CLOCK_RSC_PILO,
1353 #endif
1354 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
1355 &CYHAL_CLOCK_RSC_WCO,
1356 #endif
1357 #if SRSS_ALTLF_PRESENT
1358 &CYHAL_CLOCK_RSC_ALTLF,
1359 #endif
1360 };
1361
1362 *sources = _CYHAL_CLOCK_SOURCE_PATHMUX;
1363 *count = sizeof(_CYHAL_CLOCK_SOURCE_PATHMUX) / sizeof(_CYHAL_CLOCK_SOURCE_PATHMUX[0]);
1364 return CY_RSLT_SUCCESS;
1365 }
1366
_cyhal_clock_set_source_pathmux(cyhal_clock_t * clock,const cyhal_clock_t * source)1367 static cy_rslt_t _cyhal_clock_set_source_pathmux(cyhal_clock_t *clock, const cyhal_clock_t *source)
1368 {
1369 uint32_t new_freq;
1370 cy_en_clkpath_in_sources_t clkpath_src;
1371 switch (source->block)
1372 {
1373 #if !defined(COMPONENT_CAT1D)
1374 case CYHAL_CLOCK_BLOCK_IMO:
1375 clkpath_src = CY_SYSCLK_CLKPATH_IN_IMO;
1376 new_freq = CY_SYSCLK_IMO_FREQ;
1377 break;
1378 #endif
1379 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
1380 case CYHAL_CLOCK_BLOCK_IHO:
1381 clkpath_src = CY_SYSCLK_CLKPATH_IN_IHO;
1382 new_freq = CY_SYSCLK_IHO_FREQ;
1383 break;
1384 #endif
1385 case CYHAL_CLOCK_BLOCK_EXT:
1386 clkpath_src = CY_SYSCLK_CLKPATH_IN_EXT;
1387 new_freq = Cy_SysClk_ExtClkGetFrequency();
1388 break;
1389 #if SRSS_ECO_PRESENT
1390 case CYHAL_CLOCK_BLOCK_ECO:
1391 clkpath_src = CY_SYSCLK_CLKPATH_IN_ECO;
1392 new_freq = Cy_SysClk_EcoGetFrequency();
1393 break;
1394 #endif
1395 #if SRSS_ALTHF_PRESENT
1396 case CYHAL_CLOCK_BLOCK_ALTHF:
1397 clkpath_src = CY_SYSCLK_CLKPATH_IN_ALTHF;
1398 new_freq = Cy_SysClk_AltHfGetFrequency();
1399 break;
1400 #endif
1401 #if !defined(COMPONENT_CAT1D)
1402 case CYHAL_CLOCK_BLOCK_ILO:
1403 #if defined(COMPONENT_CAT1C)
1404 if (1 == source->channel)
1405 {
1406 clkpath_src = CY_SYSCLK_CLKPATH_IN_ILO1;
1407 new_freq = CY_SYSCLK_ILO_FREQ;
1408 }
1409 else
1410 #endif
1411 {
1412 clkpath_src = CY_SYSCLK_CLKPATH_IN_ILO;
1413 new_freq = CY_SYSCLK_ILO_FREQ;
1414 }
1415 break;
1416 #endif
1417 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
1418 case CYHAL_CLOCK_BLOCK_WCO:
1419 clkpath_src = CY_SYSCLK_CLKPATH_IN_WCO;
1420 new_freq = CY_SYSCLK_WCO_FREQ;
1421 break;
1422 #endif
1423 #if SRSS_ALTLF_PRESENT
1424 case CYHAL_CLOCK_BLOCK_ALTLF:
1425 clkpath_src = CY_SYSCLK_CLKPATH_IN_ALTLF;
1426 new_freq = Cy_SysClk_AltLfGetFrequency();
1427 break;
1428 #endif
1429 #if _CYHAL_SRSS_PILO_PRESENT
1430 case CYHAL_CLOCK_BLOCK_PILO:
1431 clkpath_src = CY_SYSCLK_CLKPATH_IN_PILO;
1432 new_freq = CY_SYSCLK_PILO_FREQ;
1433 break;
1434 #endif
1435 default:
1436 CY_ASSERT(false); //Unhandled clock
1437 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
1438 }
1439
1440 uint32_t old_hf_freq = Cy_SysClk_ClkHfGetFrequency(0);
1441 uint32_t new_hf_freq = new_freq >> ((uint8_t)Cy_SysClk_ClkHfGetDivider(0));
1442 bool is_sysclk_path = (clock->channel == (uint32_t)Cy_SysClk_ClkHfGetSource(0));
1443
1444 if (is_sysclk_path)
1445 _cyhal_clock_update_system_state(true, old_hf_freq, new_hf_freq);
1446
1447 cy_rslt_t rslt = Cy_SysClk_ClkPathSetSource(clock->channel, clkpath_src);
1448
1449 if (is_sysclk_path)
1450 {
1451 if (CY_RSLT_SUCCESS == rslt)
1452 _cyhal_clock_update_system_state(false, old_hf_freq, new_hf_freq);
1453 else // revert the change if there was one
1454 _cyhal_clock_update_system_state(false, new_hf_freq, old_hf_freq);
1455 }
1456
1457 return rslt;
1458 }
1459
1460
1461 // FLL
1462 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
_cyhal_clock_is_enabled_fll(const cyhal_clock_t * clock)1463 static bool _cyhal_clock_is_enabled_fll(const cyhal_clock_t *clock)
1464 {
1465 CY_UNUSED_PARAMETER(clock);
1466 return Cy_SysClk_FllIsEnabled();
1467 }
_cyhal_clock_set_enabled_fll(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1468 static cy_rslt_t _cyhal_clock_set_enabled_fll(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1469 {
1470 CY_UNUSED_PARAMETER(clock);
1471 CY_UNUSED_PARAMETER(wait_for_lock);
1472
1473 cy_stc_fll_manual_config_t cfg;
1474 Cy_SysClk_FllGetConfiguration(&cfg);
1475 uint32_t new_freq, old_freq;
1476 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0);
1477 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(0);
1478 uint32_t fll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.refDiv * ((cfg.enableOutputDiv) ? 2UL : 1UL));
1479 if (enabled)
1480 {
1481 new_freq = fll_freq >> div;
1482 old_freq = src_freq >> div;
1483 }
1484 else
1485 {
1486 new_freq = src_freq >> div;
1487 old_freq = fll_freq >> div;
1488 }
1489
1490 bool fll_sources_hf0 = (0 == (uint32_t)Cy_SysClk_ClkHfGetSource(0));
1491 if (fll_sources_hf0)
1492 _cyhal_clock_update_system_state(true, old_freq, new_freq);
1493
1494 cy_rslt_t rslt = (enabled)
1495 ? Cy_SysClk_FllEnable(wait_for_lock ? _CYHAL_CLOCK_FLL_LOCK_TIME : 0UL)
1496 : Cy_SysClk_FllDisable();
1497
1498 if (fll_sources_hf0)
1499 {
1500 if (CY_RSLT_SUCCESS == rslt)
1501 _cyhal_clock_update_system_state(false, old_freq, new_freq);
1502 else // revert the change if there was one
1503 _cyhal_clock_update_system_state(false, new_freq, old_freq);
1504 }
1505
1506 return rslt;
1507 }
_cyhal_clock_get_frequency_fll(const cyhal_clock_t * clock)1508 static uint32_t _cyhal_clock_get_frequency_fll(const cyhal_clock_t *clock)
1509 {
1510 CY_UNUSED_PARAMETER(clock);
1511 return Cy_SysClk_ClkPathGetFrequency(0);
1512 }
_cyhal_clock_set_frequency_fll(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)1513 static cy_rslt_t _cyhal_clock_set_frequency_fll(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
1514 {
1515 CY_UNUSED_PARAMETER(clock);
1516 CY_UNUSED_PARAMETER(tolerance);
1517
1518 cy_rslt_t rslt = CY_RSLT_SUCCESS;
1519 cy_stc_fll_manual_config_t cfg;
1520 Cy_SysClk_FllGetConfiguration(&cfg);
1521 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(0);
1522
1523 if (0 == src_freq)
1524 rslt = CYHAL_CLOCK_RSLT_ERR_SOURCE;
1525 else
1526 {
1527 uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.refDiv * ((cfg.enableOutputDiv) ? 2UL : 1UL));
1528 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0);
1529 uint32_t old_hf_freq = old_freq >> div;
1530 uint32_t new_hf_freq = hz /*new_freq*/ >> div;
1531
1532 bool fll_sources_hf0 = (0 == (uint32_t)Cy_SysClk_ClkHfGetSource(0));
1533 if (fll_sources_hf0)
1534 _cyhal_clock_update_system_state(true, old_hf_freq, new_hf_freq);
1535
1536 bool enabled = Cy_SysClk_FllIsEnabled();
1537 if (enabled)
1538 rslt = Cy_SysClk_FllDisable();
1539 if (CY_RSLT_SUCCESS == rslt)
1540 {
1541 rslt = Cy_SysClk_FllConfigure(src_freq, hz/*new_freq*/, CY_SYSCLK_FLLPLL_OUTPUT_AUTO);
1542
1543 if (enabled)
1544 {
1545 cy_rslt_t rslt2 = Cy_SysClk_FllEnable(_CYHAL_CLOCK_FLL_LOCK_TIME);
1546 if (CY_RSLT_SUCCESS == rslt)
1547 rslt = rslt2;
1548 }
1549 }
1550
1551 if (fll_sources_hf0)
1552 {
1553 if (CY_RSLT_SUCCESS == rslt)
1554 _cyhal_clock_update_system_state(false, old_hf_freq, new_hf_freq);
1555 else // revert the change if there was one
1556 _cyhal_clock_update_system_state(false, new_hf_freq, old_hf_freq);
1557 }
1558 }
1559
1560 return rslt;
1561 }
_cyhal_clock_get_sources_fll(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)1562 static cy_rslt_t _cyhal_clock_get_sources_fll(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
1563 {
1564 CY_UNUSED_PARAMETER(clock);
1565 *sources = &(_CYHAL_CLOCK_SOURCE_HF[1 + _CYHAL_SRSS_NUM_PLL]);
1566 *count = 1;
1567 return CY_RSLT_SUCCESS;
1568 }
1569 #endif
1570
1571 // PLL
1572 #if (_CYHAL_SRSS_NUM_PLL > 0)
_cyhal_clock_is_enabled_pll(const cyhal_clock_t * clock)1573 static bool _cyhal_clock_is_enabled_pll(const cyhal_clock_t *clock)
1574 {
1575 #if defined(COMPONENT_CAT1C)
1576 if (clock->block == CYHAL_CLOCK_BLOCK_PLL200)
1577 {
1578 return Cy_SysClk_PllIsEnabled(clock->channel + 1 + SRSS_NUM_PLL400M);
1579 }
1580 #elif defined(COMPONENT_CAT1D)
1581 if (clock->block == CYHAL_CLOCK_BLOCK_DPLL500)
1582 {
1583 return Cy_SysClk_PllIsEnabled(clock->channel + 1 + SRSS_NUM_DPLL_LP);
1584 }
1585 #endif
1586 return Cy_SysClk_PllIsEnabled(clock->channel + 1);
1587 }
1588
_cyhal_clock_extract_pll_params(cyhal_clock_t * clock,cy_stc_pll_manual_config_t * cfg,uint64_t * feedbackDiv,uint32_t * referenceDiv,uint32_t * outputDiv)1589 static void _cyhal_clock_extract_pll_params(cyhal_clock_t *clock, cy_stc_pll_manual_config_t *cfg, uint64_t *feedbackDiv,
1590 uint32_t *referenceDiv, uint32_t *outputDiv)
1591 {
1592 #if defined (CY_IP_MXS40SRSS)
1593 *feedbackDiv = cfg->feedbackDiv;
1594 *referenceDiv = cfg->referenceDiv;
1595 *outputDiv = cfg->outputDiv;
1596 CY_UNUSED_PARAMETER(clock);
1597 #elif defined (CY_IP_MXS22SRSS)
1598 if (clock->block == CYHAL_CLOCK_BLOCK_DPLL250)
1599 {
1600 *feedbackDiv = cfg->lpPllCfg->feedbackDiv;
1601 *referenceDiv = cfg->lpPllCfg->referenceDiv;
1602 *outputDiv = cfg->lpPllCfg->outputDiv;
1603 }
1604 else if (clock->block == CYHAL_CLOCK_BLOCK_DPLL500)
1605 {
1606 /* Per IP block documentation, each divider requires +1 for correct output clock calculation */
1607 *feedbackDiv = cfg->hpPllCfg->nDiv + 1;
1608 *referenceDiv = cfg->hpPllCfg->pDiv + 1;
1609 *outputDiv = cfg->hpPllCfg->kDiv + 1;
1610 }
1611 #else
1612 #error "Unhandled SRSS block type"
1613 #endif /* defined (CY_IP_MXS40SRSS) or defined (CY_IP_MXS22SRSS) or other (error) */
1614 }
1615
_cyhal_clock_set_enabled_pll(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1616 static cy_rslt_t _cyhal_clock_set_enabled_pll(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1617 {
1618 CY_UNUSED_PARAMETER(clock);
1619 CY_UNUSED_PARAMETER(wait_for_lock);
1620
1621 //pll_idx is the path mux index (eg PLL number + 1) as used by PDL APIs
1622 uint32_t pll_idx = clock->channel + 1;
1623 #if defined(COMPONENT_CAT1C)
1624 if (clock->block == CYHAL_CLOCK_BLOCK_PLL200)
1625 {
1626 pll_idx = pll_idx + SRSS_NUM_PLL400M;
1627 }
1628 #elif defined(COMPONENT_CAT1D)
1629 if (clock->block == CYHAL_CLOCK_BLOCK_DPLL500)
1630 {
1631 pll_idx = pll_idx + SRSS_NUM_DPLL_LP;
1632 }
1633 #endif
1634 cy_stc_pll_manual_config_t cfg;
1635 cy_rslt_t rslt = Cy_SysClk_PllGetConfiguration(pll_idx, &cfg);
1636 if (CY_RSLT_SUCCESS == rslt)
1637 {
1638 uint32_t new_freq, old_freq;
1639 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0);
1640 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(pll_idx);
1641
1642 uint64_t feedbackDiv = 0;
1643 uint32_t referenceDiv = 0;
1644 uint32_t outputDiv = 0;
1645 _cyhal_clock_extract_pll_params(clock, &cfg, &feedbackDiv, &referenceDiv, &outputDiv);
1646
1647 uint32_t pll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * feedbackDiv, referenceDiv * outputDiv);
1648
1649 if (enabled)
1650 {
1651 new_freq = pll_freq >> div;
1652 old_freq = src_freq >> div;
1653 }
1654 else
1655 {
1656 new_freq = src_freq >> div;
1657 old_freq = pll_freq >> div;
1658 }
1659
1660 bool pll_sources_hf0 = (pll_idx == (uint32_t)Cy_SysClk_ClkHfGetSource(0));
1661 if (pll_sources_hf0)
1662 _cyhal_clock_update_system_state(true, old_freq, new_freq);
1663
1664 rslt = (enabled)
1665 ? Cy_SysClk_PllEnable(pll_idx, wait_for_lock ? _CYHAL_CLOCK_PLL_LOCK_TIME : 0UL)
1666 : Cy_SysClk_PllDisable(pll_idx);
1667
1668 if (pll_sources_hf0)
1669 {
1670 if (CY_RSLT_SUCCESS == rslt)
1671 _cyhal_clock_update_system_state(false, old_freq, new_freq);
1672 else // revert the change if there was one
1673 _cyhal_clock_update_system_state(false, new_freq, old_freq);
1674 }
1675 }
1676
1677 return rslt;
1678 }
_cyhal_clock_get_frequency_pll(const cyhal_clock_t * clock)1679 static uint32_t _cyhal_clock_get_frequency_pll(const cyhal_clock_t *clock)
1680 {
1681 #if defined(COMPONENT_CAT1C)
1682 if (clock->block == CYHAL_CLOCK_BLOCK_PLL200)
1683 {
1684 return Cy_SysClk_ClkPathGetFrequency(clock->channel + 1 + SRSS_NUM_PLL400M);
1685 }
1686 #elif defined(COMPONENT_CAT1D)
1687 if (clock->block == CYHAL_CLOCK_BLOCK_DPLL500)
1688 {
1689 return Cy_SysClk_ClkPathGetFrequency(clock->channel + 1 + SRSS_NUM_DPLL_LP);
1690 }
1691 #endif
1692 return Cy_SysClk_ClkPathGetFrequency(clock->channel + 1);
1693 }
_cyhal_clock_set_frequency_pll(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)1694 static cy_rslt_t _cyhal_clock_set_frequency_pll(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
1695 {
1696 CY_UNUSED_PARAMETER(tolerance);
1697
1698 cy_stc_pll_manual_config_t cfg;
1699 uint8_t pll_idx = clock->channel + 1;
1700 #if defined(COMPONENT_CAT1C)
1701 if (clock->block == CYHAL_CLOCK_BLOCK_PLL200)
1702 {
1703 pll_idx = pll_idx + SRSS_NUM_PLL400M;
1704 }
1705 #elif defined(COMPONENT_CAT1D)
1706 if (clock->block == CYHAL_CLOCK_BLOCK_DPLL500)
1707 {
1708 pll_idx = pll_idx + SRSS_NUM_DPLL_LP;
1709 }
1710 #endif
1711 cy_rslt_t rslt = Cy_SysClk_PllGetConfiguration(pll_idx, &cfg);
1712 if (CY_RSLT_SUCCESS == rslt)
1713 {
1714 bool enabled = Cy_SysClk_PllIsEnabled(pll_idx);
1715 if (enabled)
1716 rslt = Cy_SysClk_PllDisable(pll_idx);
1717 if (CY_RSLT_SUCCESS == rslt)
1718 {
1719 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(pll_idx);
1720
1721 uint64_t feedbackDiv = 0;
1722 uint32_t referenceDiv = 0;
1723 uint32_t outputDiv = 0;
1724 _cyhal_clock_extract_pll_params(clock, &cfg, &feedbackDiv, &referenceDiv, &outputDiv);
1725
1726 uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * feedbackDiv, referenceDiv * outputDiv);
1727
1728 uint32_t div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0);
1729 uint32_t old_hf_freq = old_freq >> div;
1730 uint32_t new_hf_freq = hz/*new_freq*/ >> div;
1731
1732 bool pll_sources_hf0 = (pll_idx == (uint32_t)Cy_SysClk_ClkHfGetSource(0));
1733 if (pll_sources_hf0)
1734 _cyhal_clock_update_system_state(true, old_hf_freq, new_hf_freq);
1735
1736 uint32_t input_hz = Cy_SysClk_ClkPathMuxGetFrequency(pll_idx);
1737 cy_stc_pll_config_t cfg2 =
1738 {
1739 .inputFreq = input_hz,
1740 .outputFreq = hz/*new_freq*/,
1741 .lfMode = false,
1742 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
1743 };
1744 rslt = Cy_SysClk_PllConfigure(pll_idx, &cfg2);
1745
1746 if (enabled)
1747 {
1748 cy_rslt_t rslt2 = Cy_SysClk_PllEnable(pll_idx, _CYHAL_CLOCK_PLL_LOCK_TIME);
1749 if (CY_RSLT_SUCCESS == rslt)
1750 rslt = rslt2;
1751 }
1752
1753 if (pll_sources_hf0)
1754 {
1755 if (CY_RSLT_SUCCESS == rslt)
1756 _cyhal_clock_update_system_state(false, old_hf_freq, new_hf_freq);
1757 else // revert the change if there was one
1758 _cyhal_clock_update_system_state(false, new_hf_freq, old_hf_freq);
1759 }
1760 }
1761 }
1762
1763 return rslt;
1764 }
_cyhal_clock_get_sources_pll(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)1765 static cy_rslt_t _cyhal_clock_get_sources_pll(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
1766 {
1767 // _CYHAL_CLOCK_SOURCE_HF has entries for FLL, PLL[n], PathMux[m]
1768 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
1769 #if defined(COMPONENT_CAT1C)
1770 uint8_t channel = clock->channel;
1771 if (clock->block == CYHAL_CLOCK_BLOCK_PLL200)
1772 {
1773 channel = channel + SRSS_NUM_PLL400M;
1774 }
1775 *sources = &(_CYHAL_CLOCK_SOURCE_HF[2 + _CYHAL_SRSS_NUM_PLL + channel]);
1776 #endif
1777 *sources = &(_CYHAL_CLOCK_SOURCE_HF[2 + _CYHAL_SRSS_NUM_PLL + clock->channel]); /* PATHMUX[n] entry is after the FLL (+1), PLLs (+num) and FLL path mux (+1) */
1778 #elif defined(COMPONENT_CAT1D)
1779 uint8_t channel = clock->channel;
1780 if (clock->block == CYHAL_CLOCK_BLOCK_DPLL500)
1781 {
1782 channel = channel + SRSS_NUM_DPLL_LP;
1783 }
1784 *sources = &(_CYHAL_CLOCK_SOURCE_HF[_CYHAL_SRSS_NUM_PLL + channel]);
1785 #else
1786 *sources = &(_CYHAL_CLOCK_SOURCE_HF[_CYHAL_SRSS_NUM_PLL + clock->channel]); /* PATHMUX[n] entry is after the PLLs (+num) */
1787 #endif
1788 *count = 1;
1789 return CY_RSLT_SUCCESS;
1790 }
1791 #endif
1792
1793 // MF
1794 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT) || defined(CY_IP_MXS22SRSS)
_cyhal_clock_is_enabled_mf(const cyhal_clock_t * clock)1795 static bool _cyhal_clock_is_enabled_mf(const cyhal_clock_t *clock)
1796 {
1797 CY_UNUSED_PARAMETER(clock);
1798 return Cy_SysClk_ClkMfIsEnabled();
1799 }
_cyhal_clock_set_enabled_mf(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1800 static cy_rslt_t _cyhal_clock_set_enabled_mf(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1801 {
1802 CY_UNUSED_PARAMETER(clock);
1803 CY_UNUSED_PARAMETER(wait_for_lock);
1804
1805 if (enabled)
1806 Cy_SysClk_ClkMfEnable();
1807 else
1808 Cy_SysClk_ClkMfDisable();
1809 return CY_RSLT_SUCCESS;
1810 }
_cyhal_clock_get_frequency_mf(const cyhal_clock_t * clock)1811 static uint32_t _cyhal_clock_get_frequency_mf(const cyhal_clock_t *clock)
1812 {
1813 CY_UNUSED_PARAMETER(clock);
1814 return Cy_SysClk_ClkMfGetFrequency();
1815 }
1816 #if defined(COMPONENT_CAT1D)
_cyhal_clock_get_source_frequency_mf()1817 static uint32_t _cyhal_clock_get_source_frequency_mf()
1818 {
1819 uint32_t output_freq = 0;
1820 cyhal_clock_t tmp_clk;
1821 cy_rslt_t result = ~CY_RSLT_SUCCESS;
1822 switch (Cy_SysClk_ClkMfGetSource())
1823 {
1824 case CY_SYSCLK_CLKMF_IN_IHO:
1825 result = cyhal_clock_get(&tmp_clk, &CYHAL_CLOCK_RSC_IHO);
1826 break;
1827 case CY_SYSCLK_CLKMF_IN_WCO:
1828 result = cyhal_clock_get(&tmp_clk, &CYHAL_CLOCK_RSC_WCO);
1829 break;
1830 default:
1831 /* Should never get here */
1832 CY_ASSERT(false);
1833 }
1834 if (CY_RSLT_SUCCESS == result)
1835 {
1836 output_freq = cyhal_clock_get_frequency(&tmp_clk);
1837 }
1838
1839 return output_freq;
1840 }
1841 #endif
_cyhal_clock_set_frequency_mf(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)1842 static cy_rslt_t _cyhal_clock_set_frequency_mf(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
1843 {
1844 CY_UNUSED_PARAMETER(clock);
1845
1846 uint32_t div;
1847 #if defined(COMPONENT_CAT1D)
1848 cy_rslt_t rslt = _cyhal_clock_compute_div(_cyhal_clock_get_source_frequency_mf(), hz, 8, tolerance, &div);
1849 #else
1850 cy_rslt_t rslt = _cyhal_clock_compute_div(CY_SYSCLK_MFO_FREQ, hz, 8, tolerance, &div);
1851 #endif /* defined(COMPONENT_CAT1D) or other */
1852
1853 if(false == CY_SYSCLK_IS_MF_DIVIDER_VALID(div))
1854 rslt = CYHAL_CLOCK_RSLT_ERR_FREQ;
1855
1856 if (CY_RSLT_SUCCESS == rslt)
1857 Cy_SysClk_ClkMfSetDivider(div);
1858
1859 return rslt;
1860 }
_cyhal_clock_set_divider_mf(cyhal_clock_t * clock,uint32_t divider)1861 static cy_rslt_t _cyhal_clock_set_divider_mf(cyhal_clock_t *clock, uint32_t divider)
1862 {
1863 CY_UNUSED_PARAMETER(clock);
1864
1865 if (divider <= 256)
1866 {
1867 Cy_SysClk_ClkMfSetDivider(divider);
1868 return CY_RSLT_SUCCESS;
1869 }
1870 return CYHAL_CLOCK_RSLT_ERR_FREQ;
1871 }
_cyhal_clock_get_sources_mf(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)1872 static cy_rslt_t _cyhal_clock_get_sources_mf(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
1873 {
1874 CY_UNUSED_PARAMETER(clock);
1875
1876 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_MF[] =
1877 {
1878 /* CAT1A only supports driving from the MFO */
1879 #if !defined(COMPONENT_CAT1D)
1880 &CYHAL_CLOCK_RSC_MFO,
1881 #endif
1882 #if _CYHAL_SRSS_ILO_PRESENT
1883 &CYHAL_CLOCK_RSC_ILO,
1884 #endif
1885 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
1886 &CYHAL_CLOCK_RSC_WCO,
1887 #endif
1888 #if _CYHAL_SRSS_PILO_PRESENT
1889 &CYHAL_CLOCK_RSC_PILO,
1890 #endif
1891 #if SRSS_ALTLF_PRESENT
1892 &CYHAL_CLOCK_RSC_ALTLF,
1893 #endif
1894 #if SRSS_ECO_PRESENT
1895 &CYHAL_CLOCK_RSC_ECO_PRESCALER,
1896 #endif
1897 #if SRSS_BACKUP_S40E_LPECO_PRESENT
1898 &CYHAL_CLOCK_RSC_LPECO_PRESCALER,
1899 #endif
1900 };
1901
1902 *sources = _CYHAL_CLOCK_SOURCE_MF;
1903 *count = sizeof(_CYHAL_CLOCK_SOURCE_MF) / sizeof(_CYHAL_CLOCK_SOURCE_MF[0]);
1904 return CY_RSLT_SUCCESS;
1905 }
_cyhal_clock_set_source_mf(cyhal_clock_t * clock,const cyhal_clock_t * source)1906 static cy_rslt_t _cyhal_clock_set_source_mf(cyhal_clock_t *clock, const cyhal_clock_t *source)
1907 {
1908 CY_UNUSED_PARAMETER(clock);
1909
1910 switch(source->block)
1911 {
1912 #if !defined(COMPONENT_CAT1D)
1913 case CYHAL_CLOCK_BLOCK_MFO:
1914 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_MFO);
1915 return CY_RSLT_SUCCESS;
1916 #else
1917 case CYHAL_CLOCK_BLOCK_IHO:
1918 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_IHO);
1919 return CY_RSLT_SUCCESS;
1920 #endif
1921 #if _CYHAL_SRSS_ILO_PRESENT
1922 case CYHAL_CLOCK_BLOCK_ILO:
1923 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_ILO);
1924 return CY_RSLT_SUCCESS;
1925 #endif
1926 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
1927 case CYHAL_CLOCK_BLOCK_WCO:
1928 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_WCO);
1929 return CY_RSLT_SUCCESS;
1930 #endif
1931 #if _CYHAL_SRSS_PILO_PRESENT
1932 case CYHAL_CLOCK_BLOCK_PILO:
1933 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_PILO);
1934 return CY_RSLT_SUCCESS;
1935 #endif
1936 #if SRSS_ALTLF_PRESENT
1937 case CYHAL_CLOCK_BLOCK_ALTLF:
1938 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_ALTLF);
1939 return CY_RSLT_SUCCESS;
1940 #endif
1941 #if SRSS_ECO_PRESENT
1942 case CYHAL_CLOCK_BLOCK_ECO_PRESCALER:
1943 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_ECO_PRESCALER);
1944 return CY_RSLT_SUCCESS;
1945 #endif
1946 #if SRSS_BACKUP_S40E_LPECO_PRESENT
1947 case CYHAL_CLOCK_BLOCK_LPECO_PRESCALER:
1948 Cy_SysClk_ClkMfSetSource(CY_SYSCLK_CLKMF_IN_LPECO);
1949 return CY_RSLT_SUCCESS;
1950 #endif
1951 default:
1952 CY_ASSERT(false); //Unhandled clock
1953 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
1954 }
1955 }
1956 #endif
1957
1958 // HF
_cyhal_clock_is_enabled_hf(const cyhal_clock_t * clock)1959 static bool _cyhal_clock_is_enabled_hf(const cyhal_clock_t *clock)
1960 {
1961 return Cy_SysClk_ClkHfIsEnabled(clock->channel);
1962 }
_cyhal_clock_set_enabled_hf(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)1963 static cy_rslt_t _cyhal_clock_set_enabled_hf(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
1964 {
1965 CY_UNUSED_PARAMETER(wait_for_lock);
1966
1967 return (enabled)
1968 ? Cy_SysClk_ClkHfEnable(clock->channel)
1969 : Cy_SysClk_ClkHfDisable(clock->channel);
1970 }
_cyhal_clock_get_frequency_hf(const cyhal_clock_t * clock)1971 static uint32_t _cyhal_clock_get_frequency_hf(const cyhal_clock_t *clock)
1972 {
1973 return Cy_SysClk_ClkHfGetFrequency(clock->channel);
1974 }
_cyhal_clock_set_divider_hf(cyhal_clock_t * clock,uint32_t divider)1975 static cy_rslt_t _cyhal_clock_set_divider_hf(cyhal_clock_t *clock, uint32_t divider)
1976 {
1977 cy_en_clkhf_dividers_t new_div;
1978 #if defined (CY_IP_MXS22SRSS)
1979 switch (divider)
1980 {
1981 case 1:
1982 new_div = CY_SYSCLK_CLKHF_NO_DIVIDE;
1983 break;
1984 case 2:
1985 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_2;
1986 break;
1987 case 3:
1988 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_3;
1989 break;
1990 case 4:
1991 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_4;
1992 break;
1993 case 5:
1994 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_5;
1995 break;
1996 case 6:
1997 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_6;
1998 break;
1999 case 7:
2000 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_7;
2001 break;
2002 case 8:
2003 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_8;
2004 break;
2005 case 9:
2006 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_9;
2007 break;
2008 case 10:
2009 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_10;
2010 break;
2011 case 11:
2012 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_11;
2013 break;
2014 case 12:
2015 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_12;
2016 break;
2017 case 13:
2018 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_13;
2019 break;
2020 case 14:
2021 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_14;
2022 break;
2023 case 15:
2024 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_15;
2025 break;
2026 case 16:
2027 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_16;
2028 break;
2029 default:
2030 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2031 }
2032 #else
2033 switch (divider)
2034 {
2035 case 1:
2036 new_div = CY_SYSCLK_CLKHF_NO_DIVIDE;
2037 break;
2038 case 2:
2039 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_2;
2040 break;
2041 case 4:
2042 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_4;
2043 break;
2044 case 8:
2045 new_div = CY_SYSCLK_CLKHF_DIVIDE_BY_8;
2046 break;
2047 default:
2048 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2049 }
2050 #endif
2051
2052 /* Only used if updating HFClk 0 */
2053 uint32_t old_div = (uint32_t)Cy_SysClk_ClkHfGetDivider(0);
2054 uint32_t src = (uint32_t)Cy_SysClk_ClkHfGetSource(0);
2055 uint32_t path_freq = Cy_SysClk_ClkPathGetFrequency(src);
2056 uint32_t old_freq = path_freq >> old_div;
2057 uint32_t new_freq = path_freq >> ((uint32_t)new_div);
2058
2059 if (0 == clock->channel)
2060 _cyhal_clock_update_system_state(true, old_freq, new_freq);
2061
2062 cy_rslt_t rslt = (cy_rslt_t)Cy_SysClk_ClkHfSetDivider(clock->channel, new_div);
2063
2064 if (0 == clock->channel)
2065 {
2066 if (CY_RSLT_SUCCESS == rslt)
2067 _cyhal_clock_update_system_state(false, old_freq, new_freq);
2068 else // revert the change if there was one
2069 _cyhal_clock_update_system_state(false, new_freq, old_freq);
2070 }
2071
2072 return rslt;
2073 }
_cyhal_clock_get_sources_hf(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2074 static cy_rslt_t _cyhal_clock_get_sources_hf(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2075 {
2076 CY_UNUSED_PARAMETER(clock);
2077 *sources = _CYHAL_CLOCK_SOURCE_HF;
2078 *count = sizeof(_CYHAL_CLOCK_SOURCE_HF) / sizeof(_CYHAL_CLOCK_SOURCE_HF[0]);
2079 return CY_RSLT_SUCCESS;
2080 }
_cyhal_clock_set_source_hf(cyhal_clock_t * clock,const cyhal_clock_t * source)2081 static cy_rslt_t _cyhal_clock_set_source_hf(cyhal_clock_t *clock, const cyhal_clock_t *source)
2082 {
2083 uint32_t new_src;
2084 if (source->block == CYHAL_CLOCK_BLOCK_PATHMUX
2085 #if !defined(COMPONENT_CAT1D)
2086 || source->block == CYHAL_CLOCK_BLOCK_FLL
2087 #endif
2088 )
2089 new_src = source->channel;
2090 #if defined(COMPONENT_CAT1A)
2091 else if (source->block == CYHAL_CLOCK_BLOCK_PLL)
2092 #elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
2093 else if ((source->block == CYHAL_CLOCK_BLOCK_PLL200) || (source->block == CYHAL_CLOCK_BLOCK_PLL400))
2094 #elif defined(COMPONENT_CAT1D)
2095 else if ((source->block == CYHAL_CLOCK_BLOCK_DPLL250) || (source->block == CYHAL_CLOCK_BLOCK_DPLL500))
2096 #endif
2097 {
2098 new_src = source->channel + 1;
2099 #if defined(SRSS_NUM_PLL400M) && (defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C))
2100 if (source->block == CYHAL_CLOCK_BLOCK_PLL200)
2101 {
2102 /* As PLL200 and PLL400 has their own channels and PLL400 sits on lower PATH_MUX numbers
2103 * we need to increase calculated source num with respect to number of PLL400's */
2104 new_src += SRSS_NUM_PLL400M;
2105 }
2106 #endif /* defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) */
2107 }
2108 else
2109 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
2110
2111 /* Only used if updating HFClk 0 */
2112 uint32_t div_hf0 = (uint32_t)Cy_SysClk_ClkHfGetDivider(0);
2113 uint32_t old_src_hf0 = (uint32_t)Cy_SysClk_ClkHfGetSource(0);
2114 uint32_t old_freq_hf0 = Cy_SysClk_ClkPathGetFrequency(old_src_hf0) >> div_hf0;
2115 uint32_t new_freq_hf0 = Cy_SysClk_ClkPathGetFrequency(new_src) >> div_hf0;
2116
2117 if (0 == clock->channel)
2118 _cyhal_clock_update_system_state(true, old_freq_hf0, new_freq_hf0);
2119
2120 cy_rslt_t rslt = Cy_SysClk_ClkHfSetSource(clock->channel, (cy_en_clkhf_in_sources_t)new_src);
2121
2122 if (0 == clock->channel)
2123 {
2124 if (CY_RSLT_SUCCESS == rslt)
2125 _cyhal_clock_update_system_state(false, old_freq_hf0, new_freq_hf0);
2126 else // revert the change if there was one
2127 _cyhal_clock_update_system_state(false, new_freq_hf0, old_freq_hf0);
2128 }
2129
2130 return rslt;
2131 }
2132
2133 // LF
_cyhal_clock_get_frequency_lf(const cyhal_clock_t * clock)2134 static uint32_t _cyhal_clock_get_frequency_lf(const cyhal_clock_t *clock)
2135 {
2136 CY_UNUSED_PARAMETER(clock);
2137 return _cyhal_clock_get_lf_frequency();
2138 }
_cyhal_clock_get_sources_lf(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2139 static cy_rslt_t _cyhal_clock_get_sources_lf(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2140 {
2141 CY_UNUSED_PARAMETER(clock);
2142 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_LF[] =
2143 {
2144 #if _CYHAL_SRSS_ILO_PRESENT
2145 #if defined(COMPONENT_CAT1C)
2146 &CYHAL_CLOCK_RSC_ILO[0],
2147 #if (SRSS_HT_VARIANT > 0)
2148 &CYHAL_CLOCK_RSC_ILO[1],
2149 #endif
2150 #else
2151 &CYHAL_CLOCK_RSC_ILO,
2152 #endif
2153 #endif
2154 #if _CYHAL_SRSS_PILO_PRESENT
2155 &CYHAL_CLOCK_RSC_PILO,
2156 #endif
2157 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
2158 &CYHAL_CLOCK_RSC_WCO,
2159 #endif
2160 #if SRSS_ALTLF_PRESENT
2161 &CYHAL_CLOCK_RSC_ALTLF,
2162 #endif
2163 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
2164 #if SRSS_ECO_PRESENT
2165 &CYHAL_CLOCK_RSC_ECO_PRESCALER,
2166 #endif
2167 #if SRSS_BACKUP_S40E_LPECO_PRESENT
2168 &CYHAL_CLOCK_RSC_LPECO_PRESCALER,
2169 #endif
2170 #endif
2171 };
2172
2173 *sources = _CYHAL_CLOCK_SOURCE_LF;
2174 *count = sizeof(_CYHAL_CLOCK_SOURCE_LF) / sizeof(_CYHAL_CLOCK_SOURCE_LF[0]);
2175 return CY_RSLT_SUCCESS;
2176 }
_cyhal_clock_set_source_lf(cyhal_clock_t * clock,const cyhal_clock_t * source)2177 static cy_rslt_t _cyhal_clock_set_source_lf(cyhal_clock_t *clock, const cyhal_clock_t *source)
2178 {
2179 CY_UNUSED_PARAMETER(clock);
2180 cy_rslt_t result = CY_RSLT_SUCCESS;
2181 #if defined(COMPONENT_CAT1C)
2182 Cy_WDT_Unlock();
2183 #endif
2184 switch (source->block)
2185 {
2186 #if _CYHAL_SRSS_ILO_PRESENT
2187 case CYHAL_CLOCK_BLOCK_ILO:
2188 #if defined(COMPONENT_CAT1C)
2189 if(1 == source->channel)
2190 {
2191 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO1);
2192 }
2193 else
2194 #endif
2195 {
2196 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
2197 }
2198 break;
2199 #endif
2200 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
2201 case CYHAL_CLOCK_BLOCK_WCO:
2202 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
2203 break;
2204 #endif
2205 #if SRSS_ALTLF_PRESENT
2206 case CYHAL_CLOCK_BLOCK_ALTLF:
2207 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ALTLF);
2208 break;
2209 #endif
2210 #if _CYHAL_SRSS_PILO_PRESENT
2211 case CYHAL_CLOCK_BLOCK_PILO:
2212 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
2213 break;
2214 #endif
2215 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
2216 #if SRSS_ECO_PRESENT
2217 case CYHAL_CLOCK_BLOCK_ECO_PRESCALER:
2218 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ECO_PRESCALER);
2219 break;
2220 #endif
2221 #if SRSS_BACKUP_S40E_LPECO_PRESENT
2222 case CYHAL_CLOCK_BLOCK_LPECO_PRESCALER:
2223 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER);
2224 break;
2225 #endif
2226 #endif
2227 default:
2228 CY_ASSERT(false); //Unhandled clock
2229 result = CYHAL_CLOCK_RSLT_ERR_SOURCE;
2230 }
2231 #if defined(COMPONENT_CAT1C)
2232 Cy_WDT_Lock();
2233 #endif
2234 return result;
2235 }
2236
2237 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2238 // FAST
_cyhal_clock_get_frequency_fast(const cyhal_clock_t * clock)2239 static uint32_t _cyhal_clock_get_frequency_fast(const cyhal_clock_t *clock)
2240 {
2241 CY_UNUSED_PARAMETER(clock);
2242 #if defined(COMPONENT_CAT1A)
2243 return Cy_SysClk_ClkFastGetFrequency();
2244 #else
2245 return Cy_SysClk_ClkFastSrcGetFrequency(clock->channel);
2246 #endif
2247 }
_cyhal_clock_set_frequency_fast(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)2248 static cy_rslt_t _cyhal_clock_set_frequency_fast(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
2249 {
2250 CY_UNUSED_PARAMETER(clock);
2251
2252 uint32_t div;
2253 cy_rslt_t rslt;
2254 #if defined(COMPONENT_CAT1A)
2255 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(0);
2256 rslt = _cyhal_clock_compute_div((uint64_t)input_hz, hz, 8, tolerance, &div);
2257 #else
2258 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(1);
2259 rslt = _cyhal_clock_compute_div(((uint64_t)input_hz) << 5, hz, 13, tolerance, &div);
2260 #endif
2261
2262 if (CY_RSLT_SUCCESS == rslt)
2263 {
2264 #if defined(COMPONENT_CAT1A)
2265 Cy_SysClk_ClkFastSetDivider((uint8_t)(div - 1));
2266 #else
2267 uint32_t div_int = (div >> 5) - 1;
2268 uint32_t div_frac = div & 0x1F;
2269 Cy_SysClk_ClkFastSrcSetDivider(clock->channel, (uint8_t)div_int, (uint8_t)div_frac);
2270 Cy_SysLib_SetWaitStates(false, 340);
2271 #endif
2272 SystemCoreClockUpdate();
2273 }
2274 return rslt;
2275 }
_cyhal_clock_set_divider_fast(cyhal_clock_t * clock,uint32_t divider)2276 static cy_rslt_t _cyhal_clock_set_divider_fast(cyhal_clock_t *clock, uint32_t divider)
2277 {
2278 CY_UNUSED_PARAMETER(clock);
2279
2280 if (divider <= 256)
2281 {
2282 uint32_t divVal = divider - 1;
2283 #if defined(COMPONENT_CAT1A)
2284 Cy_SysClk_ClkFastSetDivider((uint8_t)divVal);
2285 #else
2286 Cy_SysClk_ClkFastSrcSetDivider(clock->channel, (uint8_t)divVal, 0);
2287 #endif
2288 SystemCoreClockUpdate();
2289 return CY_RSLT_SUCCESS;
2290 }
2291 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2292 }
_cyhal_clock_get_sources_fast(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2293 static cy_rslt_t _cyhal_clock_get_sources_fast(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2294 {
2295 CY_UNUSED_PARAMETER(clock);
2296
2297 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_FAST[] =
2298 {
2299 #if defined(COMPONENT_CAT1C)
2300 &CYHAL_CLOCK_RSC_HF[1],
2301 #else
2302 &CYHAL_CLOCK_RSC_HF[0],
2303 #endif
2304 };
2305
2306 *sources = _CYHAL_CLOCK_SOURCE_FAST;
2307 *count = sizeof(_CYHAL_CLOCK_SOURCE_FAST) / sizeof(_CYHAL_CLOCK_SOURCE_FAST[0]);
2308 return CY_RSLT_SUCCESS;
2309 }
2310
2311 // SLOW
_cyhal_clock_get_frequency_slow(const cyhal_clock_t * clock)2312 static uint32_t _cyhal_clock_get_frequency_slow(const cyhal_clock_t *clock)
2313 {
2314 CY_UNUSED_PARAMETER(clock);
2315 return Cy_SysClk_ClkSlowGetFrequency();
2316 }
_cyhal_clock_set_frequency_slow(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)2317 static cy_rslt_t _cyhal_clock_set_frequency_slow(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
2318 {
2319 CY_UNUSED_PARAMETER(clock);
2320
2321 uint32_t div;
2322 uint32_t input_hz = Cy_SysClk_ClkPeriGetFrequency();
2323 cy_rslt_t rslt = _cyhal_clock_compute_div((uint64_t)input_hz, hz, 8, tolerance, &div);
2324
2325 if (CY_RSLT_SUCCESS == rslt)
2326 {
2327 Cy_SysClk_ClkSlowSetDivider((uint8_t)(div - 1));
2328 SystemCoreClockUpdate();
2329 }
2330
2331 return rslt;
2332 }
_cyhal_clock_set_divider_slow(cyhal_clock_t * clock,uint32_t divider)2333 static cy_rslt_t _cyhal_clock_set_divider_slow(cyhal_clock_t *clock, uint32_t divider)
2334 {
2335 CY_UNUSED_PARAMETER(clock);
2336
2337 if (divider <= 256)
2338 {
2339 uint32_t divVal = divider - 1;
2340 Cy_SysClk_ClkSlowSetDivider((uint8_t)divVal);
2341 SystemCoreClockUpdate();
2342 return CY_RSLT_SUCCESS;
2343 }
2344 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2345 }
_cyhal_clock_get_sources_slow(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2346 static cy_rslt_t _cyhal_clock_get_sources_slow(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2347 {
2348 CY_UNUSED_PARAMETER(clock);
2349 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_SLOW[] =
2350 {
2351 #if defined(COMPONENT_CAT1A)
2352 &CYHAL_CLOCK_RSC_PERI,
2353 #else
2354 &CYHAL_CLOCK_RSC_MEM,
2355 #endif
2356 };
2357
2358 *sources = _CYHAL_CLOCK_SOURCE_SLOW;
2359 *count = sizeof(_CYHAL_CLOCK_SOURCE_SLOW) / sizeof(_CYHAL_CLOCK_SOURCE_SLOW[0]);
2360 return CY_RSLT_SUCCESS;
2361 }
2362 #endif
2363 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
2364 #if SRSS_ECO_PRESENT
2365 // ECO_PRESCALER - NOTE: This clock is not supported on any device yet
_cyhal_clock_get_frequency_eco_prescaler(const cyhal_clock_t * clock)2366 static uint32_t _cyhal_clock_get_frequency_eco_prescaler(const cyhal_clock_t *clock)
2367 {
2368 CY_UNUSED_PARAMETER(clock);
2369 //return Cy_SysClk_EcoPrescalerGetFrequency();
2370 return 0;
2371 }
_cyhal_clock_set_divider_eco_prescaler(cyhal_clock_t * clock,uint32_t divider)2372 static cy_rslt_t _cyhal_clock_set_divider_eco_prescaler(cyhal_clock_t *clock, uint32_t divider)
2373 {
2374 CY_UNUSED_PARAMETER(clock);
2375 CY_UNUSED_PARAMETER(divider);
2376
2377 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
2378 }
_cyhal_clock_get_sources_eco_prescaler(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2379 static cy_rslt_t _cyhal_clock_get_sources_eco_prescaler(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2380 {
2381 CY_UNUSED_PARAMETER(clock);
2382 CY_UNUSED_PARAMETER(sources);
2383 CY_UNUSED_PARAMETER(count);
2384
2385 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
2386 }
2387 #endif
2388
2389 #if SRSS_BACKUP_S40E_LPECO_PRESENT
2390 // LPECO_PRESCALER - NOTE: This clock is not supported on any device yet
_cyhal_clock_get_frequency_lpeco_prescaler(const cyhal_clock_t * clock)2391 static uint32_t _cyhal_clock_get_frequency_lpeco_prescaler(const cyhal_clock_t *clock)
2392 {
2393 CY_UNUSED_PARAMETER(clock);
2394 return Cy_SysClk_LpEcoPrescalerGetFrequency();
2395 }
_cyhal_clock_set_divider_lpeco_prescaler(cyhal_clock_t * clock,uint32_t divider)2396 static cy_rslt_t _cyhal_clock_set_divider_lpeco_prescaler(cyhal_clock_t *clock, uint32_t divider)
2397 {
2398 CY_UNUSED_PARAMETER(clock);
2399 CY_UNUSED_PARAMETER(divider);
2400
2401 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
2402 }
_cyhal_clock_get_sources_lpeco_prescaler(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2403 static cy_rslt_t _cyhal_clock_get_sources_lpeco_prescaler(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2404 {
2405 CY_UNUSED_PARAMETER(clock);
2406 CY_UNUSED_PARAMETER(sources);
2407 CY_UNUSED_PARAMETER(count);
2408
2409 return CYHAL_CLOCK_RSLT_ERR_NOT_SUPPORTED;
2410 }
2411 #endif
2412 #endif
2413
2414 // MEM
2415 #if defined(COMPONENT_CAT1C)
_cyhal_clock_set_divider_mem(cyhal_clock_t * clock,uint32_t divider)2416 static cy_rslt_t _cyhal_clock_set_divider_mem(cyhal_clock_t *clock, uint32_t divider)
2417 {
2418 CY_UNUSED_PARAMETER(clock);
2419 if (divider <= 256)
2420 {
2421 uint32_t divVal = divider - 1;
2422 Cy_SysClk_ClkMemSetDivider((uint8_t)divVal);
2423 SystemCoreClockUpdate();
2424 return CY_RSLT_SUCCESS;
2425 }
2426 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2427 }
_cyhal_clock_get_frequency_mem(const cyhal_clock_t * clock)2428 static uint32_t _cyhal_clock_get_frequency_mem(const cyhal_clock_t *clock)
2429 {
2430 CY_UNUSED_PARAMETER(clock);
2431 return Cy_SysClk_ClkMemGetFrequency();
2432 }
_cyhal_clock_set_frequency_mem(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)2433 static cy_rslt_t _cyhal_clock_set_frequency_mem(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
2434 {
2435 CY_UNUSED_PARAMETER(clock);
2436
2437 uint32_t div;
2438 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(0);
2439 cy_rslt_t rslt = _cyhal_clock_compute_div((uint64_t)input_hz, hz, 8, tolerance, &div);
2440 if (CY_RSLT_SUCCESS == rslt)
2441 {
2442 Cy_SysClk_ClkMemSetDivider((uint8_t)(div - 1));
2443 SystemCoreClockUpdate();
2444 }
2445 return rslt;
2446 }
_cyhal_clock_get_sources_mem(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2447 static cy_rslt_t _cyhal_clock_get_sources_mem(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2448 {
2449 CY_UNUSED_PARAMETER(clock);
2450
2451 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_MEM[] =
2452 {
2453 &CYHAL_CLOCK_RSC_HF[0],
2454 };
2455 *sources = _CYHAL_CLOCK_SOURCE_MEM;
2456 *count = 1;
2457 return CY_RSLT_SUCCESS;
2458 }
2459 #endif
2460
2461 // PERI
_cyhal_clock_get_frequency_peri(const cyhal_clock_t * clock)2462 static uint32_t _cyhal_clock_get_frequency_peri(const cyhal_clock_t *clock)
2463 {
2464 CY_UNUSED_PARAMETER(clock);
2465 #if defined(COMPONENT_CAT1C)
2466 if(clock->channel == 0)
2467 #endif
2468 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2469 {
2470 return Cy_SysClk_ClkPeriGetFrequency();
2471 }
2472 #endif
2473 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
2474 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
2475 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(clock->channel);
2476 #elif defined(COMPONENT_CAT1D)
2477 uint8_t instance = _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock->block);
2478 uint8_t group = _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock->block);
2479 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(_CYHAL_UTILS_PACK_INSTANCE_GROUP(instance, group));
2480 #endif /* defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) or defined(COMPONENT_CAT1D) or other */
2481 return Cy_SysClk_ClkHfGetFrequency(hfclk) / (Cy_SysClk_PeriGroupGetDivider(clock->channel) + 1);
2482 #endif /* defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D) */
2483 }
_cyhal_clock_set_frequency_peri(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)2484 static cy_rslt_t _cyhal_clock_set_frequency_peri(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
2485 {
2486 CY_UNUSED_PARAMETER(clock);
2487
2488 uint32_t div;
2489 cy_rslt_t rslt;
2490 #if defined(COMPONENT_CAT1C)
2491 if(clock->channel == 0)
2492 #endif
2493 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2494 {
2495 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(0);
2496 rslt = _cyhal_clock_compute_div((uint64_t)input_hz, hz, 8, tolerance, &div);
2497
2498 if (CY_RSLT_SUCCESS == rslt)
2499 {
2500 Cy_SysClk_ClkPeriSetDivider((uint8_t)(div - 1));
2501 SystemCoreClockUpdate();
2502 }
2503 return rslt;
2504 }
2505 #endif
2506 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
2507 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
2508 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(clock->channel == 1 ? 1 : 0);
2509 #elif defined(COMPONENT_CAT1D)
2510 uint8_t instance = _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock->block);
2511 uint8_t group = _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock->block);
2512 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(_cyhal_utils_get_hfclk_for_peri_group(_CYHAL_UTILS_PACK_INSTANCE_GROUP(instance, group)));
2513 #endif /* defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) or defined(COMPONENT_CAT1D) */
2514 rslt = _cyhal_clock_compute_div((uint64_t)input_hz, hz, 8, tolerance, &div);
2515
2516
2517 if (CY_RSLT_SUCCESS == rslt)
2518 {
2519 uint32_t group_num = clock->channel;
2520 #if defined(COMPONENT_CAT1D)
2521 /* I'm not completely confident in line below */
2522 group_num += _VAL2FLD(PERI_GR_INST_NUM, instance);
2523 #endif /* defined(COMPONENT_CAT1D) or other */
2524 Cy_SysClk_PeriGroupSetDivider(group_num, (uint8_t)(div - 1));
2525 }
2526 return rslt;
2527 #endif /* defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D) */
2528 }
_cyhal_clock_set_divider_peri(cyhal_clock_t * clock,uint32_t divider)2529 static cy_rslt_t _cyhal_clock_set_divider_peri(cyhal_clock_t *clock, uint32_t divider)
2530 {
2531 CY_UNUSED_PARAMETER(clock);
2532 if (divider <= 256)
2533 {
2534 uint32_t divVal = divider - 1;
2535 #if defined(COMPONENT_CAT1C)
2536 if (clock->channel == 0)
2537 #endif
2538 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2539 {
2540 Cy_SysClk_ClkPeriSetDivider((uint8_t)divVal);
2541 SystemCoreClockUpdate();
2542 return CY_RSLT_SUCCESS;
2543 }
2544 #endif
2545 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
2546 Cy_SysClk_PeriGroupSetDivider(clock->channel, (uint8_t)divVal);
2547 SystemCoreClockUpdate();
2548 return CY_RSLT_SUCCESS;
2549 #endif
2550 }
2551 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2552 }
_cyhal_clock_get_sources_peri(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2553 static cy_rslt_t _cyhal_clock_get_sources_peri(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2554 {
2555 #if defined(COMPONENT_CAT1A)
2556 CY_UNUSED_PARAMETER(clock);
2557 #endif
2558 #if defined(COMPONENT_CAT1C)
2559 if (clock->channel == 0)
2560 #endif
2561 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2562 {
2563 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_PERI[] =
2564 {
2565 &CYHAL_CLOCK_RSC_HF[0],
2566 };
2567
2568 *sources = _CYHAL_CLOCK_SOURCE_PERI;
2569 *count = 1;
2570 return CY_RSLT_SUCCESS;
2571 }
2572 #endif
2573
2574 #if defined (COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
2575 #if !defined(COMPONENT_CAT1D)
2576 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(clock->channel);
2577 #else /* defined(COMPONENT_CAT1D) */
2578 uint8_t instance = _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock->block);
2579 uint8_t group = _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock->block);
2580 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(_CYHAL_UTILS_PACK_INSTANCE_GROUP(instance, group));
2581 #endif /* !defined(COMPONENT_CAT1D) or other */
2582 return _cyhal_clock_get_sources_peri_peripheral(hfclk, sources, count);
2583 #endif
2584 }
2585
2586 // PUMP (only available on CAT1A and CAT1B devices)
2587 #if defined (COMPONENT_CAT1A) || defined (COMPONENT_CAT1B)
_cyhal_clock_is_enabled_pump(const cyhal_clock_t * clock)2588 static bool _cyhal_clock_is_enabled_pump(const cyhal_clock_t *clock)
2589 {
2590 CY_UNUSED_PARAMETER(clock);
2591 return Cy_SysClk_ClkPumpIsEnabled();
2592 }
_cyhal_clock_set_enabled_pump(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)2593 static cy_rslt_t _cyhal_clock_set_enabled_pump(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
2594 {
2595 CY_UNUSED_PARAMETER(clock);
2596 CY_UNUSED_PARAMETER(wait_for_lock);
2597
2598 if (enabled)
2599 Cy_SysClk_ClkPumpEnable();
2600 else
2601 Cy_SysClk_ClkPumpDisable();
2602 return CY_RSLT_SUCCESS;
2603 }
_cyhal_clock_get_frequency_pump(const cyhal_clock_t * clock)2604 static uint32_t _cyhal_clock_get_frequency_pump(const cyhal_clock_t *clock)
2605 {
2606 CY_UNUSED_PARAMETER(clock);
2607 return Cy_SysClk_ClkPumpGetFrequency();
2608 }
_cyhal_clock_set_divider_pump(cyhal_clock_t * clock,uint32_t divider)2609 static cy_rslt_t _cyhal_clock_set_divider_pump(cyhal_clock_t *clock, uint32_t divider)
2610 {
2611 CY_UNUSED_PARAMETER(clock);
2612
2613 cy_en_clkpump_divide_t divVal;
2614 switch (divider)
2615 {
2616 case 1:
2617 divVal = CY_SYSCLK_PUMP_NO_DIV;
2618 break;
2619 case 2:
2620 divVal = CY_SYSCLK_PUMP_DIV_2;
2621 break;
2622 case 4:
2623 divVal = CY_SYSCLK_PUMP_DIV_4;
2624 break;
2625 case 8:
2626 divVal = CY_SYSCLK_PUMP_DIV_8;
2627 break;
2628 case 16:
2629 divVal = CY_SYSCLK_PUMP_DIV_16;
2630 break;
2631 default:
2632 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2633 }
2634 Cy_SysClk_ClkPumpSetDivider(divVal);
2635 return CY_RSLT_SUCCESS;
2636 }
2637 #define _cyhal_clock_get_sources_pump _cyhal_clock_get_sources_hf
_cyhal_clock_set_source_pump(cyhal_clock_t * clock,const cyhal_clock_t * source)2638 static cy_rslt_t _cyhal_clock_set_source_pump(cyhal_clock_t *clock, const cyhal_clock_t *source)
2639 {
2640 CY_UNUSED_PARAMETER(clock);
2641
2642 if (source->block == CYHAL_CLOCK_BLOCK_PATHMUX || source->block == CYHAL_CLOCK_BLOCK_FLL)
2643 {
2644 Cy_SysClk_ClkPumpSetSource((cy_en_clkpump_in_sources_t)source->channel);
2645 return CY_RSLT_SUCCESS;
2646 }
2647 #if defined(COMPONENT_CAT1A)
2648 else if (source->block == CYHAL_CLOCK_BLOCK_PLL)
2649 #elif defined(COMPONENT_CAT1B)
2650 else if ((source->block == CYHAL_CLOCK_BLOCK_PLL200) || (source->block == CYHAL_CLOCK_BLOCK_PLL400))
2651 #endif
2652 {
2653 Cy_SysClk_ClkPumpSetSource((cy_en_clkpump_in_sources_t)(source->channel + 1));
2654 return CY_RSLT_SUCCESS;
2655 }
2656 else
2657 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
2658 }
2659 #endif /* defined (COMPONENT_CAT1A) || defined (COMPONENT_CAT1B) */
2660
2661 // TIMER
2662 // TODO: Need to enable timer functionality for CAT1C once PDL team updates clk_timer API's
2663 #if defined(COMPONENT_CAT1A)
_cyhal_clock_is_enabled_timer(const cyhal_clock_t * clock)2664 static bool _cyhal_clock_is_enabled_timer(const cyhal_clock_t *clock)
2665 {
2666 CY_UNUSED_PARAMETER(clock);
2667 return Cy_SysClk_ClkTimerIsEnabled();
2668 }
_cyhal_clock_set_enabled_timer(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)2669 static cy_rslt_t _cyhal_clock_set_enabled_timer(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
2670 {
2671 CY_UNUSED_PARAMETER(clock);
2672 CY_UNUSED_PARAMETER(wait_for_lock);
2673
2674 if (enabled)
2675 Cy_SysClk_ClkTimerEnable();
2676 else
2677 Cy_SysClk_ClkTimerDisable();
2678 return CY_RSLT_SUCCESS;
2679 }
_cyhal_clock_get_frequency_timer(const cyhal_clock_t * clock)2680 static uint32_t _cyhal_clock_get_frequency_timer(const cyhal_clock_t *clock)
2681 {
2682 CY_UNUSED_PARAMETER(clock);
2683 return Cy_SysClk_ClkTimerGetFrequency();
2684 }
_cyhal_clock_set_divider_timer(cyhal_clock_t * clock,uint32_t divider)2685 static cy_rslt_t _cyhal_clock_set_divider_timer(cyhal_clock_t *clock, uint32_t divider)
2686 {
2687 CY_UNUSED_PARAMETER(clock);
2688
2689 if (divider <= 256)
2690 {
2691 uint32_t divVal = divider - 1;
2692 Cy_SysClk_ClkTimerSetDivider((uint8_t)divVal);
2693 return CY_RSLT_SUCCESS;
2694 }
2695 return CYHAL_CLOCK_RSLT_ERR_FREQ;
2696 }
_cyhal_clock_get_sources_timer(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2697 static cy_rslt_t _cyhal_clock_get_sources_timer(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2698 {
2699 CY_UNUSED_PARAMETER(clock);
2700 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_TIMER[] =
2701 {
2702 &CYHAL_CLOCK_RSC_IMO,
2703 &CYHAL_CLOCK_RSC_HF[0],
2704 };
2705
2706 *sources = _CYHAL_CLOCK_SOURCE_TIMER;
2707 *count = sizeof(_CYHAL_CLOCK_SOURCE_TIMER) / sizeof(_CYHAL_CLOCK_SOURCE_TIMER[0]);
2708 return CY_RSLT_SUCCESS;
2709 }
_cyhal_clock_set_source_timer(cyhal_clock_t * clock,const cyhal_clock_t * source)2710 static cy_rslt_t _cyhal_clock_set_source_timer(cyhal_clock_t *clock, const cyhal_clock_t *source)
2711 {
2712 CY_UNUSED_PARAMETER(clock);
2713
2714 if (source->block == CYHAL_CLOCK_BLOCK_IMO)
2715 {
2716 Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
2717 return CY_RSLT_SUCCESS;
2718 }
2719 else if (source->block == CYHAL_CLOCK_BLOCK_HF && source->channel == 0)
2720 {
2721 Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
2722 return CY_RSLT_SUCCESS;
2723 }
2724 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
2725 }
2726 #endif
2727
2728 // BAK
_cyhal_clock_get_frequency_bak(const cyhal_clock_t * clock)2729 static uint32_t _cyhal_clock_get_frequency_bak(const cyhal_clock_t *clock)
2730 {
2731 CY_UNUSED_PARAMETER(clock);
2732 cy_en_clkbak_in_sources_t src = Cy_SysClk_ClkBakGetSource();
2733 #if SRSS_BACKUP_PRESENT
2734 if (src == CY_SYSCLK_BAK_IN_WCO)
2735 return CY_SYSCLK_WCO_FREQ;
2736 #else
2737 (void)src;
2738 #endif
2739 return _cyhal_clock_get_lf_frequency();
2740 }
_cyhal_clock_get_sources_bak(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2741 static cy_rslt_t _cyhal_clock_get_sources_bak(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2742 {
2743 CY_UNUSED_PARAMETER(clock);
2744 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_BAK[] =
2745 {
2746 &CYHAL_CLOCK_RSC_LF,
2747 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
2748 &CYHAL_CLOCK_RSC_WCO,
2749 #endif
2750 #if (_CYHAL_SRSS_ILO_PRESENT)
2751 #if defined(COMPONENT_CAT1C)
2752 &CYHAL_CLOCK_RSC_ILO[0],
2753 #elif defined(COMPONENT_CAT1B)
2754 &CYHAL_CLOCK_RSC_ILO,
2755 #endif
2756 #endif
2757 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
2758 #if _CYHAL_SRSS_PILO_PRESENT
2759 &CYHAL_CLOCK_RSC_PILO,
2760 #endif
2761 #endif
2762 #if defined(COMPONENT_CAT1B)
2763 #if SRSS_BACKUP_S40E_LPECO_PRESENT
2764 &CYHAL_CLOCK_RSC_LPECO_PRESCALER,
2765 #endif
2766 #endif
2767 };
2768
2769 *sources = _CYHAL_CLOCK_SOURCE_BAK;
2770 *count = sizeof(_CYHAL_CLOCK_SOURCE_BAK) / sizeof(_CYHAL_CLOCK_SOURCE_BAK[0]);
2771 return CY_RSLT_SUCCESS;
2772 }
_cyhal_clock_set_source_bak(cyhal_clock_t * clock,const cyhal_clock_t * source)2773 static cy_rslt_t _cyhal_clock_set_source_bak(cyhal_clock_t *clock, const cyhal_clock_t *source)
2774 {
2775 CY_UNUSED_PARAMETER(clock);
2776
2777 switch (source->block)
2778 {
2779 case CYHAL_CLOCK_BLOCK_WCO:
2780 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
2781 return CY_RSLT_SUCCESS;
2782 case CYHAL_CLOCK_BLOCK_LF:
2783 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
2784 return CY_RSLT_SUCCESS;
2785 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
2786 case CYHAL_CLOCK_BLOCK_ILO:
2787 if(1 == source->channel)
2788 {
2789 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
2790 }
2791 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_ILO);
2792 return CY_RSLT_SUCCESS;
2793 #endif
2794 #if _CYHAL_SRSS_PILO_PRESENT && (defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D))
2795 case CYHAL_CLOCK_BLOCK_PILO:
2796 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_PILO);
2797 return CY_RSLT_SUCCESS;
2798 #endif
2799 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
2800 #if SRSS_BACKUP_S40E_LPECO_PRESENT
2801 case CYHAL_CLOCK_BLOCK_LPECO_PRESCALER:
2802 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_LPECO_PRESCALER);
2803 return CY_RSLT_SUCCESS;
2804 #endif
2805 #endif
2806 default:
2807 CY_ASSERT(false); //Unhandled clock
2808 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
2809 }
2810 }
2811
2812 #if !defined(COMPONENT_CAT1D)
2813 // ALT_SYS_TICK
_cyhal_clock_get_frequency_alt_sys_tick(const cyhal_clock_t * clock)2814 static uint32_t _cyhal_clock_get_frequency_alt_sys_tick(const cyhal_clock_t *clock)
2815 {
2816 CY_UNUSED_PARAMETER(clock);
2817 CY_ASSERT(false); // This is not supported at this time
2818 return 0;
2819 }
_cyhal_clock_get_sources_alt_sys_tick(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)2820 static cy_rslt_t _cyhal_clock_get_sources_alt_sys_tick(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
2821 {
2822 CY_UNUSED_PARAMETER(clock);
2823 static const cyhal_resource_inst_t *_CYHAL_CLOCK_SOURCE_ALT_SYS_TICK[] =
2824 {
2825 #if !defined(COMPONENT_CAT1D)
2826 &CYHAL_CLOCK_RSC_IMO,
2827 #endif
2828 #if SRSS_ECO_PRESENT
2829 &CYHAL_CLOCK_RSC_ECO,
2830 #endif
2831 &CYHAL_CLOCK_RSC_LF,
2832 #if defined(COMPONENT_CAT1A)
2833 &CYHAL_CLOCK_RSC_TIMER, /* Technically present on CAT1B and CAT1C, but deprecated */
2834 #endif
2835 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2836 #if defined(COMPONENT_CAT1C)
2837 &CYHAL_CLOCK_RSC_FAST[0],
2838 &CYHAL_CLOCK_RSC_FAST[1],
2839 #else
2840 &CYHAL_CLOCK_RSC_FAST,
2841 #endif
2842 &CYHAL_CLOCK_RSC_SLOW,
2843 #elif defined(COMPONENT_CAT1B)
2844 &CYHAL_CLOCK_RSC_HF[0], /* CPU clock */
2845 #endif
2846 };
2847
2848 *sources = _CYHAL_CLOCK_SOURCE_ALT_SYS_TICK;
2849 *count = sizeof(_CYHAL_CLOCK_SOURCE_ALT_SYS_TICK) / sizeof(_CYHAL_CLOCK_SOURCE_ALT_SYS_TICK[0]);
2850 return CY_RSLT_SUCCESS;
2851 }
_cyhal_clock_set_source_alt_sys_tick(cyhal_clock_t * clock,const cyhal_clock_t * source)2852 static cy_rslt_t _cyhal_clock_set_source_alt_sys_tick(cyhal_clock_t *clock, const cyhal_clock_t *source)
2853 {
2854 CY_UNUSED_PARAMETER(clock);
2855
2856 switch (source->block)
2857 {
2858 case CYHAL_CLOCK_BLOCK_LF:
2859 Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
2860 return CY_RSLT_SUCCESS;
2861 #if !defined(COMPONENT_CAT1D)
2862 case CYHAL_CLOCK_BLOCK_IMO:
2863 Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_IMO);
2864 return CY_RSLT_SUCCESS;
2865 #endif
2866 #if SRSS_ECO_PRESENT
2867 case CYHAL_CLOCK_BLOCK_ECO:
2868 Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_ECO);
2869 return CY_RSLT_SUCCESS;
2870 #endif
2871 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
2872 #if defined(COMPONENT_CAT1A)
2873 case CYHAL_CLOCK_BLOCK_TIMER:
2874 Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_TIMER);
2875 return CY_RSLT_SUCCESS;
2876 #endif
2877 case CYHAL_CLOCK_BLOCK_FAST:
2878 case CYHAL_CLOCK_BLOCK_SLOW:
2879 Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_CPU);
2880 return CY_RSLT_SUCCESS;
2881 #endif
2882 default:
2883 CY_ASSERT(false); //Unhandled clock
2884 return CYHAL_CLOCK_RSLT_ERR_SOURCE;
2885 }
2886 }
2887 #endif
2888
2889 // Peripheral
2890 #if defined(COMPONENT_CAT1D)
_cyhal_clock_is_source_enabled_peripheral(const cyhal_clock_t * clock)2891 static bool _cyhal_clock_is_source_enabled_peripheral(const cyhal_clock_t *clock)
2892 {
2893 uint8_t instance = _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock->block);
2894 uint8_t group = _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock->block);
2895 uint8_t hfclk_idx = _cyhal_utils_get_hfclk_for_peri_group(_CYHAL_UTILS_PACK_INSTANCE_GROUP(instance, group));
2896 return Cy_SysClk_ClkHfIsEnabled(hfclk_idx);
2897 }
2898 #endif
2899
_cyhal_clock_is_enabled_peripheral(const cyhal_clock_t * clock)2900 static bool _cyhal_clock_is_enabled_peripheral(const cyhal_clock_t *clock)
2901 {
2902 #if defined(COMPONENT_CAT1D)
2903 if (!_cyhal_clock_is_source_enabled_peripheral(clock))
2904 {
2905 /** Access to peri clock configuration registers will give no effect if
2906 * corresponding source HF clock is turned off. It needs to be turned on in order to proceed */
2907 CY_ASSERT(false);
2908 return false;
2909 }
2910 #endif
2911 return _cyhal_utils_peri_pclk_is_divider_enabled(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock);
2912 }
_cyhal_clock_set_enabled_peripheral(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)2913 static cy_rslt_t _cyhal_clock_set_enabled_peripheral(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
2914 {
2915 CY_UNUSED_PARAMETER(wait_for_lock);
2916
2917 #if defined(COMPONENT_CAT1D)
2918 if (!_cyhal_clock_is_source_enabled_peripheral(clock))
2919 {
2920 /** Access to peri clock configuration registers will give no effect if
2921 * corresponding source HF clock is turned off. It needs to be turned on in order to proceed */
2922 return CYHAL_CLOCK_RSLT_ERR_SOURCE_DISABLED;
2923 }
2924 #endif
2925
2926 return (enabled)
2927 ? _cyhal_utils_peri_pclk_enable_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock)
2928 : _cyhal_utils_peri_pclk_disable_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock);
2929 }
_cyhal_clock_get_frequency_peripheral(const cyhal_clock_t * clock)2930 static uint32_t _cyhal_clock_get_frequency_peripheral(const cyhal_clock_t *clock)
2931 {
2932 #if defined(COMPONENT_CAT1D)
2933 if (!_cyhal_clock_is_source_enabled_peripheral(clock))
2934 {
2935 /** Access to peri clock configuration registers will give no effect if
2936 * corresponding source HF clock is turned off. It needs to be turned on in order to proceed */
2937 CY_ASSERT(false);
2938 return 0;
2939 }
2940 #endif
2941 return _cyhal_utils_peri_pclk_get_frequency(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock);
2942 }
_cyhal_clock_set_frequency_peripheral(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)2943 static cy_rslt_t _cyhal_clock_set_frequency_peripheral(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
2944 {
2945 #if !defined(COMPONENT_CAT1D)
2946 CY_UNUSED_PARAMETER(clock);
2947 #endif
2948 CY_UNUSED_PARAMETER(tolerance);
2949
2950 #if defined(COMPONENT_CAT1D)
2951 if (!_cyhal_clock_is_source_enabled_peripheral(clock))
2952 {
2953 /** Access to peri clock configuration registers will give no effect if
2954 * corresponding source HF clock is turned off. It needs to be turned on in order to proceed */
2955 return CYHAL_CLOCK_RSLT_ERR_SOURCE_DISABLED;
2956 }
2957 #endif
2958
2959 // blocks 0b00 & 0b01 are integer, 0b10 & 0b11 are fractional
2960 uint32_t div;
2961
2962 #if defined(COMPONENT_CAT1A)
2963 uint32_t input_hz = Cy_SysClk_ClkPeriGetFrequency();
2964 #elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
2965 #if defined(COMPONENT_CAT1D)
2966 uint8_t instance = _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock->block);
2967 uint8_t group = _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock->block);
2968 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(_CYHAL_UTILS_PACK_INSTANCE_GROUP(instance, group));
2969 #else /* !defined(COMPONENT_CAT1D) */
2970 uint8_t group = _CYHAL_PERIPHERAL_GROUP_GET_GROUP(clock->block);
2971 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(group);
2972 #endif /* defined(COMPONENT_CAT1D) or other */
2973 uint32_t input_hz = Cy_SysClk_ClkHfGetFrequency(hfclk);
2974 #endif
2975
2976 if ((clock->block & 0x02) == 0) // Integer (8 or 16)
2977 {
2978 uint32_t bits = (clock->block & 0x01) ? 16 : 8;
2979 cy_rslt_t rslt = _cyhal_clock_compute_div((uint64_t)input_hz, hz, bits, tolerance, &div);
2980 return (CY_RSLT_SUCCESS == rslt)
2981 ? _cyhal_utils_peri_pclk_set_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock, (div - 1))
2982 : rslt;
2983 }
2984 else //Fractional (16.5 or 24.5)
2985 {
2986 // Multiply input by 32 so we can treat the 5 fractional bits as though they are extentions of the integer divider
2987 // Leave the the desired frequency alone, so we can just strip out the integer & fractional bits at the end.
2988 uint32_t bits = (clock->block & 0x01) ? 29 : 21; // Integer bits + 5
2989 cy_rslt_t rslt = _cyhal_clock_compute_div(((uint64_t)input_hz) << 5, hz, bits, tolerance, &div);
2990 if (CY_RSLT_SUCCESS == rslt)
2991 {
2992 uint32_t div_int = (div >> 5) - 1;
2993 uint32_t div_frac = div & 0x1F;
2994 return _cyhal_utils_peri_pclk_set_frac_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock, div_int, div_frac);
2995 }
2996 else
2997 return rslt;
2998 }
2999 }
_cyhal_clock_set_divider_peripheral(cyhal_clock_t * clock,uint32_t divider)3000 static cy_rslt_t _cyhal_clock_set_divider_peripheral(cyhal_clock_t *clock, uint32_t divider)
3001 {
3002 #if !defined(COMPONENT_CAT1D)
3003 CY_UNUSED_PARAMETER(clock);
3004 #else
3005 if (!_cyhal_clock_is_source_enabled_peripheral(clock))
3006 {
3007 /** Access to peri clock configuration registers will give no effect if
3008 * corresponding source HF clock is turned off. It needs to be turned on in order to proceed */
3009 return CYHAL_CLOCK_RSLT_ERR_SOURCE_DISABLED;
3010 }
3011 #endif
3012
3013 // blocks 0b00 & 0b01 are integer, 0b10 & 0b11 are fractional
3014 return ((clock->block & 0x02) == 0)
3015 ? _cyhal_utils_peri_pclk_set_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock, divider - 1)
3016 : _cyhal_utils_peri_pclk_set_frac_divider(_CYHAL_CLOCK_GET_PCLK_GR_NUM(clock->block), clock, divider - 1, 0);
3017 }
_cyhal_clock_get_sources_peripheral(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)3018 static cy_rslt_t _cyhal_clock_get_sources_peripheral(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
3019 {
3020 #if defined(COMPONENT_CAT1A)
3021 return _cyhal_clock_get_sources_slow(clock, sources, count);
3022 #elif defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C) || defined(COMPONENT_CAT1D)
3023 #if defined(COMPONENT_CAT1D)
3024 uint8_t instance = _CYHAL_PERIPHERAL_CLOCK_GET_INSTANCE(clock->block);
3025 uint8_t group = _CYHAL_PERIPHERAL_CLOCK_GET_GROUP(clock->block);
3026 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(_CYHAL_UTILS_PACK_INSTANCE_GROUP(instance, group));
3027 #else /* !defined(COMPONENT_CAT1D) */
3028 uint8_t group = _CYHAL_PERIPHERAL_GROUP_GET_GROUP(clock->block);
3029 uint8_t hfclk = _cyhal_utils_get_hfclk_for_peri_group(group);
3030 #endif /* defined(COMPONENT_CAT1D) or other */
3031 return _cyhal_clock_get_sources_peri_peripheral(hfclk, sources, count);
3032 #endif
3033 }
3034
3035
3036
3037 /******************************************************************************
3038 ******************************* Clock Structs ********************************
3039 *****************************************************************************/
3040
3041 /* Use a structure with function pointers to allow the driver to optimize out entire clocks if they
3042 * are not used. We make two exceptions to this. HF and peripheral clocks are called directly by
3043 * the public functions. This allows those clocks to be optimized based on what the user actually
3044 * calls. This distinction is done based on what the user is most likely to do with the HAL driver.
3045 * HF & peripheral clocks are likely to be configured at runtime based on setting up different
3046 * peripherals. Other system clocks are likely to be be set once at startup and never modified.
3047 * Based on this, we design the code so the compiler can optimize out the unused items most
3048 * efficiently.
3049 */
3050
3051 typedef struct
3052 {
3053 bool (*is_enabled)(const cyhal_clock_t *clock);
3054 cy_rslt_t (*set_enabled)(cyhal_clock_t *clock, bool enabled, bool wait_for_lock);
3055 uint32_t (*get_frequency)(const cyhal_clock_t *clock);
3056 cy_rslt_t (*set_frequency)(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance);
3057 cy_rslt_t (*set_divider)(cyhal_clock_t *clock, uint32_t divider);
3058 cy_rslt_t (*get_sources)(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count);
3059 cy_rslt_t (*set_source)(cyhal_clock_t *clock, const cyhal_clock_t *source);
3060 cyhal_clock_feature_t features;
3061 } cyhal_clock_funcs_t;
3062
3063 #if !defined(COMPONENT_CAT1D)
3064 static const cyhal_clock_funcs_t FUNCS_IMO =
3065 {
3066 .features = CYHAL_CLOCK_FEATURE_NONE,
3067 .is_enabled = _cyhal_clock_is_enabled_true,
3068 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3069 .get_frequency = _cyhal_clock_get_frequency_imo,
3070 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3071 .set_divider = _cyhal_clock_set_divider_unsupported,
3072 .get_sources = _cyhal_clock_get_sources_none,
3073 .set_source = _cyhal_clock_set_source_unsupported,
3074 };
3075 #endif
3076
3077 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
3078 static const cyhal_clock_funcs_t FUNCS_IHO =
3079 {
3080 .features = CYHAL_CLOCK_FEATURE_ENABLE,
3081 .is_enabled = _cyhal_clock_is_enabled_iho,
3082 .set_enabled = _cyhal_clock_set_enabled_iho,
3083 .get_frequency = _cyhal_clock_get_frequency_iho,
3084 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3085 .set_divider = _cyhal_clock_set_divider_unsupported,
3086 .get_sources = _cyhal_clock_get_sources_none,
3087 .set_source = _cyhal_clock_set_source_unsupported,
3088 };
3089 #endif
3090
3091 #if defined(COMPONENT_CAT1C)
3092 static const cyhal_clock_funcs_t FUNCS_MEM =
3093 {
3094 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY),
3095 .is_enabled = _cyhal_clock_is_enabled_true,
3096 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3097 .get_frequency = _cyhal_clock_get_frequency_mem,
3098 .set_frequency = _cyhal_clock_set_frequency_mem,
3099 .set_divider = _cyhal_clock_set_divider_mem,
3100 .get_sources = _cyhal_clock_get_sources_mem,
3101 .set_source = _cyhal_clock_set_source_unsupported,
3102 };
3103 #endif
3104
3105 #if SRSS_ECO_PRESENT
3106 static const cyhal_clock_funcs_t FUNCS_ECO =
3107 {
3108 .features = CYHAL_CLOCK_FEATURE_ENABLE,
3109 .is_enabled = _cyhal_clock_is_enabled_eco,
3110 .set_enabled = _cyhal_clock_set_enabled_eco,
3111 .get_frequency = _cyhal_clock_get_frequency_eco,
3112 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3113 .set_divider = _cyhal_clock_set_divider_unsupported,
3114 .get_sources = _cyhal_clock_get_sources_none,
3115 .set_source = _cyhal_clock_set_source_unsupported,
3116 };
3117 #endif
3118
3119 static const cyhal_clock_funcs_t FUNCS_EXT =
3120 {
3121 .features = CYHAL_CLOCK_FEATURE_FREQUENCY,
3122 .is_enabled = _cyhal_clock_is_enabled_ext,
3123 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3124 .get_frequency = _cyhal_clock_get_frequency_ext,
3125 .set_frequency = _cyhal_clock_set_frequency_ext,
3126 .set_divider = _cyhal_clock_set_divider_unsupported,
3127 .get_sources = _cyhal_clock_get_sources_none,
3128 .set_source = _cyhal_clock_set_source_unsupported,
3129 };
3130
3131 #if SRSS_ALTHF_PRESENT
3132 static const cyhal_clock_funcs_t FUNCS_ALTHF =
3133 {
3134 .features = CYHAL_CLOCK_FEATURE_NONE,
3135 .is_enabled = _cyhal_clock_is_enabled_althf,
3136 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3137 .get_frequency = _cyhal_clock_get_frequency_althf,
3138 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3139 .set_divider = _cyhal_clock_set_divider_unsupported,
3140 .get_sources = _cyhal_clock_get_sources_none,
3141 .set_source = _cyhal_clock_set_source_unsupported,
3142 };
3143 #endif
3144
3145 #if SRSS_ALTLF_PRESENT
3146 static const cyhal_clock_funcs_t FUNCS_ALTLF =
3147 {
3148 .features = CYHAL_CLOCK_FEATURE_NONE,
3149 .is_enabled = _cyhal_clock_is_enabled_altlf,
3150 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3151 .get_frequency = _cyhal_clock_get_frequency_altlf,
3152 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3153 .set_divider = _cyhal_clock_set_divider_unsupported,
3154 .get_sources = _cyhal_clock_get_sources_none,
3155 .set_source = _cyhal_clock_set_source_unsupported,
3156 };
3157 #endif
3158
3159 #if _CYHAL_SRSS_ILO_PRESENT
3160 static const cyhal_clock_funcs_t FUNCS_ILO =
3161 {
3162 .features = CYHAL_CLOCK_FEATURE_ENABLE,
3163 .is_enabled = _cyhal_clock_is_enabled_ilo,
3164 .set_enabled = _cyhal_clock_set_enabled_ilo,
3165 .get_frequency = _cyhal_clock_get_frequency_ilo,
3166 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3167 .set_divider = _cyhal_clock_set_divider_unsupported,
3168 .get_sources = _cyhal_clock_get_sources_none,
3169 .set_source = _cyhal_clock_set_source_unsupported,
3170 };
3171 #endif
3172
3173 #if _CYHAL_SRSS_PILO_PRESENT
3174 static const cyhal_clock_funcs_t FUNCS_PILO =
3175 {
3176 .features = CYHAL_CLOCK_FEATURE_ENABLE,
3177 .is_enabled = _cyhal_clock_is_enabled_pilo,
3178 .set_enabled = _cyhal_clock_set_enabled_pilo,
3179 .get_frequency = _cyhal_clock_get_frequency_pilo,
3180 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3181 .set_divider = _cyhal_clock_set_divider_unsupported,
3182 .get_sources = _cyhal_clock_get_sources_none,
3183 .set_source = _cyhal_clock_set_source_unsupported,
3184 };
3185 #endif
3186
3187 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
3188 static const cyhal_clock_funcs_t FUNCS_WCO =
3189 {
3190 .features = CYHAL_CLOCK_FEATURE_ENABLE,
3191 .is_enabled = _cyhal_clock_is_enabled_wco,
3192 .set_enabled = _cyhal_clock_set_enabled_wco,
3193 .get_frequency = _cyhal_clock_get_frequency_wco,
3194 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3195 .set_divider = _cyhal_clock_set_divider_unsupported,
3196 .get_sources = _cyhal_clock_get_sources_none,
3197 .set_source = _cyhal_clock_set_source_unsupported,
3198 };
3199 #endif
3200
3201 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
3202 static const cyhal_clock_funcs_t FUNCS_MFO =
3203 {
3204 .features = CYHAL_CLOCK_FEATURE_ENABLE,
3205 .is_enabled = _cyhal_clock_is_enabled_mfo,
3206 .set_enabled = _cyhal_clock_set_enabled_mfo,
3207 .get_frequency = _cyhal_clock_get_frequency_mfo,
3208 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3209 .set_divider = _cyhal_clock_set_divider_unsupported,
3210 .get_sources = _cyhal_clock_get_sources_mfo,
3211 .set_source = _cyhal_clock_set_source_unsupported,
3212 };
3213 #endif
3214
3215 static const cyhal_clock_funcs_t FUNCS_PATHMUX =
3216 {
3217 .features = CYHAL_CLOCK_FEATURE_SOURCE,
3218 .is_enabled = _cyhal_clock_is_enabled_true,
3219 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3220 .get_frequency = _cyhal_clock_get_frequency_pathmux,
3221 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3222 .set_divider = _cyhal_clock_set_divider_unsupported,
3223 .get_sources = _cyhal_clock_get_sources_pathmux,
3224 .set_source = _cyhal_clock_set_source_pathmux,
3225 };
3226
3227 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
3228 static const cyhal_clock_funcs_t FUNCS_FLL =
3229 {
3230 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_FREQUENCY),
3231 .is_enabled = _cyhal_clock_is_enabled_fll,
3232 .set_enabled = _cyhal_clock_set_enabled_fll,
3233 .get_frequency = _cyhal_clock_get_frequency_fll,
3234 .set_frequency = _cyhal_clock_set_frequency_fll,
3235 .set_divider = _cyhal_clock_set_divider_unsupported,
3236 .get_sources = _cyhal_clock_get_sources_fll,
3237 .set_source = _cyhal_clock_set_source_unsupported,
3238 };
3239 #endif
3240
3241 #if (_CYHAL_SRSS_NUM_PLL > 0)
3242 static const cyhal_clock_funcs_t FUNCS_PLL =
3243 {
3244 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_FREQUENCY),
3245 .is_enabled = _cyhal_clock_is_enabled_pll,
3246 .set_enabled = _cyhal_clock_set_enabled_pll,
3247 .get_frequency = _cyhal_clock_get_frequency_pll,
3248 .set_frequency = _cyhal_clock_set_frequency_pll,
3249 .set_divider = _cyhal_clock_set_divider_unsupported,
3250 .get_sources = _cyhal_clock_get_sources_pll,
3251 .set_source = _cyhal_clock_set_source_unsupported,
3252 };
3253 #endif
3254
3255 #if defined(COMPONENT_CAT1C)
3256 #if (SRSS_NUM_PLL > 0)
3257 #define FUNCS_PLL200 FUNCS_PLL
3258 #endif
3259 #if (SRSS_NUM_PLL400M > 0)
3260 #define FUNCS_PLL400 FUNCS_PLL
3261 #endif
3262 #endif /* defined(COMPONENT_CAT1C) */
3263
3264 #if defined(COMPONENT_CAT1D)
3265 #if (SRSS_NUM_DPLL250M > 0)
3266 #define FUNCS_DPLL250 FUNCS_PLL
3267 #endif
3268 #if (SRSS_NUM_DPLL500M > 0)
3269 #define FUNCS_DPLL500 FUNCS_PLL
3270 #endif
3271 #endif /* defined(COMPONENT_CAT1D) */
3272
3273 static const cyhal_clock_funcs_t FUNCS_LF =
3274 {
3275 .features = CYHAL_CLOCK_FEATURE_SOURCE,
3276 .is_enabled = _cyhal_clock_is_enabled_true,
3277 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3278 .get_frequency = _cyhal_clock_get_frequency_lf,
3279 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3280 .set_divider = _cyhal_clock_set_divider_unsupported,
3281 .get_sources = _cyhal_clock_get_sources_lf,
3282 .set_source = _cyhal_clock_set_source_lf,
3283 };
3284
3285 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT) || defined(CY_IP_MXS22SRSS)
3286 static const cyhal_clock_funcs_t FUNCS_MF =
3287 {
3288 #if defined(COMPONENT_CAT1A) /* CAT1A only supports driving clk_mf from the MFO */
3289 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY),
3290 #else
3291 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY | CYHAL_CLOCK_FEATURE_SOURCE),
3292 #endif
3293 .is_enabled = _cyhal_clock_is_enabled_mf,
3294 .set_enabled = _cyhal_clock_set_enabled_mf,
3295 .get_frequency = _cyhal_clock_get_frequency_mf,
3296 .set_frequency = _cyhal_clock_set_frequency_mf,
3297 .set_divider = _cyhal_clock_set_divider_mf,
3298 .get_sources = _cyhal_clock_get_sources_mf,
3299 .set_source = _cyhal_clock_set_source_mf,
3300 };
3301 #endif
3302
3303 static const cyhal_clock_funcs_t FUNCS_HF =
3304 {
3305 // NOTE: HF0 cannot be disabled, it would stop the MCUs. Ideally HF0 would not support
3306 // CYHAL_CLOCK_FEATURE_ENABLE, but this struct is never actually used in practice so it doesn't
3307 // matter.
3308 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_SOURCE | CYHAL_CLOCK_FEATURE_DIVIDER),
3309 .is_enabled = _cyhal_clock_is_enabled_hf,
3310 .set_enabled = _cyhal_clock_set_enabled_hf,
3311 .get_frequency = _cyhal_clock_get_frequency_hf,
3312 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3313 .set_divider = _cyhal_clock_set_divider_hf,
3314 .get_sources = _cyhal_clock_get_sources_hf,
3315 .set_source = _cyhal_clock_set_source_hf,
3316 };
3317
3318 // PUMP clock is only available on CAT1A and CAT1B devices
3319 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
3320 static const cyhal_clock_funcs_t FUNCS_PUMP =
3321 {
3322 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_SOURCE | CYHAL_CLOCK_FEATURE_DIVIDER),
3323 .is_enabled = _cyhal_clock_is_enabled_pump,
3324 .set_enabled = _cyhal_clock_set_enabled_pump,
3325 .get_frequency = _cyhal_clock_get_frequency_pump,
3326 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3327 .set_divider = _cyhal_clock_set_divider_pump,
3328 .get_sources = _cyhal_clock_get_sources_pump,
3329 .set_source = _cyhal_clock_set_source_pump,
3330 };
3331 #endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
3332
3333 #if defined(COMPONENT_CAT1A)
3334 static const cyhal_clock_funcs_t FUNCS_TIMER =
3335 {
3336 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_SOURCE | CYHAL_CLOCK_FEATURE_DIVIDER),
3337 .is_enabled = _cyhal_clock_is_enabled_timer,
3338 .set_enabled = _cyhal_clock_set_enabled_timer,
3339 .get_frequency = _cyhal_clock_get_frequency_timer,
3340 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3341 .set_divider = _cyhal_clock_set_divider_timer,
3342 .get_sources = _cyhal_clock_get_sources_timer,
3343 .set_source = _cyhal_clock_set_source_timer,
3344 };
3345 #endif
3346
3347 static const cyhal_clock_funcs_t FUNCS_BAK =
3348 {
3349 .features = CYHAL_CLOCK_FEATURE_SOURCE,
3350 .is_enabled = _cyhal_clock_is_enabled_true,
3351 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3352 .get_frequency = _cyhal_clock_get_frequency_bak,
3353 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3354 .set_divider = _cyhal_clock_set_divider_unsupported,
3355 .get_sources = _cyhal_clock_get_sources_bak,
3356 .set_source = _cyhal_clock_set_source_bak,
3357 };
3358
3359 #if !defined(COMPONENT_CAT1D)
3360 static const cyhal_clock_funcs_t FUNCS_ALT_SYS_TICK =
3361 {
3362 .features = CYHAL_CLOCK_FEATURE_SOURCE,
3363 .is_enabled = _cyhal_clock_is_enabled_true,
3364 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3365 .get_frequency = _cyhal_clock_get_frequency_alt_sys_tick,
3366 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3367 .set_divider = _cyhal_clock_set_divider_unsupported,
3368 .get_sources = _cyhal_clock_get_sources_alt_sys_tick,
3369 .set_source = _cyhal_clock_set_source_alt_sys_tick,
3370 };
3371 #endif
3372
3373 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
3374 static const cyhal_clock_funcs_t FUNCS_FAST =
3375 {
3376 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY),
3377 .is_enabled = _cyhal_clock_is_enabled_true,
3378 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3379 .get_frequency = _cyhal_clock_get_frequency_fast,
3380 .set_frequency = _cyhal_clock_set_frequency_fast,
3381 .set_divider = _cyhal_clock_set_divider_fast,
3382 .get_sources = _cyhal_clock_get_sources_fast,
3383 .set_source = _cyhal_clock_set_source_unsupported,
3384 };
3385
3386 static const cyhal_clock_funcs_t FUNCS_SLOW =
3387 {
3388 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY),
3389 .is_enabled = _cyhal_clock_is_enabled_true,
3390 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3391 .get_frequency = _cyhal_clock_get_frequency_slow,
3392 .set_frequency = _cyhal_clock_set_frequency_slow,
3393 .set_divider = _cyhal_clock_set_divider_slow,
3394 .get_sources = _cyhal_clock_get_sources_slow,
3395 .set_source = _cyhal_clock_set_source_unsupported,
3396 };
3397 #endif
3398 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
3399 #if SRSS_ECO_PRESENT
3400 static const cyhal_clock_funcs_t FUNCS_ECO_PRESCALER =
3401 {
3402 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_DIVIDER),
3403 .is_enabled = _cyhal_clock_is_enabled_true,
3404 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3405 .get_frequency = _cyhal_clock_get_frequency_eco_prescaler,
3406 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3407 .set_divider = _cyhal_clock_set_divider_eco_prescaler,
3408 .get_sources = _cyhal_clock_get_sources_eco_prescaler,
3409 .set_source = _cyhal_clock_set_source_unsupported,
3410 };
3411 #endif
3412
3413 #if SRSS_BACKUP_S40E_LPECO_PRESENT
3414 static const cyhal_clock_funcs_t FUNCS_LPECO_PRESCALER =
3415 {
3416 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_DIVIDER),
3417 .is_enabled = _cyhal_clock_is_enabled_true,
3418 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3419 .get_frequency = _cyhal_clock_get_frequency_lpeco_prescaler,
3420 .set_frequency = _cyhal_clock_set_frequency_unsupported,
3421 .set_divider = _cyhal_clock_set_divider_lpeco_prescaler,
3422 .get_sources = _cyhal_clock_get_sources_lpeco_prescaler,
3423 .set_source = _cyhal_clock_set_source_unsupported,
3424 };
3425 #endif
3426 #endif
3427
3428 static const cyhal_clock_funcs_t FUNCS_PERI =
3429 {
3430 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY),
3431 .is_enabled = _cyhal_clock_is_enabled_true,
3432 .set_enabled = _cyhal_clock_set_enabled_unsupported,
3433 .get_frequency = _cyhal_clock_get_frequency_peri,
3434 .set_frequency = _cyhal_clock_set_frequency_peri,
3435 .set_divider = _cyhal_clock_set_divider_peri,
3436 .get_sources = _cyhal_clock_get_sources_peri,
3437 .set_source = _cyhal_clock_set_source_unsupported,
3438 };
3439
3440 static const cyhal_clock_funcs_t FUNCS_PERIPHERAL =
3441 {
3442 .features = (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY),
3443 .is_enabled = _cyhal_clock_is_enabled_peripheral,
3444 .set_enabled = _cyhal_clock_set_enabled_peripheral,
3445 .get_frequency = _cyhal_clock_get_frequency_peripheral,
3446 .set_frequency = _cyhal_clock_set_frequency_peripheral,
3447 .set_divider = _cyhal_clock_set_divider_peripheral,
3448 .get_sources = _cyhal_clock_get_sources_peripheral,
3449 .set_source = _cyhal_clock_set_source_unsupported,
3450 };
3451
3452
3453 static const cyhal_clock_funcs_t FUNCS_EMPTY =
3454 {
3455 .features = CYHAL_CLOCK_FEATURE_NONE,
3456 .is_enabled = NULL,
3457 .set_enabled = NULL,
3458 .get_frequency = NULL,
3459 .set_frequency = NULL,
3460 .set_divider = NULL,
3461 .get_sources = NULL,
3462 .set_source = NULL,
3463 };
3464
_cyhal_clock_get_funcs_pathmux(void)3465 const void* _cyhal_clock_get_funcs_pathmux(void) { return &FUNCS_PATHMUX; }
3466 #if (_CYHAL_SRSS_NUM_PLL > 0)
_cyhal_clock_get_funcs_pll(void)3467 const void* _cyhal_clock_get_funcs_pll(void) { return &FUNCS_PLL; }
3468 #endif
3469 // HF and peripheral functions are called directly from the public APIs and do not go through
3470 // the struct lookup. This allows them to get optimized out based on what the user calls. We
3471 // return FUNCS_EMPTY here so as to avoid unnecessarily pulling in all functions for those clocks.
_cyhal_clock_get_funcs_hf(void)3472 const void* _cyhal_clock_get_funcs_hf(void) { return &FUNCS_EMPTY/*FUNCS_HF*/; }
_cyhal_clock_get_funcs_peripheral(void)3473 const void* _cyhal_clock_get_funcs_peripheral(void) { return &FUNCS_EMPTY/*FUNCS_PERIPHERAL*/; }
3474
_cyhal_clock_get_funcs_all(cyhal_clock_block_t block)3475 static const cyhal_clock_funcs_t* _cyhal_clock_get_funcs_all(cyhal_clock_block_t block)
3476 {
3477 switch (block)
3478 {
3479 #if !defined(COMPONENT_CAT1D)
3480 case CYHAL_CLOCK_BLOCK_IMO:
3481 return &FUNCS_IMO;
3482 #endif
3483 #if SRSS_ECO_PRESENT
3484 case CYHAL_CLOCK_BLOCK_ECO:
3485 return &FUNCS_ECO;
3486 #endif
3487 case CYHAL_CLOCK_BLOCK_EXT:
3488 return &FUNCS_EXT;
3489 #if SRSS_ALTHF_PRESENT
3490 case CYHAL_CLOCK_BLOCK_ALTHF:
3491 return &FUNCS_ALTHF;
3492 #endif
3493 #if SRSS_ALTLF_PRESENT
3494 case CYHAL_CLOCK_BLOCK_ALTLF:
3495 return &FUNCS_ALTLF;
3496 #endif
3497 #if _CYHAL_SRSS_ILO_PRESENT
3498 case CYHAL_CLOCK_BLOCK_ILO:
3499 return &FUNCS_ILO;
3500 #endif
3501 #if _CYHAL_SRSS_PILO_PRESENT
3502 case CYHAL_CLOCK_BLOCK_PILO:
3503 return &FUNCS_PILO;
3504 #endif
3505 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
3506 case CYHAL_CLOCK_BLOCK_WCO:
3507 return &FUNCS_WCO;
3508 #endif
3509 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
3510 case CYHAL_CLOCK_BLOCK_MFO:
3511 return &FUNCS_MFO;
3512 #endif
3513 case CYHAL_CLOCK_BLOCK_PATHMUX:
3514 return &FUNCS_PATHMUX;
3515 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
3516 case CYHAL_CLOCK_BLOCK_FLL:
3517 return &FUNCS_FLL;
3518 #endif
3519 case CYHAL_CLOCK_BLOCK_LF:
3520 return &FUNCS_LF;
3521 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT) || defined(CY_IP_MXS22SRSS)
3522 case CYHAL_CLOCK_BLOCK_MF:
3523 return &FUNCS_MF;
3524 #endif
3525 case CYHAL_CLOCK_BLOCK_HF:
3526 return &FUNCS_HF;
3527 // PUMP clock is only available on CAT1A and CAT1B devices
3528 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
3529 case CYHAL_CLOCK_BLOCK_PUMP:
3530 return &FUNCS_PUMP;
3531 #endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
3532 case CYHAL_CLOCK_BLOCK_BAK:
3533 return &FUNCS_BAK;
3534 #if !defined(COMPONENT_CAT1D)
3535 case CYHAL_CLOCK_BLOCK_ALT_SYS_TICK:
3536 return &FUNCS_ALT_SYS_TICK;
3537 #endif
3538 case CYHAL_CLOCK_BLOCK_PERI:
3539 return &FUNCS_PERI;
3540 #if defined(COMPONENT_CAT1A)
3541 #if (_CYHAL_SRSS_NUM_PLL > 0)
3542 case CYHAL_CLOCK_BLOCK_PLL:
3543 return &FUNCS_PLL;
3544 #endif
3545 #endif
3546 #if defined(COMPONENT_CAT1C)
3547 case CYHAL_CLOCK_BLOCK_MEM:
3548 return &FUNCS_MEM;
3549 #endif
3550 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
3551 #if defined(COMPONENT_CAT1A)
3552 case CYHAL_CLOCK_BLOCK_TIMER:
3553 return &FUNCS_TIMER;
3554 #endif
3555 case CYHAL_CLOCK_BLOCK_FAST:
3556 return &FUNCS_FAST;
3557 case CYHAL_CLOCK_BLOCK_SLOW:
3558 return &FUNCS_SLOW;
3559 #endif
3560 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
3561 #if (_CYHAL_SRSS_NUM_PLL > 0)
3562 case CYHAL_CLOCK_BLOCK_PLL200:
3563 return &FUNCS_PLL200;
3564 case CYHAL_CLOCK_BLOCK_PLL400:
3565 return &FUNCS_PLL400;
3566 #endif
3567 #endif
3568 #if defined(COMPONENT_CAT1D)
3569 #if (_CYHAL_SRSS_NUM_PLL > 0)
3570 case CYHAL_CLOCK_BLOCK_DPLL250:
3571 return &FUNCS_DPLL250;
3572 case CYHAL_CLOCK_BLOCK_DPLL500:
3573 return &FUNCS_DPLL500;
3574 #endif
3575 #endif
3576 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1D)
3577 case CYHAL_CLOCK_BLOCK_IHO:
3578 return &FUNCS_IHO;
3579 #if SRSS_ECO_PRESENT
3580 case CYHAL_CLOCK_BLOCK_ECO_PRESCALER:
3581 return &FUNCS_ECO_PRESCALER;
3582 #endif
3583 #if SRSS_BACKUP_S40E_LPECO_PRESENT
3584 case CY_SYSCLK_CLKLF_IN_LPECO_PRESCALER:
3585 return &FUNCS_LPECO_PRESCALER;
3586 #endif
3587 #endif
3588 default:
3589 return &FUNCS_PERIPHERAL;
3590 }
3591 }
3592
3593 #define _CYHAL_CLOCK_CREATE(x,y) { .block = (CYHAL_CLOCK_BLOCK_##x), .channel = (y), .reserved = false, .funcs = &(FUNCS_##x) }
3594
3595 #if !defined(COMPONENT_CAT1D)
3596 const cyhal_clock_t CYHAL_CLOCK_IMO = _CYHAL_CLOCK_CREATE(IMO, 0);
3597 #endif
3598 const cyhal_clock_t CYHAL_CLOCK_EXT = _CYHAL_CLOCK_CREATE(EXT, 0);
3599 #if _CYHAL_SRSS_ILO_PRESENT
3600 #if defined(COMPONENT_CAT1C)
3601 const cyhal_clock_t CYHAL_CLOCK_ILO[_CYHAL_SRSS_NUM_ILO] =
3602 {
3603 _CYHAL_CLOCK_CREATE(ILO, 0),
3604 #if (SRSS_HT_VARIANT > 0)
3605 _CYHAL_CLOCK_CREATE(ILO, 1),
3606 #endif
3607 };
3608 #else
3609 const cyhal_clock_t CYHAL_CLOCK_ILO = _CYHAL_CLOCK_CREATE(ILO, 0);
3610 #endif
3611 #endif
3612 const cyhal_clock_t CYHAL_CLOCK_LF = _CYHAL_CLOCK_CREATE(LF, 0);
3613 // PUMP clock is only available on CAT1A and CAT1B devices
3614 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
3615 const cyhal_clock_t CYHAL_CLOCK_PUMP = _CYHAL_CLOCK_CREATE(PUMP, 0);
3616 #endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
3617 const cyhal_clock_t CYHAL_CLOCK_BAK = _CYHAL_CLOCK_CREATE(BAK, 0);
3618 #if !defined (COMPONENT_CAT1D)
3619 const cyhal_clock_t CYHAL_CLOCK_ALT_SYS_TICK = _CYHAL_CLOCK_CREATE(ALT_SYS_TICK, 0);
3620 #endif
3621
3622 const cyhal_clock_t CYHAL_CLOCK_PATHMUX[SRSS_NUM_CLKPATH] =
3623 {
3624 _CYHAL_CLOCK_CREATE(PATHMUX, 0),
3625 #if (SRSS_NUM_CLKPATH > 1)
3626 _CYHAL_CLOCK_CREATE(PATHMUX, 1),
3627 #endif
3628 #if (SRSS_NUM_CLKPATH > 2)
3629 _CYHAL_CLOCK_CREATE(PATHMUX, 2),
3630 #endif
3631 #if (SRSS_NUM_CLKPATH > 3)
3632 _CYHAL_CLOCK_CREATE(PATHMUX, 3),
3633 #endif
3634 #if (SRSS_NUM_CLKPATH > 4)
3635 _CYHAL_CLOCK_CREATE(PATHMUX, 4),
3636 #endif
3637 #if (SRSS_NUM_CLKPATH > 5)
3638 _CYHAL_CLOCK_CREATE(PATHMUX, 5),
3639 #endif
3640 #if (SRSS_NUM_CLKPATH > 6)
3641 _CYHAL_CLOCK_CREATE(PATHMUX, 6),
3642 #endif
3643 #if (SRSS_NUM_CLKPATH > 7)
3644 _CYHAL_CLOCK_CREATE(PATHMUX, 7),
3645 #endif
3646 #if (SRSS_NUM_CLKPATH > 8)
3647 _CYHAL_CLOCK_CREATE(PATHMUX, 8),
3648 #endif
3649 #if (SRSS_NUM_CLKPATH > 9)
3650 _CYHAL_CLOCK_CREATE(PATHMUX, 9),
3651 #endif
3652 #if (SRSS_NUM_CLKPATH > 10)
3653 _CYHAL_CLOCK_CREATE(PATHMUX, 10),
3654 #endif
3655 #if (SRSS_NUM_CLKPATH > 11)
3656 _CYHAL_CLOCK_CREATE(PATHMUX, 11),
3657 #endif
3658 #if (SRSS_NUM_CLKPATH > 12)
3659 _CYHAL_CLOCK_CREATE(PATHMUX, 12),
3660 #endif
3661 #if (SRSS_NUM_CLKPATH > 13)
3662 _CYHAL_CLOCK_CREATE(PATHMUX, 13),
3663 #endif
3664 #if (SRSS_NUM_CLKPATH > 14)
3665 _CYHAL_CLOCK_CREATE(PATHMUX, 14),
3666 #endif
3667 #if (SRSS_NUM_CLKPATH > 15)
3668 _CYHAL_CLOCK_CREATE(PATHMUX, 15),
3669 #endif
3670 };
3671
3672 const cyhal_clock_t CYHAL_CLOCK_HF[SRSS_NUM_HFROOT] =
3673 {
3674 _CYHAL_CLOCK_CREATE(HF, 0),
3675 #if (SRSS_NUM_HFROOT > 1)
3676 _CYHAL_CLOCK_CREATE(HF, 1),
3677 #endif
3678 #if (SRSS_NUM_HFROOT > 2)
3679 _CYHAL_CLOCK_CREATE(HF, 2),
3680 #endif
3681 #if (SRSS_NUM_HFROOT > 3)
3682 _CYHAL_CLOCK_CREATE(HF, 3),
3683 #endif
3684 #if (SRSS_NUM_HFROOT > 4)
3685 _CYHAL_CLOCK_CREATE(HF, 4),
3686 #endif
3687 #if (SRSS_NUM_HFROOT > 5)
3688 _CYHAL_CLOCK_CREATE(HF, 5),
3689 #endif
3690 #if (SRSS_NUM_HFROOT > 6)
3691 _CYHAL_CLOCK_CREATE(HF, 6),
3692 #endif
3693 #if (SRSS_NUM_HFROOT > 7)
3694 _CYHAL_CLOCK_CREATE(HF, 7),
3695 #endif
3696 #if (SRSS_NUM_HFROOT > 8)
3697 _CYHAL_CLOCK_CREATE(HF, 8),
3698 #endif
3699 #if (SRSS_NUM_HFROOT > 9)
3700 _CYHAL_CLOCK_CREATE(HF, 9),
3701 #endif
3702 #if (SRSS_NUM_HFROOT > 10)
3703 _CYHAL_CLOCK_CREATE(HF, 10),
3704 #endif
3705 #if (SRSS_NUM_HFROOT > 11)
3706 _CYHAL_CLOCK_CREATE(HF, 11),
3707 #endif
3708 #if (SRSS_NUM_HFROOT > 12)
3709 _CYHAL_CLOCK_CREATE(HF, 12),
3710 #endif
3711 #if (SRSS_NUM_HFROOT > 13)
3712 _CYHAL_CLOCK_CREATE(HF, 13),
3713 #endif
3714 #if (SRSS_NUM_HFROOT > 14)
3715 _CYHAL_CLOCK_CREATE(HF, 14),
3716 #endif
3717 #if (SRSS_NUM_HFROOT > 15)
3718 _CYHAL_CLOCK_CREATE(HF, 15),
3719 #endif
3720 };
3721
3722 #if SRSS_ECO_PRESENT
3723 const cyhal_clock_t CYHAL_CLOCK_ECO = _CYHAL_CLOCK_CREATE(ECO, 0);
3724 #endif
3725 #if SRSS_ALTHF_PRESENT
3726 const cyhal_clock_t CYHAL_CLOCK_ALTHF = _CYHAL_CLOCK_CREATE(ALTHF, 0);
3727 #endif
3728 #if SRSS_ALTLF_PRESENT
3729 const cyhal_clock_t CYHAL_CLOCK_ALTLF = _CYHAL_CLOCK_CREATE(ALTLF, 0);
3730 #endif
3731 #if _CYHAL_SRSS_PILO_PRESENT
3732 const cyhal_clock_t CYHAL_CLOCK_PILO = _CYHAL_CLOCK_CREATE(PILO, 0);
3733 #endif
3734 #if SRSS_BACKUP_PRESENT || SRSS_WCO_PRESENT
3735 const cyhal_clock_t CYHAL_CLOCK_WCO = _CYHAL_CLOCK_CREATE(WCO, 0);
3736 #endif
3737 #if defined(COMPONENT_CAT1B) || (SRSS_MFO_PRESENT)
3738 const cyhal_clock_t CYHAL_CLOCK_MFO = _CYHAL_CLOCK_CREATE(MFO, 0);
3739 const cyhal_clock_t CYHAL_CLOCK_MF = _CYHAL_CLOCK_CREATE(MF, 0);
3740 #endif
3741 #if defined(COMPONENT_CAT1C)
3742 const cyhal_clock_t CYHAL_CLOCK_MEM = _CYHAL_CLOCK_CREATE(MEM, 0);
3743 #endif
3744
3745 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C) || (SRSS_FLL_PRESENT)
3746 const cyhal_clock_t CYHAL_CLOCK_FLL = _CYHAL_CLOCK_CREATE(FLL, 0);
3747 #endif
3748
3749 #if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1C)
3750 #if defined(COMPONENT_CAT1C)
3751 const cyhal_clock_t CYHAL_CLOCK_FAST[2] =
3752 {
3753 _CYHAL_CLOCK_CREATE(FAST, 0),
3754 _CYHAL_CLOCK_CREATE(FAST, 1),
3755 };
3756 #else
3757 const cyhal_clock_t CYHAL_CLOCK_FAST = _CYHAL_CLOCK_CREATE(FAST, 0);
3758 #endif
3759 const cyhal_clock_t CYHAL_CLOCK_SLOW = _CYHAL_CLOCK_CREATE(SLOW, 0);
3760 #if defined(COMPONENT_CAT1A)
3761 const cyhal_clock_t CYHAL_CLOCK_PERI = _CYHAL_CLOCK_CREATE(PERI, 0);
3762 const cyhal_clock_t CYHAL_CLOCK_TIMER = _CYHAL_CLOCK_CREATE(TIMER, 0);
3763 #endif
3764
3765 #if (_CYHAL_SRSS_NUM_PLL > 0) && defined(COMPONENT_CAT1A)
3766 const cyhal_clock_t CYHAL_CLOCK_PLL[_CYHAL_SRSS_NUM_PLL] =
3767 {
3768 _CYHAL_CLOCK_CREATE(PLL, 0),
3769 #if (_CYHAL_SRSS_NUM_PLL > 1)
3770 _CYHAL_CLOCK_CREATE(PLL, 1),
3771 #endif
3772 #if (_CYHAL_SRSS_NUM_PLL > 2)
3773 _CYHAL_CLOCK_CREATE(PLL, 2),
3774 #endif
3775 #if (_CYHAL_SRSS_NUM_PLL > 3)
3776 _CYHAL_CLOCK_CREATE(PLL, 3),
3777 #endif
3778 #if (_CYHAL_SRSS_NUM_PLL > 4)
3779 _CYHAL_CLOCK_CREATE(PLL, 4),
3780 #endif
3781 #if (_CYHAL_SRSS_NUM_PLL > 5)
3782 _CYHAL_CLOCK_CREATE(PLL, 5),
3783 #endif
3784 #if (_CYHAL_SRSS_NUM_PLL > 6)
3785 _CYHAL_CLOCK_CREATE(PLL, 6),
3786 #endif
3787 #if (_CYHAL_SRSS_NUM_PLL > 7)
3788 _CYHAL_CLOCK_CREATE(PLL, 7),
3789 #endif
3790 #if (_CYHAL_SRSS_NUM_PLL > 8)
3791 _CYHAL_CLOCK_CREATE(PLL, 8),
3792 #endif
3793 #if (_CYHAL_SRSS_NUM_PLL > 9)
3794 _CYHAL_CLOCK_CREATE(PLL, 9),
3795 #endif
3796 #if (_CYHAL_SRSS_NUM_PLL > 10)
3797 _CYHAL_CLOCK_CREATE(PLL, 10),
3798 #endif
3799 #if (_CYHAL_SRSS_NUM_PLL > 11)
3800 _CYHAL_CLOCK_CREATE(PLL, 11),
3801 #endif
3802 #if (_CYHAL_SRSS_NUM_PLL > 12)
3803 _CYHAL_CLOCK_CREATE(PLL, 12),
3804 #endif
3805 #if (_CYHAL_SRSS_NUM_PLL > 13)
3806 _CYHAL_CLOCK_CREATE(PLL, 13),
3807 #endif
3808 #if (_CYHAL_SRSS_NUM_PLL > 14)
3809 _CYHAL_CLOCK_CREATE(PLL, 14),
3810 #endif
3811 };
3812 #endif
3813 #endif
3814
3815 #if defined(COMPONENT_CAT1B) || defined(COMPONENT_CAT1C)
3816 #if defined(COMPONENT_CAT1B)
3817 const cyhal_clock_t CYHAL_CLOCK_IHO = _CYHAL_CLOCK_CREATE(IHO, 0);
3818 #if SRSS_ECO_PRESENT
3819 const cyhal_clock_t CYHAL_CLOCK_ECO_PRESCALER = _CYHAL_CLOCK_CREATE(ECO_PRESCALER, 0);
3820 #endif
3821 #if SRSS_BACKUP_S40E_LPECO_PRESENT
3822 const cyhal_clock_t CYHAL_CLOCK_LPECO_PRESCALER = _CYHAL_CLOCK_CREATE(LPECO_PRESCALER, 0);
3823 #endif
3824 #endif
3825
3826 const cyhal_clock_t CYHAL_CLOCK_PERI[CY_PERI_GROUP_NR] =
3827 {
3828 _CYHAL_CLOCK_CREATE(PERI, 0),
3829 #if (CY_PERI_GROUP_NR > 1)
3830 _CYHAL_CLOCK_CREATE(PERI, 1),
3831 #endif
3832 #if (CY_PERI_GROUP_NR > 2)
3833 _CYHAL_CLOCK_CREATE(PERI, 2),
3834 #endif
3835 #if (CY_PERI_GROUP_NR > 3)
3836 _CYHAL_CLOCK_CREATE(PERI, 3),
3837 #endif
3838 #if (CY_PERI_GROUP_NR > 4)
3839 _CYHAL_CLOCK_CREATE(PERI, 4),
3840 #endif
3841 #if (CY_PERI_GROUP_NR > 5)
3842 _CYHAL_CLOCK_CREATE(PERI, 5),
3843 #endif
3844 #if (CY_PERI_GROUP_NR > 6)
3845 _CYHAL_CLOCK_CREATE(PERI, 6),
3846 #endif
3847 #if (CY_PERI_GROUP_NR > 7)
3848 _CYHAL_CLOCK_CREATE(PERI, 7),
3849 #endif
3850 #if (CY_PERI_GROUP_NR > 8)
3851 _CYHAL_CLOCK_CREATE(PERI, 8),
3852 #endif
3853 #if (CY_PERI_GROUP_NR > 9)
3854 _CYHAL_CLOCK_CREATE(PERI, 9),
3855 #endif
3856 #if (CY_PERI_GROUP_NR > 10)
3857 _CYHAL_CLOCK_CREATE(PERI, 10),
3858 #endif
3859 #if (CY_PERI_GROUP_NR > 11)
3860 _CYHAL_CLOCK_CREATE(PERI, 11),
3861 #endif
3862 #if (CY_PERI_GROUP_NR > 12)
3863 _CYHAL_CLOCK_CREATE(PERI, 12),
3864 #endif
3865 #if (CY_PERI_GROUP_NR > 13)
3866 _CYHAL_CLOCK_CREATE(PERI, 13),
3867 #endif
3868 #if (CY_PERI_GROUP_NR > 14)
3869 _CYHAL_CLOCK_CREATE(PERI, 14),
3870 #endif
3871 #if (CY_PERI_GROUP_NR > 15)
3872 _CYHAL_CLOCK_CREATE(PERI, 15),
3873 #endif
3874 };
3875
3876 #if (SRSS_NUM_PLL200M > 0)
3877 #if defined(COMPONENT_CAT1B)
3878 const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL200M] =
3879 {
3880 #else
3881 const cyhal_clock_t CYHAL_CLOCK_PLL200[SRSS_NUM_PLL200M] =
3882 {
3883 #endif
3884 _CYHAL_CLOCK_CREATE(PLL200, 0),
3885 #if (SRSS_NUM_PLL200M > 1)
3886 _CYHAL_CLOCK_CREATE(PLL200, 1),
3887 #endif
3888 #if (SRSS_NUM_PLL200M > 2)
3889 _CYHAL_CLOCK_CREATE(PLL200, 2),
3890 #endif
3891 #if (SRSS_NUM_PLL200M > 3)
3892 _CYHAL_CLOCK_CREATE(PLL200, 3),
3893 #endif
3894 #if (SRSS_NUM_PLL200M > 4)
3895 _CYHAL_CLOCK_CREATE(PLL200, 4),
3896 #endif
3897 #if (SRSS_NUM_PLL200M > 5)
3898 _CYHAL_CLOCK_CREATE(PLL200, 5),
3899 #endif
3900 #if (SRSS_NUM_PLL200M > 6)
3901 _CYHAL_CLOCK_CREATE(PLL200, 6),
3902 #endif
3903 #if (SRSS_NUM_PLL200M > 7)
3904 _CYHAL_CLOCK_CREATE(PLL200, 7),
3905 #endif
3906 #if (SRSS_NUM_PLL200M > 8)
3907 _CYHAL_CLOCK_CREATE(PLL200, 8),
3908 #endif
3909 #if (SRSS_NUM_PLL200M > 9)
3910 _CYHAL_CLOCK_CREATE(PLL200, 9),
3911 #endif
3912 #if (SRSS_NUM_PLL200M > 10)
3913 _CYHAL_CLOCK_CREATE(PLL200, 10),
3914 #endif
3915 #if (SRSS_NUM_PLL200M > 11)
3916 _CYHAL_CLOCK_CREATE(PLL200, 11),
3917 #endif
3918 #if (SRSS_NUM_PLL200M > 12)
3919 _CYHAL_CLOCK_CREATE(PLL200, 12),
3920 #endif
3921 #if (SRSS_NUM_PLL200M > 13)
3922 _CYHAL_CLOCK_CREATE(PLL200, 13),
3923 #endif
3924 #if (SRSS_NUM_PLL200M > 14)
3925 _CYHAL_CLOCK_CREATE(PLL200, 14),
3926 #endif
3927 };
3928 #endif
3929
3930 #if (SRSS_NUM_PLL400M > 0)
3931 #if defined(COMPONENT_CAT1B)
3932 const cyhal_clock_t CYHAL_CLOCK_PLL[SRSS_NUM_PLL400M] =
3933 {
3934 #else
3935 const cyhal_clock_t CYHAL_CLOCK_PLL400[SRSS_NUM_PLL400M] =
3936 {
3937 #endif
3938 _CYHAL_CLOCK_CREATE(PLL400, 0),
3939 #if (SRSS_NUM_PLL400M > 1)
3940 _CYHAL_CLOCK_CREATE(PLL400, 1),
3941 #endif
3942 #if (SRSS_NUM_PLL400M > 2)
3943 _CYHAL_CLOCK_CREATE(PLL400, 2),
3944 #endif
3945 #if (SRSS_NUM_PLL400M > 3)
3946 _CYHAL_CLOCK_CREATE(PLL400, 3),
3947 #endif
3948 #if (SRSS_NUM_PLL400M > 4)
3949 _CYHAL_CLOCK_CREATE(PLL400, 4),
3950 #endif
3951 #if (SRSS_NUM_PLL400M > 5)
3952 _CYHAL_CLOCK_CREATE(PLL400, 5),
3953 #endif
3954 #if (SRSS_NUM_PLL400M > 6)
3955 _CYHAL_CLOCK_CREATE(PLL400, 6),
3956 #endif
3957 #if (SRSS_NUM_PLL400M > 7)
3958 _CYHAL_CLOCK_CREATE(PLL400, 7),
3959 #endif
3960 #if (SRSS_NUM_PLL400M > 8)
3961 _CYHAL_CLOCK_CREATE(PLL400, 8),
3962 #endif
3963 #if (SRSS_NUM_PLL400M > 9)
3964 _CYHAL_CLOCK_CREATE(PLL400, 9),
3965 #endif
3966 #if (SRSS_NUM_PLL400M > 10)
3967 _CYHAL_CLOCK_CREATE(PLL400, 10),
3968 #endif
3969 #if (SRSS_NUM_PLL400M > 11)
3970 _CYHAL_CLOCK_CREATE(PLL400, 11),
3971 #endif
3972 #if (SRSS_NUM_PLL400M > 12)
3973 _CYHAL_CLOCK_CREATE(PLL400, 12),
3974 #endif
3975 #if (SRSS_NUM_PLL400M > 13)
3976 _CYHAL_CLOCK_CREATE(PLL400, 13),
3977 #endif
3978 #if (SRSS_NUM_PLL400M > 14)
3979 _CYHAL_CLOCK_CREATE(PLL400, 14),
3980 #endif
3981 };
3982 #endif
3983 #endif
3984
3985 #if defined(COMPONENT_CAT1D)
3986 const cyhal_clock_t CYHAL_CLOCK_DPLL250[SRSS_NUM_DPLL250M] =
3987 {
3988 #if (SRSS_NUM_DPLL250M > 0)
3989 _CYHAL_CLOCK_CREATE(DPLL250, 0),
3990 #endif
3991 #if (SRSS_NUM_DPLL250M > 1)
3992 _CYHAL_CLOCK_CREATE(DPLL250, 1),
3993 #endif
3994 #if (SRSS_NUM_DPLL250M > 2)
3995 _CYHAL_CLOCK_CREATE(DPLL250, 2),
3996 #endif
3997 #if (SRSS_NUM_DPLL250M > 3)
3998 _CYHAL_CLOCK_CREATE(DPLL250, 4),
3999 #endif
4000 #if (SRSS_NUM_DPLL250M > 4)
4001 _CYHAL_CLOCK_CREATE(DPLL250, 4),
4002 #endif
4003 };
4004 const cyhal_clock_t CYHAL_CLOCK_DPLL500[SRSS_NUM_DPLL500M] =
4005 {
4006 #if (SRSS_NUM_DPLL500M > 0)
4007 _CYHAL_CLOCK_CREATE(DPLL500, 0),
4008 #endif
4009 #if (SRSS_NUM_DPLL500M > 1)
4010 _CYHAL_CLOCK_CREATE(DPLL500, 1),
4011 #endif
4012 #if (SRSS_NUM_DPLL500M > 2)
4013 _CYHAL_CLOCK_CREATE(DPLL500, 2),
4014 #endif
4015 #if (SRSS_NUM_DPLL500M > 3)
4016 _CYHAL_CLOCK_CREATE(DPLL500, 4),
4017 #endif
4018 #if (SRSS_NUM_DPLL500M > 4)
4019 _CYHAL_CLOCK_CREATE(DPLL500, 4),
4020 #endif
4021 };
4022 #endif /* defined(COMPONENT_CAT1D) */
4023
4024
4025
4026 /******************************************************************************
4027 **************************** Public API (clocks) *****************************
4028 *****************************************************************************/
4029
_cyhal_clock_allocate_channel(cyhal_clock_t * clock,cyhal_clock_block_t block,const void * funcs)4030 cy_rslt_t _cyhal_clock_allocate_channel(cyhal_clock_t *clock, cyhal_clock_block_t block, const void* funcs)
4031 {
4032 uint8_t maxChannels = (uint8_t)_cyhal_utils_get_clock_count(block);
4033 for (uint8_t i = 0; i < maxChannels; i++)
4034 {
4035 cyhal_resource_inst_t clock_resource = { CYHAL_RSC_CLOCK, block, i };
4036 if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(&clock_resource))
4037 {
4038 clock->block = block;
4039 clock->channel = i;
4040 clock->reserved = true;
4041 clock->funcs = funcs;
4042 return CY_RSLT_SUCCESS;
4043 }
4044 }
4045 return CYHAL_HWMGR_RSLT_ERR_NONE_FREE;
4046 }
4047
cyhal_clock_get(cyhal_clock_t * clock,const cyhal_resource_inst_t * resource)4048 cy_rslt_t cyhal_clock_get(cyhal_clock_t *clock, const cyhal_resource_inst_t *resource)
4049 {
4050 CY_ASSERT(NULL != clock);
4051 CY_ASSERT(NULL != resource);
4052 CY_ASSERT(CYHAL_RSC_CLOCK == resource->type);
4053
4054 clock->block = (cyhal_clock_block_t)resource->block_num;
4055 clock->channel = resource->channel_num;
4056 clock->reserved = false;
4057 clock->funcs = _cyhal_clock_get_funcs_all((cyhal_clock_block_t)resource->block_num);
4058
4059 return CY_RSLT_SUCCESS;
4060 }
4061
cyhal_clock_reserve(cyhal_clock_t * clock,const cyhal_clock_t * clock_)4062 cy_rslt_t cyhal_clock_reserve(cyhal_clock_t *clock, const cyhal_clock_t *clock_)
4063 {
4064 CY_ASSERT(NULL != clock);
4065 CY_ASSERT(NULL != clock_);
4066
4067 cyhal_resource_inst_t clock_resource = { CYHAL_RSC_CLOCK, clock_->block, clock_->channel };
4068 cy_rslt_t rslt = cyhal_hwmgr_reserve(&clock_resource);
4069 if (CY_RSLT_SUCCESS == rslt)
4070 {
4071 memcpy(clock, clock_, sizeof(cyhal_clock_t));
4072 clock->reserved = true;
4073 }
4074 return rslt;
4075 }
4076
cyhal_clock_get_features(const cyhal_clock_t * clock)4077 cyhal_clock_feature_t cyhal_clock_get_features(const cyhal_clock_t *clock)
4078 {
4079 CY_ASSERT(NULL != clock);
4080
4081 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4082 {
4083 return (clock->channel == 0) // HF0 cannot be disabled
4084 ? (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_SOURCE | CYHAL_CLOCK_FEATURE_DIVIDER)
4085 : (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_SOURCE | CYHAL_CLOCK_FEATURE_DIVIDER);
4086 }
4087 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4088 return (cyhal_clock_feature_t)(CYHAL_CLOCK_FEATURE_ENABLE | CYHAL_CLOCK_FEATURE_DIVIDER | CYHAL_CLOCK_FEATURE_FREQUENCY);
4089 else
4090 return ((cyhal_clock_funcs_t*)clock->funcs)->features;
4091 }
4092
cyhal_clock_is_enabled(const cyhal_clock_t * clock)4093 bool cyhal_clock_is_enabled(const cyhal_clock_t *clock)
4094 {
4095 CY_ASSERT(NULL != clock);
4096
4097 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4098 return _cyhal_clock_is_enabled_hf(clock);
4099 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4100 return _cyhal_clock_is_enabled_peripheral(clock);
4101 else
4102 return ((cyhal_clock_funcs_t*)clock->funcs)->is_enabled(clock);
4103 }
4104
cyhal_clock_set_enabled(cyhal_clock_t * clock,bool enabled,bool wait_for_lock)4105 cy_rslt_t cyhal_clock_set_enabled(cyhal_clock_t *clock, bool enabled, bool wait_for_lock)
4106 {
4107 CY_ASSERT(NULL != clock);
4108
4109 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4110 return _cyhal_clock_set_enabled_hf(clock, enabled, wait_for_lock);
4111 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4112 return _cyhal_clock_set_enabled_peripheral(clock, enabled, wait_for_lock);
4113 else
4114 return ((cyhal_clock_funcs_t*)clock->funcs)->set_enabled(clock, enabled, wait_for_lock);
4115 }
4116
cyhal_clock_get_frequency(const cyhal_clock_t * clock)4117 uint32_t cyhal_clock_get_frequency(const cyhal_clock_t *clock)
4118 {
4119 CY_ASSERT(NULL != clock);
4120
4121 if (cyhal_clock_is_enabled(clock))
4122 {
4123 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4124 return _cyhal_clock_get_frequency_hf(clock);
4125 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4126 return _cyhal_clock_get_frequency_peripheral(clock);
4127 else
4128 return ((cyhal_clock_funcs_t*)clock->funcs)->get_frequency(clock);
4129 }
4130 return 0;
4131 }
4132
cyhal_clock_set_frequency(cyhal_clock_t * clock,uint32_t hz,const cyhal_clock_tolerance_t * tolerance)4133 cy_rslt_t cyhal_clock_set_frequency(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance)
4134 {
4135 CY_ASSERT(NULL != clock);
4136
4137 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4138 return _cyhal_clock_set_frequency_unsupported(clock, hz, tolerance);
4139 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4140 return _cyhal_clock_set_frequency_peripheral(clock, hz, tolerance);
4141 else
4142 return ((cyhal_clock_funcs_t*)clock->funcs)->set_frequency(clock, hz, tolerance);
4143 }
4144
cyhal_clock_set_divider(cyhal_clock_t * clock,uint32_t divider)4145 cy_rslt_t cyhal_clock_set_divider(cyhal_clock_t *clock, uint32_t divider)
4146 {
4147 CY_ASSERT(NULL != clock);
4148
4149 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4150 return _cyhal_clock_set_divider_hf(clock, divider);
4151 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4152 return _cyhal_clock_set_divider_peripheral(clock, divider);
4153 else
4154 return ((cyhal_clock_funcs_t*)clock->funcs)->set_divider(clock, divider);
4155 }
4156
cyhal_clock_get_sources(const cyhal_clock_t * clock,const cyhal_resource_inst_t ** sources[],uint32_t * count)4157 cy_rslt_t cyhal_clock_get_sources(const cyhal_clock_t *clock, const cyhal_resource_inst_t **sources[], uint32_t *count)
4158 {
4159 CY_ASSERT(NULL != clock);
4160
4161 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4162 return _cyhal_clock_get_sources_hf(clock, sources, count);
4163 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4164 return _cyhal_clock_get_sources_peripheral(clock, sources, count);
4165 else
4166 return ((cyhal_clock_funcs_t*)clock->funcs)->get_sources(clock, sources, count);
4167 }
4168
cyhal_clock_set_source(cyhal_clock_t * clock,const cyhal_clock_t * source)4169 cy_rslt_t cyhal_clock_set_source(cyhal_clock_t *clock, const cyhal_clock_t *source)
4170 {
4171 CY_ASSERT(NULL != clock && NULL != source);
4172
4173 if (clock->block == CYHAL_CLOCK_BLOCK_HF)
4174 return _cyhal_clock_set_source_hf(clock, source);
4175 else if (clock->block < 4 * _CYHAL_CLOCK_PERI_GROUPS)
4176 return _cyhal_clock_set_source_unsupported(clock, source);
4177 else
4178 return ((cyhal_clock_funcs_t*)clock->funcs)->set_source(clock, source);
4179 }
4180
cyhal_clock_free(cyhal_clock_t * clock)4181 void cyhal_clock_free(cyhal_clock_t *clock)
4182 {
4183 CY_ASSERT(NULL != clock);
4184 CY_ASSERT(clock->reserved);
4185
4186 cyhal_resource_inst_t rsc = { CYHAL_RSC_CLOCK, clock->block, clock->channel };
4187 cyhal_hwmgr_free(&rsc);
4188 clock->reserved = false;
4189 }
4190
4191 #if defined(__cplusplus)
4192 }
4193 #endif
4194
4195 #endif // CYHAL_DRIVER_AVAILABLE_CLOCK
4196
