1 /*******************************************************************************
2 * File Name: cycfg_pins.c
3 *
4 * Description:
5 * Pin configuration
6 * This file was automatically generated and should not be modified.
7 * Tools Package 2.2.0.2801
8 * latest-v2.X 2.0.0.6211
9 * personalities 3.0.0.0
10 * udd 3.0.0.562
11 *
12 ********************************************************************************
13 * Copyright 2020 Cypress Semiconductor Corporation
14 * SPDX-License-Identifier: Apache-2.0
15 *
16 * Licensed under the Apache License, Version 2.0 (the "License");
17 * you may not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
19 *
20 * http://www.apache.org/licenses/LICENSE-2.0
21 *
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an "AS IS" BASIS,
24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
27 ********************************************************************************/
28
29 #include "cycfg_pins.h"
30
31 const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
32 {
33 .outVal = 1,
34 .driveMode = CY_GPIO_DM_ANALOG,
35 .hsiom = CYBSP_WCO_IN_HSIOM,
36 .intEdge = CY_GPIO_INTR_DISABLE,
37 .intMask = 0UL,
38 .vtrip = CY_GPIO_VTRIP_CMOS,
39 .slewRate = CY_GPIO_SLEW_FAST,
40 .driveSel = CY_GPIO_DRIVE_1_2,
41 .vregEn = 0UL,
42 .ibufMode = 0UL,
43 .vtripSel = 0UL,
44 .vrefSel = 0UL,
45 .vohSel = 0UL,
46 };
47 #if defined (CY_USING_HAL)
48 const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
49 {
50 .type = CYHAL_RSC_GPIO,
51 .block_num = CYBSP_WCO_IN_PORT_NUM,
52 .channel_num = CYBSP_WCO_IN_PIN,
53 };
54 #endif //defined (CY_USING_HAL)
55 const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
56 {
57 .outVal = 1,
58 .driveMode = CY_GPIO_DM_ANALOG,
59 .hsiom = CYBSP_WCO_OUT_HSIOM,
60 .intEdge = CY_GPIO_INTR_DISABLE,
61 .intMask = 0UL,
62 .vtrip = CY_GPIO_VTRIP_CMOS,
63 .slewRate = CY_GPIO_SLEW_FAST,
64 .driveSel = CY_GPIO_DRIVE_1_2,
65 .vregEn = 0UL,
66 .ibufMode = 0UL,
67 .vtripSel = 0UL,
68 .vrefSel = 0UL,
69 .vohSel = 0UL,
70 };
71 #if defined (CY_USING_HAL)
72 const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
73 {
74 .type = CYHAL_RSC_GPIO,
75 .block_num = CYBSP_WCO_OUT_PORT_NUM,
76 .channel_num = CYBSP_WCO_OUT_PIN,
77 };
78 #endif //defined (CY_USING_HAL)
79 const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
80 {
81 .outVal = 1,
82 .driveMode = CY_GPIO_DM_ANALOG,
83 .hsiom = CYBSP_CSD_RX_HSIOM,
84 .intEdge = CY_GPIO_INTR_DISABLE,
85 .intMask = 0UL,
86 .vtrip = CY_GPIO_VTRIP_CMOS,
87 .slewRate = CY_GPIO_SLEW_FAST,
88 .driveSel = CY_GPIO_DRIVE_1_2,
89 .vregEn = 0UL,
90 .ibufMode = 0UL,
91 .vtripSel = 0UL,
92 .vrefSel = 0UL,
93 .vohSel = 0UL,
94 };
95 #if defined (CY_USING_HAL)
96 const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
97 {
98 .type = CYHAL_RSC_GPIO,
99 .block_num = CYBSP_CSD_RX_PORT_NUM,
100 .channel_num = CYBSP_CSD_RX_PIN,
101 };
102 #endif //defined (CY_USING_HAL)
103 const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
104 {
105 .outVal = 1,
106 .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
107 .hsiom = CYBSP_SWO_HSIOM,
108 .intEdge = CY_GPIO_INTR_DISABLE,
109 .intMask = 0UL,
110 .vtrip = CY_GPIO_VTRIP_CMOS,
111 .slewRate = CY_GPIO_SLEW_FAST,
112 .driveSel = CY_GPIO_DRIVE_1_2,
113 .vregEn = 0UL,
114 .ibufMode = 0UL,
115 .vtripSel = 0UL,
116 .vrefSel = 0UL,
117 .vohSel = 0UL,
118 };
119 #if defined (CY_USING_HAL)
120 const cyhal_resource_inst_t CYBSP_SWO_obj =
121 {
122 .type = CYHAL_RSC_GPIO,
123 .block_num = CYBSP_SWO_PORT_NUM,
124 .channel_num = CYBSP_SWO_PIN,
125 };
126 #endif //defined (CY_USING_HAL)
127 const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
128 {
129 .outVal = 1,
130 .driveMode = CY_GPIO_DM_PULLUP,
131 .hsiom = CYBSP_SWDIO_HSIOM,
132 .intEdge = CY_GPIO_INTR_DISABLE,
133 .intMask = 0UL,
134 .vtrip = CY_GPIO_VTRIP_CMOS,
135 .slewRate = CY_GPIO_SLEW_FAST,
136 .driveSel = CY_GPIO_DRIVE_1_2,
137 .vregEn = 0UL,
138 .ibufMode = 0UL,
139 .vtripSel = 0UL,
140 .vrefSel = 0UL,
141 .vohSel = 0UL,
142 };
143 #if defined (CY_USING_HAL)
144 const cyhal_resource_inst_t CYBSP_SWDIO_obj =
145 {
146 .type = CYHAL_RSC_GPIO,
147 .block_num = CYBSP_SWDIO_PORT_NUM,
148 .channel_num = CYBSP_SWDIO_PIN,
149 };
150 #endif //defined (CY_USING_HAL)
151 const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
152 {
153 .outVal = 1,
154 .driveMode = CY_GPIO_DM_PULLDOWN,
155 .hsiom = CYBSP_SWDCK_HSIOM,
156 .intEdge = CY_GPIO_INTR_DISABLE,
157 .intMask = 0UL,
158 .vtrip = CY_GPIO_VTRIP_CMOS,
159 .slewRate = CY_GPIO_SLEW_FAST,
160 .driveSel = CY_GPIO_DRIVE_1_2,
161 .vregEn = 0UL,
162 .ibufMode = 0UL,
163 .vtripSel = 0UL,
164 .vrefSel = 0UL,
165 .vohSel = 0UL,
166 };
167 #if defined (CY_USING_HAL)
168 const cyhal_resource_inst_t CYBSP_SWDCK_obj =
169 {
170 .type = CYHAL_RSC_GPIO,
171 .block_num = CYBSP_SWDCK_PORT_NUM,
172 .channel_num = CYBSP_SWDCK_PIN,
173 };
174 #endif //defined (CY_USING_HAL)
175 const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
176 {
177 .outVal = 1,
178 .driveMode = CY_GPIO_DM_ANALOG,
179 .hsiom = CYBSP_CINA_HSIOM,
180 .intEdge = CY_GPIO_INTR_DISABLE,
181 .intMask = 0UL,
182 .vtrip = CY_GPIO_VTRIP_CMOS,
183 .slewRate = CY_GPIO_SLEW_FAST,
184 .driveSel = CY_GPIO_DRIVE_1_2,
185 .vregEn = 0UL,
186 .ibufMode = 0UL,
187 .vtripSel = 0UL,
188 .vrefSel = 0UL,
189 .vohSel = 0UL,
190 };
191 #if defined (CY_USING_HAL)
192 const cyhal_resource_inst_t CYBSP_CINA_obj =
193 {
194 .type = CYHAL_RSC_GPIO,
195 .block_num = CYBSP_CINA_PORT_NUM,
196 .channel_num = CYBSP_CINA_PIN,
197 };
198 #endif //defined (CY_USING_HAL)
199 const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
200 {
201 .outVal = 1,
202 .driveMode = CY_GPIO_DM_ANALOG,
203 .hsiom = CYBSP_CINB_HSIOM,
204 .intEdge = CY_GPIO_INTR_DISABLE,
205 .intMask = 0UL,
206 .vtrip = CY_GPIO_VTRIP_CMOS,
207 .slewRate = CY_GPIO_SLEW_FAST,
208 .driveSel = CY_GPIO_DRIVE_1_2,
209 .vregEn = 0UL,
210 .ibufMode = 0UL,
211 .vtripSel = 0UL,
212 .vrefSel = 0UL,
213 .vohSel = 0UL,
214 };
215 #if defined (CY_USING_HAL)
216 const cyhal_resource_inst_t CYBSP_CINB_obj =
217 {
218 .type = CYHAL_RSC_GPIO,
219 .block_num = CYBSP_CINB_PORT_NUM,
220 .channel_num = CYBSP_CINB_PIN,
221 };
222 #endif //defined (CY_USING_HAL)
223 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
224 {
225 .outVal = 1,
226 .driveMode = CY_GPIO_DM_ANALOG,
227 .hsiom = CYBSP_CMOD_HSIOM,
228 .intEdge = CY_GPIO_INTR_DISABLE,
229 .intMask = 0UL,
230 .vtrip = CY_GPIO_VTRIP_CMOS,
231 .slewRate = CY_GPIO_SLEW_FAST,
232 .driveSel = CY_GPIO_DRIVE_1_2,
233 .vregEn = 0UL,
234 .ibufMode = 0UL,
235 .vtripSel = 0UL,
236 .vrefSel = 0UL,
237 .vohSel = 0UL,
238 };
239 #if defined (CY_USING_HAL)
240 const cyhal_resource_inst_t CYBSP_CMOD_obj =
241 {
242 .type = CYHAL_RSC_GPIO,
243 .block_num = CYBSP_CMOD_PORT_NUM,
244 .channel_num = CYBSP_CMOD_PIN,
245 };
246 #endif //defined (CY_USING_HAL)
247 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
248 {
249 .outVal = 1,
250 .driveMode = CY_GPIO_DM_ANALOG,
251 .hsiom = CYBSP_CSD_BTN0_HSIOM,
252 .intEdge = CY_GPIO_INTR_DISABLE,
253 .intMask = 0UL,
254 .vtrip = CY_GPIO_VTRIP_CMOS,
255 .slewRate = CY_GPIO_SLEW_FAST,
256 .driveSel = CY_GPIO_DRIVE_1_2,
257 .vregEn = 0UL,
258 .ibufMode = 0UL,
259 .vtripSel = 0UL,
260 .vrefSel = 0UL,
261 .vohSel = 0UL,
262 };
263 #if defined (CY_USING_HAL)
264 const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
265 {
266 .type = CYHAL_RSC_GPIO,
267 .block_num = CYBSP_CSD_BTN0_PORT_NUM,
268 .channel_num = CYBSP_CSD_BTN0_PIN,
269 };
270 #endif //defined (CY_USING_HAL)
271 const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
272 {
273 .outVal = 1,
274 .driveMode = CY_GPIO_DM_ANALOG,
275 .hsiom = CYBSP_CSD_BTN1_HSIOM,
276 .intEdge = CY_GPIO_INTR_DISABLE,
277 .intMask = 0UL,
278 .vtrip = CY_GPIO_VTRIP_CMOS,
279 .slewRate = CY_GPIO_SLEW_FAST,
280 .driveSel = CY_GPIO_DRIVE_1_2,
281 .vregEn = 0UL,
282 .ibufMode = 0UL,
283 .vtripSel = 0UL,
284 .vrefSel = 0UL,
285 .vohSel = 0UL,
286 };
287 #if defined (CY_USING_HAL)
288 const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
289 {
290 .type = CYHAL_RSC_GPIO,
291 .block_num = CYBSP_CSD_BTN1_PORT_NUM,
292 .channel_num = CYBSP_CSD_BTN1_PIN,
293 };
294 #endif //defined (CY_USING_HAL)
295 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
296 {
297 .outVal = 1,
298 .driveMode = CY_GPIO_DM_ANALOG,
299 .hsiom = CYBSP_CSD_SLD0_HSIOM,
300 .intEdge = CY_GPIO_INTR_DISABLE,
301 .intMask = 0UL,
302 .vtrip = CY_GPIO_VTRIP_CMOS,
303 .slewRate = CY_GPIO_SLEW_FAST,
304 .driveSel = CY_GPIO_DRIVE_1_2,
305 .vregEn = 0UL,
306 .ibufMode = 0UL,
307 .vtripSel = 0UL,
308 .vrefSel = 0UL,
309 .vohSel = 0UL,
310 };
311 #if defined (CY_USING_HAL)
312 const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
313 {
314 .type = CYHAL_RSC_GPIO,
315 .block_num = CYBSP_CSD_SLD0_PORT_NUM,
316 .channel_num = CYBSP_CSD_SLD0_PIN,
317 };
318 #endif //defined (CY_USING_HAL)
319 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
320 {
321 .outVal = 1,
322 .driveMode = CY_GPIO_DM_ANALOG,
323 .hsiom = CYBSP_CSD_SLD1_HSIOM,
324 .intEdge = CY_GPIO_INTR_DISABLE,
325 .intMask = 0UL,
326 .vtrip = CY_GPIO_VTRIP_CMOS,
327 .slewRate = CY_GPIO_SLEW_FAST,
328 .driveSel = CY_GPIO_DRIVE_1_2,
329 .vregEn = 0UL,
330 .ibufMode = 0UL,
331 .vtripSel = 0UL,
332 .vrefSel = 0UL,
333 .vohSel = 0UL,
334 };
335 #if defined (CY_USING_HAL)
336 const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
337 {
338 .type = CYHAL_RSC_GPIO,
339 .block_num = CYBSP_CSD_SLD1_PORT_NUM,
340 .channel_num = CYBSP_CSD_SLD1_PIN,
341 };
342 #endif //defined (CY_USING_HAL)
343 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
344 {
345 .outVal = 1,
346 .driveMode = CY_GPIO_DM_ANALOG,
347 .hsiom = CYBSP_CSD_SLD2_HSIOM,
348 .intEdge = CY_GPIO_INTR_DISABLE,
349 .intMask = 0UL,
350 .vtrip = CY_GPIO_VTRIP_CMOS,
351 .slewRate = CY_GPIO_SLEW_FAST,
352 .driveSel = CY_GPIO_DRIVE_1_2,
353 .vregEn = 0UL,
354 .ibufMode = 0UL,
355 .vtripSel = 0UL,
356 .vrefSel = 0UL,
357 .vohSel = 0UL,
358 };
359 #if defined (CY_USING_HAL)
360 const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
361 {
362 .type = CYHAL_RSC_GPIO,
363 .block_num = CYBSP_CSD_SLD2_PORT_NUM,
364 .channel_num = CYBSP_CSD_SLD2_PIN,
365 };
366 #endif //defined (CY_USING_HAL)
367 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
368 {
369 .outVal = 1,
370 .driveMode = CY_GPIO_DM_ANALOG,
371 .hsiom = CYBSP_CSD_SLD3_HSIOM,
372 .intEdge = CY_GPIO_INTR_DISABLE,
373 .intMask = 0UL,
374 .vtrip = CY_GPIO_VTRIP_CMOS,
375 .slewRate = CY_GPIO_SLEW_FAST,
376 .driveSel = CY_GPIO_DRIVE_1_2,
377 .vregEn = 0UL,
378 .ibufMode = 0UL,
379 .vtripSel = 0UL,
380 .vrefSel = 0UL,
381 .vohSel = 0UL,
382 };
383 #if defined (CY_USING_HAL)
384 const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
385 {
386 .type = CYHAL_RSC_GPIO,
387 .block_num = CYBSP_CSD_SLD3_PORT_NUM,
388 .channel_num = CYBSP_CSD_SLD3_PIN,
389 };
390 #endif //defined (CY_USING_HAL)
391 const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
392 {
393 .outVal = 1,
394 .driveMode = CY_GPIO_DM_ANALOG,
395 .hsiom = CYBSP_CSD_SLD4_HSIOM,
396 .intEdge = CY_GPIO_INTR_DISABLE,
397 .intMask = 0UL,
398 .vtrip = CY_GPIO_VTRIP_CMOS,
399 .slewRate = CY_GPIO_SLEW_FAST,
400 .driveSel = CY_GPIO_DRIVE_1_2,
401 .vregEn = 0UL,
402 .ibufMode = 0UL,
403 .vtripSel = 0UL,
404 .vrefSel = 0UL,
405 .vohSel = 0UL,
406 };
407 #if defined (CY_USING_HAL)
408 const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
409 {
410 .type = CYHAL_RSC_GPIO,
411 .block_num = CYBSP_CSD_SLD4_PORT_NUM,
412 .channel_num = CYBSP_CSD_SLD4_PIN,
413 };
414 #endif //defined (CY_USING_HAL)
415
416
init_cycfg_pins(void)417 void init_cycfg_pins(void)
418 {
419 Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
420 #if defined (CY_USING_HAL)
421 cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
422 #endif //defined (CY_USING_HAL)
423
424 Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
425 #if defined (CY_USING_HAL)
426 cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
427 #endif //defined (CY_USING_HAL)
428
429 #if defined (CY_USING_HAL)
430 cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
431 #endif //defined (CY_USING_HAL)
432
433 Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
434 #if defined (CY_USING_HAL)
435 cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
436 #endif //defined (CY_USING_HAL)
437
438 Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
439 #if defined (CY_USING_HAL)
440 cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
441 #endif //defined (CY_USING_HAL)
442
443 Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
444 #if defined (CY_USING_HAL)
445 cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
446 #endif //defined (CY_USING_HAL)
447
448 #if defined (CY_USING_HAL)
449 cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
450 #endif //defined (CY_USING_HAL)
451
452 #if defined (CY_USING_HAL)
453 cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
454 #endif //defined (CY_USING_HAL)
455
456 #if defined (CY_USING_HAL)
457 cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
458 #endif //defined (CY_USING_HAL)
459
460 #if defined (CY_USING_HAL)
461 cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
462 #endif //defined (CY_USING_HAL)
463
464 #if defined (CY_USING_HAL)
465 cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
466 #endif //defined (CY_USING_HAL)
467
468 #if defined (CY_USING_HAL)
469 cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
470 #endif //defined (CY_USING_HAL)
471
472 #if defined (CY_USING_HAL)
473 cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
474 #endif //defined (CY_USING_HAL)
475
476 #if defined (CY_USING_HAL)
477 cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
478 #endif //defined (CY_USING_HAL)
479
480 #if defined (CY_USING_HAL)
481 cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
482 #endif //defined (CY_USING_HAL)
483
484 #if defined (CY_USING_HAL)
485 cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
486 #endif //defined (CY_USING_HAL)
487 }
488
