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Searched defs:CTRL_CLR (Results 1 – 25 of 129) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12321 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
26930 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
31679 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
37161 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
46364 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12609 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
27457 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
32125 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
37656 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
46515 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h13839 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
28987 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
33658 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
39197 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
48621 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h13761 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
28979 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
33651 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
39190 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
48685 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h8240 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
20908 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
31795 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h8954 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
23857 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
34738 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10494 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
27900 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
40021 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10514 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
27921 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
40042 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11536 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
28972 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
42098 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12607 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
30274 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
43105 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h12975 __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ member
31016 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
44491 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h53343 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
55246 …__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x… member
61308 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
67377 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
81538 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
DMIMXRT1166_cm7.h53346 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
55249 …__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x… member
60406 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
66475 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
80636 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h53870 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
55773 …__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x… member
61829 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
67876 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
82037 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
DMIMXRT1173_cm7.h53873 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
55776 …__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x… member
60927 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
66974 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
81135 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h53876 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
55779 …__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x… member
60930 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
66977 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
81138 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h1818 …__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control R… member
10342 __IO uint32_t CTRL_CLR; /**< GIS Control Register, offset: 0x8 */ member
27707 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offse… member
37841 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offs… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h10187 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
36691 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h10188 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
36692 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h6219 …__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Registe… member
36043 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
43146 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h6219 …__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Registe… member
36043 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
43146 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h6219 …__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Registe… member
36043 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
40973 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h6219 …__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Registe… member
36043 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
43146 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h6219 …__IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Registe… member
36043 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
43146 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h64543 …__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 … member
66446 …__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x… member
71597 …__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, … member
77644 __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ member
91805 …__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x… member

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