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Searched defs:CTRL (Results 1 – 17 of 17) sorted by relevance

/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Include/
Dcore_cm0plus.h475 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
528 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_sc000.h491 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
544 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm23.h561 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
613 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
858 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
964 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_sc300.h694 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
821 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1131 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm0.h451 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_cm1.h477 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_cm3.h711 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
838 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1148 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm33.h984 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1135 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1452 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm35p.h984 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1135 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1452 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm4.h776 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
903 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1213 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_starmc1.h1045 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1184 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1549 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1661 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm7.h995 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1122 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1432 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm52.h1140 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1291 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
2184 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ member
2954 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
3069 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm55.h1088 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1239 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
2134 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ member
2904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
3019 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm85.h1088 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1239 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
2158 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ member
2928 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
3043 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
/trusted-firmware-m-latest/platform/ext/target/nxp/lpcxpresso55s69/Native_Driver/
DLPC55S69_cm33_core1.h289 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ member
6930 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ member
9758 …__IO uint32_t CTRL; /**< GPIO grouped interrupt control register, off… member
10180 …__IO uint32_t CTRL; /**< Control register to enable and operate Hash … member
13388 …__IO uint32_t CTRL; /**< MRT Control register. This register controls… member
16514 __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ member
17474 __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ member
17714 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ member
17813 …__IO uint32_t CTRL; /**< SCT event control register 0, array offset: … member
19386 __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ member
[all …]
DLPC55S69_cm33_core0.h289 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ member
6930 __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ member
9758 …__IO uint32_t CTRL; /**< GPIO grouped interrupt control register, off… member
10180 …__IO uint32_t CTRL; /**< Control register to enable and operate Hash … member
13388 …__IO uint32_t CTRL; /**< MRT Control register. This register controls… member
16514 __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */ member
17474 __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ member
17714 __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ member
17813 …__IO uint32_t CTRL; /**< SCT event control register 0, array offset: … member
19386 __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ member
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