Home
last modified time | relevance | path

Searched defs:CTRL (Results 1 – 17 of 17) sorted by relevance

/cmsis-latest/CMSIS/Core/Include/
Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_sc000.h490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_armv8mbl.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm23.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1010 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm3.h708 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
848 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1158 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_sc300.h693 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1143 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm4.h766 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
906 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1216 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_armv8mml.h967 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1119 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1405 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1517 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm35p.h967 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1119 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1480 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1592 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm33.h967 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1119 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1480 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1592 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_starmc1.h1025 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1177 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1650 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_armv81mml.h1028 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1181 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1492 …__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ member
2283 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
2398 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm7.h990 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1130 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1443 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm0.h450 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_cm1.h476 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_cm85.h1069 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1222 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1892 …__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ member
2684 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
2799 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm55.h1073 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1226 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1987 …__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ member
2779 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
2894 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member