1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_GPIO_8F_6PORT_V1_5_H 7 #define _MEC5_GPIO_8F_6PORT_V1_5_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief GPIO pin control and access as register arrays (MEC_GPIO) 15 */ 16 17 typedef struct mec_gpio_regs { /*!< (@ 0x40081000) MEC_GPIO Structure */ 18 __IOM uint32_t CTRL[192]; /*!< (@ 0x00000000) GPIO Control n */ 19 __IOM uint32_t PARIN[6]; /*!< (@ 0x00000300) GPIO bank n parallel input */ 20 __IM uint32_t RESERVED[26]; 21 __IOM uint32_t PAROUT[6]; /*!< (@ 0x00000380) GPIO bank n parallel outpu */ 22 __IM uint32_t RESERVED1[20]; 23 __IOM uint32_t LOCK[6]; /*!< (@ 0x000003E8) Lock registers for each GPIO bank of pins */ 24 __IM uint32_t RESERVED2[64]; 25 __IOM uint32_t CTL2[192]; /*!< (@ 0x00000500) GPIO n Control 2: Drive str. and slew control */ 26 } MEC_GPIO_Type; /*!< Size = 2048 (0x800) */ 27 28 /** @} */ /* End of group Device_Peripheral_peripherals */ 29 30 /** @addtogroup PosMask_peripherals 31 * @{ 32 */ 33 /* ========================================================= CTRL ========================================================== */ 34 #define MEC_GPIO_CTRL_PUD_Pos (0UL) /*!< PUD (Bit 0) */ 35 #define MEC_GPIO_CTRL_PUD_Msk (0x3UL) /*!< PUD (Bitfield-Mask: 0x03) */ 36 #define MEC_GPIO_CTRL_PGS_Pos (2UL) /*!< PGS (Bit 2) */ 37 #define MEC_GPIO_CTRL_PGS_Msk (0xcUL) /*!< PGS (Bitfield-Mask: 0x03) */ 38 #define MEC_GPIO_CTRL_IDET_Pos (4UL) /*!< IDET (Bit 4) */ 39 #define MEC_GPIO_CTRL_IDET_Msk (0xf0UL) /*!< IDET (Bitfield-Mask: 0x0f) */ 40 #define MEC_GPIO_CTRL_OBT_Pos (8UL) /*!< OBT (Bit 8) */ 41 #define MEC_GPIO_CTRL_OBT_Msk (0x100UL) /*!< OBT (Bitfield-Mask: 0x01) */ 42 #define MEC_GPIO_CTRL_DIR_Pos (9UL) /*!< DIR (Bit 9) */ 43 #define MEC_GPIO_CTRL_DIR_Msk (0x200UL) /*!< DIR (Bitfield-Mask: 0x01) */ 44 #define MEC_GPIO_CTRL_PAREN_Pos (10UL) /*!< PAREN (Bit 10) */ 45 #define MEC_GPIO_CTRL_PAREN_Msk (0x400UL) /*!< PAREN (Bitfield-Mask: 0x01) */ 46 #define MEC_GPIO_CTRL_ALTPOL_Pos (11UL) /*!< ALTPOL (Bit 11) */ 47 #define MEC_GPIO_CTRL_ALTPOL_Msk (0x800UL) /*!< ALTPOL (Bitfield-Mask: 0x01) */ 48 #define MEC_GPIO_CTRL_MUX_Pos (12UL) /*!< MUX (Bit 12) */ 49 #define MEC_GPIO_CTRL_MUX_Msk (0x7000UL) /*!< MUX (Bitfield-Mask: 0x07) */ 50 #define MEC_GPIO_CTRL_INPD_Pos (15UL) /*!< INPD (Bit 15) */ 51 #define MEC_GPIO_CTRL_INPD_Msk (0x8000UL) /*!< INPD (Bitfield-Mask: 0x01) */ 52 #define MEC_GPIO_CTRL_ALTVAL_Pos (16UL) /*!< ALTVAL (Bit 16) */ 53 #define MEC_GPIO_CTRL_ALTVAL_Msk (0x10000UL) /*!< ALTVAL (Bitfield-Mask: 0x01) */ 54 #define MEC_GPIO_CTRL_PADIN_Pos (24UL) /*!< PADIN (Bit 24) */ 55 #define MEC_GPIO_CTRL_PADIN_Msk (0x1000000UL) /*!< PADIN (Bitfield-Mask: 0x01) */ 56 /* ========================================================= PARIN ========================================================= */ 57 /* ======================================================== PAROUT ========================================================= */ 58 /* ========================================================= LOCK ========================================================== */ 59 /* ========================================================= CTL2 ========================================================== */ 60 #define MEC_GPIO_CTL2_SLR_Pos (0UL) /*!< SLR (Bit 0) */ 61 #define MEC_GPIO_CTL2_SLR_Msk (0x1UL) /*!< SLR (Bitfield-Mask: 0x01) */ 62 #define MEC_GPIO_CTL2_DRVSTR_Pos (4UL) /*!< DRVSTR (Bit 4) */ 63 #define MEC_GPIO_CTL2_DRVSTR_Msk (0x30UL) /*!< DRVSTR (Bitfield-Mask: 0x03) */ 64 65 /** @} */ /* End of group PosMask_peripherals */ 66 67 /** @addtogroup EnumValue_peripherals 68 * @{ 69 */ 70 /* ========================================================= CTRL ========================================================== */ 71 /* =============================================== MEC_GPIO CTRL PUD [0..1] ================================================ */ 72 typedef enum { /*!< MEC_GPIO_CTRL_PUD */ 73 MEC_GPIO_CTRL_PUD_NONE = 0, /*!< NONE : No internal pull up/down enabled */ 74 MEC_GPIO_CTRL_PUD_PULLUP = 1, /*!< PULLUP : Enable internal(weak) pull up resistor */ 75 MEC_GPIO_CTRL_PUD_PULLDN = 2, /*!< PULLDN : Enable internal(weak) pull down resistor */ 76 MEC_GPIO_CTRL_PUD_REPEATER = 3, /*!< REPEATER : Pin kept at previous voltage level when no active 77 driver present */ 78 } MEC_GPIO_CTRL_PUD_Enum; 79 80 /* =============================================== MEC_GPIO CTRL PGS [2..3] ================================================ */ 81 typedef enum { /*!< MEC_GPIO_CTRL_PGS */ 82 MEC_GPIO_CTRL_PGS_VTR = 0, /*!< VTR : Pin output buffer tri-stated when VTR_PWRGD is 0 */ 83 MEC_GPIO_CTRL_PGS_VCC = 1, /*!< VCC : Pin output buffer tri-stated when VCC_PWRGD is 0 */ 84 MEC_GPIO_CTRL_PGS_UNPWRD = 2, /*!< UNPWRD : Disable pin input and output */ 85 MEC_GPIO_CTRL_PGS_RSVD = 3, /*!< RSVD : Reserved value */ 86 } MEC_GPIO_CTRL_PGS_Enum; 87 88 /* =============================================== MEC_GPIO CTRL IDET [4..7] =============================================== */ 89 typedef enum { /*!< MEC_GPIO_CTRL_IDET */ 90 MEC_GPIO_CTRL_IDET_LVL_LO = 0, /*!< LVL_LO : Level Low interrupt detection */ 91 MEC_GPIO_CTRL_IDET_LVL_HI = 1, /*!< LVL_HI : Level High interrupt detection */ 92 MEC_GPIO_CTRL_IDET_DIS = 4, /*!< DIS : Interrupt detection is disabled */ 93 MEC_GPIO_CTRL_IDET_REDGE = 13, /*!< REDGE : Rising edge interrupt detection */ 94 MEC_GPIO_CTRL_IDET_FEDGE = 14, /*!< FEDGE : Falling edge interrupt detection */ 95 MEC_GPIO_CTRL_IDET_BEDGE = 15, /*!< BEDGE : Both edges interrupt detection */ 96 } MEC_GPIO_CTRL_IDET_Enum; 97 98 /* =============================================== MEC_GPIO CTRL OBT [8..8] ================================================ */ 99 typedef enum { /*!< MEC_GPIO_CTRL_OBT */ 100 MEC_GPIO_CTRL_OBT_PUSH_PULL = 0, /*!< PUSH_PULL : Output buffer is push-pull */ 101 MEC_GPIO_CTRL_OBT_OPEN_DRAIN = 1, /*!< OPEN_DRAIN : Output buffer is open-drain */ 102 } MEC_GPIO_CTRL_OBT_Enum; 103 104 /* =============================================== MEC_GPIO CTRL DIR [9..9] ================================================ */ 105 typedef enum { /*!< MEC_GPIO_CTRL_DIR */ 106 MEC_GPIO_CTRL_DIR_INPUT = 0, /*!< INPUT : GPIO is in input mode */ 107 MEC_GPIO_CTRL_DIR_OUTPUT = 1, /*!< OUTPUT : GPIO is in output mode */ 108 } MEC_GPIO_CTRL_DIR_Enum; 109 110 /* ============================================= MEC_GPIO CTRL PAREN [10..10] ============================================== */ 111 typedef enum { /*!< MEC_GPIO_CTRL_PAREN */ 112 MEC_GPIO_CTRL_PAREN_DISABLE = 0, /*!< DISABLE : Disable parallel(grouped) output bit. Output state 113 is Control register bit[16] */ 114 MEC_GPIO_CTRL_PAREN_ENABLE = 1, /*!< ENABLE : Enable parallel(grouped) output bit. Control register 115 bit[16] disabled */ 116 } MEC_GPIO_CTRL_PAREN_Enum; 117 118 /* ============================================= MEC_GPIO CTRL ALTPOL [11..11] ============================================= */ 119 typedef enum { /*!< MEC_GPIO_CTRL_ALTPOL */ 120 MEC_GPIO_CTRL_ALTPOL_NORM = 0, /*!< NORM : Pin alternate function polarity is normal */ 121 MEC_GPIO_CTRL_ALTPOL_INVERT = 1, /*!< INVERT : Pin alternate function polarity is inverted */ 122 } MEC_GPIO_CTRL_ALTPOL_Enum; 123 124 /* ============================================== MEC_GPIO CTRL MUX [12..14] =============================================== */ 125 typedef enum { /*!< MEC_GPIO_CTRL_MUX */ 126 MEC_GPIO_CTRL_MUX_GPIO = 0, /*!< GPIO : GPIO function */ 127 MEC_GPIO_CTRL_MUX_FUNC1 = 1, /*!< FUNC1 : Pin function 1 */ 128 MEC_GPIO_CTRL_MUX_FUNC2 = 2, /*!< FUNC2 : Pin function 2 */ 129 MEC_GPIO_CTRL_MUX_FUNC3 = 3, /*!< FUNC3 : Pin function 3 */ 130 MEC_GPIO_CTRL_MUX_FUNC4 = 4, /*!< FUNC4 : Pin function 4 */ 131 MEC_GPIO_CTRL_MUX_FUNC5 = 5, /*!< FUNC5 : Pin function 5 */ 132 MEC_GPIO_CTRL_MUX_FUNC6 = 6, /*!< FUNC6 : Pin function 6 */ 133 MEC_GPIO_CTRL_MUX_FUNC7 = 7, /*!< FUNC7 : Pin function 7 */ 134 } MEC_GPIO_CTRL_MUX_Enum; 135 136 /* ============================================== MEC_GPIO CTRL INPD [15..15] ============================================== */ 137 typedef enum { /*!< MEC_GPIO_CTRL_INPD */ 138 MEC_GPIO_CTRL_INPD_PAD_EN = 0, /*!< PAD_EN : Input pad is Not disabled */ 139 MEC_GPIO_CTRL_INPD_PAD_DIS = 1, /*!< PAD_DIS : Input pad is disabled */ 140 } MEC_GPIO_CTRL_INPD_Enum; 141 142 /* ============================================= MEC_GPIO CTRL ALTVAL [16..16] ============================================= */ 143 typedef enum { /*!< MEC_GPIO_CTRL_ALTVAL */ 144 MEC_GPIO_CTRL_ALTVAL_LO = 0, /*!< LO : Drive GPIO pin output low */ 145 MEC_GPIO_CTRL_ALTVAL_HI = 1, /*!< HI : Drive GPIO pin output high */ 146 } MEC_GPIO_CTRL_ALTVAL_Enum; 147 148 /* ============================================= MEC_GPIO CTRL PADIN [24..24] ============================================== */ 149 typedef enum { /*!< MEC_GPIO_CTRL_PADIN */ 150 MEC_GPIO_CTRL_PADIN_LO = 0, /*!< LO : GPIO input pad value is low */ 151 MEC_GPIO_CTRL_PADIN_HI = 1, /*!< HI : GPIO input pad value is high */ 152 } MEC_GPIO_CTRL_PADIN_Enum; 153 154 /* ========================================================= PARIN ========================================================= */ 155 /* ======================================================== PAROUT ========================================================= */ 156 /* ========================================================= LOCK ========================================================== */ 157 /* ===================================================== MEC_GPIO LOCK ===================================================== */ 158 typedef enum { /*!< MEC_GPIO_LOCK */ 159 MEC_GPIO_LOCK5_IDX = 0, /*!< LOCK5_IDX : Array index for GPIO LOCK5 */ 160 MEC_GPIO_LOCK4_IDX = 1, /*!< LOCK4_IDX : Array index for GPIO LOCK4 */ 161 MEC_GPIO_LOCK3_IDX = 2, /*!< LOCK3_IDX : Array index for GPIO LOCK3 */ 162 MEC_GPIO_LOCK2_IDX = 3, /*!< LOCK2_IDX : Array index for GPIO LOCK2 */ 163 MEC_GPIO_LOCK1_IDX = 4, /*!< LOCK1_IDX : Array index for GPIO LOCK1 */ 164 MEC_GPIO_LOCK0_IDX = 5, /*!< LOCK0_IDX : Array index for GPIO LOCK0 */ 165 } MEC_GPIO_Enum; 166 167 /* ========================================================= CTL2 ========================================================== */ 168 /* =============================================== MEC_GPIO CTL2 SLR [0..0] ================================================ */ 169 typedef enum { /*!< MEC_GPIO_CTL2_SLR */ 170 MEC_GPIO_CTL2_SLR_SLOW = 0, /*!< SLOW : Slow(half-frequency) slew rate */ 171 MEC_GPIO_CTL2_SLR_FAST = 1, /*!< FAST : Fast slew rate */ 172 } MEC_GPIO_CTL2_SLR_Enum; 173 174 /* ============================================== MEC_GPIO CTL2 DRVSTR [4..5] ============================================== */ 175 typedef enum { /*!< MEC_GPIO_CTL2_DRVSTR */ 176 MEC_GPIO_CTL2_DRVSTR_2MA = 0, /*!< 2MA : Driver strength is 2 mA */ 177 MEC_GPIO_CTL2_DRVSTR_4MA = 1, /*!< 4MA : Driver strength is 4 mA */ 178 MEC_GPIO_CTL2_DRVSTR_8MA = 2, /*!< 8MA : Driver strength is 8 mA */ 179 MEC_GPIO_CTL2_DRVSTR_12MA = 3, /*!< 12MA : Driver strength is 12 mA */ 180 } MEC_GPIO_CTL2_DRVSTR_Enum; 181 182 /** @} */ /* End of group EnumValue_peripherals */ 183 184 #endif /* _MEC5_GPIO_8F_6PORT_V1_5_H */ 185
