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Searched defs:CTL (Results 1 – 25 of 70) sorted by relevance

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/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_profile.h43 __IOM uint32_t CTL; /*!< 0x00000000 Profile counter configuration */ member
53 __IOM uint32_t CTL; /*!< 0x00000000 Profile control */ member
Dcyip_dmac_v2.h43 __IOM uint32_t CTL; /*!< 0x00000000 Channel control */ member
74 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_mxpdm.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
67 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_smartio.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control register */ member
Dcyip_smartio_v2.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control register */ member
Dcyip_fault.h43 __IOM uint32_t CTL; /*!< 0x00000000 Fault control */ member
Dcyip_smif.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
68 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_evtgen.h53 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_pdm.h42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_pwm.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
69 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_dmac.h43 __IOM uint32_t CTL; /*!< 0x00000000 Channel control */ member
74 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_axi_dmac.h43 __IOM uint32_t CTL; /*!< 0x00000000 Channel control */ member
77 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_pd.h42 __IOM uint32_t CTL; /*!< 0x00000000 Power Domain Control */ member
Dcyip_smif_v4.h47 __IOM uint32_t CTL; /*!< 0x00000000 Control bits for remap region */ member
60 …__IOM uint32_t CTL; /*!< 0x00000000 Global control registers for the bri… member
97 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
129 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_smartio_v3.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control register */ member
Dcyip_smartio_v5.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control register */ member
Dcyip_evtgen.h53 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_sg.h43 __IOM uint32_t CTL; /*!< 0x00000000 Source control */ member
Dcyip_dac.h42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_icache.h42 __IOM uint32_t CTL; /*!< 0x00000000 Cache control */ member
Dcyip_pdm.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
67 __IOM uint32_t CTL; /*!< 0x00000000 Control */ member
Dcyip_smartio.h43 __IOM uint32_t CTL; /*!< 0x00000000 Control register */ member
Dcyip_ms_ctl_1_2.h44 …__IOM uint32_t CTL; /*!< 0x00000000 Master 'x' protection context contro… member
Dcyip_ppc.h58 __IOM uint32_t CTL; /*!< 0x00000000 PPC Control Registers */ member
Dcyip_mxcordic_1_0.h42 __IOM uint32_t CTL; /*!< 0x00000000 N/A */ member

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