1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016, NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _FSL_RESET_H_ 10 #define _FSL_RESET_H_ 11 12 #include <assert.h> 13 #include <stdbool.h> 14 #include <stdint.h> 15 #include <string.h> 16 #include "fsl_device_registers.h" 17 18 /*! 19 * @addtogroup reset 20 * @{ 21 */ 22 23 /******************************************************************************* 24 * Definitions 25 ******************************************************************************/ 26 27 /*! @name Driver version */ 28 /*@{*/ 29 /*! @brief reset driver version 2.0.2. */ 30 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) 31 /*@}*/ 32 33 /*! 34 * @brief Enumeration for peripheral reset control bits 35 * 36 * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers 37 */ 38 typedef enum _SYSCON_RSTn 39 { 40 kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ 41 kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ 42 kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ 43 kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ 44 kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ 45 kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ 46 kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ 47 kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ 48 kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ 49 kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ 50 kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ 51 kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ 52 kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ 53 kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ 54 kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ 55 kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ 56 kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ 57 kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ 58 kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ 59 kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ 60 kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ 61 kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ 62 63 kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ 64 kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ 65 kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ 66 kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ 67 kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ 68 kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ 69 kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ 70 kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ 71 kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ 72 kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ 73 kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ 74 kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ 75 kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ 76 kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ 77 kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ 78 kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ 79 kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ 80 kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ 81 kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ 82 kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ 83 84 kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ 85 kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ 86 kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ 87 kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ 88 kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ 89 kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ 90 kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ 91 kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ 92 kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ 93 kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ 94 kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ 95 kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ 96 kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ 97 kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ 98 kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ 99 kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ 100 kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ 101 kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ 102 kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ 103 kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ 104 kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ 105 kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ 106 kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ 107 kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ 108 kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ 109 kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ 110 kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ 111 kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ 112 kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ 113 } SYSCON_RSTn_t; 114 115 /** Array initializers with peripheral reset bits **/ 116 #define ADC_RSTS \ 117 { \ 118 kADC0_RST_SHIFT_RSTn \ 119 } /* Reset bits for ADC peripheral */ 120 #define AES_RSTS \ 121 { \ 122 kAES_RST_SHIFT_RSTn \ 123 } /* Reset bits for AES peripheral */ 124 #define CRC_RSTS \ 125 { \ 126 kCRC_RST_SHIFT_RSTn \ 127 } /* Reset bits for CRC peripheral */ 128 #define CTIMER_RSTS \ 129 { \ 130 kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ 131 kCTIMER4_RST_SHIFT_RSTn \ 132 } /* Reset bits for CTIMER peripheral */ 133 #define DMA_RSTS_N \ 134 { \ 135 kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ 136 } /* Reset bits for DMA peripheral */ 137 138 #define FLEXCOMM_RSTS \ 139 { \ 140 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ 141 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \ 142 } /* Reset bits for FLEXCOMM peripheral */ 143 #define GINT_RSTS \ 144 { \ 145 kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ 146 } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ 147 #define GPIO_RSTS_N \ 148 { \ 149 kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ 150 kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \ 151 } /* Reset bits for GPIO peripheral */ 152 #define INPUTMUX_RSTS \ 153 { \ 154 kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \ 155 } /* Reset bits for INPUTMUX peripheral */ 156 #define IOCON_RSTS \ 157 { \ 158 kIOCON_RST_SHIFT_RSTn \ 159 } /* Reset bits for IOCON peripheral */ 160 #define FLASH_RSTS \ 161 { \ 162 kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ 163 } /* Reset bits for Flash peripheral */ 164 #define MRT_RSTS \ 165 { \ 166 kMRT_RST_SHIFT_RSTn \ 167 } /* Reset bits for MRT peripheral */ 168 #define OTP_RSTS \ 169 { \ 170 kOTP_RST_SHIFT_RSTn \ 171 } /* Reset bits for OTP peripheral */ 172 #define PINT_RSTS \ 173 { \ 174 kPINT_RST_SHIFT_RSTn \ 175 } /* Reset bits for PINT peripheral */ 176 #define RNG_RSTS \ 177 { \ 178 kRNG_RST_SHIFT_RSTn \ 179 } /* Reset bits for RNG peripheral */ 180 #define SDIO_RST \ 181 { \ 182 kSDIO_RST_SHIFT_RSTn \ 183 } /* Reset bits for SDIO peripheral */ 184 #define SCT_RSTS \ 185 { \ 186 kSCT0_RST_SHIFT_RSTn \ 187 } /* Reset bits for SCT peripheral */ 188 #define SPIFI_RSTS \ 189 { \ 190 kSPIFI_RST_SHIFT_RSTn \ 191 } /* Reset bits for SPIFI peripheral */ 192 #define USB0D_RST \ 193 { \ 194 kUSB0D_RST_SHIFT_RSTn \ 195 } /* Reset bits for USB0D peripheral */ 196 #define USB0HMR_RST \ 197 { \ 198 kUSB0HMR_RST_SHIFT_RSTn \ 199 } /* Reset bits for USB0HMR peripheral */ 200 #define USB0HSL_RST \ 201 { \ 202 kUSB0HSL_RST_SHIFT_RSTn \ 203 } /* Reset bits for USB0HSL peripheral */ 204 #define USB1H_RST \ 205 { \ 206 kUSB1H_RST_SHIFT_RSTn \ 207 } /* Reset bits for USB1H peripheral */ 208 #define USB1D_RST \ 209 { \ 210 kUSB1D_RST_SHIFT_RSTn \ 211 } /* Reset bits for USB1D peripheral */ 212 #define USB1RAM_RST \ 213 { \ 214 kUSB1RAM_RST_SHIFT_RSTn \ 215 } /* Reset bits for USB1RAM peripheral */ 216 #define UTICK_RSTS \ 217 { \ 218 kUTICK_RST_SHIFT_RSTn \ 219 } /* Reset bits for UTICK peripheral */ 220 #define WWDT_RSTS \ 221 { \ 222 kWWDT_RST_SHIFT_RSTn \ 223 } /* Reset bits for WWDT peripheral */ 224 #define CAPT_RSTS_N \ 225 { \ 226 kCAP0_RST_SHIFT_RSTn \ 227 } /* Reset bits for CAPT peripheral */ 228 #define PLU_RSTS_N \ 229 { \ 230 kPLULUT_RST_SHIFT_RSTn \ 231 } /* Reset bits for PLU peripheral */ 232 #define OSTIMER_RSTS \ 233 { \ 234 kOSTIMER0_RST_SHIFT_RSTn \ 235 } /* Reset bits for OSTIMER peripheral */ 236 typedef SYSCON_RSTn_t reset_ip_name_t; 237 238 /******************************************************************************* 239 * API 240 ******************************************************************************/ 241 #if defined(__cplusplus) 242 extern "C" { 243 #endif 244 245 /*! 246 * @brief Assert reset to peripheral. 247 * 248 * Asserts reset signal to specified peripheral module. 249 * 250 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register 251 * and reset bit position in the reset register. 252 */ 253 void RESET_SetPeripheralReset(reset_ip_name_t peripheral); 254 255 /*! 256 * @brief Clear reset to peripheral. 257 * 258 * Clears reset signal to specified peripheral module, allows it to operate. 259 * 260 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register 261 * and reset bit position in the reset register. 262 */ 263 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); 264 265 /*! 266 * @brief Reset peripheral module. 267 * 268 * Reset peripheral module. 269 * 270 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register 271 * and reset bit position in the reset register. 272 */ 273 void RESET_PeripheralReset(reset_ip_name_t peripheral); 274 275 #if defined(__cplusplus) 276 } 277 #endif 278 279 /*! @} */ 280 281 #endif /* _FSL_RESET_H_ */ 282
