1 /***************************************************************************//** 2 * \file cyip_ctdac.h 3 * 4 * \brief 5 * CTDAC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CTDAC_H_ 28 #define _CYIP_CTDAC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CTDAC 34 *******************************************************************************/ 35 36 #define CTDAC_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Continuous Time DAC (CTDAC) 40 */ 41 typedef struct { 42 __IOM uint32_t CTDAC_CTRL; /*!< 0x00000000 Global CTDAC control */ 43 __IM uint32_t RESERVED[7]; 44 __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ 45 __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ 46 __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ 47 __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ 48 __IM uint32_t RESERVED1[32]; 49 __IOM uint32_t CTDAC_SW; /*!< 0x000000B0 CTDAC switch control */ 50 __IOM uint32_t CTDAC_SW_CLEAR; /*!< 0x000000B4 CTDAC switch control clear */ 51 __IM uint32_t RESERVED2[18]; 52 __IOM uint32_t CTDAC_VAL; /*!< 0x00000100 DAC Value */ 53 __IOM uint32_t CTDAC_VAL_NXT; /*!< 0x00000104 Next DAC value (double buffering) */ 54 } CTDAC_V1_Type; /*!< Size = 264 (0x108) */ 55 56 57 /* CTDAC.CTDAC_CTRL */ 58 #define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos 0UL 59 #define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk 0x3FUL 60 #define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Pos 8UL 61 #define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk 0x100UL 62 #define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Pos 9UL 63 #define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk 0x200UL 64 #define CTDAC_CTDAC_CTRL_OUT_EN_Pos 22UL 65 #define CTDAC_CTDAC_CTRL_OUT_EN_Msk 0x400000UL 66 #define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Pos 23UL 67 #define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk 0x800000UL 68 #define CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos 24UL 69 #define CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk 0x3000000UL 70 #define CTDAC_CTDAC_CTRL_DISABLED_MODE_Pos 27UL 71 #define CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk 0x8000000UL 72 #define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Pos 28UL 73 #define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk 0x10000000UL 74 #define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Pos 29UL 75 #define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk 0x20000000UL 76 #define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Pos 30UL 77 #define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL 78 #define CTDAC_CTDAC_CTRL_ENABLED_Pos 31UL 79 #define CTDAC_CTDAC_CTRL_ENABLED_Msk 0x80000000UL 80 /* CTDAC.INTR */ 81 #define CTDAC_INTR_VDAC_EMPTY_Pos 0UL 82 #define CTDAC_INTR_VDAC_EMPTY_Msk 0x1UL 83 /* CTDAC.INTR_SET */ 84 #define CTDAC_INTR_SET_VDAC_EMPTY_SET_Pos 0UL 85 #define CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk 0x1UL 86 /* CTDAC.INTR_MASK */ 87 #define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos 0UL 88 #define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk 0x1UL 89 /* CTDAC.INTR_MASKED */ 90 #define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos 0UL 91 #define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk 0x1UL 92 /* CTDAC.CTDAC_SW */ 93 #define CTDAC_CTDAC_SW_CTDD_CVD_Pos 0UL 94 #define CTDAC_CTDAC_SW_CTDD_CVD_Msk 0x1UL 95 #define CTDAC_CTDAC_SW_CTDO_CO6_Pos 8UL 96 #define CTDAC_CTDAC_SW_CTDO_CO6_Msk 0x100UL 97 /* CTDAC.CTDAC_SW_CLEAR */ 98 #define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Pos 0UL 99 #define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk 0x1UL 100 #define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Pos 8UL 101 #define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk 0x100UL 102 /* CTDAC.CTDAC_VAL */ 103 #define CTDAC_CTDAC_VAL_VALUE_Pos 0UL 104 #define CTDAC_CTDAC_VAL_VALUE_Msk 0xFFFUL 105 /* CTDAC.CTDAC_VAL_NXT */ 106 #define CTDAC_CTDAC_VAL_NXT_VALUE_Pos 0UL 107 #define CTDAC_CTDAC_VAL_NXT_VALUE_Msk 0xFFFUL 108 109 110 #endif /* _CYIP_CTDAC_H_ */ 111 112 113 /* [] END OF FILE */ 114
