1 /******************************************************************************* 2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * PolarFire SoC MSS USB Driver Stack 7 * USB Core Interface Layer (USB-CIFL) 8 * USB-CIF driver 9 * 10 * 11 * Register bit offset and mask definitions for PolarFire SoC MSS USB. 12 * 13 */ 14 15 #ifndef __MSS_USB_CORE_REGS_H_ 16 #define __MSS_USB_CORE_REGS_H_ 17 18 #include <stdint.h> 19 #include <stddef.h> 20 21 /****************************************************************************** 22 * Power register 23 */ 24 #define POWER_REG_ENABLE_SUSPENDM_MASK 0x01u 25 #define POWER_REG_SUSPEND_MODE_MASK 0x02u 26 #define POWER_REG_RESUME_SIGNAL_MASK 0x04u 27 #define POWER_REG_BUS_RESET_SIGNAL_MASK 0x08u 28 #define POWER_REG_HS_MODE_MASK 0x10u 29 #define POWER_REG_ENABLE_HS_MASK 0x20u 30 #define POWER_REG_SOFT_CONN_MASK 0x40u 31 #define POWER_REG_ISO_UPDATE_MASK 0x80u 32 33 /****************************************************************************** 34 * Soft_reset_mask 35 */ 36 #define SOFT_RESET_REG_MASK 0x03u 37 38 /****************************************************************************** 39 * DevCTL register bit masks 40 */ 41 #define DEV_CTRL_SESSION_MASK 0x01u 42 #define DEV_CTRL_HOST_REQ_MASK 0x02u 43 #define DEV_CTRL_HOST_MODE_MASK 0x04u 44 #define DEV_CTRL_VBUS_MASK 0x18u 45 #define DEV_CTRL_LS_DEV_MASK 0x20u 46 #define DEV_CTRL_FS_DEV_MASK 0x40u 47 #define DEV_CTRL_B_DEVICE_MASK 0x80u 48 49 #define VBUS_BELOW_SESSION_END 0x00u 50 #define VBUS_ABOVE_SESSION_END 0x08u 51 #define VBUS_ABOVE_AVALID 0x10u 52 #define VBUS_ABOVE_VBUS_VALID 0x18u 53 54 /****************************************************************************** 55 * CSR0L bit masks (peripheral mode) 56 */ 57 #define CSR0L_DEV_RX_PKT_RDY_MASK 0x0001u 58 #define CSR0L_DEV_TX_PKT_RDY_MASK 0x0002u 59 #define CSR0L_DEV_STALL_SENT_MASK 0x0004u 60 #define CSR0L_DEV_DATA_END_MASK 0x0008u 61 #define CSR0L_DEV_SETUP_END_MASK 0x0010u 62 #define CSR0L_DEV_SEND_STALL_MASK 0x0020u 63 #define CSR0L_DEV_SERVICED_RX_PKT_RDY_MASK 0x0040u 64 #define CSR0L_DEV_SERVICED_SETUP_END_MASK 0x0080u 65 66 /****************************************************************************** 67 * CSR0H bit masks (peripheral mode) 68 */ 69 #define CSR0H_DEV_FLUSH_FIFO_MASK 0x0100u 70 71 /****************************************************************************** 72 * COUNT0 register masks 73 */ 74 #define COUNT0_REG_MASK 0x7fu 75 76 /****************************************************************************** 77 * Endpoint TxMAXP register bit masks 78 */ 79 #define TX_MAX_P_REG_NUM_USB_PKT_SHIFT 11u 80 81 /****************************************************************************** 82 * Endpoint TxCSRL register bit masks 83 */ 84 #define TxCSRL_REG_EPN_TX_PKT_RDY_MASK 0x0001u 85 #define TxCSRL_REG_EPN_TX_FIFO_NE_MASK 0x0002u 86 #define TxCSRL_REG_EPN_UNDERRUN_MASK 0x0004u 87 #define TxCSRL_REG_EPN_FLUSH_FIFO_MASK 0x0008u 88 #define TxCSRL_REG_EPN_SEND_STALL_MASK 0x0010u 89 #define TxCSRL_REG_EPN_STALL_SENT_MASK 0x0020u 90 #define TxCSRL_REG_EPN_CLR_DATA_TOG_MASK 0x0040u 91 #define TxCSRL_REG_EPN_ISO_INCOMP_TX_MASK 0x0080u 92 93 /****************************************************************************** 94 * Endpoint TxCSRH register bit masks 95 */ 96 /*D0,D1 are un-used*/ 97 #define TxCSRH_REG_EPN_DMA_MODE_MASK 0x0400u 98 #define TxCSRH_REG_EPN_FRC_DAT_TOG_MASK 0x0800u 99 #define TxCSRH_REG_EPN_ENABLE_DMA_MASK 0x1000u 100 #define TxCSRH_REG_EPN_TXRX_MODE_MASK 0x2000u 101 #define TxCSRH_REG_EPN_ENABLE_ISO_MASK 0x4000u 102 #define TxCSRH_REG_EPN_ENABLE_AUTOSET_MASK 0x8000u 103 104 /****************************************************************************** 105 * Endpoint TxMAXP register bit masks 106 */ 107 #define RX_MAX_P_REG_NUM_USB_PKT_SHIFT 11u 108 109 /****************************************************************************** 110 * Endpoint RxCSRL register bit masks 111 */ 112 #define RxCSRL_REG_EPN_RX_PKT_RDY_MASK 0x0001u 113 #define RxCSRL_REG_EPN_RX_FIFO_FULL_MASK 0x0002u 114 #define RxCSRL_REG_EPN_OVERRUN_MASK 0x0004u 115 #define RxCSRL_REG_EPN_DATA_ERR_MASK 0x0008u 116 #define RxCSRL_REG_EPN_FLUSH_FIFO_MASK 0x0010u 117 #define RxCSRL_REG_EPN_SEND_STALL_MASK 0x0020u 118 #define RxCSRL_REG_EPN_STALL_SENT_MASK 0x0040u 119 #define RxCSRL_REG_EPN_CLR_DAT_TOG_MASK 0x0080u 120 121 /****************************************************************************** 122 * Endpoint RxCSRH register bit masks 123 */ 124 #define RxCSRL_REG_EPN_RX_ISO_INCOMP 0x0100u 125 /*D1,D2 are unused*/ 126 #define RxCSRL_REG_EPN_DMA_MODE_MASK 0x0800u 127 128 #define RxCSRL_REG_EPN_ISO_PID_ERR_MASK 0x1000u 129 #define RxCSRL_REG_EPN_BI_DIS_NYET_MASK 0x1000u 130 131 #define RxCSRL_REG_EPN_ENABLE_DMA_MASK 0x2000u 132 #define RxCSRL_REG_EPN_ENABLE_ISO_MASK 0x4000u 133 #define RxCSRL_REG_EPN_ENABLE_AUTOCLR_MASK 0x8000u 134 135 /****************************************************************************** 136 * Endpoint DMA_CNTL register bit masks 137 */ 138 #define DMA_CNTL_REG_START_XFR_MASK 0x00000001u 139 #define DMA_CNTL_REG_DMA_DIR_MASK 0x00000002u 140 #define DMA_CNTL_REG_DMA_MODE_MASK 0x00000004u 141 #define DMA_CNTL_REG_ENABLE_DMA_IRQ_MASK 0x00000008u 142 #define DMA_CNTL_REG_DMA_EP_NUM_MASK 0x000000F0u 143 #define DMA_CNTL_REG_DMA_BUS_ERR_MASK 0x00000100u 144 #define DMA_CNTL_REG_DMA_BURST_MODE_MASK 0x00000600u 145 146 #define DMA_CNTL_REG_DMA_BURST_MODE_SHIFT 9u 147 #define DMA_CNTL_REG_DMA_EP_NUM_SHIFT 4u 148 #define DMA_CNTL_REG_DMA_DIR_SHIFT 1u 149 #define DMA_CNTL_REG_DMA_MODE_SHIFT 2u 150 151 /****************************************************************************** 152 * TX Endpoint Fifo size masks 153 */ 154 #define TXFIFOSZ_REG_DPB_SHIFT 4u 155 156 /****************************************************************************** 157 * RX Endpoint Fifo size masks 158 */ 159 #define RXFIFOSZ_REG_DPB_SHIFT 4u 160 161 /****************************************************************************** 162 * TX_IRQ_ENABLE register masks 163 */ 164 #define TX_IRQ_ENABLE_REG_CEP_MASK 0x0001u 165 166 167 /****************************************************************************** 168 * Host Side register definitions 169 */ 170 171 /****************************************************************************** 172 * CSR0L bit masks 173 */ 174 #define CSR0L_HOST_RX_PKT_RDY_MASK 0x0001u 175 #define CSR0L_HOST_TX_PKT_RDY_MASK 0x0002u 176 #define CSR0L_HOST_STALL_RCVD_MASK 0x0004u 177 #define CSR0L_HOST_SETUP_PKT_MASK 0x0008u 178 #define CSR0L_HOST_RETRY_ERR_MASK 0x0010u 179 #define CSR0L_HOST_IN_PKT_REQ_MASK 0x0020u 180 #define CSR0L_HOST_STATUS_PKT_MASK 0x0040u 181 #define CSR0L_HOST_NAK_TIMEOUT_MASK 0x0080u 182 183 /****************************************************************************** 184 * CSR0H bit masks 185 */ 186 #define CSR0H_HOST_FLUSH_FIFO_MASK 0x0100u/*Self Clearing*/ 187 #define CSR0H_HOST_DATA_TOG_MASK 0x0200u 188 #define CSR0H_HOST_DATA_TOG_WE_MASK 0x0400u/*Self Clearing*/ 189 #define CSR0H_HOST_DISABLE_PING_MASK 0x0800u 190 191 /****************************************************************************** 192 * Type0 register bit masks 193 */ 194 #define TYPE0_HOST_MP_TARGET_SPEED_MASK 0xC0u 195 196 #define TYPE0_HOST_MP_TARGET_SPEED_HIGH 0x40u 197 #define TYPE0_HOST_MP_TARGET_SPEED_FULL 0x80u 198 #define TYPE0_HOST_MP_TARGET_SPEED_LOW 0xC0u 199 #define TYPE0_HOST_MP_TARGET_SPEED_SELF 0x00u 200 201 #define TYPE0_HOST_MP_TARGET_SPEED_SHIFT 6u 202 203 /****************************************************************************** 204 * NAKLIMIT0 register bit masks 205 */ 206 #define NAKLIMIT0_REG_MASK 0x00u 207 208 /****************************************************************************** 209 * Endpoint TxCSRL register bit masks 210 */ 211 #define TxCSRL_HOST_EPN_TX_PKT_RDY_MASK 0x0001u 212 #define TxCSRL_HOST_EPN_TX_FIFO_NE_MASK 0x0002u 213 #define TxCSRL_HOST_EPN_RESPONSE_ERR_MASK 0x0004u 214 #define TxCSRL_HOST_EPN_FLUSH_FIFO_MASK 0x0008u 215 #define TxCSRL_HOST_EPN_SETUP_PKT_MASK 0x0010u 216 #define TxCSRL_HOST_EPN_STALL_RCVD_MASK 0x0020u 217 #define TxCSRL_HOST_EPN_CLR_DATA_TOG_MASK 0x0040u 218 #define TxCSRL_HOST_EPN_NAK_TIMEOUT_MASK 0x0080u 219 220 /****************************************************************************** 221 * Endpoint TxCSRH register bit masks 222 */ 223 #define TxCSRH_HOST_EPN_DATA_TOG_MASK 0x0100u 224 #define TxCSRH_HOST_EPN_DATA_TOG_WE_MASK 0x0200u 225 #define TxCSRH_HOST_EPN_DMA_MODE_MASK 0x0400u 226 #define TxCSRH_HOST_EPN_FRC_DATA_TOG_MASK 0x0800u 227 #define TxCSRH_HOST_EPN_ENABLE_DMA_MASK 0x1000u 228 #define TxCSRH_HOST_EPN_TXRX_MODE_MASK 0x2000u 229 /*D6 is unused*/ 230 #define TxCSRH_HOST_EPN_ENABLE_AUTOSET_MASK 0x8000u 231 232 /****************************************************************************** 233 * Endpoint RxCSRL register bit masks 234 */ 235 #define RXCSRL_HOST_EPN_RX_PKT_RDY_MASK 0x0001u 236 #define RXCSRL_HOST_EPN_RX_FIFO_FULL_MASK 0x0002u 237 #define RXCSRL_HOST_EPN_RESPONSE_ERR_MASK 0x0004u 238 #define RXCSRL_HOST_EPN_NAK_TIMEOUT_ERR_MASK 0x0008u 239 #define RXCSRL_HOST_EPN_FLUSH_FIFO_MASK 0x0010u 240 #define RXCSRL_HOST_EPN_IN_PKT_REQ_MASK 0x0020u 241 #define RXCSRL_HOST_EPN_STALL_RCVD_MASK 0x0040u 242 #define RXCSRL_HOST_EPN_CLR_DATA_TOG_MASK 0x0080u 243 244 /****************************************************************************** 245 * Endpoint RxCSRH register bit masks 246 */ 247 #define RXCSRH_HOST_EPN_RX_ISO_INCOMP 0x0100u 248 #define RXCSRH_HOST_EPN_DATA_TOG_MASK 0x0200u 249 #define RXCSRH_HOST_EPN_DATA_TOG_WE_MASK 0x0400u 250 #define RXCSRH_HOST_EPN_DMA_MODE_MASK 0x0800u 251 #define RXCSRH_HOST_EPN_PID_ERR_MASK 0x1000u 252 #define RXCSRH_HOST_EPN_ENABLE_DMA_MASK 0x2000u 253 #define RXCSRH_HOST_EPN_ENABLE_AUTOREQ_MASK 0x4000u 254 #define RXCSRH_HOST_EPN_ENABLE_AUTOCLR_MASK 0x8000u 255 256 /****************************************************************************** 257 * TXType register bit masks 258 */ 259 #define TXTYPE_HOST_TARGET_EP_NUM_MASK 0x0Fu 260 #define TXTYPE_HOST_TARGET_EP_PROTOCOL_MASK 0x30u 261 #define TXTYPE_HOST_TARGET_EP_SPEED_MASK 0xC0u 262 263 #define TXTYPE_HOST_TARGET_EP_NUM_SHIFT 0u 264 #define TXTYPE_HOST_TARGET_EP_PROTOCOL_SHIFT 4u 265 #define TXTYPE_HOST_TARGET_EP_SPEED_SHIFT 6u 266 267 /****************************************************************************** 268 TXINTERVAL register bit masks 269 */ 270 #define TXINTERVAL_HOST_REG_MASK 0x00 271 272 /****************************************************************************** 273 TXType register bit masks 274 */ 275 #define RXTYPE_HOST_TARGET_EP_NUM_MASK 0x0Fu 276 #define RXTYPE_HOST_TARGET_EP_PROTOCOL_MASK 0x30u 277 #define RXTYPE_HOST_TARGET_EP_SPEED_MASK 0xC0u 278 279 #define RXTYPE_HOST_TARGET_EP_NUM_SHIFT 0u 280 #define RXTYPE_HOST_TARGET_EP_PROTOCOL_SHIFT 4u 281 #define RXTYPE_HOST_TARGET_EP_SPEED_SHIFT 6u 282 283 /****************************************************************************** 284 RXINTERVAL register bit masks 285 */ 286 #define RXINTERVAL_HOST_REG_MASK 0x00u 287 288 /****************************************************************************** 289 TX/RXFUNCTIONADDR register bit masks 290 */ 291 #define TARGET_DEVICE_ADDR_MASK 0x7Fu 292 293 /****************************************************************************** 294 TX/RXHUBADDR register bit masks 295 */ 296 #define TARGET_DEVICE_HUB_ADDR_MASK 0x7Fu 297 #define TARGET_DEVICE_HUB_MT_MASK 0x10u 298 299 #define TARGET_DEVICE_HUB_MT_SHIFT 7u 300 301 /****************************************************************************** 302 TX/RXHUBPORT register bit masks 303 */ 304 #define TARGET_DEVICE_HUB_PORT_MASK 0x7Fu 305 306 /****************************************************************************** 307 TESTMODE register bit masks 308 */ 309 #define TESTMODE_SE0NAK_MASK 0x01u 310 #define TESTMODE_TESTJ_MASK 0x02u 311 #define TESTMODE_TESTK_MASK 0x04u 312 #define TESTMODE_TESTPACKET_MASK 0x08u 313 #define TESTMODE_FORCEHS_MASK 0x10u 314 #define TESTMODE_FORCEFS_MASK 0x20u 315 #define TESTMODE_FIFOACCESS_MASK 0x40u/*Self Clearing*/ 316 #define TESTMODE_FORCEHOST_MASK 0x80u 317 318 319 typedef struct 320 { 321 volatile uint16_t TX_MAX_P; 322 volatile uint16_t TX_CSR; 323 volatile uint16_t RX_MAX_P; 324 volatile uint16_t RX_CSR; 325 volatile uint16_t RX_COUNT; 326 volatile uint8_t TX_TYPE; 327 volatile uint8_t TX_INTERVAL; 328 volatile uint8_t RX_TYPE; 329 volatile uint8_t RX_INTERVAL; 330 volatile uint8_t RESERVED; 331 volatile uint8_t FIFO_SIZE; 332 } USB_endpoint_regs_t; 333 334 typedef struct 335 { 336 volatile uint8_t TX_FUNC_ADDR; 337 volatile uint8_t UNUSED0; 338 volatile uint8_t TX_HUB_ADDR; 339 volatile uint8_t TX_HUB_PORT; 340 volatile uint8_t RX_FUNC_ADDR; 341 volatile uint8_t UNUSED1; 342 volatile uint8_t RX_HUB_ADDR; 343 volatile uint8_t RX_HUB_PORT; 344 } USB_tar_t; 345 346 typedef union 347 { 348 struct 349 { 350 volatile uint32_t VALUE; 351 } WORD; 352 353 struct 354 { 355 volatile uint8_t VALUE; 356 volatile uint8_t RESERVED1; 357 volatile uint8_t RESERVED2; 358 volatile uint8_t RESERVED3; 359 } BYTE; 360 361 struct 362 { 363 volatile uint16_t VALUE; 364 volatile uint16_t RESERVED; 365 } HALFWORD; 366 } USB_fifo_t; 367 368 typedef union 369 { 370 struct 371 { 372 volatile uint16_t TX_MAX_P; 373 volatile uint16_t CSR0; 374 volatile uint16_t RX_MAX_P; 375 volatile uint16_t RX_CSR; 376 volatile uint16_t COUNT0; 377 volatile uint8_t RESERVED0; 378 volatile uint8_t RESERVED1; 379 volatile uint8_t RESERVED2; 380 volatile uint8_t RESERVED3; 381 volatile uint8_t RESERVED4; 382 volatile uint8_t CONFIG_DATA; 383 } DEVICE_EP0; 384 385 struct 386 { 387 volatile uint16_t TX_MAX_P; 388 volatile uint16_t TX_CSR; 389 volatile uint16_t RX_MAX_P; 390 volatile uint16_t RX_CSR; 391 volatile uint16_t RX_COUNT; 392 volatile uint8_t RESERVED0; 393 volatile uint8_t RESERVED1; 394 volatile uint8_t RESERVED2; 395 volatile uint8_t RESERVED3; 396 volatile uint8_t RESERVED4; 397 volatile uint8_t FIFO_SIZE; 398 } DEVICE_EPN; 399 400 struct 401 { 402 volatile uint16_t TX_MAX_P; 403 volatile uint16_t CSR0; 404 volatile uint16_t RX_MAX_P; 405 volatile uint16_t RX_CSR; 406 volatile uint16_t COUNT0; 407 volatile uint8_t TYPE0; 408 volatile uint8_t NAK_LIMIT0; 409 volatile uint8_t RX_TYPE; 410 volatile uint8_t RX_INTERVAL; 411 volatile uint8_t RESERVED0; 412 volatile uint8_t CONFIG_DATA; 413 } HOST_EP0; 414 415 struct 416 { 417 volatile uint16_t TX_MAX_P; 418 volatile uint16_t TX_CSR; 419 volatile uint16_t RX_MAX_P; 420 volatile uint16_t RX_CSR; 421 volatile uint16_t RX_COUNT; 422 volatile uint8_t TX_TYPE; 423 volatile uint8_t TX_INTERVAL; 424 volatile uint8_t RX_TYPE; 425 volatile uint8_t RX_INTERVAL; 426 volatile uint8_t RESERVED0; 427 volatile uint8_t FIFO_SIZE; 428 } HOST_EPN; 429 430 } USB_indexed_csr_t; 431 432 typedef struct { 433 volatile uint32_t IRQ; 434 volatile uint32_t CNTL; 435 volatile uint32_t ADDR; 436 volatile uint32_t COUNT; 437 } USB_DMA_channel; 438 439 typedef struct 440 { 441 /* 442 * Common USB Registers 443 */ 444 volatile uint8_t FADDR; 445 volatile uint8_t POWER; 446 volatile uint16_t TX_IRQ; 447 volatile uint16_t RX_IRQ; 448 volatile uint16_t TX_IRQ_ENABLE; 449 volatile uint16_t RX_IRQ_ENABLE; 450 volatile uint8_t USB_IRQ; 451 volatile uint8_t USB_ENABLE; 452 volatile uint16_t FRAME; 453 volatile uint8_t INDEX; 454 volatile uint8_t TEST_MODE; 455 456 /* 457 * Indexed CSR 458 */ 459 USB_indexed_csr_t INDEXED_CSR; 460 461 /* 462 * Endpoint FIFOs 463 */ 464 USB_fifo_t FIFO[16]; 465 466 /* 467 * OTG, dynamic FIFO and version 468 */ 469 volatile uint8_t DEV_CTRL; 470 volatile uint8_t MISC; 471 volatile uint8_t TX_FIFO_SIZE; 472 volatile uint8_t RX_FIFO_SIZE; 473 volatile uint16_t TX_FIFO_ADDR; 474 volatile uint16_t RX_FIFO_ADDR; 475 volatile uint32_t VBUS_CSR; 476 volatile uint16_t HW_VERSION; 477 volatile uint16_t RESERVED; 478 479 /* 480 * ULPI and configuration registers 481 */ 482 volatile uint8_t ULPI_VBUS_CTRL; 483 volatile uint8_t ULPI_CARKIT_CTRL; 484 volatile uint8_t ULPI_IRQ_MASK; 485 volatile uint8_t ULPI_IRQ_SRC; 486 volatile uint8_t ULPI_DATA_REG; 487 volatile uint8_t ULPI_ADDR_REG; 488 volatile uint8_t ULPI_CTRL_REG; 489 volatile uint8_t ULPI_RAW_DATA; 490 volatile uint8_t EP_INFO; 491 volatile uint8_t RAM_INFO; 492 volatile uint8_t LINK_INFO; 493 volatile uint8_t VP_LEN; 494 volatile uint8_t HS_EOF1; 495 volatile uint8_t FS_EOF1; 496 volatile uint8_t LS_EOF1; 497 volatile uint8_t SOFT_RST; 498 499 /* 500 * Target Address registers 501 */ 502 USB_tar_t TAR[16]; 503 504 /* 505 * Endpoints CSR 506 */ 507 USB_endpoint_regs_t ENDPOINT[16]; 508 509 /* 510 * DMA 511 */ 512 USB_DMA_channel DMA_CHANNEL[8]; 513 514 volatile uint32_t RESERVED_EXT[32]; 515 volatile uint32_t RQ_PKT_CNT[16]; 516 volatile uint16_t RX_DPBUF_DIS; 517 volatile uint16_t TX_DPBUF_DIS; 518 volatile uint16_t C_T_UCH; 519 volatile uint16_t C_T_HHSRTN; 520 volatile uint16_t C_T_HSBT; 521 522 } MSS_USB_TypeDef; 523 524 #define USB ((MSS_USB_TypeDef *) USB_BASE) 525 #define USB_BASE 0x20201000u 526 527 #endif /*__MSS_USB_CORE_REGS_H_*/ 528
