Searched defs:CSR (Results 1 – 3 of 3) sorted by relevance
| /trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32l5xx/Device/Include/ |
| D | stm32l552xx.h | 277 …__IO uint32_t CSR; /*!< ADC common status register, Address offset: AD… member
374 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ member
379 …__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several … member
488 …__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x00… member
689 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ member
833 …__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset:… member
840 …__IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPA… member
922 …__IO uint32_t CSR; /*!< RCC clock control & status register, … member
1278 …__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 … member
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| D | stm32l562xx.h | 280 …__IO uint32_t CSR; /*!< ADC common status register, Address offset: AD… member
408 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ member
413 …__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several … member
522 …__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x00… member
723 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ member
867 …__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset:… member
874 …__IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPA… member
996 …__IO uint32_t CSR; /*!< RCC clock control & status register, … member
1352 …__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 … member
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| /trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32u5xx/Device/Include/ |
| D | stm32u585xx.h | 372 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ member
447 …__IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: … member
786 __IO uint32_t CSR; /*!< Comparator control/status register , Address offset: 0x00 */ member
800 …__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset:… member
1069 …__IO uint32_t CSR; /*!< V33 Clock Control & Status Register … member
1535 …__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 … member
1601 …__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 … member
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