1 /*
2 * Copyright 2017-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_csi.h"
10 #if CSI_DRIVER_FRAG_MODE
11 #include "fsl_cache.h"
12 #endif
13
14 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
15 #include "fsl_memory.h"
16 #endif
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21 /* Macro remap. */
22 #if (!defined(CSI_CR3_TWO_8BIT_SENSOR_MASK) && defined(CSI_CR3_SENSOR_16BITS_MASK))
23 #define CSI_CR3_TWO_8BIT_SENSOR_MASK CSI_CR3_SENSOR_16BITS_MASK
24 #endif
25
26 /* Component ID definition, used by tools. */
27 #ifndef FSL_COMPONENT_ID
28 #define FSL_COMPONENT_ID "platform.drivers.csi"
29 #endif
30
31 /* Two frame buffer loaded to CSI register at most. */
32 #define CSI_MAX_ACTIVE_FRAME_NUM 2U
33
34 /* CSI driver only support RGB565 and YUV422 in fragment mode, 2 bytes per pixel. */
35 #define CSI_FRAG_INPUT_BYTES_PER_PIXEL 2U
36
37 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
38 #define CSI_ADDR_CPU_2_IP(addr) (MEMORY_ConvertMemoryMapAddress((uint32_t)(addr), kMEMORY_Local2DMA))
39 #define CSI_ADDR_IP_2_CPU(addr) (MEMORY_ConvertMemoryMapAddress((uint32_t)(addr), kMEMORY_DMA2Local))
40 #else
41 #define CSI_ADDR_CPU_2_IP(addr) (addr)
42 #define CSI_ADDR_IP_2_CPU(addr) (addr)
43 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
44
45 /*!
46 * @brief Used for conversion between `void*` and `uint32_t`.
47 */
48 typedef union pvoid_to_u32
49 {
50 void *pvoid;
51 uint32_t u32;
52 } pvoid_to_u32_t;
53
54 /*******************************************************************************
55 * Prototypes
56 ******************************************************************************/
57
58 /*!
59 * @brief Get the instance from the base address
60 *
61 * @param base CSI peripheral base address
62 *
63 * @return The CSI module instance
64 */
65 static uint32_t CSI_GetInstance(CSI_Type *base);
66
67 #if !CSI_DRIVER_FRAG_MODE
68 /*!
69 * @brief Get the delta value of two index in queue.
70 *
71 * @param startIdx Start index.
72 * @param endIdx End index.
73 *
74 * @return The delta between startIdx and endIdx in queue.
75 */
76 static uint8_t CSI_TransferGetQueueDelta(uint8_t startIdx, uint8_t endIdx);
77
78 /*!
79 * @brief Increase a index value in queue.
80 *
81 * This function increases the index value in the queue, if the index is out of
82 * the queue range, it is reset to 0.
83 *
84 * @param idx The index value to increase.
85 *
86 * @return The index value after increase.
87 */
88 static uint8_t CSI_TransferIncreaseQueueIdx(uint8_t idx);
89
90 /*!
91 * @brief Get the empty frame buffer count in queue.
92 *
93 * @param base CSI peripheral base address
94 * @param handle Pointer to CSI driver handle.
95 *
96 * @return Number of the empty frame buffer count in queue.
97 */
98 static uint32_t CSI_TransferGetEmptyBufferCount(csi_handle_t *handle);
99
100 /*!
101 * @brief Get the empty frame buffer.
102 *
103 * This function should only be called when frame buffer count larger than 0.
104 *
105 * @param handle Pointer to CSI driver handle.
106 *
107 * @return Empty buffer
108 */
109 static uint32_t CSI_TransferGetEmptyBuffer(csi_handle_t *handle);
110
111 /*!
112 * @brief Put the empty frame buffer.
113 *
114 * @param handle Pointer to CSI driver handle.
115 * @param buffer The empty buffer to put.
116 */
117 static void CSI_TransferPutEmptyBuffer(csi_handle_t *handle, uint32_t buffer);
118
119 /*!
120 * @brief Get the RX frame buffer address.
121 *
122 * @param base CSI peripheral base address.
123 * @param index Buffer index.
124 * @return Frame buffer address.
125 */
126 static uint32_t CSI_GetRxBufferAddr(CSI_Type *base, uint8_t index);
127
128 /* Typedef for interrupt handler. */
129 typedef void (*csi_isr_t)(CSI_Type *base, csi_handle_t *handle);
130
131 #else
132
133 /* Typedef for interrupt handler to work in fragment mode. */
134 typedef void (*csi_isr_t)(CSI_Type *base, csi_frag_handle_t *handle);
135 #endif /* CSI_DRIVER_FRAG_MODE */
136
137 /*******************************************************************************
138 * Variables
139 ******************************************************************************/
140 /*! @brief Pointers to CSI bases for each instance. */
141 static CSI_Type *const s_csiBases[] = CSI_BASE_PTRS;
142
143 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
144 /*! @brief Pointers to CSI clocks for each CSI submodule. */
145 static const clock_ip_name_t s_csiClocks[] = CSI_CLOCKS;
146 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
147
148 /* Array for the CSI driver handle. */
149 #if !CSI_DRIVER_FRAG_MODE
150 static csi_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
151 #else
152 static csi_frag_handle_t *s_csiHandle[ARRAY_SIZE(s_csiBases)];
153 #endif
154
155 /* Array of CSI IRQ number. */
156 static const IRQn_Type s_csiIRQ[] = CSI_IRQS;
157
158 /* CSI ISR for transactional APIs. */
159 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
160 static csi_isr_t s_csiIsr = (csi_isr_t)DefaultISR;
161 #else
162 static csi_isr_t s_csiIsr;
163 #endif
164
165 /*******************************************************************************
166 * Code
167 ******************************************************************************/
CSI_GetInstance(CSI_Type * base)168 static uint32_t CSI_GetInstance(CSI_Type *base)
169 {
170 uint32_t instance;
171
172 /* Find the instance index from base address mappings. */
173 for (instance = 0; instance < ARRAY_SIZE(s_csiBases); instance++)
174 {
175 if (s_csiBases[instance] == base)
176 {
177 break;
178 }
179 }
180
181 assert(instance < ARRAY_SIZE(s_csiBases));
182
183 return instance;
184 }
185
186 #if !CSI_DRIVER_FRAG_MODE
CSI_TransferGetQueueDelta(uint8_t startIdx,uint8_t endIdx)187 static uint8_t CSI_TransferGetQueueDelta(uint8_t startIdx, uint8_t endIdx)
188 {
189 uint8_t ret;
190
191 if (endIdx >= startIdx)
192 {
193 ret = endIdx - startIdx;
194 }
195 else
196 {
197 ret = (uint8_t)(endIdx + CSI_DRIVER_ACTUAL_QUEUE_SIZE - startIdx);
198 }
199
200 return ret;
201 }
202
CSI_TransferIncreaseQueueIdx(uint8_t idx)203 static uint8_t CSI_TransferIncreaseQueueIdx(uint8_t idx)
204 {
205 uint8_t ret;
206
207 /*
208 * Here not use the method:
209 * ret = (idx+1) % CSI_DRIVER_ACTUAL_QUEUE_SIZE;
210 *
211 * Because the mod function might be slow.
212 */
213
214 ret = idx + 1U;
215
216 if (ret >= CSI_DRIVER_ACTUAL_QUEUE_SIZE)
217 {
218 ret = 0U;
219 }
220
221 return ret;
222 }
223
CSI_TransferGetEmptyBufferCount(csi_handle_t * handle)224 static uint32_t CSI_TransferGetEmptyBufferCount(csi_handle_t *handle)
225 {
226 return handle->emptyBufferCnt;
227 }
228
CSI_TransferGetEmptyBuffer(csi_handle_t * handle)229 static uint32_t CSI_TransferGetEmptyBuffer(csi_handle_t *handle)
230 {
231 pvoid_to_u32_t buf;
232
233 buf.pvoid = handle->emptyBuffer;
234 handle->emptyBufferCnt--;
235 handle->emptyBuffer = *(void **)(buf.pvoid);
236
237 return buf.u32;
238 }
239
CSI_TransferPutEmptyBuffer(csi_handle_t * handle,uint32_t buffer)240 static void CSI_TransferPutEmptyBuffer(csi_handle_t *handle, uint32_t buffer)
241 {
242 pvoid_to_u32_t buf;
243 buf.u32 = buffer;
244
245 *(void **)(buf.pvoid) = handle->emptyBuffer;
246 handle->emptyBuffer = buf.pvoid;
247 handle->emptyBufferCnt++;
248 }
249
CSI_GetRxBufferAddr(CSI_Type * base,uint8_t index)250 static uint32_t CSI_GetRxBufferAddr(CSI_Type *base, uint8_t index)
251 {
252 uint32_t addr;
253
254 if (index != 0U)
255 {
256 addr = CSI_REG_DMASA_FB2(base);
257 }
258 else
259 {
260 addr = CSI_REG_DMASA_FB1(base);
261 }
262
263 return CSI_ADDR_IP_2_CPU(addr);
264 }
265
266 #endif /* CSI_DRIVER_FRAG_MODE */
267
268 /*!
269 * brief Initialize the CSI.
270 *
271 * This function enables the CSI peripheral clock, and resets the CSI registers.
272 *
273 * param base CSI peripheral base address.
274 * param config Pointer to the configuration structure.
275 *
276 * retval kStatus_Success Initialize successfully.
277 * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
278 */
CSI_Init(CSI_Type * base,const csi_config_t * config)279 status_t CSI_Init(CSI_Type *base, const csi_config_t *config)
280 {
281 assert(NULL != config);
282 uint32_t reg;
283 uint32_t imgWidth_Bytes;
284 uint8_t busCyclePerPixel;
285
286 imgWidth_Bytes = (uint32_t)config->width * (uint32_t)config->bytesPerPixel;
287
288 /* The image width and frame buffer pitch should be multiple of 8-bytes. */
289 if ((0U != (imgWidth_Bytes & 0x07U)) || (0U != ((uint32_t)config->linePitch_Bytes & 0x07U)))
290 {
291 return kStatus_InvalidArgument;
292 }
293
294 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
295 uint32_t instance = CSI_GetInstance(base);
296 CLOCK_EnableClock(s_csiClocks[instance]);
297 #endif
298
299 CSI_Reset(base);
300
301 /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
302 reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CR1_FCC_MASK;
303
304 if (config->useExtVsync)
305 {
306 reg |= CSI_CR1_EXT_VSYNC_MASK;
307 }
308
309 CSI_REG_CR1(base) = reg;
310
311 /*
312 * Generally, CSIIMAG_PARA[IMAGE_WIDTH] indicates how many data bus cycles per line.
313 * One special case is when receiving 24-bit pixels through 8-bit data bus.
314 * In this case, the CSIIMAG_PARA[IMAGE_WIDTH] should be set to the pixel number per line.
315 */
316 if ((kCSI_DataBus8Bit == config->dataBus) && (2U == config->bytesPerPixel))
317 {
318 busCyclePerPixel = 2U;
319 }
320 else
321 {
322 busCyclePerPixel = 1U;
323 }
324
325 if (4U == config->bytesPerPixel)
326 {
327 CSI_REG_CR18(base) |= CSI_CR18_PARALLEL24_EN_MASK;
328 }
329
330 if (kCSI_DataBus16Bit == config->dataBus)
331 {
332 CSI_REG_CR3(base) |= CSI_CR3_TWO_8BIT_SENSOR_MASK;
333 }
334
335 /* Image parameter. */
336 CSI_REG_IMAG_PARA(base) =
337 (((uint32_t)config->width * (uint32_t)busCyclePerPixel) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT) |
338 ((uint32_t)(config->height) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT);
339
340 /* The CSI frame buffer bus is 8-byte width. */
341 CSI_REG_FBUF_PARA(base) = (uint32_t)((config->linePitch_Bytes - imgWidth_Bytes) / 8U)
342 << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT;
343
344 /* Enable auto ECC. */
345 CSI_REG_CR3(base) |= CSI_CR3_ECC_AUTO_EN_MASK;
346
347 /*
348 * For better performance.
349 * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
350 * choose the best burst size based on bytes per line.
351 */
352 if (0U == (imgWidth_Bytes % (8U * 16U)))
353 {
354 CSI_REG_CR2(base) = CSI_CR2_DMA_BURST_TYPE_RFF(3U);
355 CSI_REG_CR3(base) = (CSI_REG_CR3(base) & ~CSI_CR3_RxFF_LEVEL_MASK) | ((2U << CSI_CR3_RxFF_LEVEL_SHIFT));
356 }
357 else if (0U == (imgWidth_Bytes % (8U * 8U)))
358 {
359 CSI_REG_CR2(base) = CSI_CR2_DMA_BURST_TYPE_RFF(2U);
360 CSI_REG_CR3(base) = (CSI_REG_CR3(base) & ~CSI_CR3_RxFF_LEVEL_MASK) | ((1U << CSI_CR3_RxFF_LEVEL_SHIFT));
361 }
362 else
363 {
364 CSI_REG_CR2(base) = CSI_CR2_DMA_BURST_TYPE_RFF(1U);
365 CSI_REG_CR3(base) = (CSI_REG_CR3(base) & ~CSI_CR3_RxFF_LEVEL_MASK) | ((0U << CSI_CR3_RxFF_LEVEL_SHIFT));
366 }
367
368 CSI_ReflashFifoDma(base, kCSI_RxFifo);
369
370 return kStatus_Success;
371 }
372
373 /*!
374 * brief De-initialize the CSI.
375 *
376 * This function disables the CSI peripheral clock.
377 *
378 * param base CSI peripheral base address.
379 */
CSI_Deinit(CSI_Type * base)380 void CSI_Deinit(CSI_Type *base)
381 {
382 /* Disable transfer first. */
383 CSI_Stop(base);
384 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
385 uint32_t instance = CSI_GetInstance(base);
386 CLOCK_DisableClock(s_csiClocks[instance]);
387 #endif
388 }
389
390 /*!
391 * brief Reset the CSI.
392 *
393 * This function resets the CSI peripheral registers to default status.
394 *
395 * param base CSI peripheral base address.
396 */
CSI_Reset(CSI_Type * base)397 void CSI_Reset(CSI_Type *base)
398 {
399 uint32_t csisr;
400
401 /* Disable transfer first. */
402 CSI_Stop(base);
403
404 /* Disable DMA request. */
405 CSI_REG_CR3(base) = 0U;
406
407 /* Reset the fame count. */
408 CSI_REG_CR3(base) |= CSI_CR3_FRMCNT_RST_MASK;
409 while (0U != (CSI_REG_CR3(base) & CSI_CR3_FRMCNT_RST_MASK))
410 {
411 }
412
413 /* Clear the RX FIFO. */
414 CSI_ClearFifo(base, kCSI_AllFifo);
415
416 /* Reflash DMA. */
417 CSI_ReflashFifoDma(base, kCSI_AllFifo);
418
419 /* Clear the status. */
420 csisr = CSI_REG_SR(base);
421 CSI_REG_SR(base) = csisr;
422
423 /* Set the control registers to default value. */
424 CSI_REG_CR1(base) = CSI_CR1_HSYNC_POL_MASK | CSI_CR1_EXT_VSYNC_MASK;
425 CSI_REG_CR2(base) = 0U;
426 CSI_REG_CR3(base) = 0U;
427 #if defined(CSI_CR18_CSI_LCDIF_BUFFER_LINES)
428 CSI_REG_CR18(base) = CSI_CR18_AHB_HPROT(0x0DU) | CSI_CR18_CSI_LCDIF_BUFFER_LINES(0x02U);
429 #else
430 CSI_REG_CR18(base) = CSI_CR18_AHB_HPROT(0x0DU);
431 #endif
432 CSI_REG_FBUF_PARA(base) = 0U;
433 CSI_REG_IMAG_PARA(base) = 0U;
434 }
435
436 /*!
437 * brief Get the default configuration for to initialize the CSI.
438 *
439 * The default configuration value is:
440 *
441 * code
442 config->width = 320U;
443 config->height = 240U;
444 config->polarityFlags = kCSI_HsyncActiveHigh | kCSI_DataLatchOnRisingEdge;
445 config->bytesPerPixel = 2U;
446 config->linePitch_Bytes = 320U * 2U;
447 config->workMode = kCSI_GatedClockMode;
448 config->dataBus = kCSI_DataBus8Bit;
449 config->useExtVsync = true;
450 endcode
451 *
452 * param config Pointer to the CSI configuration.
453 */
CSI_GetDefaultConfig(csi_config_t * config)454 void CSI_GetDefaultConfig(csi_config_t *config)
455 {
456 assert(NULL != config);
457
458 /* Initializes the configure structure to zero. */
459 (void)memset(config, 0, sizeof(*config));
460
461 config->width = 320U;
462 config->height = 240U;
463 config->polarityFlags = (uint32_t)kCSI_HsyncActiveHigh | (uint32_t)kCSI_DataLatchOnRisingEdge;
464 config->bytesPerPixel = 2U;
465 config->linePitch_Bytes = 320U * 2U;
466 config->workMode = kCSI_GatedClockMode;
467 config->dataBus = kCSI_DataBus8Bit;
468 config->useExtVsync = true;
469 }
470
471 /*!
472 * brief Set the RX frame buffer address.
473 *
474 * param base CSI peripheral base address.
475 * param index Buffer index.
476 * param addr Frame buffer address to set.
477 */
CSI_SetRxBufferAddr(CSI_Type * base,uint8_t index,uint32_t addr)478 void CSI_SetRxBufferAddr(CSI_Type *base, uint8_t index, uint32_t addr)
479 {
480 addr = CSI_ADDR_CPU_2_IP(addr);
481
482 if (0U != index)
483 {
484 CSI_REG_DMASA_FB2(base) = addr;
485 }
486 else
487 {
488 CSI_REG_DMASA_FB1(base) = addr;
489 }
490 }
491
492 /*!
493 * brief Clear the CSI FIFO.
494 *
495 * This function clears the CSI FIFO.
496 *
497 * param base CSI peripheral base address.
498 * param fifo The FIFO to clear.
499 */
CSI_ClearFifo(CSI_Type * base,csi_fifo_t fifo)500 void CSI_ClearFifo(CSI_Type *base, csi_fifo_t fifo)
501 {
502 uint32_t cr1;
503 uint32_t mask = 0U;
504
505 /* The FIFO could only be cleared when CSICR1[FCC] = 0, so first clear the FCC. */
506 cr1 = CSI_REG_CR1(base);
507 CSI_REG_CR1(base) = (cr1 & ~CSI_CR1_FCC_MASK);
508
509 if (0U != ((uint32_t)fifo & (uint32_t)kCSI_RxFifo))
510 {
511 mask |= CSI_CR1_CLR_RXFIFO_MASK;
512 }
513
514 if (0U != ((uint32_t)fifo & (uint32_t)kCSI_StatFifo))
515 {
516 mask |= CSI_CR1_CLR_STATFIFO_MASK;
517 }
518
519 CSI_REG_CR1(base) = (cr1 & ~CSI_CR1_FCC_MASK) | mask;
520
521 /* Wait clear completed. */
522 while (0U != (CSI_REG_CR1(base) & mask))
523 {
524 }
525
526 /* Recover the FCC. */
527 CSI_REG_CR1(base) = cr1;
528 }
529
530 /*!
531 * brief Reflash the CSI FIFO DMA.
532 *
533 * This function reflashes the CSI FIFO DMA.
534 *
535 * For RXFIFO, there are two frame buffers. When the CSI module started, it saves
536 * the frames to frame buffer 0 then frame buffer 1, the two buffers will be
537 * written by turns. After reflash DMA using this function, the CSI is reset to
538 * save frame to buffer 0.
539 *
540 * param base CSI peripheral base address.
541 * param fifo The FIFO DMA to reflash.
542 */
CSI_ReflashFifoDma(CSI_Type * base,csi_fifo_t fifo)543 void CSI_ReflashFifoDma(CSI_Type *base, csi_fifo_t fifo)
544 {
545 uint32_t cr3 = 0U;
546
547 if (0U != ((uint32_t)fifo & (uint32_t)kCSI_RxFifo))
548 {
549 cr3 |= CSI_CR3_DMA_REFLASH_RFF_MASK;
550 }
551
552 if (0U != ((uint32_t)fifo & (uint32_t)kCSI_StatFifo))
553 {
554 cr3 |= CSI_CR3_DMA_REFLASH_SFF_MASK;
555 }
556
557 CSI_REG_CR3(base) |= cr3;
558
559 /* Wait clear completed. */
560 while (0U != (CSI_REG_CR3(base) & cr3))
561 {
562 }
563 }
564
565 /*!
566 * brief Enable or disable the CSI FIFO DMA request.
567 *
568 * param base CSI peripheral base address.
569 * param fifo The FIFO DMA reques to enable or disable.
570 * param enable True to enable, false to disable.
571 */
CSI_EnableFifoDmaRequest(CSI_Type * base,csi_fifo_t fifo,bool enable)572 void CSI_EnableFifoDmaRequest(CSI_Type *base, csi_fifo_t fifo, bool enable)
573 {
574 uint32_t cr3 = 0U;
575
576 if (0U != ((uint32_t)fifo & (uint32_t)kCSI_RxFifo))
577 {
578 cr3 |= CSI_CR3_DMA_REQ_EN_RFF_MASK;
579 }
580
581 if (0U != ((uint32_t)fifo & (uint32_t)kCSI_StatFifo))
582 {
583 cr3 |= CSI_CR3_DMA_REQ_EN_SFF_MASK;
584 }
585
586 if (enable)
587 {
588 CSI_REG_CR3(base) |= cr3;
589 }
590 else
591 {
592 CSI_REG_CR3(base) &= ~cr3;
593 }
594 }
595
596 /*!
597 * brief Enables CSI interrupt requests.
598 *
599 * param base CSI peripheral base address.
600 * param mask The interrupts to enable, pass in as OR'ed value of ref _csi_interrupt_enable.
601 */
CSI_EnableInterrupts(CSI_Type * base,uint32_t mask)602 void CSI_EnableInterrupts(CSI_Type *base, uint32_t mask)
603 {
604 CSI_REG_CR1(base) |= (mask & CSI_CR1_INT_EN_MASK);
605 CSI_REG_CR3(base) |= (mask & CSI_CR3_INT_EN_MASK);
606 CSI_REG_CR18(base) |= ((mask & CSI_CR18_INT_EN_MASK) >> 6U);
607 }
608
609 /*!
610 * brief Disable CSI interrupt requests.
611 *
612 * param base CSI peripheral base address.
613 * param mask The interrupts to disable, pass in as OR'ed value of ref _csi_interrupt_enable.
614 */
CSI_DisableInterrupts(CSI_Type * base,uint32_t mask)615 void CSI_DisableInterrupts(CSI_Type *base, uint32_t mask)
616 {
617 CSI_REG_CR1(base) &= ~(mask & CSI_CR1_INT_EN_MASK);
618 CSI_REG_CR3(base) &= ~(mask & CSI_CR3_INT_EN_MASK);
619 CSI_REG_CR18(base) &= ~((mask & CSI_CR18_INT_EN_MASK) >> 6U);
620 }
621
622 #if !CSI_DRIVER_FRAG_MODE
623 /*!
624 * brief Initializes the CSI handle.
625 *
626 * This function initializes CSI handle, it should be called before any other
627 * CSI transactional functions.
628 *
629 * param base CSI peripheral base address.
630 * param handle Pointer to the handle structure.
631 * param callback Callback function for CSI transfer.
632 * param userData Callback function parameter.
633 *
634 * retval kStatus_Success Handle created successfully.
635 */
CSI_TransferCreateHandle(CSI_Type * base,csi_handle_t * handle,csi_transfer_callback_t callback,void * userData)636 status_t CSI_TransferCreateHandle(CSI_Type *base,
637 csi_handle_t *handle,
638 csi_transfer_callback_t callback,
639 void *userData)
640 {
641 assert(NULL != handle);
642 uint32_t instance;
643
644 (void)memset(handle, 0, sizeof(*handle));
645
646 /* Set the callback and user data. */
647 handle->callback = callback;
648 handle->userData = userData;
649
650 /* Get instance from peripheral base address. */
651 instance = CSI_GetInstance(base);
652
653 /* Save the handle in global variables to support the double weak mechanism. */
654 s_csiHandle[instance] = handle;
655
656 s_csiIsr = CSI_TransferHandleIRQ;
657
658 /* Enable interrupt. */
659 (void)EnableIRQ(s_csiIRQ[instance]);
660
661 return kStatus_Success;
662 }
663
664 /*!
665 * brief Start the transfer using transactional functions.
666 *
667 * When the empty frame buffers have been submit to CSI driver using function
668 * ref CSI_TransferSubmitEmptyBuffer, user could call this function to start
669 * the transfer. The incoming frame will be saved to the empty frame buffer,
670 * and user could be optionally notified through callback function.
671 *
672 * param base CSI peripheral base address.
673 * param handle Pointer to the handle structure.
674 *
675 * retval kStatus_Success Started successfully.
676 * retval kStatus_CSI_NoEmptyBuffer Could not start because no empty frame buffer in queue.
677 */
CSI_TransferStart(CSI_Type * base,csi_handle_t * handle)678 status_t CSI_TransferStart(CSI_Type *base, csi_handle_t *handle)
679 {
680 assert(NULL != handle);
681
682 uint32_t emptyBufferCount;
683
684 emptyBufferCount = CSI_TransferGetEmptyBufferCount(handle);
685
686 if (emptyBufferCount < 2U)
687 {
688 return kStatus_CSI_NoEmptyBuffer;
689 }
690
691 /*
692 * Write to memory from first completed frame.
693 * DMA base addr switch at the edge of the first data of each frame, thus
694 * if one frame is broken, it could be reset at the next frame.
695 */
696 CSI_REG_CR18(base) = (CSI_REG_CR18(base) & ~CSI_CR18_MASK_OPTION_MASK) | CSI_CR18_MASK_OPTION(0) |
697 CSI_CR18_BASEADDR_SWITCH_SEL_MASK | CSI_CR18_BASEADDR_SWITCH_EN_MASK;
698
699 /* Load the frame buffer to CSI register, there are at least two empty buffers. */
700 CSI_REG_DMASA_FB1(base) = CSI_ADDR_CPU_2_IP(CSI_TransferGetEmptyBuffer(handle));
701 CSI_REG_DMASA_FB2(base) = CSI_ADDR_CPU_2_IP(CSI_TransferGetEmptyBuffer(handle));
702
703 handle->activeBufferNum = CSI_MAX_ACTIVE_FRAME_NUM;
704
705 /* After reflash DMA, the CSI saves frame to frame buffer 0. */
706 CSI_ReflashFifoDma(base, kCSI_RxFifo);
707
708 handle->transferStarted = true;
709
710 CSI_EnableInterrupts(
711 base, (uint32_t)kCSI_RxBuffer1DmaDoneInterruptEnable | (uint32_t)kCSI_RxBuffer0DmaDoneInterruptEnable);
712
713 CSI_Start(base);
714
715 return kStatus_Success;
716 }
717
718 /*!
719 * brief Stop the transfer using transactional functions.
720 *
721 * The driver does not clean the full frame buffers in queue. In other words, after
722 * calling this function, user still could get the full frame buffers in queue
723 * using function ref CSI_TransferGetFullBuffer.
724 *
725 * param base CSI peripheral base address.
726 * param handle Pointer to the handle structure.
727 *
728 * retval kStatus_Success Stoped successfully.
729 */
CSI_TransferStop(CSI_Type * base,csi_handle_t * handle)730 status_t CSI_TransferStop(CSI_Type *base, csi_handle_t *handle)
731 {
732 assert(NULL != handle);
733 uint8_t activeBufferNum;
734 uint8_t bufIdx;
735
736 CSI_Stop(base);
737 CSI_DisableInterrupts(
738 base, (uint32_t)kCSI_RxBuffer1DmaDoneInterruptEnable | (uint32_t)kCSI_RxBuffer0DmaDoneInterruptEnable);
739
740 activeBufferNum = handle->activeBufferNum;
741
742 handle->transferStarted = false;
743 handle->activeBufferNum = 0;
744
745 /*
746 * Put active buffers to empty queue.
747 *
748 * If there is only one active frame buffers, then FB0 and FB1 use the same address,
749 * put FB0 to empty buffer queue is OK.
750 */
751 for (bufIdx = 0; bufIdx < activeBufferNum; bufIdx++)
752 {
753 CSI_TransferPutEmptyBuffer(handle, CSI_GetRxBufferAddr(base, bufIdx));
754 }
755
756 return kStatus_Success;
757 }
758
759 /*!
760 * brief Submit empty frame buffer to queue.
761 *
762 * This function could be called before ref CSI_TransferStart or after ref
763 * CSI_TransferStart. If there is no room in queue to store the empty frame
764 * buffer, this function returns error.
765 *
766 * param base CSI peripheral base address.
767 * param handle Pointer to the handle structure.
768 * param frameBuffer Empty frame buffer to submit.
769 *
770 * retval kStatus_Success Started successfully.
771 * retval kStatus_CSI_QueueFull Could not submit because there is no room in queue.
772 */
CSI_TransferSubmitEmptyBuffer(CSI_Type * base,csi_handle_t * handle,uint32_t frameBuffer)773 status_t CSI_TransferSubmitEmptyBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t frameBuffer)
774 {
775 uint32_t csicr1;
776
777 /* Disable the interrupt to protect the index information in handle. */
778 csicr1 = CSI_REG_CR1(base);
779
780 CSI_REG_CR1(base) = (csicr1 & ~(CSI_CR1_FB2_DMA_DONE_INTEN_MASK | CSI_CR1_FB1_DMA_DONE_INTEN_MASK));
781
782 /* Save the empty frame buffer address to queue. */
783 CSI_TransferPutEmptyBuffer(handle, frameBuffer);
784
785 CSI_REG_CR1(base) = csicr1;
786
787 return kStatus_Success;
788 }
789
790 /*!
791 * brief Get one full frame buffer from queue.
792 *
793 * After the transfer started using function ref CSI_TransferStart, the incoming
794 * frames will be saved to the empty frame buffers in queue. This function gets
795 * the full-filled frame buffer from the queue. If there is no full frame buffer
796 * in queue, this function returns error.
797 *
798 * param base CSI peripheral base address.
799 * param handle Pointer to the handle structure.
800 * param frameBuffer Full frame buffer.
801 *
802 * retval kStatus_Success Started successfully.
803 * retval kStatus_CSI_NoFullBuffer There is no full frame buffer in queue.
804 */
CSI_TransferGetFullBuffer(CSI_Type * base,csi_handle_t * handle,uint32_t * frameBuffer)805 status_t CSI_TransferGetFullBuffer(CSI_Type *base, csi_handle_t *handle, uint32_t *frameBuffer)
806 {
807 uint32_t csicr1;
808 status_t status;
809 uint8_t queueReadIdx;
810 uint8_t queueWriteIdx;
811
812 queueReadIdx = handle->queueReadIdx;
813 queueWriteIdx = handle->queueWriteIdx;
814
815 /* No full frame buffer. */
816 if (queueReadIdx == queueWriteIdx)
817 {
818 status = kStatus_CSI_NoFullBuffer;
819 }
820 else
821 {
822 /* Disable the interrupt to protect the index information in handle. */
823 csicr1 = CSI_REG_CR1(base);
824
825 CSI_REG_CR1(base) = (csicr1 & ~(CSI_CR1_FB2_DMA_DONE_INTEN_MASK | CSI_CR1_FB1_DMA_DONE_INTEN_MASK));
826
827 *frameBuffer = handle->frameBufferQueue[handle->queueReadIdx];
828
829 handle->queueReadIdx = CSI_TransferIncreaseQueueIdx(handle->queueReadIdx);
830
831 CSI_REG_CR1(base) = csicr1;
832
833 status = kStatus_Success;
834 }
835
836 return status;
837 }
838
839 /*!
840 * brief CSI IRQ handle function.
841 *
842 * This function handles the CSI IRQ request to work with CSI driver transactional
843 * APIs.
844 *
845 * param base CSI peripheral base address.
846 * param handle CSI handle pointer.
847 */
CSI_TransferHandleIRQ(CSI_Type * base,csi_handle_t * handle)848 void CSI_TransferHandleIRQ(CSI_Type *base, csi_handle_t *handle)
849 {
850 uint8_t queueWriteIdx;
851 uint8_t queueReadIdx;
852 uint8_t dmaDoneBufferIdx;
853 uint32_t frameBuffer;
854 uint32_t csisr = CSI_REG_SR(base);
855
856 /* Clear the error flags. */
857 CSI_REG_SR(base) = csisr;
858
859 /*
860 * If both frame buffer 0 and frame buffer 1 flags assert, driver does not
861 * know which frame buffer ready just now, so skip them.
862 */
863 if ((csisr & (CSI_SR_DMA_TSF_DONE_FB2_MASK | CSI_SR_DMA_TSF_DONE_FB1_MASK)) ==
864 (CSI_SR_DMA_TSF_DONE_FB2_MASK | CSI_SR_DMA_TSF_DONE_FB1_MASK))
865 {
866 ; /* Skip the frames. */
867 }
868 else if (0U != (csisr & (CSI_SR_DMA_TSF_DONE_FB2_MASK | CSI_SR_DMA_TSF_DONE_FB1_MASK)))
869 {
870 if (0U != (csisr & CSI_SR_DMA_TSF_DONE_FB2_MASK))
871 {
872 dmaDoneBufferIdx = 1;
873 }
874 else
875 {
876 dmaDoneBufferIdx = 0;
877 }
878
879 if (handle->activeBufferNum == CSI_MAX_ACTIVE_FRAME_NUM)
880 {
881 queueWriteIdx = handle->queueWriteIdx;
882 queueReadIdx = handle->queueReadIdx;
883
884 if (CSI_TransferGetQueueDelta(queueReadIdx, queueWriteIdx) < CSI_DRIVER_QUEUE_SIZE)
885 {
886 /* Put the full frame buffer to full buffer queue. */
887 frameBuffer = CSI_GetRxBufferAddr(base, dmaDoneBufferIdx);
888 handle->frameBufferQueue[queueWriteIdx] = frameBuffer;
889
890 handle->queueWriteIdx = CSI_TransferIncreaseQueueIdx(queueWriteIdx);
891
892 handle->activeBufferNum--;
893
894 if (NULL != handle->callback)
895 {
896 handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
897 }
898 }
899 else
900 {
901 }
902 }
903
904 /*
905 * User may submit new frame buffer in callback, so recheck activeBufferNum here,
906 * if there is only one active buffer in CSI device, the two buffer registers
907 * are both set to the frame buffer address.
908 */
909 if (handle->activeBufferNum < CSI_MAX_ACTIVE_FRAME_NUM)
910 {
911 if (CSI_TransferGetEmptyBufferCount(handle) > 0U)
912 {
913 /* Get the empty frameBuffer, and submit to CSI device. */
914 CSI_SetRxBufferAddr(base, dmaDoneBufferIdx, CSI_TransferGetEmptyBuffer(handle));
915 handle->activeBufferNum++;
916 }
917 else
918 {
919 /* If there is only one active frame buffer, then the two CSI
920 * output buffer address are all set to this frame buffer.
921 */
922 frameBuffer = CSI_GetRxBufferAddr(base, dmaDoneBufferIdx ^ 1U);
923 CSI_SetRxBufferAddr(base, dmaDoneBufferIdx, frameBuffer);
924 }
925 }
926 }
927 else
928 {
929 }
930 }
931
932 #else /* CSI_DRIVER_FRAG_MODE */
933
934 #if defined(__CC_ARM)
CSI_ExtractYFromYUYV(void * datBase,const void * dmaBase,size_t count)935 __asm void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
936 {
937 /* clang-format off */
938 push {r4-r7, lr}
939 10
940 LDMIA R1!, {r3-r6}
941 bfi r7, r3, #0, #8 /* Y0 */
942 bfi ip, r5, #0, #8 /* Y4 */
943 lsr r3, r3, #16
944 lsr r5, r5, #16
945 bfi r7, r3, #8, #8 /* Y1 */
946 bfi ip, r5, #8, #8 /* Y5 */
947 bfi r7, r4, #16, #8 /* Y2 */
948 bfi ip, r6, #16, #8 /* Y6 */
949 lsr r4, r4, #16
950 lsr r6, r6, #16
951 bfi r7, r4, #24, #8 /* Y3 */
952 bfi ip, r6, #24, #8 /* Y7 */
953 STMIA r0!, {r7, ip}
954 subs r2, #8
955 bne %b10
956 pop {r4-r7, pc}
957 /* clang-format on */
958 }
959
CSI_ExtractYFromUYVY(void * datBase,const void * dmaBase,size_t count)960 __asm void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
961 {
962 /* clang-format off */
963 push {r4-r7, lr}
964 10
965 LDMIA R1!, {r3-r6}
966 lsr r3, r3, #8
967 lsr r5, r5, #8
968 bfi r7, r3, #0, #8 /* Y0 */
969 bfi ip, r5, #0, #8 /* Y4 */
970 lsr r3, r3, #16
971 lsr r5, r5, #16
972 bfi r7, r3, #8, #8 /* Y1 */
973 bfi ip, r5, #8, #8 /* Y5 */
974 lsr r4, r4, #8
975 lsr r6, r6, #8
976 bfi r7, r4, #16, #8 /* Y2 */
977 bfi ip, r6, #16, #8 /* Y6 */
978 lsr r4, r4, #16
979 lsr r6, r6, #16
980 bfi r7, r4, #24, #8 /* Y3 */
981 bfi ip, r6, #24, #8 /* Y7 */
982 STMIA r0!, {r7, ip}
983 subs r2, #8
984 bne %b10
985 pop {r4-r7, pc}
986 /* clang-format on */
987 }
988
989 #elif (defined(__GNUC__) || defined(__ICCARM__)) || defined(__ARMCC_VERSION)
990 #if defined(__ICCARM__)
991 #pragma diag_suppress = Pe940
992 #endif
993 __attribute__((naked)) void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count);
CSI_ExtractYFromYUYV(void * datBase,const void * dmaBase,size_t count)994 void CSI_ExtractYFromYUYV(void *datBase, const void *dmaBase, size_t count)
995 {
996 /* clang-format off */
997 __asm volatile(
998 " push {r1-r7, r12, lr} \n"
999 "loop0: \n"
1000 " ldmia r1!, {r3-r6} \n"
1001 " bfi r7, r3, #0, #8 \n" /* Y0 */
1002 " bfi r12, r5, #0, #8 \n" /* Y4 */
1003 " lsr r3, r3, #16 \n"
1004 " lsr r5, r5, #16 \n"
1005 " bfi r7, r3, #8, #8 \n" /* Y1 */
1006 " bfi r12, r5, #8, #8 \n" /* Y5 */
1007 " bfi r7, r4, #16, #8 \n" /* Y2 */
1008 " bfi r12, r6, #16, #8 \n" /* Y6 */
1009 " lsr r4, r4, #16 \n"
1010 " lsr r6, r6, #16 \n"
1011 " bfi r7, r4, #24, #8 \n" /* Y3 */
1012 " bfi r12, r6, #24, #8 \n" /* Y7 */
1013 " stmia r0!, {r7, r12} \n"
1014 " subs r2, #8 \n"
1015 " bne loop0 \n"
1016 " pop {r1-r7, r12, pc} \n");
1017 /* clang-format on */
1018 }
1019
1020 __attribute__((naked)) void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count);
CSI_ExtractYFromUYVY(void * datBase,const void * dmaBase,size_t count)1021 void CSI_ExtractYFromUYVY(void *datBase, const void *dmaBase, size_t count)
1022 {
1023 /* clang-format off */
1024 __asm volatile(
1025 " push {r1-r7, r12, lr} \n"
1026 "loop1: \n"
1027 " ldmia r1!, {r3-r6} \n"
1028 " lsr r3, r3, #8 \n"
1029 " lsr r5, r5, #8 \n"
1030 " bfi r7, r3, #0, #8 \n" /* Y0 */
1031 " bfi r12, r5, #0, #8 \n" /* Y4 */
1032 " lsr r3, r3, #16 \n"
1033 " lsr r5, r5, #16 \n"
1034 " bfi r7, r3, #8, #8 \n" /* Y1 */
1035 " bfi r12, r5, #8, #8 \n" /* Y5 */
1036 " lsr r4, r4, #8 \n"
1037 " lsr r6, r6, #8 \n"
1038 " bfi r7, r4, #16, #8 \n" /* Y2 */
1039 " bfi r12, r6, #16, #8 \n" /* Y6 */
1040 " lsr r4, r4, #16 \n"
1041 " lsr r6, r6, #16 \n"
1042 " bfi r7, r4, #24, #8 \n" /* Y3 */
1043 " bfi r12, r6, #24, #8 \n" /* Y7 */
1044 " stmia r0!, {r7, r12} \n"
1045 " subs r2, #8 \n"
1046 " bne loop1 \n"
1047 " pop {r1-r7, r12, pc} \n");
1048 /* clang-format on */
1049 }
1050 #if defined(__ICCARM__)
1051 #pragma diag_default = Pe940
1052 #endif
1053 #else
1054 #error Toolchain not supported.
1055 #endif
1056
CSI_MemCopy(void * pDest,const void * pSrc,size_t cnt)1057 static void CSI_MemCopy(void *pDest, const void *pSrc, size_t cnt)
1058 {
1059 (void)memcpy(pDest, pSrc, cnt);
1060 }
1061
1062 /*!
1063 * brief Initialize the CSI to work in fragment mode.
1064 *
1065 * This function enables the CSI peripheral clock, and resets the CSI registers.
1066 *
1067 * param base CSI peripheral base address.
1068 */
CSI_FragModeInit(CSI_Type * base)1069 void CSI_FragModeInit(CSI_Type *base)
1070 {
1071 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1072 uint32_t instance = CSI_GetInstance(base);
1073 CLOCK_EnableClock(s_csiClocks[instance]);
1074 #endif
1075
1076 CSI_Reset(base);
1077 }
1078
1079 /*!
1080 * brief De-initialize the CSI.
1081 *
1082 * This function disables the CSI peripheral clock.
1083 *
1084 * param base CSI peripheral base address.
1085 */
CSI_FragModeDeinit(CSI_Type * base)1086 void CSI_FragModeDeinit(CSI_Type *base)
1087 {
1088 CSI_Deinit(base);
1089 }
1090
1091 /*!
1092 * brief Create handle for CSI work in fragment mode.
1093 *
1094 * param base CSI peripheral base address.
1095 * param handle Pointer to the transactional handle.
1096 * param config Pointer to the configuration structure.
1097 * param callback Callback function for CSI transfer.
1098 * param userData Callback function parameter.
1099 *
1100 * retval kStatus_Success Initialize successfully.
1101 * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
1102 */
CSI_FragModeCreateHandle(CSI_Type * base,csi_frag_handle_t * handle,const csi_frag_config_t * config,csi_frag_transfer_callback_t callback,void * userData)1103 status_t CSI_FragModeCreateHandle(CSI_Type *base,
1104 csi_frag_handle_t *handle,
1105 const csi_frag_config_t *config,
1106 csi_frag_transfer_callback_t callback,
1107 void *userData)
1108 {
1109 assert(NULL != config);
1110 uint32_t reg;
1111 uint32_t instance;
1112 uint32_t imgWidth_Bytes;
1113
1114 if (config->dataBus != kCSI_DataBus8Bit)
1115 {
1116 return kStatus_InvalidArgument;
1117 }
1118
1119 imgWidth_Bytes = (uint32_t)config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
1120
1121 /* The image buffer line width should be multiple of 8-bytes. */
1122 if ((imgWidth_Bytes & 0x07U) != 0U)
1123 {
1124 return kStatus_InvalidArgument;
1125 }
1126
1127 /* Camera frame height must be dividable by DMA buffer line. */
1128 if (config->height % config->dmaBufferLine != 0U)
1129 {
1130 return kStatus_InvalidArgument;
1131 }
1132
1133 (void)memset(handle, 0, sizeof(*handle));
1134 handle->callback = callback;
1135 handle->userData = userData;
1136 handle->height = config->height;
1137 handle->width = config->width;
1138 handle->maxLinePerFrag = config->dmaBufferLine;
1139 handle->dmaBytePerLine = config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
1140 handle->isDmaBufferCachable = config->isDmaBufferCachable;
1141
1142 /* Get instance from peripheral base address. */
1143 instance = CSI_GetInstance(base);
1144 /* Save the handle in global variables to support the double weak mechanism. */
1145 s_csiHandle[instance] = handle;
1146
1147 s_csiIsr = CSI_FragModeTransferHandleIRQ;
1148
1149 (void)EnableIRQ(s_csiIRQ[instance]);
1150
1151 /* Configure CSICR1. CSICR1 has been reset to the default value, so could write it directly. */
1152 reg = ((uint32_t)config->workMode) | config->polarityFlags | CSI_CR1_FCC_MASK;
1153
1154 if (config->useExtVsync)
1155 {
1156 reg |= CSI_CR1_EXT_VSYNC_MASK;
1157 }
1158
1159 CSI_REG_CR1(base) = reg;
1160
1161 /* No stride. */
1162 CSI_REG_FBUF_PARA(base) = 0;
1163
1164 /* Enable auto ECC. */
1165 CSI_REG_CR3(base) |= CSI_CR3_ECC_AUTO_EN_MASK;
1166
1167 /*
1168 * For better performance.
1169 * The DMA burst size could be set to 16 * 8 byte, 8 * 8 byte, or 4 * 8 byte,
1170 * choose the best burst size based on bytes per line.
1171 */
1172 if (0U == (imgWidth_Bytes % (8U * 16U)))
1173 {
1174 CSI_REG_CR2(base) = CSI_CR2_DMA_BURST_TYPE_RFF(3U);
1175 CSI_REG_CR3(base) = (CSI_REG_CR3(base) & ~CSI_CR3_RxFF_LEVEL_MASK) | ((2U << CSI_CR3_RxFF_LEVEL_SHIFT));
1176 }
1177 else if (0U == (imgWidth_Bytes % (8U * 8U)))
1178 {
1179 CSI_REG_CR2(base) = CSI_CR2_DMA_BURST_TYPE_RFF(2U);
1180 CSI_REG_CR3(base) = (CSI_REG_CR3(base) & ~CSI_CR3_RxFF_LEVEL_MASK) | ((1U << CSI_CR3_RxFF_LEVEL_SHIFT));
1181 }
1182 else
1183 {
1184 CSI_REG_CR2(base) = CSI_CR2_DMA_BURST_TYPE_RFF(1U);
1185 CSI_REG_CR3(base) = (CSI_REG_CR3(base) & ~CSI_CR3_RxFF_LEVEL_MASK) | ((0U << CSI_CR3_RxFF_LEVEL_SHIFT));
1186 }
1187
1188 CSI_REG_DMASA_FB1(base) = CSI_ADDR_CPU_2_IP(config->dmaBufferAddr0);
1189 CSI_REG_DMASA_FB2(base) = CSI_ADDR_CPU_2_IP(config->dmaBufferAddr1);
1190
1191 if (handle->isDmaBufferCachable)
1192 {
1193 DCACHE_CleanInvalidateByRange(
1194 config->dmaBufferAddr0,
1195 (uint32_t)config->dmaBufferLine * (uint32_t)config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
1196 DCACHE_CleanInvalidateByRange(
1197 config->dmaBufferAddr1,
1198 (uint32_t)config->dmaBufferLine * (uint32_t)config->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
1199 }
1200
1201 return kStatus_Success;
1202 }
1203
1204 /*!
1205 * brief Start to capture a image.
1206 *
1207 * param base CSI peripheral base address.
1208 * param handle Pointer to the transactional handle.
1209 * param config Pointer to the capture configuration.
1210 *
1211 * retval kStatus_Success Initialize successfully.
1212 * retval kStatus_InvalidArgument Initialize failed because of invalid argument.
1213 */
CSI_FragModeTransferCaptureImage(CSI_Type * base,csi_frag_handle_t * handle,const csi_frag_capture_config_t * config)1214 status_t CSI_FragModeTransferCaptureImage(CSI_Type *base,
1215 csi_frag_handle_t *handle,
1216 const csi_frag_capture_config_t *config)
1217 {
1218 assert(NULL != config);
1219
1220 uint16_t windowWidth;
1221
1222 /*
1223 * If no special window setting, capture full frame.
1224 * If capture window, then capture 1 one each fragment.
1225 */
1226 if (config->window != NULL)
1227 {
1228 handle->windowULX = config->window->windowULX;
1229 handle->windowULY = config->window->windowULY;
1230 handle->windowLRX = config->window->windowLRX;
1231 handle->windowLRY = config->window->windowLRY;
1232 handle->linePerFrag = 1;
1233 }
1234 else
1235 {
1236 handle->windowULX = 0;
1237 handle->windowULY = 0;
1238 handle->windowLRX = handle->width - 1U;
1239 handle->windowLRY = handle->height - 1U;
1240 handle->linePerFrag = handle->maxLinePerFrag;
1241 }
1242
1243 windowWidth = handle->windowLRX - handle->windowULX + 1U;
1244
1245 if (config->outputGrayScale)
1246 {
1247 /* When output format is gray, the window width must be multiple value of 8. */
1248 if (windowWidth % 8U != 0U)
1249 {
1250 return kStatus_InvalidArgument;
1251 }
1252
1253 handle->datBytePerLine = windowWidth;
1254 if (handle->inputFormat == kCSI_FragInputYUYV)
1255 {
1256 handle->copyFunc = CSI_ExtractYFromYUYV;
1257 }
1258 else
1259 {
1260 handle->copyFunc = CSI_ExtractYFromUYVY;
1261 }
1262 }
1263 else
1264 {
1265 handle->datBytePerLine = windowWidth * CSI_FRAG_INPUT_BYTES_PER_PIXEL;
1266 handle->copyFunc = CSI_MemCopy;
1267 }
1268
1269 handle->dmaCurLine = 0;
1270 handle->outputBuffer = (uint32_t)config->buffer;
1271 handle->datCurWriteAddr = (uint32_t)config->buffer;
1272
1273 /* Image parameter. */
1274 CSI_REG_IMAG_PARA(base) =
1275 (((uint32_t)handle->width * CSI_FRAG_INPUT_BYTES_PER_PIXEL) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT) |
1276 ((uint32_t)(handle->linePerFrag) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT);
1277
1278 /*
1279 * Write to memory from first completed frame.
1280 * DMA base addr switch at dma transfer done.
1281 */
1282 CSI_REG_CR18(base) = (CSI_REG_CR18(base) & ~CSI_CR18_MASK_OPTION_MASK) | CSI_CR18_MASK_OPTION(0);
1283
1284 CSI_EnableInterrupts(base, (uint32_t)kCSI_StartOfFrameInterruptEnable |
1285 (uint32_t)kCSI_RxBuffer1DmaDoneInterruptEnable |
1286 (uint32_t)kCSI_RxBuffer0DmaDoneInterruptEnable);
1287
1288 return kStatus_Success;
1289 }
1290
1291 /*!
1292 * brief Abort image capture.
1293 *
1294 * Abort image capture initialized by ref CSI_FragModeTransferCaptureImage.
1295 *
1296 * param base CSI peripheral base address.
1297 * param handle Pointer to the transactional handle.
1298 */
CSI_FragModeTransferAbortCaptureImage(CSI_Type * base,csi_frag_handle_t * handle)1299 void CSI_FragModeTransferAbortCaptureImage(CSI_Type *base, csi_frag_handle_t *handle)
1300 {
1301 CSI_Stop(base);
1302 CSI_DisableInterrupts(base, (uint32_t)kCSI_StartOfFrameInterruptEnable |
1303 (uint32_t)kCSI_RxBuffer1DmaDoneInterruptEnable |
1304 (uint32_t)kCSI_RxBuffer0DmaDoneInterruptEnable);
1305 }
1306
1307 /*!
1308 * brief CSI IRQ handle function.
1309 *
1310 * This function handles the CSI IRQ request to work with CSI driver fragment mode
1311 * APIs.
1312 *
1313 * param base CSI peripheral base address.
1314 * param handle CSI handle pointer.
1315 */
CSI_FragModeTransferHandleIRQ(CSI_Type * base,csi_frag_handle_t * handle)1316 void CSI_FragModeTransferHandleIRQ(CSI_Type *base, csi_frag_handle_t *handle)
1317 {
1318 uint32_t csisr = CSI_REG_SR(base);
1319 uint32_t dmaBufAddr;
1320 uint16_t line;
1321 pvoid_to_u32_t memSrc;
1322 pvoid_to_u32_t memDest;
1323
1324 /* Clear the error flags. */
1325 CSI_REG_SR(base) = csisr;
1326
1327 /* Start of frame, clear the FIFO and start receiving. */
1328 if (0U != (csisr & (uint32_t)kCSI_StartOfFrameFlag))
1329 {
1330 /* Reflash the DMA and enable RX DMA request. */
1331 CSI_REG_CR3(base) |= (CSI_CR3_DMA_REFLASH_RFF_MASK | CSI_CR3_DMA_REQ_EN_RFF_MASK);
1332 CSI_Start(base);
1333 handle->dmaCurLine = 0;
1334 handle->datCurWriteAddr = handle->outputBuffer;
1335 }
1336 else if ((csisr & (CSI_SR_DMA_TSF_DONE_FB2_MASK | CSI_SR_DMA_TSF_DONE_FB1_MASK)) != 0U)
1337 {
1338 if ((csisr & CSI_SR_DMA_TSF_DONE_FB1_MASK) == CSI_SR_DMA_TSF_DONE_FB1_MASK)
1339 {
1340 dmaBufAddr = CSI_REG_DMASA_FB1(base);
1341 }
1342 else
1343 {
1344 dmaBufAddr = CSI_REG_DMASA_FB2(base);
1345 }
1346
1347 dmaBufAddr = CSI_ADDR_IP_2_CPU(dmaBufAddr);
1348
1349 if (handle->isDmaBufferCachable)
1350 {
1351 DCACHE_InvalidateByRange(dmaBufAddr, (uint32_t)handle->dmaBytePerLine * (uint32_t)handle->linePerFrag);
1352 }
1353
1354 /* Copy from DMA buffer to user data buffer. */
1355 dmaBufAddr += ((uint32_t)handle->windowULX * CSI_FRAG_INPUT_BYTES_PER_PIXEL);
1356
1357 for (line = 0; line < handle->linePerFrag; line++)
1358 {
1359 if (handle->dmaCurLine + line > handle->windowLRY)
1360 {
1361 /* out of window range */
1362 break;
1363 }
1364 else if (handle->dmaCurLine + line >= handle->windowULY)
1365 {
1366 memDest.u32 = handle->datCurWriteAddr;
1367 memSrc.u32 = dmaBufAddr;
1368
1369 handle->copyFunc(memDest.pvoid, memSrc.pvoid, handle->datBytePerLine);
1370 handle->datCurWriteAddr += handle->datBytePerLine;
1371 dmaBufAddr += handle->dmaBytePerLine;
1372 }
1373 else
1374 {
1375 ; /* For MISRA C-2012 Rule 15.7 */
1376 }
1377 }
1378
1379 handle->dmaCurLine += handle->linePerFrag;
1380
1381 if (handle->dmaCurLine >= handle->height)
1382 {
1383 CSI_Stop(base);
1384 CSI_DisableInterrupts(base, (uint32_t)kCSI_StartOfFrameInterruptEnable |
1385 (uint32_t)kCSI_RxBuffer1DmaDoneInterruptEnable |
1386 (uint32_t)kCSI_RxBuffer0DmaDoneInterruptEnable);
1387
1388 /* Image captured. Stop the CSI. */
1389 if (NULL != handle->callback)
1390 {
1391 handle->callback(base, handle, kStatus_CSI_FrameDone, handle->userData);
1392 }
1393 }
1394 }
1395 else
1396 {
1397 }
1398 }
1399 #endif /* CSI_DRIVER_FRAG_MODE */
1400
1401 #if defined(CSI)
1402 void CSI_DriverIRQHandler(void);
CSI_DriverIRQHandler(void)1403 void CSI_DriverIRQHandler(void)
1404 {
1405 s_csiIsr(CSI, s_csiHandle[0]);
1406 SDK_ISR_EXIT_BARRIER;
1407 }
1408 #endif
1409
1410 #if defined(CSI0)
1411 void CSI0_DriverIRQHandler(void);
CSI0_DriverIRQHandler(void)1412 void CSI0_DriverIRQHandler(void)
1413 {
1414 s_csiIsr(CSI, s_csiHandle[0]);
1415 SDK_ISR_EXIT_BARRIER;
1416 }
1417 #endif
1418
