1 /***************************************************************************//** 2 * \file cyip_crypto.h 3 * 4 * \brief 5 * CRYPTO IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_CRYPTO_H_ 29 #define _CYIP_CRYPTO_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * CRYPTO 35 *******************************************************************************/ 36 37 #define CRYPTO_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Cryptography component (CRYPTO) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 44 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 45 __IOM uint32_t RAM_PWRUP_DELAY; /*!< 0x00000008 Power up delay used for SRAM power domain */ 46 __IM uint32_t RESERVED[5]; 47 __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */ 48 __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */ 49 __IM uint32_t RESERVED1[6]; 50 __IOM uint32_t INSTR_FF_CTL; /*!< 0x00000040 Instruction FIFO control */ 51 __IM uint32_t INSTR_FF_STATUS; /*!< 0x00000044 Instruction FIFO status */ 52 __OM uint32_t INSTR_FF_WR; /*!< 0x00000048 Instruction FIFO write */ 53 __IM uint32_t RESERVED2[13]; 54 __IM uint32_t RF_DATA[16]; /*!< 0x00000080 Register-file */ 55 __IM uint32_t RESERVED3[16]; 56 __IOM uint32_t AES_CTL; /*!< 0x00000100 AES control */ 57 __IM uint32_t RESERVED4[31]; 58 __IM uint32_t STR_RESULT; /*!< 0x00000180 String result */ 59 __IM uint32_t RESERVED5[31]; 60 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ 61 __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */ 62 __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */ 63 __IM uint32_t RESERVED6; 64 __IOM uint32_t PR_RESULT; /*!< 0x00000210 Pseudo random result */ 65 __IM uint32_t RESERVED7[27]; 66 __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */ 67 __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */ 68 __IOM uint32_t TR_RESULT; /*!< 0x00000288 True random result */ 69 __IM uint32_t RESERVED8[5]; 70 __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */ 71 __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */ 72 __IM uint32_t RESERVED9[6]; 73 __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */ 74 __IM uint32_t RESERVED10; 75 __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */ 76 __IM uint32_t RESERVED11; 77 __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */ 78 __IM uint32_t RESERVED12; 79 __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */ 80 __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */ 81 __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */ 82 __IM uint32_t RESERVED13; 83 __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */ 84 __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */ 85 __IM uint32_t RESERVED14[4]; 86 __IOM uint32_t SHA_CTL; /*!< 0x00000300 SHA control */ 87 __IM uint32_t RESERVED15[63]; 88 __IOM uint32_t CRC_CTL; /*!< 0x00000400 CRC control */ 89 __IM uint32_t RESERVED16[3]; 90 __IOM uint32_t CRC_DATA_CTL; /*!< 0x00000410 CRC data control */ 91 __IM uint32_t RESERVED17[3]; 92 __IOM uint32_t CRC_POL_CTL; /*!< 0x00000420 CRC polynomial control */ 93 __IM uint32_t RESERVED18[3]; 94 __IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000430 CRC LFSR control */ 95 __IM uint32_t RESERVED19[3]; 96 __IOM uint32_t CRC_REM_CTL; /*!< 0x00000440 CRC remainder control */ 97 __IM uint32_t RESERVED20; 98 __IM uint32_t CRC_REM_RESULT; /*!< 0x00000448 CRC remainder result */ 99 __IM uint32_t RESERVED21[13]; 100 __IOM uint32_t VU_CTL0; /*!< 0x00000480 Vector unit control 0 */ 101 __IOM uint32_t VU_CTL1; /*!< 0x00000484 Vector unit control 1 */ 102 __IM uint32_t RESERVED22[2]; 103 __IM uint32_t VU_STATUS; /*!< 0x00000490 Vector unit status */ 104 __IM uint32_t RESERVED23[203]; 105 __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ 106 __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ 107 __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ 108 __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ 109 __IM uint32_t RESERVED24[3596]; 110 __IOM uint32_t MEM_BUFF[4096]; /*!< 0x00004000 Memory buffer */ 111 } CRYPTO_V1_Type; /*!< Size = 32768 (0x8000) */ 112 113 114 /* CRYPTO.CTL */ 115 #define CRYPTO_CTL_PWR_MODE_Pos 0UL 116 #define CRYPTO_CTL_PWR_MODE_Msk 0x3UL 117 #define CRYPTO_CTL_ENABLED_Pos 31UL 118 #define CRYPTO_CTL_ENABLED_Msk 0x80000000UL 119 /* CRYPTO.STATUS */ 120 #define CRYPTO_STATUS_AES_BUSY_Pos 0UL 121 #define CRYPTO_STATUS_AES_BUSY_Msk 0x1UL 122 #define CRYPTO_STATUS_DES_BUSY_Pos 1UL 123 #define CRYPTO_STATUS_DES_BUSY_Msk 0x2UL 124 #define CRYPTO_STATUS_SHA_BUSY_Pos 2UL 125 #define CRYPTO_STATUS_SHA_BUSY_Msk 0x4UL 126 #define CRYPTO_STATUS_CRC_BUSY_Pos 3UL 127 #define CRYPTO_STATUS_CRC_BUSY_Msk 0x8UL 128 #define CRYPTO_STATUS_STR_BUSY_Pos 4UL 129 #define CRYPTO_STATUS_STR_BUSY_Msk 0x10UL 130 #define CRYPTO_STATUS_PR_BUSY_Pos 5UL 131 #define CRYPTO_STATUS_PR_BUSY_Msk 0x20UL 132 #define CRYPTO_STATUS_TR_BUSY_Pos 6UL 133 #define CRYPTO_STATUS_TR_BUSY_Msk 0x40UL 134 #define CRYPTO_STATUS_VU_BUSY_Pos 7UL 135 #define CRYPTO_STATUS_VU_BUSY_Msk 0x80UL 136 #define CRYPTO_STATUS_CMD_FF_BUSY_Pos 31UL 137 #define CRYPTO_STATUS_CMD_FF_BUSY_Msk 0x80000000UL 138 /* CRYPTO.RAM_PWRUP_DELAY */ 139 #define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Pos 0UL 140 #define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Msk 0x3FFUL 141 /* CRYPTO.ERROR_STATUS0 */ 142 #define CRYPTO_ERROR_STATUS0_DATA32_Pos 0UL 143 #define CRYPTO_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL 144 /* CRYPTO.ERROR_STATUS1 */ 145 #define CRYPTO_ERROR_STATUS1_DATA23_Pos 0UL 146 #define CRYPTO_ERROR_STATUS1_DATA23_Msk 0xFFFFFFUL 147 #define CRYPTO_ERROR_STATUS1_IDX_Pos 24UL 148 #define CRYPTO_ERROR_STATUS1_IDX_Msk 0x7000000UL 149 #define CRYPTO_ERROR_STATUS1_VALID_Pos 31UL 150 #define CRYPTO_ERROR_STATUS1_VALID_Msk 0x80000000UL 151 /* CRYPTO.INSTR_FF_CTL */ 152 #define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL 153 #define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL 154 #define CRYPTO_INSTR_FF_CTL_CLEAR_Pos 16UL 155 #define CRYPTO_INSTR_FF_CTL_CLEAR_Msk 0x10000UL 156 #define CRYPTO_INSTR_FF_CTL_BLOCK_Pos 17UL 157 #define CRYPTO_INSTR_FF_CTL_BLOCK_Msk 0x20000UL 158 /* CRYPTO.INSTR_FF_STATUS */ 159 #define CRYPTO_INSTR_FF_STATUS_USED_Pos 0UL 160 #define CRYPTO_INSTR_FF_STATUS_USED_Msk 0xFUL 161 #define CRYPTO_INSTR_FF_STATUS_EVENT_Pos 16UL 162 #define CRYPTO_INSTR_FF_STATUS_EVENT_Msk 0x10000UL 163 #define CRYPTO_INSTR_FF_STATUS_BUSY_Pos 31UL 164 #define CRYPTO_INSTR_FF_STATUS_BUSY_Msk 0x80000000UL 165 /* CRYPTO.INSTR_FF_WR */ 166 #define CRYPTO_INSTR_FF_WR_DATA32_Pos 0UL 167 #define CRYPTO_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL 168 /* CRYPTO.RF_DATA */ 169 #define CRYPTO_RF_DATA_DATA32_Pos 0UL 170 #define CRYPTO_RF_DATA_DATA32_Msk 0xFFFFFFFFUL 171 /* CRYPTO.AES_CTL */ 172 #define CRYPTO_AES_CTL_KEY_SIZE_Pos 0UL 173 #define CRYPTO_AES_CTL_KEY_SIZE_Msk 0x3UL 174 /* CRYPTO.STR_RESULT */ 175 #define CRYPTO_STR_RESULT_MEMCMP_Pos 0UL 176 #define CRYPTO_STR_RESULT_MEMCMP_Msk 0x1UL 177 /* CRYPTO.PR_LFSR_CTL0 */ 178 #define CRYPTO_PR_LFSR_CTL0_LFSR32_Pos 0UL 179 #define CRYPTO_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL 180 /* CRYPTO.PR_LFSR_CTL1 */ 181 #define CRYPTO_PR_LFSR_CTL1_LFSR31_Pos 0UL 182 #define CRYPTO_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL 183 /* CRYPTO.PR_LFSR_CTL2 */ 184 #define CRYPTO_PR_LFSR_CTL2_LFSR29_Pos 0UL 185 #define CRYPTO_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL 186 /* CRYPTO.PR_RESULT */ 187 #define CRYPTO_PR_RESULT_DATA32_Pos 0UL 188 #define CRYPTO_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL 189 /* CRYPTO.TR_CTL0 */ 190 #define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL 191 #define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL 192 #define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Pos 8UL 193 #define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL 194 #define CRYPTO_TR_CTL0_INIT_DELAY_Pos 16UL 195 #define CRYPTO_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL 196 #define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL 197 #define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL 198 #define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL 199 #define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL 200 #define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL 201 #define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL 202 /* CRYPTO.TR_CTL1 */ 203 #define CRYPTO_TR_CTL1_RO11_EN_Pos 0UL 204 #define CRYPTO_TR_CTL1_RO11_EN_Msk 0x1UL 205 #define CRYPTO_TR_CTL1_RO15_EN_Pos 1UL 206 #define CRYPTO_TR_CTL1_RO15_EN_Msk 0x2UL 207 #define CRYPTO_TR_CTL1_GARO15_EN_Pos 2UL 208 #define CRYPTO_TR_CTL1_GARO15_EN_Msk 0x4UL 209 #define CRYPTO_TR_CTL1_GARO31_EN_Pos 3UL 210 #define CRYPTO_TR_CTL1_GARO31_EN_Msk 0x8UL 211 #define CRYPTO_TR_CTL1_FIRO15_EN_Pos 4UL 212 #define CRYPTO_TR_CTL1_FIRO15_EN_Msk 0x10UL 213 #define CRYPTO_TR_CTL1_FIRO31_EN_Pos 5UL 214 #define CRYPTO_TR_CTL1_FIRO31_EN_Msk 0x20UL 215 /* CRYPTO.TR_RESULT */ 216 #define CRYPTO_TR_RESULT_DATA32_Pos 0UL 217 #define CRYPTO_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL 218 /* CRYPTO.TR_GARO_CTL */ 219 #define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL 220 #define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 221 /* CRYPTO.TR_FIRO_CTL */ 222 #define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL 223 #define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 224 /* CRYPTO.TR_MON_CTL */ 225 #define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL 226 #define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL 227 /* CRYPTO.TR_MON_CMD */ 228 #define CRYPTO_TR_MON_CMD_START_AP_Pos 0UL 229 #define CRYPTO_TR_MON_CMD_START_AP_Msk 0x1UL 230 #define CRYPTO_TR_MON_CMD_START_RC_Pos 1UL 231 #define CRYPTO_TR_MON_CMD_START_RC_Msk 0x2UL 232 /* CRYPTO.TR_MON_RC_CTL */ 233 #define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL 234 #define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL 235 /* CRYPTO.TR_MON_RC_STATUS0 */ 236 #define CRYPTO_TR_MON_RC_STATUS0_BIT_Pos 0UL 237 #define CRYPTO_TR_MON_RC_STATUS0_BIT_Msk 0x1UL 238 /* CRYPTO.TR_MON_RC_STATUS1 */ 239 #define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL 240 #define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL 241 /* CRYPTO.TR_MON_AP_CTL */ 242 #define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL 243 #define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL 244 #define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL 245 #define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL 246 /* CRYPTO.TR_MON_AP_STATUS0 */ 247 #define CRYPTO_TR_MON_AP_STATUS0_BIT_Pos 0UL 248 #define CRYPTO_TR_MON_AP_STATUS0_BIT_Msk 0x1UL 249 /* CRYPTO.TR_MON_AP_STATUS1 */ 250 #define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL 251 #define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL 252 #define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL 253 #define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL 254 /* CRYPTO.SHA_CTL */ 255 #define CRYPTO_SHA_CTL_MODE_Pos 0UL 256 #define CRYPTO_SHA_CTL_MODE_Msk 0x7UL 257 /* CRYPTO.CRC_CTL */ 258 #define CRYPTO_CRC_CTL_DATA_REVERSE_Pos 0UL 259 #define CRYPTO_CRC_CTL_DATA_REVERSE_Msk 0x1UL 260 #define CRYPTO_CRC_CTL_REM_REVERSE_Pos 8UL 261 #define CRYPTO_CRC_CTL_REM_REVERSE_Msk 0x100UL 262 /* CRYPTO.CRC_DATA_CTL */ 263 #define CRYPTO_CRC_DATA_CTL_DATA_XOR_Pos 0UL 264 #define CRYPTO_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL 265 /* CRYPTO.CRC_POL_CTL */ 266 #define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Pos 0UL 267 #define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL 268 /* CRYPTO.CRC_LFSR_CTL */ 269 #define CRYPTO_CRC_LFSR_CTL_LFSR32_Pos 0UL 270 #define CRYPTO_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL 271 /* CRYPTO.CRC_REM_CTL */ 272 #define CRYPTO_CRC_REM_CTL_REM_XOR_Pos 0UL 273 #define CRYPTO_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL 274 /* CRYPTO.CRC_REM_RESULT */ 275 #define CRYPTO_CRC_REM_RESULT_REM_Pos 0UL 276 #define CRYPTO_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL 277 /* CRYPTO.VU_CTL0 */ 278 #define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL 279 #define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL 280 /* CRYPTO.VU_CTL1 */ 281 #define CRYPTO_VU_CTL1_ADDR_Pos 14UL 282 #define CRYPTO_VU_CTL1_ADDR_Msk 0xFFFFC000UL 283 /* CRYPTO.VU_STATUS */ 284 #define CRYPTO_VU_STATUS_CARRY_Pos 0UL 285 #define CRYPTO_VU_STATUS_CARRY_Msk 0x1UL 286 #define CRYPTO_VU_STATUS_EVEN_Pos 1UL 287 #define CRYPTO_VU_STATUS_EVEN_Msk 0x2UL 288 #define CRYPTO_VU_STATUS_ZERO_Pos 2UL 289 #define CRYPTO_VU_STATUS_ZERO_Msk 0x4UL 290 #define CRYPTO_VU_STATUS_ONE_Pos 3UL 291 #define CRYPTO_VU_STATUS_ONE_Msk 0x8UL 292 /* CRYPTO.INTR */ 293 #define CRYPTO_INTR_INSTR_FF_LEVEL_Pos 0UL 294 #define CRYPTO_INTR_INSTR_FF_LEVEL_Msk 0x1UL 295 #define CRYPTO_INTR_INSTR_FF_OVERFLOW_Pos 1UL 296 #define CRYPTO_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL 297 #define CRYPTO_INTR_TR_INITIALIZED_Pos 2UL 298 #define CRYPTO_INTR_TR_INITIALIZED_Msk 0x4UL 299 #define CRYPTO_INTR_TR_DATA_AVAILABLE_Pos 3UL 300 #define CRYPTO_INTR_TR_DATA_AVAILABLE_Msk 0x8UL 301 #define CRYPTO_INTR_PR_DATA_AVAILABLE_Pos 4UL 302 #define CRYPTO_INTR_PR_DATA_AVAILABLE_Msk 0x10UL 303 #define CRYPTO_INTR_INSTR_OPC_ERROR_Pos 16UL 304 #define CRYPTO_INTR_INSTR_OPC_ERROR_Msk 0x10000UL 305 #define CRYPTO_INTR_INSTR_CC_ERROR_Pos 17UL 306 #define CRYPTO_INTR_INSTR_CC_ERROR_Msk 0x20000UL 307 #define CRYPTO_INTR_BUS_ERROR_Pos 18UL 308 #define CRYPTO_INTR_BUS_ERROR_Msk 0x40000UL 309 #define CRYPTO_INTR_TR_AP_DETECT_ERROR_Pos 19UL 310 #define CRYPTO_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL 311 #define CRYPTO_INTR_TR_RC_DETECT_ERROR_Pos 20UL 312 #define CRYPTO_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL 313 /* CRYPTO.INTR_SET */ 314 #define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Pos 0UL 315 #define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL 316 #define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL 317 #define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL 318 #define CRYPTO_INTR_SET_TR_INITIALIZED_Pos 2UL 319 #define CRYPTO_INTR_SET_TR_INITIALIZED_Msk 0x4UL 320 #define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL 321 #define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL 322 #define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL 323 #define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL 324 #define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Pos 16UL 325 #define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL 326 #define CRYPTO_INTR_SET_INSTR_CC_ERROR_Pos 17UL 327 #define CRYPTO_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL 328 #define CRYPTO_INTR_SET_BUS_ERROR_Pos 18UL 329 #define CRYPTO_INTR_SET_BUS_ERROR_Msk 0x40000UL 330 #define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL 331 #define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL 332 #define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL 333 #define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL 334 /* CRYPTO.INTR_MASK */ 335 #define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL 336 #define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL 337 #define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL 338 #define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL 339 #define CRYPTO_INTR_MASK_TR_INITIALIZED_Pos 2UL 340 #define CRYPTO_INTR_MASK_TR_INITIALIZED_Msk 0x4UL 341 #define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL 342 #define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL 343 #define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL 344 #define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL 345 #define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL 346 #define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL 347 #define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Pos 17UL 348 #define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL 349 #define CRYPTO_INTR_MASK_BUS_ERROR_Pos 18UL 350 #define CRYPTO_INTR_MASK_BUS_ERROR_Msk 0x40000UL 351 #define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL 352 #define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL 353 #define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL 354 #define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL 355 /* CRYPTO.INTR_MASKED */ 356 #define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL 357 #define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL 358 #define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL 359 #define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL 360 #define CRYPTO_INTR_MASKED_TR_INITIALIZED_Pos 2UL 361 #define CRYPTO_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL 362 #define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL 363 #define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL 364 #define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL 365 #define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL 366 #define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL 367 #define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL 368 #define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL 369 #define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL 370 #define CRYPTO_INTR_MASKED_BUS_ERROR_Pos 18UL 371 #define CRYPTO_INTR_MASKED_BUS_ERROR_Msk 0x40000UL 372 #define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL 373 #define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL 374 #define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL 375 #define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL 376 /* CRYPTO.MEM_BUFF */ 377 #define CRYPTO_MEM_BUFF_DATA32_Pos 0UL 378 #define CRYPTO_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL 379 380 381 #endif /* _CYIP_CRYPTO_H_ */ 382 383 384 /* [] END OF FILE */ 385
