1 /***************************************************************************//** 2 * \file cyip_crypto.h 3 * 4 * \brief 5 * CRYPTO IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CRYPTO_H_ 28 #define _CYIP_CRYPTO_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CRYPTO 34 *******************************************************************************/ 35 36 #define CRYPTO_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Cryptography component (CRYPTO) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 43 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 44 __IOM uint32_t RAM_PWRUP_DELAY; /*!< 0x00000008 Power up delay used for SRAM power domain */ 45 __IM uint32_t RESERVED[5]; 46 __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */ 47 __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */ 48 __IM uint32_t RESERVED1[6]; 49 __IOM uint32_t INSTR_FF_CTL; /*!< 0x00000040 Instruction FIFO control */ 50 __IM uint32_t INSTR_FF_STATUS; /*!< 0x00000044 Instruction FIFO status */ 51 __OM uint32_t INSTR_FF_WR; /*!< 0x00000048 Instruction FIFO write */ 52 __IM uint32_t RESERVED2[13]; 53 __IM uint32_t RF_DATA[16]; /*!< 0x00000080 Register-file */ 54 __IM uint32_t RESERVED3[16]; 55 __IOM uint32_t AES_CTL; /*!< 0x00000100 AES control */ 56 __IM uint32_t RESERVED4[31]; 57 __IM uint32_t STR_RESULT; /*!< 0x00000180 String result */ 58 __IM uint32_t RESERVED5[31]; 59 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ 60 __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */ 61 __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */ 62 __IM uint32_t RESERVED6; 63 __IOM uint32_t PR_RESULT; /*!< 0x00000210 Pseudo random result */ 64 __IM uint32_t RESERVED7[27]; 65 __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */ 66 __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */ 67 __IOM uint32_t TR_RESULT; /*!< 0x00000288 True random result */ 68 __IM uint32_t RESERVED8[5]; 69 __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */ 70 __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */ 71 __IM uint32_t RESERVED9[6]; 72 __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */ 73 __IM uint32_t RESERVED10; 74 __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */ 75 __IM uint32_t RESERVED11; 76 __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */ 77 __IM uint32_t RESERVED12; 78 __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */ 79 __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */ 80 __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */ 81 __IM uint32_t RESERVED13; 82 __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */ 83 __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */ 84 __IM uint32_t RESERVED14[4]; 85 __IOM uint32_t SHA_CTL; /*!< 0x00000300 SHA control */ 86 __IM uint32_t RESERVED15[63]; 87 __IOM uint32_t CRC_CTL; /*!< 0x00000400 CRC control */ 88 __IM uint32_t RESERVED16[3]; 89 __IOM uint32_t CRC_DATA_CTL; /*!< 0x00000410 CRC data control */ 90 __IM uint32_t RESERVED17[3]; 91 __IOM uint32_t CRC_POL_CTL; /*!< 0x00000420 CRC polynomial control */ 92 __IM uint32_t RESERVED18[3]; 93 __IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000430 CRC LFSR control */ 94 __IM uint32_t RESERVED19[3]; 95 __IOM uint32_t CRC_REM_CTL; /*!< 0x00000440 CRC remainder control */ 96 __IM uint32_t RESERVED20; 97 __IM uint32_t CRC_REM_RESULT; /*!< 0x00000448 CRC remainder result */ 98 __IM uint32_t RESERVED21[13]; 99 __IOM uint32_t VU_CTL0; /*!< 0x00000480 Vector unit control 0 */ 100 __IOM uint32_t VU_CTL1; /*!< 0x00000484 Vector unit control 1 */ 101 __IM uint32_t RESERVED22[2]; 102 __IM uint32_t VU_STATUS; /*!< 0x00000490 Vector unit status */ 103 __IM uint32_t RESERVED23[203]; 104 __IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */ 105 __IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */ 106 __IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */ 107 __IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */ 108 __IM uint32_t RESERVED24[3596]; 109 __IOM uint32_t MEM_BUFF[4096]; /*!< 0x00004000 Memory buffer */ 110 } CRYPTO_V1_Type; /*!< Size = 32768 (0x8000) */ 111 112 113 /* CRYPTO.CTL */ 114 #define CRYPTO_CTL_PWR_MODE_Pos 0UL 115 #define CRYPTO_CTL_PWR_MODE_Msk 0x3UL 116 #define CRYPTO_CTL_ENABLED_Pos 31UL 117 #define CRYPTO_CTL_ENABLED_Msk 0x80000000UL 118 /* CRYPTO.STATUS */ 119 #define CRYPTO_STATUS_AES_BUSY_Pos 0UL 120 #define CRYPTO_STATUS_AES_BUSY_Msk 0x1UL 121 #define CRYPTO_STATUS_DES_BUSY_Pos 1UL 122 #define CRYPTO_STATUS_DES_BUSY_Msk 0x2UL 123 #define CRYPTO_STATUS_SHA_BUSY_Pos 2UL 124 #define CRYPTO_STATUS_SHA_BUSY_Msk 0x4UL 125 #define CRYPTO_STATUS_CRC_BUSY_Pos 3UL 126 #define CRYPTO_STATUS_CRC_BUSY_Msk 0x8UL 127 #define CRYPTO_STATUS_STR_BUSY_Pos 4UL 128 #define CRYPTO_STATUS_STR_BUSY_Msk 0x10UL 129 #define CRYPTO_STATUS_PR_BUSY_Pos 5UL 130 #define CRYPTO_STATUS_PR_BUSY_Msk 0x20UL 131 #define CRYPTO_STATUS_TR_BUSY_Pos 6UL 132 #define CRYPTO_STATUS_TR_BUSY_Msk 0x40UL 133 #define CRYPTO_STATUS_VU_BUSY_Pos 7UL 134 #define CRYPTO_STATUS_VU_BUSY_Msk 0x80UL 135 #define CRYPTO_STATUS_CMD_FF_BUSY_Pos 31UL 136 #define CRYPTO_STATUS_CMD_FF_BUSY_Msk 0x80000000UL 137 /* CRYPTO.RAM_PWRUP_DELAY */ 138 #define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Pos 0UL 139 #define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Msk 0x3FFUL 140 /* CRYPTO.ERROR_STATUS0 */ 141 #define CRYPTO_ERROR_STATUS0_DATA32_Pos 0UL 142 #define CRYPTO_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL 143 /* CRYPTO.ERROR_STATUS1 */ 144 #define CRYPTO_ERROR_STATUS1_DATA23_Pos 0UL 145 #define CRYPTO_ERROR_STATUS1_DATA23_Msk 0xFFFFFFUL 146 #define CRYPTO_ERROR_STATUS1_IDX_Pos 24UL 147 #define CRYPTO_ERROR_STATUS1_IDX_Msk 0x7000000UL 148 #define CRYPTO_ERROR_STATUS1_VALID_Pos 31UL 149 #define CRYPTO_ERROR_STATUS1_VALID_Msk 0x80000000UL 150 /* CRYPTO.INSTR_FF_CTL */ 151 #define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL 152 #define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL 153 #define CRYPTO_INSTR_FF_CTL_CLEAR_Pos 16UL 154 #define CRYPTO_INSTR_FF_CTL_CLEAR_Msk 0x10000UL 155 #define CRYPTO_INSTR_FF_CTL_BLOCK_Pos 17UL 156 #define CRYPTO_INSTR_FF_CTL_BLOCK_Msk 0x20000UL 157 /* CRYPTO.INSTR_FF_STATUS */ 158 #define CRYPTO_INSTR_FF_STATUS_USED_Pos 0UL 159 #define CRYPTO_INSTR_FF_STATUS_USED_Msk 0xFUL 160 #define CRYPTO_INSTR_FF_STATUS_EVENT_Pos 16UL 161 #define CRYPTO_INSTR_FF_STATUS_EVENT_Msk 0x10000UL 162 #define CRYPTO_INSTR_FF_STATUS_BUSY_Pos 31UL 163 #define CRYPTO_INSTR_FF_STATUS_BUSY_Msk 0x80000000UL 164 /* CRYPTO.INSTR_FF_WR */ 165 #define CRYPTO_INSTR_FF_WR_DATA32_Pos 0UL 166 #define CRYPTO_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL 167 /* CRYPTO.RF_DATA */ 168 #define CRYPTO_RF_DATA_DATA32_Pos 0UL 169 #define CRYPTO_RF_DATA_DATA32_Msk 0xFFFFFFFFUL 170 /* CRYPTO.AES_CTL */ 171 #define CRYPTO_AES_CTL_KEY_SIZE_Pos 0UL 172 #define CRYPTO_AES_CTL_KEY_SIZE_Msk 0x3UL 173 /* CRYPTO.STR_RESULT */ 174 #define CRYPTO_STR_RESULT_MEMCMP_Pos 0UL 175 #define CRYPTO_STR_RESULT_MEMCMP_Msk 0x1UL 176 /* CRYPTO.PR_LFSR_CTL0 */ 177 #define CRYPTO_PR_LFSR_CTL0_LFSR32_Pos 0UL 178 #define CRYPTO_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL 179 /* CRYPTO.PR_LFSR_CTL1 */ 180 #define CRYPTO_PR_LFSR_CTL1_LFSR31_Pos 0UL 181 #define CRYPTO_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL 182 /* CRYPTO.PR_LFSR_CTL2 */ 183 #define CRYPTO_PR_LFSR_CTL2_LFSR29_Pos 0UL 184 #define CRYPTO_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL 185 /* CRYPTO.PR_RESULT */ 186 #define CRYPTO_PR_RESULT_DATA32_Pos 0UL 187 #define CRYPTO_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL 188 /* CRYPTO.TR_CTL0 */ 189 #define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL 190 #define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL 191 #define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Pos 8UL 192 #define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL 193 #define CRYPTO_TR_CTL0_INIT_DELAY_Pos 16UL 194 #define CRYPTO_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL 195 #define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL 196 #define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL 197 #define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL 198 #define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL 199 #define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL 200 #define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL 201 /* CRYPTO.TR_CTL1 */ 202 #define CRYPTO_TR_CTL1_RO11_EN_Pos 0UL 203 #define CRYPTO_TR_CTL1_RO11_EN_Msk 0x1UL 204 #define CRYPTO_TR_CTL1_RO15_EN_Pos 1UL 205 #define CRYPTO_TR_CTL1_RO15_EN_Msk 0x2UL 206 #define CRYPTO_TR_CTL1_GARO15_EN_Pos 2UL 207 #define CRYPTO_TR_CTL1_GARO15_EN_Msk 0x4UL 208 #define CRYPTO_TR_CTL1_GARO31_EN_Pos 3UL 209 #define CRYPTO_TR_CTL1_GARO31_EN_Msk 0x8UL 210 #define CRYPTO_TR_CTL1_FIRO15_EN_Pos 4UL 211 #define CRYPTO_TR_CTL1_FIRO15_EN_Msk 0x10UL 212 #define CRYPTO_TR_CTL1_FIRO31_EN_Pos 5UL 213 #define CRYPTO_TR_CTL1_FIRO31_EN_Msk 0x20UL 214 /* CRYPTO.TR_RESULT */ 215 #define CRYPTO_TR_RESULT_DATA32_Pos 0UL 216 #define CRYPTO_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL 217 /* CRYPTO.TR_GARO_CTL */ 218 #define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL 219 #define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 220 /* CRYPTO.TR_FIRO_CTL */ 221 #define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL 222 #define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 223 /* CRYPTO.TR_MON_CTL */ 224 #define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL 225 #define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL 226 /* CRYPTO.TR_MON_CMD */ 227 #define CRYPTO_TR_MON_CMD_START_AP_Pos 0UL 228 #define CRYPTO_TR_MON_CMD_START_AP_Msk 0x1UL 229 #define CRYPTO_TR_MON_CMD_START_RC_Pos 1UL 230 #define CRYPTO_TR_MON_CMD_START_RC_Msk 0x2UL 231 /* CRYPTO.TR_MON_RC_CTL */ 232 #define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL 233 #define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL 234 /* CRYPTO.TR_MON_RC_STATUS0 */ 235 #define CRYPTO_TR_MON_RC_STATUS0_BIT_Pos 0UL 236 #define CRYPTO_TR_MON_RC_STATUS0_BIT_Msk 0x1UL 237 /* CRYPTO.TR_MON_RC_STATUS1 */ 238 #define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL 239 #define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL 240 /* CRYPTO.TR_MON_AP_CTL */ 241 #define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL 242 #define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL 243 #define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL 244 #define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL 245 /* CRYPTO.TR_MON_AP_STATUS0 */ 246 #define CRYPTO_TR_MON_AP_STATUS0_BIT_Pos 0UL 247 #define CRYPTO_TR_MON_AP_STATUS0_BIT_Msk 0x1UL 248 /* CRYPTO.TR_MON_AP_STATUS1 */ 249 #define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL 250 #define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL 251 #define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL 252 #define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL 253 /* CRYPTO.SHA_CTL */ 254 #define CRYPTO_SHA_CTL_MODE_Pos 0UL 255 #define CRYPTO_SHA_CTL_MODE_Msk 0x7UL 256 /* CRYPTO.CRC_CTL */ 257 #define CRYPTO_CRC_CTL_DATA_REVERSE_Pos 0UL 258 #define CRYPTO_CRC_CTL_DATA_REVERSE_Msk 0x1UL 259 #define CRYPTO_CRC_CTL_REM_REVERSE_Pos 8UL 260 #define CRYPTO_CRC_CTL_REM_REVERSE_Msk 0x100UL 261 /* CRYPTO.CRC_DATA_CTL */ 262 #define CRYPTO_CRC_DATA_CTL_DATA_XOR_Pos 0UL 263 #define CRYPTO_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL 264 /* CRYPTO.CRC_POL_CTL */ 265 #define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Pos 0UL 266 #define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL 267 /* CRYPTO.CRC_LFSR_CTL */ 268 #define CRYPTO_CRC_LFSR_CTL_LFSR32_Pos 0UL 269 #define CRYPTO_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL 270 /* CRYPTO.CRC_REM_CTL */ 271 #define CRYPTO_CRC_REM_CTL_REM_XOR_Pos 0UL 272 #define CRYPTO_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL 273 /* CRYPTO.CRC_REM_RESULT */ 274 #define CRYPTO_CRC_REM_RESULT_REM_Pos 0UL 275 #define CRYPTO_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL 276 /* CRYPTO.VU_CTL0 */ 277 #define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL 278 #define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL 279 /* CRYPTO.VU_CTL1 */ 280 #define CRYPTO_VU_CTL1_ADDR_Pos 14UL 281 #define CRYPTO_VU_CTL1_ADDR_Msk 0xFFFFC000UL 282 /* CRYPTO.VU_STATUS */ 283 #define CRYPTO_VU_STATUS_CARRY_Pos 0UL 284 #define CRYPTO_VU_STATUS_CARRY_Msk 0x1UL 285 #define CRYPTO_VU_STATUS_EVEN_Pos 1UL 286 #define CRYPTO_VU_STATUS_EVEN_Msk 0x2UL 287 #define CRYPTO_VU_STATUS_ZERO_Pos 2UL 288 #define CRYPTO_VU_STATUS_ZERO_Msk 0x4UL 289 #define CRYPTO_VU_STATUS_ONE_Pos 3UL 290 #define CRYPTO_VU_STATUS_ONE_Msk 0x8UL 291 /* CRYPTO.INTR */ 292 #define CRYPTO_INTR_INSTR_FF_LEVEL_Pos 0UL 293 #define CRYPTO_INTR_INSTR_FF_LEVEL_Msk 0x1UL 294 #define CRYPTO_INTR_INSTR_FF_OVERFLOW_Pos 1UL 295 #define CRYPTO_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL 296 #define CRYPTO_INTR_TR_INITIALIZED_Pos 2UL 297 #define CRYPTO_INTR_TR_INITIALIZED_Msk 0x4UL 298 #define CRYPTO_INTR_TR_DATA_AVAILABLE_Pos 3UL 299 #define CRYPTO_INTR_TR_DATA_AVAILABLE_Msk 0x8UL 300 #define CRYPTO_INTR_PR_DATA_AVAILABLE_Pos 4UL 301 #define CRYPTO_INTR_PR_DATA_AVAILABLE_Msk 0x10UL 302 #define CRYPTO_INTR_INSTR_OPC_ERROR_Pos 16UL 303 #define CRYPTO_INTR_INSTR_OPC_ERROR_Msk 0x10000UL 304 #define CRYPTO_INTR_INSTR_CC_ERROR_Pos 17UL 305 #define CRYPTO_INTR_INSTR_CC_ERROR_Msk 0x20000UL 306 #define CRYPTO_INTR_BUS_ERROR_Pos 18UL 307 #define CRYPTO_INTR_BUS_ERROR_Msk 0x40000UL 308 #define CRYPTO_INTR_TR_AP_DETECT_ERROR_Pos 19UL 309 #define CRYPTO_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL 310 #define CRYPTO_INTR_TR_RC_DETECT_ERROR_Pos 20UL 311 #define CRYPTO_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL 312 /* CRYPTO.INTR_SET */ 313 #define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Pos 0UL 314 #define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL 315 #define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL 316 #define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL 317 #define CRYPTO_INTR_SET_TR_INITIALIZED_Pos 2UL 318 #define CRYPTO_INTR_SET_TR_INITIALIZED_Msk 0x4UL 319 #define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL 320 #define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL 321 #define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL 322 #define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL 323 #define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Pos 16UL 324 #define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL 325 #define CRYPTO_INTR_SET_INSTR_CC_ERROR_Pos 17UL 326 #define CRYPTO_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL 327 #define CRYPTO_INTR_SET_BUS_ERROR_Pos 18UL 328 #define CRYPTO_INTR_SET_BUS_ERROR_Msk 0x40000UL 329 #define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL 330 #define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL 331 #define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL 332 #define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL 333 /* CRYPTO.INTR_MASK */ 334 #define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL 335 #define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL 336 #define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL 337 #define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL 338 #define CRYPTO_INTR_MASK_TR_INITIALIZED_Pos 2UL 339 #define CRYPTO_INTR_MASK_TR_INITIALIZED_Msk 0x4UL 340 #define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL 341 #define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL 342 #define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL 343 #define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL 344 #define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL 345 #define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL 346 #define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Pos 17UL 347 #define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL 348 #define CRYPTO_INTR_MASK_BUS_ERROR_Pos 18UL 349 #define CRYPTO_INTR_MASK_BUS_ERROR_Msk 0x40000UL 350 #define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL 351 #define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL 352 #define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL 353 #define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL 354 /* CRYPTO.INTR_MASKED */ 355 #define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL 356 #define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL 357 #define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL 358 #define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL 359 #define CRYPTO_INTR_MASKED_TR_INITIALIZED_Pos 2UL 360 #define CRYPTO_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL 361 #define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL 362 #define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL 363 #define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL 364 #define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL 365 #define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL 366 #define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL 367 #define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL 368 #define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL 369 #define CRYPTO_INTR_MASKED_BUS_ERROR_Pos 18UL 370 #define CRYPTO_INTR_MASKED_BUS_ERROR_Msk 0x40000UL 371 #define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL 372 #define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL 373 #define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL 374 #define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL 375 /* CRYPTO.MEM_BUFF */ 376 #define CRYPTO_MEM_BUFF_DATA32_Pos 0UL 377 #define CRYPTO_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL 378 379 380 #endif /* _CYIP_CRYPTO_H_ */ 381 382 383 /* [] END OF FILE */ 384
