1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 CRYPTOACC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_CRYPTOACC_H 31 #define EFR32BG22_CRYPTOACC_H 32 33 /**************************************************************************//** 34 * @addtogroup Parts 35 * @{ 36 ******************************************************************************/ 37 /**************************************************************************//** 38 * @defgroup EFR32BG22_CRYPTOACC CRYPTOACC 39 * @{ 40 * @brief EFR32BG22 CRYPTOACC Register Declaration. 41 *****************************************************************************/ 42 43 /** CRYPTOACC Register Declaration. */ 44 typedef struct { 45 __IOM uint32_t FETCHADDR; /**< Fetcher Address */ 46 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 47 __IOM uint32_t FETCHLEN; /**< Fetcher Length */ 48 __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ 49 __IOM uint32_t PUSHADDR; /**< Pusher Address */ 50 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 51 __IOM uint32_t PUSHLEN; /**< Pusher Length */ 52 __IOM uint32_t IEN; /**< Interrupt Enable */ 53 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 54 __IM uint32_t IF; /**< Interrupt Flags */ 55 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 56 __IOM uint32_t IF_CLR; /**< Interrupt status clear */ 57 __IOM uint32_t CTRL; /**< Control register */ 58 __IOM uint32_t CMD; /**< Command register */ 59 __IM uint32_t STATUS; /**< Status register */ 60 uint32_t RESERVED4[240U]; /**< Reserved for future use */ 61 __IM uint32_t INCL_IPS_HW_CFG; /**< General CRYPTOACC Hardware Configuration */ 62 __IM uint32_t BA411E_HW_CFG_1; /**< BA411E Hardware Configuration 1 */ 63 __IM uint32_t BA411E_HW_CFG_2; /**< BA411E Hardware Configuration 2 */ 64 __IM uint32_t BA413_HW_CFG; /**< BA413 Hardware Configuration */ 65 __IM uint32_t BA418_HW_CFG; /**< BA418 Hardware Configuration */ 66 __IM uint32_t BA419_HW_CFG; /**< BA419 Hardware Configuration */ 67 } CRYPTOACC_TypeDef; 68 /** @} End of group EFR32BG22_CRYPTOACC */ 69 70 /**************************************************************************//** 71 * @addtogroup EFR32BG22_CRYPTOACC 72 * @{ 73 * @defgroup EFR32BG22_CRYPTOACC_BitFields CRYPTOACC Bit Fields 74 * @{ 75 *****************************************************************************/ 76 77 /* Bit fields for CRYPTOACC FETCHADDR */ 78 #define _CRYPTOACC_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHADDR */ 79 #define _CRYPTOACC_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FETCHADDR */ 80 #define _CRYPTOACC_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for CRYPTOACC_ADDR */ 81 #define _CRYPTOACC_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_ADDR */ 82 #define _CRYPTOACC_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHADDR */ 83 #define CRYPTOACC_FETCHADDR_ADDR_DEFAULT (_CRYPTOACC_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHADDR*/ 84 85 /* Bit fields for CRYPTOACC FETCHLEN */ 86 #define _CRYPTOACC_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHLEN */ 87 #define _CRYPTOACC_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for CRYPTOACC_FETCHLEN */ 88 #define _CRYPTOACC_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for CRYPTOACC_LENGTH */ 89 #define _CRYPTOACC_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_LENGTH */ 90 #define _CRYPTOACC_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ 91 #define CRYPTOACC_FETCHLEN_LENGTH_DEFAULT (_CRYPTOACC_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ 92 #define CRYPTOACC_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ 93 #define _CRYPTOACC_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_CONSTADDR */ 94 #define _CRYPTOACC_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_CONSTADDR */ 95 #define _CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ 96 #define CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT (_CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ 97 #define CRYPTOACC_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign length */ 98 #define _CRYPTOACC_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_REALIGN */ 99 #define _CRYPTOACC_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_REALIGN */ 100 #define _CRYPTOACC_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ 101 #define CRYPTOACC_FETCHLEN_REALIGN_DEFAULT (_CRYPTOACC_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ 102 103 /* Bit fields for CRYPTOACC FETCHTAG */ 104 #define _CRYPTOACC_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHTAG */ 105 #define _CRYPTOACC_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FETCHTAG */ 106 #define _CRYPTOACC_FETCHTAG_TAG_SHIFT 0 /**< Shift value for CRYPTOACC_TAG */ 107 #define _CRYPTOACC_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TAG */ 108 #define _CRYPTOACC_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHTAG */ 109 #define CRYPTOACC_FETCHTAG_TAG_DEFAULT (_CRYPTOACC_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHTAG */ 110 111 /* Bit fields for CRYPTOACC PUSHADDR */ 112 #define _CRYPTOACC_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PUSHADDR */ 113 #define _CRYPTOACC_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_PUSHADDR */ 114 #define _CRYPTOACC_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for CRYPTOACC_ADDR */ 115 #define _CRYPTOACC_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_ADDR */ 116 #define _CRYPTOACC_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHADDR */ 117 #define CRYPTOACC_PUSHADDR_ADDR_DEFAULT (_CRYPTOACC_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHADDR */ 118 119 /* Bit fields for CRYPTOACC PUSHLEN */ 120 #define _CRYPTOACC_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PUSHLEN */ 121 #define _CRYPTOACC_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for CRYPTOACC_PUSHLEN */ 122 #define _CRYPTOACC_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for CRYPTOACC_LENGTH */ 123 #define _CRYPTOACC_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_LENGTH */ 124 #define _CRYPTOACC_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ 125 #define CRYPTOACC_PUSHLEN_LENGTH_DEFAULT (_CRYPTOACC_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ 126 #define CRYPTOACC_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ 127 #define _CRYPTOACC_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_CONSTADDR */ 128 #define _CRYPTOACC_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_CONSTADDR */ 129 #define _CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ 130 #define CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT (_CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ 131 #define CRYPTOACC_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ 132 #define _CRYPTOACC_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_REALIGN */ 133 #define _CRYPTOACC_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_REALIGN */ 134 #define _CRYPTOACC_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ 135 #define CRYPTOACC_PUSHLEN_REALIGN_DEFAULT (_CRYPTOACC_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ 136 #define CRYPTOACC_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ 137 #define _CRYPTOACC_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for CRYPTOACC_DISCARD */ 138 #define _CRYPTOACC_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_DISCARD */ 139 #define _CRYPTOACC_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ 140 #define CRYPTOACC_PUSHLEN_DISCARD_DEFAULT (_CRYPTOACC_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ 141 142 /* Bit fields for CRYPTOACC IEN */ 143 #define _CRYPTOACC_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IEN */ 144 #define _CRYPTOACC_IEN_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IEN */ 145 #define CRYPTOACC_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ 146 #define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ 147 #define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ 148 #define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ 149 #define CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ 150 #define CRYPTOACC_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ 151 #define _CRYPTOACC_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ 152 #define _CRYPTOACC_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ 153 #define _CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ 154 #define CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ 155 #define CRYPTOACC_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ 156 #define _CRYPTOACC_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ 157 #define _CRYPTOACC_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ 158 #define _CRYPTOACC_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ 159 #define CRYPTOACC_IEN_FETCHERERROR_DEFAULT (_CRYPTOACC_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ 160 #define CRYPTOACC_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ 161 #define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ 162 #define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ 163 #define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ 164 #define CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ 165 #define CRYPTOACC_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ 166 #define _CRYPTOACC_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ 167 #define _CRYPTOACC_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ 168 #define _CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ 169 #define CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ 170 #define CRYPTOACC_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ 171 #define _CRYPTOACC_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ 172 #define _CRYPTOACC_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ 173 #define _CRYPTOACC_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ 174 #define CRYPTOACC_IEN_PUSHERERROR_DEFAULT (_CRYPTOACC_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ 175 176 /* Bit fields for CRYPTOACC IF */ 177 #define _CRYPTOACC_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IF */ 178 #define _CRYPTOACC_IF_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IF */ 179 #define CRYPTOACC_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ 180 #define _CRYPTOACC_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ 181 #define _CRYPTOACC_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ 182 #define _CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ 183 #define CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ 184 #define CRYPTOACC_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ 185 #define _CRYPTOACC_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ 186 #define _CRYPTOACC_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ 187 #define _CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ 188 #define CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ 189 #define CRYPTOACC_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ 190 #define _CRYPTOACC_IF_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ 191 #define _CRYPTOACC_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ 192 #define _CRYPTOACC_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ 193 #define CRYPTOACC_IF_FETCHERERROR_DEFAULT (_CRYPTOACC_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ 194 #define CRYPTOACC_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ 195 #define _CRYPTOACC_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ 196 #define _CRYPTOACC_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ 197 #define _CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ 198 #define CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ 199 #define CRYPTOACC_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ 200 #define _CRYPTOACC_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ 201 #define _CRYPTOACC_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ 202 #define _CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ 203 #define CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ 204 #define CRYPTOACC_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ 205 #define _CRYPTOACC_IF_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ 206 #define _CRYPTOACC_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ 207 #define _CRYPTOACC_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ 208 #define CRYPTOACC_IF_PUSHERERROR_DEFAULT (_CRYPTOACC_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ 209 210 /* Bit fields for CRYPTOACC IF_CLR */ 211 #define _CRYPTOACC_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IF_CLR */ 212 #define _CRYPTOACC_IF_CLR_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IF_CLR */ 213 #define CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ 214 #define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ 215 #define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ 216 #define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ 217 #define CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ 218 #define CRYPTOACC_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ 219 #define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ 220 #define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ 221 #define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ 222 #define CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ 223 #define CRYPTOACC_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ 224 #define _CRYPTOACC_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ 225 #define _CRYPTOACC_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ 226 #define _CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ 227 #define CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ 228 #define CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag clear */ 229 #define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ 230 #define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ 231 #define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ 232 #define CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ 233 #define CRYPTOACC_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag clear */ 234 #define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ 235 #define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ 236 #define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ 237 #define CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ 238 #define CRYPTOACC_IF_CLR_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag clear */ 239 #define _CRYPTOACC_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ 240 #define _CRYPTOACC_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ 241 #define _CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ 242 #define CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ 243 244 /* Bit fields for CRYPTOACC CTRL */ 245 #define _CRYPTOACC_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CTRL */ 246 #define _CRYPTOACC_CTRL_MASK 0x0000001FUL /**< Mask for CRYPTOACC_CTRL */ 247 #define CRYPTOACC_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ 248 #define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERSCATTERGATHER*/ 249 #define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERSCATTERGATHER */ 250 #define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ 251 #define CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT (_CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ 252 #define CRYPTOACC_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ 253 #define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for CRYPTOACC_PUSHERSCATTERGATHER*/ 254 #define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSHERSCATTERGATHER */ 255 #define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ 256 #define CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT (_CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ 257 #define CRYPTOACC_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ 258 #define _CRYPTOACC_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for CRYPTOACC_STOPFETCHER */ 259 #define _CRYPTOACC_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for CRYPTOACC_STOPFETCHER */ 260 #define _CRYPTOACC_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ 261 #define CRYPTOACC_CTRL_STOPFETCHER_DEFAULT (_CRYPTOACC_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ 262 #define CRYPTOACC_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ 263 #define _CRYPTOACC_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for CRYPTOACC_STOPPUSHER */ 264 #define _CRYPTOACC_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for CRYPTOACC_STOPPUSHER */ 265 #define _CRYPTOACC_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ 266 #define CRYPTOACC_CTRL_STOPPUSHER_DEFAULT (_CRYPTOACC_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ 267 #define CRYPTOACC_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ 268 #define _CRYPTOACC_CTRL_SWRESET_SHIFT 4 /**< Shift value for CRYPTOACC_SWRESET */ 269 #define _CRYPTOACC_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for CRYPTOACC_SWRESET */ 270 #define _CRYPTOACC_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ 271 #define CRYPTOACC_CTRL_SWRESET_DEFAULT (_CRYPTOACC_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ 272 273 /* Bit fields for CRYPTOACC CMD */ 274 #define _CRYPTOACC_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CMD */ 275 #define _CRYPTOACC_CMD_MASK 0x00000003UL /**< Mask for CRYPTOACC_CMD */ 276 #define CRYPTOACC_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ 277 #define _CRYPTOACC_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for CRYPTOACC_STARTFETCHER */ 278 #define _CRYPTOACC_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for CRYPTOACC_STARTFETCHER */ 279 #define _CRYPTOACC_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CMD */ 280 #define CRYPTOACC_CMD_STARTFETCHER_DEFAULT (_CRYPTOACC_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CMD */ 281 #define CRYPTOACC_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ 282 #define _CRYPTOACC_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for CRYPTOACC_STARTPUSHER */ 283 #define _CRYPTOACC_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for CRYPTOACC_STARTPUSHER */ 284 #define _CRYPTOACC_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CMD */ 285 #define CRYPTOACC_CMD_STARTPUSHER_DEFAULT (_CRYPTOACC_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_CMD */ 286 287 /* Bit fields for CRYPTOACC STATUS */ 288 #define _CRYPTOACC_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_STATUS */ 289 #define _CRYPTOACC_STATUS_MASK 0xFFFF0073UL /**< Mask for CRYPTOACC_STATUS */ 290 #define CRYPTOACC_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ 291 #define _CRYPTOACC_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERBSY */ 292 #define _CRYPTOACC_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERBSY */ 293 #define _CRYPTOACC_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ 294 #define CRYPTOACC_STATUS_FETCHERBSY_DEFAULT (_CRYPTOACC_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ 295 #define CRYPTOACC_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ 296 #define _CRYPTOACC_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for CRYPTOACC_PUSHERBSY */ 297 #define _CRYPTOACC_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSHERBSY */ 298 #define _CRYPTOACC_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ 299 #define CRYPTOACC_STATUS_PUSHERBSY_DEFAULT (_CRYPTOACC_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ 300 #define CRYPTOACC_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ 301 #define _CRYPTOACC_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for CRYPTOACC_NOTEMPTY */ 302 #define _CRYPTOACC_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for CRYPTOACC_NOTEMPTY */ 303 #define _CRYPTOACC_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ 304 #define CRYPTOACC_STATUS_NOTEMPTY_DEFAULT (_CRYPTOACC_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ 305 #define CRYPTOACC_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ 306 #define _CRYPTOACC_STATUS_WAITING_SHIFT 5 /**< Shift value for CRYPTOACC_WAITING */ 307 #define _CRYPTOACC_STATUS_WAITING_MASK 0x20UL /**< Bit mask for CRYPTOACC_WAITING */ 308 #define _CRYPTOACC_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ 309 #define CRYPTOACC_STATUS_WAITING_DEFAULT (_CRYPTOACC_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ 310 #define CRYPTOACC_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ 311 #define _CRYPTOACC_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for CRYPTOACC_SOFTRSTBSY */ 312 #define _CRYPTOACC_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for CRYPTOACC_SOFTRSTBSY */ 313 #define _CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ 314 #define CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT (_CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ 315 #define _CRYPTOACC_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for CRYPTOACC_FIFODATANUM */ 316 #define _CRYPTOACC_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for CRYPTOACC_FIFODATANUM */ 317 #define _CRYPTOACC_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ 318 #define CRYPTOACC_STATUS_FIFODATANUM_DEFAULT (_CRYPTOACC_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ 319 320 /* Bit fields for CRYPTOACC INCL_IPS_HW_CFG */ 321 #define _CRYPTOACC_INCL_IPS_HW_CFG_RESETVALUE 0x00000611UL /**< Default value for CRYPTOACC_INCL_IPS_HW_CFG */ 322 #define _CRYPTOACC_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for CRYPTOACC_INCL_IPS_HW_CFG */ 323 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ 324 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for CRYPTOACC_g_IncludeAES */ 325 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for CRYPTOACC_g_IncludeAES */ 326 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 327 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 328 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ 329 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for CRYPTOACC_g_IncludeAESGCM */ 330 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for CRYPTOACC_g_IncludeAESGCM */ 331 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 332 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 333 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ 334 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for CRYPTOACC_g_IncludeAESXTS */ 335 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for CRYPTOACC_g_IncludeAESXTS */ 336 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 337 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 338 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ 339 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for CRYPTOACC_g_IncludeDES */ 340 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for CRYPTOACC_g_IncludeDES */ 341 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 342 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 343 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ 344 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for CRYPTOACC_g_IncludeHASH */ 345 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for CRYPTOACC_g_IncludeHASH */ 346 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 347 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 348 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ 349 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for CRYPTOACC_g_IncludeChachaPoly*/ 350 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for CRYPTOACC_g_IncludeChachaPoly */ 351 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 352 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 353 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ 354 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for CRYPTOACC_g_IncludeSHA3 */ 355 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for CRYPTOACC_g_IncludeSHA3 */ 356 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 357 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 358 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ 359 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for CRYPTOACC_g_IncludeZUC */ 360 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for CRYPTOACC_g_IncludeZUC */ 361 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 362 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 363 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ 364 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for CRYPTOACC_g_IncludeSM4 */ 365 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for CRYPTOACC_g_IncludeSM4 */ 366 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 367 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 368 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ 369 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for CRYPTOACC_g_IncludePKE */ 370 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for CRYPTOACC_g_IncludePKE */ 371 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 372 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 373 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ 374 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for CRYPTOACC_g_IncludeNDRNG */ 375 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for CRYPTOACC_g_IncludeNDRNG */ 376 #define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ 377 #define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ 378 379 /* Bit fields for CRYPTOACC BA411E_HW_CFG_1 */ 380 #define _CRYPTOACC_BA411E_HW_CFG_1_RESETVALUE 0x0700017FUL /**< Default value for CRYPTOACC_BA411E_HW_CFG_1 */ 381 #define _CRYPTOACC_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for CRYPTOACC_BA411E_HW_CFG_1 */ 382 #define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for CRYPTOACC_g_AesModesPoss */ 383 #define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for CRYPTOACC_g_AesModesPoss */ 384 #define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x0000017FUL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ 385 #define CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ 386 #define CRYPTOACC_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ 387 #define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for CRYPTOACC_g_CS */ 388 #define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for CRYPTOACC_g_CS */ 389 #define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ 390 #define CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ 391 #define CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ 392 #define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for CRYPTOACC_g_UseMasking */ 393 #define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for CRYPTOACC_g_UseMasking */ 394 #define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ 395 #define CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ 396 #define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for CRYPTOACC_g_Keysize */ 397 #define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for CRYPTOACC_g_Keysize */ 398 #define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000007UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ 399 #define CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ 400 401 /* Bit fields for CRYPTOACC BA411E_HW_CFG_2 */ 402 #define _CRYPTOACC_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for CRYPTOACC_BA411E_HW_CFG_2 */ 403 #define _CRYPTOACC_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_BA411E_HW_CFG_2 */ 404 #define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for CRYPTOACC_g_CtrSize */ 405 #define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_g_CtrSize */ 406 #define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_2 */ 407 #define CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_2*/ 408 409 /* Bit fields for CRYPTOACC BA413_HW_CFG */ 410 #define _CRYPTOACC_BA413_HW_CFG_RESETVALUE 0x0003007FUL /**< Default value for CRYPTOACC_BA413_HW_CFG */ 411 #define _CRYPTOACC_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for CRYPTOACC_BA413_HW_CFG */ 412 #define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for CRYPTOACC_g_HashMaskFunc */ 413 #define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for CRYPTOACC_g_HashMaskFunc */ 414 #define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ 415 #define CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ 416 #define CRYPTOACC_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ 417 #define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for CRYPTOACC_g_HashPadding */ 418 #define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for CRYPTOACC_g_HashPadding */ 419 #define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ 420 #define CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ 421 #define CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ 422 #define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for CRYPTOACC_g_HMAC_enabled */ 423 #define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for CRYPTOACC_g_HMAC_enabled */ 424 #define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ 425 #define CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ 426 #define CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ 427 #define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for CRYPTOACC_g_HashVerifyDigest*/ 428 #define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for CRYPTOACC_g_HashVerifyDigest */ 429 #define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ 430 #define CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ 431 432 /* Bit fields for CRYPTOACC BA418_HW_CFG */ 433 #define _CRYPTOACC_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for CRYPTOACC_BA418_HW_CFG */ 434 #define _CRYPTOACC_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for CRYPTOACC_BA418_HW_CFG */ 435 #define CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ 436 #define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for CRYPTOACC_g_Sha3CtxtEn */ 437 #define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for CRYPTOACC_g_Sha3CtxtEn */ 438 #define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA418_HW_CFG */ 439 #define CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA418_HW_CFG*/ 440 441 /* Bit fields for CRYPTOACC BA419_HW_CFG */ 442 #define _CRYPTOACC_BA419_HW_CFG_RESETVALUE 0x0000005FUL /**< Default value for CRYPTOACC_BA419_HW_CFG */ 443 #define _CRYPTOACC_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for CRYPTOACC_BA419_HW_CFG */ 444 #define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for CRYPTOACC_g_SM4ModesPoss */ 445 #define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for CRYPTOACC_g_SM4ModesPoss */ 446 #define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x0000005FUL /**< Mode DEFAULT for CRYPTOACC_BA419_HW_CFG */ 447 #define CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA419_HW_CFG*/ 448 449 /** @} End of group EFR32BG22_CRYPTOACC_BitFields */ 450 /** @} End of group EFR32BG22_CRYPTOACC */ 451 /**************************************************************************//** 452 * @defgroup EFR32BG22_CRYPTOACC_PKCTRL CRYPTOACC_PKCTRL 453 * @{ 454 * @brief EFR32BG22 CRYPTOACC_PKCTRL Register Declaration. 455 *****************************************************************************/ 456 457 /** CRYPTOACC_PKCTRL Register Declaration. */ 458 typedef struct { 459 __IOM uint32_t POINTER; /**< Pointers */ 460 __IOM uint32_t COMMAND; /**< Command */ 461 __IOM uint32_t PKCTRL; /**< Control */ 462 __IM uint32_t PKSTATUS; /**< Status */ 463 __IM uint32_t VERSION; /**< Version */ 464 __IM uint32_t TIMER; /**< Timer */ 465 } CRYPTOACC_PKCTRL_TypeDef; 466 /** @} End of group EFR32BG22_CRYPTOACC_PKCTRL */ 467 468 /**************************************************************************//** 469 * @addtogroup EFR32BG22_CRYPTOACC_PKCTRL 470 * @{ 471 * @defgroup EFR32BG22_CRYPTOACC_PKCTRL_BitFields CRYPTOACC_PKCTRL Bit Fields 472 * @{ 473 *****************************************************************************/ 474 475 /* Bit fields for CRYPTOACC POINTER */ 476 #define _CRYPTOACC_POINTER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_POINTER */ 477 #define _CRYPTOACC_POINTER_MASK 0x0F0F0F0FUL /**< Mask for CRYPTOACC_POINTER */ 478 #define _CRYPTOACC_POINTER_OPPTRA_SHIFT 0 /**< Shift value for CRYPTOACC_OPPTRA */ 479 #define _CRYPTOACC_POINTER_OPPTRA_MASK 0xFUL /**< Bit mask for CRYPTOACC_OPPTRA */ 480 #define _CRYPTOACC_POINTER_OPPTRA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ 481 #define CRYPTOACC_POINTER_OPPTRA_DEFAULT (_CRYPTOACC_POINTER_OPPTRA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ 482 #define _CRYPTOACC_POINTER_OPPTRB_SHIFT 8 /**< Shift value for CRYPTOACC_OPPTRB */ 483 #define _CRYPTOACC_POINTER_OPPTRB_MASK 0xF00UL /**< Bit mask for CRYPTOACC_OPPTRB */ 484 #define _CRYPTOACC_POINTER_OPPTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ 485 #define CRYPTOACC_POINTER_OPPTRB_DEFAULT (_CRYPTOACC_POINTER_OPPTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ 486 #define _CRYPTOACC_POINTER_OPPTRC_SHIFT 16 /**< Shift value for CRYPTOACC_OPPTRC */ 487 #define _CRYPTOACC_POINTER_OPPTRC_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_OPPTRC */ 488 #define _CRYPTOACC_POINTER_OPPTRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ 489 #define CRYPTOACC_POINTER_OPPTRC_DEFAULT (_CRYPTOACC_POINTER_OPPTRC_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ 490 #define _CRYPTOACC_POINTER_OPPTRN_SHIFT 24 /**< Shift value for CRYPTOACC_OPPTRN */ 491 #define _CRYPTOACC_POINTER_OPPTRN_MASK 0xF000000UL /**< Bit mask for CRYPTOACC_OPPTRN */ 492 #define _CRYPTOACC_POINTER_OPPTRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ 493 #define CRYPTOACC_POINTER_OPPTRN_DEFAULT (_CRYPTOACC_POINTER_OPPTRN_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ 494 495 /* Bit fields for CRYPTOACC COMMAND */ 496 #define _CRYPTOACC_COMMAND_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_COMMAND */ 497 #define _CRYPTOACC_COMMAND_MASK 0xFC77FFFFUL /**< Mask for CRYPTOACC_COMMAND */ 498 #define _CRYPTOACC_COMMAND_OPERATION_SHIFT 0 /**< Shift value for CRYPTOACC_OPERATION */ 499 #define _CRYPTOACC_COMMAND_OPERATION_MASK 0x7FUL /**< Bit mask for CRYPTOACC_OPERATION */ 500 #define _CRYPTOACC_COMMAND_OPERATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 501 #define CRYPTOACC_COMMAND_OPERATION_DEFAULT (_CRYPTOACC_COMMAND_OPERATION_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 502 #define CRYPTOACC_COMMAND_FIELD (0x1UL << 7) /**< Field */ 503 #define _CRYPTOACC_COMMAND_FIELD_SHIFT 7 /**< Shift value for CRYPTOACC_FIELD */ 504 #define _CRYPTOACC_COMMAND_FIELD_MASK 0x80UL /**< Bit mask for CRYPTOACC_FIELD */ 505 #define _CRYPTOACC_COMMAND_FIELD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 506 #define _CRYPTOACC_COMMAND_FIELD_GFP 0x00000000UL /**< Mode GFP for CRYPTOACC_COMMAND */ 507 #define _CRYPTOACC_COMMAND_FIELD_GF2M 0x00000001UL /**< Mode GF2M for CRYPTOACC_COMMAND */ 508 #define CRYPTOACC_COMMAND_FIELD_DEFAULT (_CRYPTOACC_COMMAND_FIELD_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 509 #define CRYPTOACC_COMMAND_FIELD_GFP (_CRYPTOACC_COMMAND_FIELD_GFP << 7) /**< Shifted mode GFP for CRYPTOACC_COMMAND */ 510 #define CRYPTOACC_COMMAND_FIELD_GF2M (_CRYPTOACC_COMMAND_FIELD_GF2M << 7) /**< Shifted mode GF2M for CRYPTOACC_COMMAND */ 511 #define _CRYPTOACC_COMMAND_SIZE_SHIFT 8 /**< Shift value for CRYPTOACC_SIZE */ 512 #define _CRYPTOACC_COMMAND_SIZE_MASK 0x7FF00UL /**< Bit mask for CRYPTOACC_SIZE */ 513 #define _CRYPTOACC_COMMAND_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 514 #define CRYPTOACC_COMMAND_SIZE_DEFAULT (_CRYPTOACC_COMMAND_SIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 515 #define _CRYPTOACC_COMMAND_SELCURVE_SHIFT 20 /**< Shift value for CRYPTOACC_SELCURVE */ 516 #define _CRYPTOACC_COMMAND_SELCURVE_MASK 0x700000UL /**< Bit mask for CRYPTOACC_SELCURVE */ 517 #define _CRYPTOACC_COMMAND_SELCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 518 #define _CRYPTOACC_COMMAND_SELCURVE_NONE 0x00000000UL /**< Mode NONE for CRYPTOACC_COMMAND */ 519 #define _CRYPTOACC_COMMAND_SELCURVE_P256 0x00000001UL /**< Mode P256 for CRYPTOACC_COMMAND */ 520 #define _CRYPTOACC_COMMAND_SELCURVE_P192 0x00000004UL /**< Mode P192 for CRYPTOACC_COMMAND */ 521 #define CRYPTOACC_COMMAND_SELCURVE_DEFAULT (_CRYPTOACC_COMMAND_SELCURVE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 522 #define CRYPTOACC_COMMAND_SELCURVE_NONE (_CRYPTOACC_COMMAND_SELCURVE_NONE << 20) /**< Shifted mode NONE for CRYPTOACC_COMMAND */ 523 #define CRYPTOACC_COMMAND_SELCURVE_P256 (_CRYPTOACC_COMMAND_SELCURVE_P256 << 20) /**< Shifted mode P256 for CRYPTOACC_COMMAND */ 524 #define CRYPTOACC_COMMAND_SELCURVE_P192 (_CRYPTOACC_COMMAND_SELCURVE_P192 << 20) /**< Shifted mode P192 for CRYPTOACC_COMMAND */ 525 #define CRYPTOACC_COMMAND_EDWARDS (0x1UL << 26) /**< Edwards Curve Enable */ 526 #define _CRYPTOACC_COMMAND_EDWARDS_SHIFT 26 /**< Shift value for CRYPTOACC_EDWARDS */ 527 #define _CRYPTOACC_COMMAND_EDWARDS_MASK 0x4000000UL /**< Bit mask for CRYPTOACC_EDWARDS */ 528 #define _CRYPTOACC_COMMAND_EDWARDS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 529 #define CRYPTOACC_COMMAND_EDWARDS_DEFAULT (_CRYPTOACC_COMMAND_EDWARDS_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 530 #define CRYPTOACC_COMMAND_BUFSEL (0x1UL << 27) /**< Buffer Select */ 531 #define _CRYPTOACC_COMMAND_BUFSEL_SHIFT 27 /**< Shift value for CRYPTOACC_BUFSEL */ 532 #define _CRYPTOACC_COMMAND_BUFSEL_MASK 0x8000000UL /**< Bit mask for CRYPTOACC_BUFSEL */ 533 #define _CRYPTOACC_COMMAND_BUFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 534 #define _CRYPTOACC_COMMAND_BUFSEL_MEM0 0x00000000UL /**< Mode MEM0 for CRYPTOACC_COMMAND */ 535 #define CRYPTOACC_COMMAND_BUFSEL_DEFAULT (_CRYPTOACC_COMMAND_BUFSEL_DEFAULT << 27) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 536 #define CRYPTOACC_COMMAND_BUFSEL_MEM0 (_CRYPTOACC_COMMAND_BUFSEL_MEM0 << 27) /**< Shifted mode MEM0 for CRYPTOACC_COMMAND */ 537 #define CRYPTOACC_COMMAND_SWAPBYTES (0x1UL << 28) /**< Swap bytes */ 538 #define _CRYPTOACC_COMMAND_SWAPBYTES_SHIFT 28 /**< Shift value for CRYPTOACC_SWAPBYTES */ 539 #define _CRYPTOACC_COMMAND_SWAPBYTES_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_SWAPBYTES */ 540 #define _CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 541 #define _CRYPTOACC_COMMAND_SWAPBYTES_NATIVE 0x00000000UL /**< Mode NATIVE for CRYPTOACC_COMMAND */ 542 #define _CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED 0x00000001UL /**< Mode SWAPPED for CRYPTOACC_COMMAND */ 543 #define CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT (_CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 544 #define CRYPTOACC_COMMAND_SWAPBYTES_NATIVE (_CRYPTOACC_COMMAND_SWAPBYTES_NATIVE << 28) /**< Shifted mode NATIVE for CRYPTOACC_COMMAND */ 545 #define CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED (_CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED << 28) /**< Shifted mode SWAPPED for CRYPTOACC_COMMAND */ 546 #define CRYPTOACC_COMMAND_FLAGA (0x1UL << 29) /**< Flag A */ 547 #define _CRYPTOACC_COMMAND_FLAGA_SHIFT 29 /**< Shift value for CRYPTOACC_FLAGA */ 548 #define _CRYPTOACC_COMMAND_FLAGA_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_FLAGA */ 549 #define _CRYPTOACC_COMMAND_FLAGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 550 #define CRYPTOACC_COMMAND_FLAGA_DEFAULT (_CRYPTOACC_COMMAND_FLAGA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 551 #define CRYPTOACC_COMMAND_FLAGB (0x1UL << 30) /**< Flag B */ 552 #define _CRYPTOACC_COMMAND_FLAGB_SHIFT 30 /**< Shift value for CRYPTOACC_FLAGB */ 553 #define _CRYPTOACC_COMMAND_FLAGB_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_FLAGB */ 554 #define _CRYPTOACC_COMMAND_FLAGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 555 #define CRYPTOACC_COMMAND_FLAGB_DEFAULT (_CRYPTOACC_COMMAND_FLAGB_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 556 #define CRYPTOACC_COMMAND_CALCR2 (0x1UL << 31) /**< Calculate R2 */ 557 #define _CRYPTOACC_COMMAND_CALCR2_SHIFT 31 /**< Shift value for CRYPTOACC_CALCR2 */ 558 #define _CRYPTOACC_COMMAND_CALCR2_MASK 0x80000000UL /**< Bit mask for CRYPTOACC_CALCR2 */ 559 #define _CRYPTOACC_COMMAND_CALCR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ 560 #define _CRYPTOACC_COMMAND_CALCR2_FALSE 0x00000000UL /**< Mode FALSE for CRYPTOACC_COMMAND */ 561 #define _CRYPTOACC_COMMAND_CALCR2_TRUE 0x00000001UL /**< Mode TRUE for CRYPTOACC_COMMAND */ 562 #define CRYPTOACC_COMMAND_CALCR2_DEFAULT (_CRYPTOACC_COMMAND_CALCR2_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ 563 #define CRYPTOACC_COMMAND_CALCR2_FALSE (_CRYPTOACC_COMMAND_CALCR2_FALSE << 31) /**< Shifted mode FALSE for CRYPTOACC_COMMAND */ 564 #define CRYPTOACC_COMMAND_CALCR2_TRUE (_CRYPTOACC_COMMAND_CALCR2_TRUE << 31) /**< Shifted mode TRUE for CRYPTOACC_COMMAND */ 565 566 /* Bit fields for CRYPTOACC PKCTRL */ 567 #define _CRYPTOACC_PKCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PKCTRL */ 568 #define _CRYPTOACC_PKCTRL_MASK 0x00000003UL /**< Mask for CRYPTOACC_PKCTRL */ 569 #define CRYPTOACC_PKCTRL_PKSTART (0x1UL << 0) /**< PK Start */ 570 #define _CRYPTOACC_PKCTRL_PKSTART_SHIFT 0 /**< Shift value for CRYPTOACC_PKSTART */ 571 #define _CRYPTOACC_PKCTRL_PKSTART_MASK 0x1UL /**< Bit mask for CRYPTOACC_PKSTART */ 572 #define _CRYPTOACC_PKCTRL_PKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKCTRL */ 573 #define CRYPTOACC_PKCTRL_PKSTART_DEFAULT (_CRYPTOACC_PKCTRL_PKSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PKCTRL */ 574 #define CRYPTOACC_PKCTRL_IFC (0x1UL << 1) /**< ClearIRQ */ 575 #define _CRYPTOACC_PKCTRL_IFC_SHIFT 1 /**< Shift value for CRYPTOACC_IFC */ 576 #define _CRYPTOACC_PKCTRL_IFC_MASK 0x2UL /**< Bit mask for CRYPTOACC_IFC */ 577 #define _CRYPTOACC_PKCTRL_IFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKCTRL */ 578 #define CRYPTOACC_PKCTRL_IFC_DEFAULT (_CRYPTOACC_PKCTRL_IFC_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_PKCTRL */ 579 580 /* Bit fields for CRYPTOACC PKSTATUS */ 581 #define _CRYPTOACC_PKSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PKSTATUS */ 582 #define _CRYPTOACC_PKSTATUS_MASK 0x00033FFFUL /**< Mask for CRYPTOACC_PKSTATUS */ 583 #define _CRYPTOACC_PKSTATUS_FAILADDR_SHIFT 0 /**< Shift value for CRYPTOACC_FAILADDR */ 584 #define _CRYPTOACC_PKSTATUS_FAILADDR_MASK 0xFUL /**< Bit mask for CRYPTOACC_FAILADDR */ 585 #define _CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 586 #define CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT (_CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 587 #define CRYPTOACC_PKSTATUS_NOTONCURVE (0x1UL << 4) /**< Point Px not on curve */ 588 #define _CRYPTOACC_PKSTATUS_NOTONCURVE_SHIFT 4 /**< Shift value for CRYPTOACC_NOTONCURVE */ 589 #define _CRYPTOACC_PKSTATUS_NOTONCURVE_MASK 0x10UL /**< Bit mask for CRYPTOACC_NOTONCURVE */ 590 #define _CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 591 #define CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT (_CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 592 #define CRYPTOACC_PKSTATUS_ATINFINITY (0x1UL << 5) /**< Point Px at infinity */ 593 #define _CRYPTOACC_PKSTATUS_ATINFINITY_SHIFT 5 /**< Shift value for CRYPTOACC_ATINFINITY */ 594 #define _CRYPTOACC_PKSTATUS_ATINFINITY_MASK 0x20UL /**< Bit mask for CRYPTOACC_ATINFINITY */ 595 #define _CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 596 #define CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT (_CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 597 #define CRYPTOACC_PKSTATUS_COUPLENOTVALID (0x1UL << 6) /**< Couple not valid */ 598 #define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_SHIFT 6 /**< Shift value for CRYPTOACC_COUPLENOTVALID */ 599 #define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_MASK 0x40UL /**< Bit mask for CRYPTOACC_COUPLENOTVALID */ 600 #define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 601 #define CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 602 #define CRYPTOACC_PKSTATUS_PARAMNNOTVALID (0x1UL << 7) /**< Param n not valid */ 603 #define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_SHIFT 7 /**< Shift value for CRYPTOACC_PARAMNNOTVALID */ 604 #define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_MASK 0x80UL /**< Bit mask for CRYPTOACC_PARAMNNOTVALID */ 605 #define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 606 #define CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 607 #define CRYPTOACC_PKSTATUS_NOTIMPLEMENTED (0x1UL << 8) /**< Not implemented */ 608 #define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_SHIFT 8 /**< Shift value for CRYPTOACC_NOTIMPLEMENTED */ 609 #define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_MASK 0x100UL /**< Bit mask for CRYPTOACC_NOTIMPLEMENTED */ 610 #define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 611 #define CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT (_CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 612 #define CRYPTOACC_PKSTATUS_SIGNOTVALID (0x1UL << 9) /**< Signature not valid */ 613 #define _CRYPTOACC_PKSTATUS_SIGNOTVALID_SHIFT 9 /**< Shift value for CRYPTOACC_SIGNOTVALID */ 614 #define _CRYPTOACC_PKSTATUS_SIGNOTVALID_MASK 0x200UL /**< Bit mask for CRYPTOACC_SIGNOTVALID */ 615 #define _CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 616 #define CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 617 #define CRYPTOACC_PKSTATUS_PARAMABNOTVALID (0x1UL << 10) /**< Param AB not valid */ 618 #define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_SHIFT 10 /**< Shift value for CRYPTOACC_PARAMABNOTVALID */ 619 #define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_MASK 0x400UL /**< Bit mask for CRYPTOACC_PARAMABNOTVALID */ 620 #define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 621 #define CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 622 #define CRYPTOACC_PKSTATUS_NOTINVERTIBLE (0x1UL << 11) /**< Not invertible */ 623 #define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_SHIFT 11 /**< Shift value for CRYPTOACC_NOTINVERTIBLE */ 624 #define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_MASK 0x800UL /**< Bit mask for CRYPTOACC_NOTINVERTIBLE */ 625 #define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 626 #define CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT (_CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 627 #define CRYPTOACC_PKSTATUS_COMPOSITE (0x1UL << 12) /**< Composite */ 628 #define _CRYPTOACC_PKSTATUS_COMPOSITE_SHIFT 12 /**< Shift value for CRYPTOACC_COMPOSITE */ 629 #define _CRYPTOACC_PKSTATUS_COMPOSITE_MASK 0x1000UL /**< Bit mask for CRYPTOACC_COMPOSITE */ 630 #define _CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 631 #define _CRYPTOACC_PKSTATUS_COMPOSITE_FALSE 0x00000000UL /**< Mode FALSE for CRYPTOACC_PKSTATUS */ 632 #define _CRYPTOACC_PKSTATUS_COMPOSITE_TRUE 0x00000001UL /**< Mode TRUE for CRYPTOACC_PKSTATUS */ 633 #define CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT (_CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 634 #define CRYPTOACC_PKSTATUS_COMPOSITE_FALSE (_CRYPTOACC_PKSTATUS_COMPOSITE_FALSE << 12) /**< Shifted mode FALSE for CRYPTOACC_PKSTATUS */ 635 #define CRYPTOACC_PKSTATUS_COMPOSITE_TRUE (_CRYPTOACC_PKSTATUS_COMPOSITE_TRUE << 12) /**< Shifted mode TRUE for CRYPTOACC_PKSTATUS */ 636 #define CRYPTOACC_PKSTATUS_NOTQUAD (0x1UL << 13) /**< Not quadratic residue */ 637 #define _CRYPTOACC_PKSTATUS_NOTQUAD_SHIFT 13 /**< Shift value for CRYPTOACC_NOTQUAD */ 638 #define _CRYPTOACC_PKSTATUS_NOTQUAD_MASK 0x2000UL /**< Bit mask for CRYPTOACC_NOTQUAD */ 639 #define _CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 640 #define CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT (_CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 641 #define CRYPTOACC_PKSTATUS_PKBUSY (0x1UL << 16) /**< PK busy */ 642 #define _CRYPTOACC_PKSTATUS_PKBUSY_SHIFT 16 /**< Shift value for CRYPTOACC_PKBUSY */ 643 #define _CRYPTOACC_PKSTATUS_PKBUSY_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PKBUSY */ 644 #define _CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 645 #define CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT (_CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 646 #define CRYPTOACC_PKSTATUS_PKIF (0x1UL << 17) /**< Interrupt status */ 647 #define _CRYPTOACC_PKSTATUS_PKIF_SHIFT 17 /**< Shift value for CRYPTOACC_PKIF */ 648 #define _CRYPTOACC_PKSTATUS_PKIF_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PKIF */ 649 #define _CRYPTOACC_PKSTATUS_PKIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ 650 #define CRYPTOACC_PKSTATUS_PKIF_DEFAULT (_CRYPTOACC_PKSTATUS_PKIF_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ 651 652 /* Bit fields for CRYPTOACC VERSION */ 653 #define _CRYPTOACC_VERSION_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_VERSION */ 654 #define _CRYPTOACC_VERSION_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_VERSION */ 655 #define _CRYPTOACC_VERSION_SW_SHIFT 0 /**< Shift value for CRYPTOACC_SW */ 656 #define _CRYPTOACC_VERSION_SW_MASK 0xFFUL /**< Bit mask for CRYPTOACC_SW */ 657 #define _CRYPTOACC_VERSION_SW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_VERSION */ 658 #define CRYPTOACC_VERSION_SW_DEFAULT (_CRYPTOACC_VERSION_SW_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_VERSION */ 659 #define _CRYPTOACC_VERSION_HW_SHIFT 8 /**< Shift value for CRYPTOACC_HW */ 660 #define _CRYPTOACC_VERSION_HW_MASK 0xFF00UL /**< Bit mask for CRYPTOACC_HW */ 661 #define _CRYPTOACC_VERSION_HW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_VERSION */ 662 #define CRYPTOACC_VERSION_HW_DEFAULT (_CRYPTOACC_VERSION_HW_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_VERSION */ 663 664 /* Bit fields for CRYPTOACC TIMER */ 665 #define _CRYPTOACC_TIMER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_TIMER */ 666 #define _CRYPTOACC_TIMER_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_TIMER */ 667 #define _CRYPTOACC_TIMER_TIMER_SHIFT 0 /**< Shift value for CRYPTOACC_TIMER */ 668 #define _CRYPTOACC_TIMER_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TIMER */ 669 #define _CRYPTOACC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_TIMER */ 670 #define CRYPTOACC_TIMER_TIMER_DEFAULT (_CRYPTOACC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_TIMER */ 671 672 /** @} End of group EFR32BG22_CRYPTOACC_PKCTRL_BitFields */ 673 /** @} End of group EFR32BG22_CRYPTOACC_PKCTRL */ 674 /**************************************************************************//** 675 * @defgroup EFR32BG22_CRYPTOACC_RNGCTRL CRYPTOACC_RNGCTRL 676 * @{ 677 * @brief EFR32BG22 CRYPTOACC_RNGCTRL Register Declaration. 678 *****************************************************************************/ 679 680 /** CRYPTOACC_RNGCTRL KEYS Register Group Declaration. */ 681 typedef struct { 682 __IOM uint32_t KEY; /**< Key Register */ 683 } CRYPTOACC_KEYS_TypeDef; 684 685 /** CRYPTOACC_RNGCTRL Register Declaration. */ 686 typedef struct { 687 __IOM uint32_t RNGCTRL; /**< RNG Control Register */ 688 __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ 689 __IM uint32_t FIFOTHRESH; /**< FIFO Threshold Register */ 690 __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ 691 CRYPTOACC_KEYS_TypeDef KEYS[4U]; /**< */ 692 __IOM uint32_t TESTDATA; /**< Test Data Register */ 693 uint32_t RESERVED0[3U]; /**< Reserved for future use */ 694 __IOM uint32_t RNGSTATUS; /**< RNG Status Register */ 695 __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ 696 uint32_t RESERVED1[2U]; /**< Reserved for future use */ 697 __IOM uint32_t SWOFFTMRVAL; /**< Switch off timer value */ 698 __IOM uint32_t CLKDIV; /**< Sample clock divider */ 699 __IOM uint32_t AIS31CONF0; /**< AIS31 configuration 0 register */ 700 __IOM uint32_t AIS31CONF1; /**< AIS31 configuration 1 register */ 701 __IOM uint32_t AIS31CONF2; /**< AIS31 configuration 2 register */ 702 __IOM uint32_t AIS31STATUS; /**< AIS31 status register */ 703 } CRYPTOACC_RNGCTRL_TypeDef; 704 /** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL */ 705 706 /**************************************************************************//** 707 * @addtogroup EFR32BG22_CRYPTOACC_RNGCTRL 708 * @{ 709 * @defgroup EFR32BG22_CRYPTOACC_RNGCTRL_BitFields CRYPTOACC_RNGCTRL Bit Fields 710 * @{ 711 *****************************************************************************/ 712 713 /* Bit fields for CRYPTOACC RNGCTRL */ 714 #define _CRYPTOACC_RNGCTRL_RESETVALUE 0x00040000UL /**< Default value for CRYPTOACC_RNGCTRL */ 715 #define _CRYPTOACC_RNGCTRL_MASK 0x001FFFFFUL /**< Mask for CRYPTOACC_RNGCTRL */ 716 #define CRYPTOACC_RNGCTRL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ 717 #define _CRYPTOACC_RNGCTRL_ENABLE_SHIFT 0 /**< Shift value for CRYPTOACC_ENABLE */ 718 #define _CRYPTOACC_RNGCTRL_ENABLE_MASK 0x1UL /**< Bit mask for CRYPTOACC_ENABLE */ 719 #define _CRYPTOACC_RNGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 720 #define _CRYPTOACC_RNGCTRL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for CRYPTOACC_RNGCTRL */ 721 #define _CRYPTOACC_RNGCTRL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for CRYPTOACC_RNGCTRL */ 722 #define CRYPTOACC_RNGCTRL_ENABLE_DEFAULT (_CRYPTOACC_RNGCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 723 #define CRYPTOACC_RNGCTRL_ENABLE_DISABLED (_CRYPTOACC_RNGCTRL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for CRYPTOACC_RNGCTRL */ 724 #define CRYPTOACC_RNGCTRL_ENABLE_ENABLED (_CRYPTOACC_RNGCTRL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for CRYPTOACC_RNGCTRL */ 725 #define CRYPTOACC_RNGCTRL_TESTEN (0x1UL << 2) /**< Test Enable */ 726 #define _CRYPTOACC_RNGCTRL_TESTEN_SHIFT 2 /**< Shift value for CRYPTOACC_TESTEN */ 727 #define _CRYPTOACC_RNGCTRL_TESTEN_MASK 0x4UL /**< Bit mask for CRYPTOACC_TESTEN */ 728 #define _CRYPTOACC_RNGCTRL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 729 #define _CRYPTOACC_RNGCTRL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for CRYPTOACC_RNGCTRL */ 730 #define _CRYPTOACC_RNGCTRL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for CRYPTOACC_RNGCTRL */ 731 #define CRYPTOACC_RNGCTRL_TESTEN_DEFAULT (_CRYPTOACC_RNGCTRL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 732 #define CRYPTOACC_RNGCTRL_TESTEN_NOISE (_CRYPTOACC_RNGCTRL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for CRYPTOACC_RNGCTRL */ 733 #define CRYPTOACC_RNGCTRL_TESTEN_TESTDATA (_CRYPTOACC_RNGCTRL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for CRYPTOACC_RNGCTRL */ 734 #define CRYPTOACC_RNGCTRL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ 735 #define _CRYPTOACC_RNGCTRL_CONDBYPASS_SHIFT 3 /**< Shift value for CRYPTOACC_CONDBYPASS */ 736 #define _CRYPTOACC_RNGCTRL_CONDBYPASS_MASK 0x8UL /**< Bit mask for CRYPTOACC_CONDBYPASS */ 737 #define _CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 738 #define _CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ 739 #define _CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ 740 #define CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT (_CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 741 #define CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL (_CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ 742 #define CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS (_CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ 743 #define CRYPTOACC_RNGCTRL_REPCOUNTIEN (0x1UL << 4) /**< IRQ enable for Repetition Count Test */ 744 #define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_SHIFT 4 /**< Shift value for CRYPTOACC_REPCOUNTIEN */ 745 #define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPCOUNTIEN */ 746 #define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 747 #define CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT (_CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 748 #define CRYPTOACC_RNGCTRL_APT64IEN (0x1UL << 5) /**< IRQ enable for APT64IF */ 749 #define _CRYPTOACC_RNGCTRL_APT64IEN_SHIFT 5 /**< Shift value for CRYPTOACC_APT64IEN */ 750 #define _CRYPTOACC_RNGCTRL_APT64IEN_MASK 0x20UL /**< Bit mask for CRYPTOACC_APT64IEN */ 751 #define _CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 752 #define CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT (_CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 753 #define CRYPTOACC_RNGCTRL_APT4096IEN (0x1UL << 6) /**< IRQ enable for APT4096IF */ 754 #define _CRYPTOACC_RNGCTRL_APT4096IEN_SHIFT 6 /**< Shift value for CRYPTOACC_APT4096IEN */ 755 #define _CRYPTOACC_RNGCTRL_APT4096IEN_MASK 0x40UL /**< Bit mask for CRYPTOACC_APT4096IEN */ 756 #define _CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 757 #define CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT (_CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 758 #define CRYPTOACC_RNGCTRL_FULLIEN (0x1UL << 7) /**< IRQ enable for FIFO full */ 759 #define _CRYPTOACC_RNGCTRL_FULLIEN_SHIFT 7 /**< Shift value for CRYPTOACC_FULLIEN */ 760 #define _CRYPTOACC_RNGCTRL_FULLIEN_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLIEN */ 761 #define _CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 762 #define CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT (_CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 763 #define CRYPTOACC_RNGCTRL_SOFTRESET (0x1UL << 8) /**< Software Reset */ 764 #define _CRYPTOACC_RNGCTRL_SOFTRESET_SHIFT 8 /**< Shift value for CRYPTOACC_SOFTRESET */ 765 #define _CRYPTOACC_RNGCTRL_SOFTRESET_MASK 0x100UL /**< Bit mask for CRYPTOACC_SOFTRESET */ 766 #define _CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 767 #define _CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ 768 #define _CRYPTOACC_RNGCTRL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for CRYPTOACC_RNGCTRL */ 769 #define CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT (_CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 770 #define CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL (_CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ 771 #define CRYPTOACC_RNGCTRL_SOFTRESET_RESET (_CRYPTOACC_RNGCTRL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for CRYPTOACC_RNGCTRL */ 772 #define CRYPTOACC_RNGCTRL_PREIEN (0x1UL << 9) /**< IRQ enable for AIS31 prelim. noise alarm */ 773 #define _CRYPTOACC_RNGCTRL_PREIEN_SHIFT 9 /**< Shift value for CRYPTOACC_PREIEN */ 774 #define _CRYPTOACC_RNGCTRL_PREIEN_MASK 0x200UL /**< Bit mask for CRYPTOACC_PREIEN */ 775 #define _CRYPTOACC_RNGCTRL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 776 #define CRYPTOACC_RNGCTRL_PREIEN_DEFAULT (_CRYPTOACC_RNGCTRL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 777 #define CRYPTOACC_RNGCTRL_ALMIEN (0x1UL << 10) /**< IRQ enable for AIS31 noise alarm */ 778 #define _CRYPTOACC_RNGCTRL_ALMIEN_SHIFT 10 /**< Shift value for CRYPTOACC_ALMIEN */ 779 #define _CRYPTOACC_RNGCTRL_ALMIEN_MASK 0x400UL /**< Bit mask for CRYPTOACC_ALMIEN */ 780 #define _CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 781 #define CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT (_CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 782 #define CRYPTOACC_RNGCTRL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ 783 #define _CRYPTOACC_RNGCTRL_FORCERUN_SHIFT 11 /**< Shift value for CRYPTOACC_FORCERUN */ 784 #define _CRYPTOACC_RNGCTRL_FORCERUN_MASK 0x800UL /**< Bit mask for CRYPTOACC_FORCERUN */ 785 #define _CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 786 #define _CRYPTOACC_RNGCTRL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ 787 #define _CRYPTOACC_RNGCTRL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for CRYPTOACC_RNGCTRL */ 788 #define CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT (_CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 789 #define CRYPTOACC_RNGCTRL_FORCERUN_NORMAL (_CRYPTOACC_RNGCTRL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ 790 #define CRYPTOACC_RNGCTRL_FORCERUN_RUN (_CRYPTOACC_RNGCTRL_FORCERUN_RUN << 11) /**< Shifted mode RUN for CRYPTOACC_RNGCTRL */ 791 #define CRYPTOACC_RNGCTRL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ 792 #define _CRYPTOACC_RNGCTRL_BYPNIST_SHIFT 12 /**< Shift value for CRYPTOACC_BYPNIST */ 793 #define _CRYPTOACC_RNGCTRL_BYPNIST_MASK 0x1000UL /**< Bit mask for CRYPTOACC_BYPNIST */ 794 #define _CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 795 #define _CRYPTOACC_RNGCTRL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ 796 #define _CRYPTOACC_RNGCTRL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ 797 #define CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT (_CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 798 #define CRYPTOACC_RNGCTRL_BYPNIST_NORMAL (_CRYPTOACC_RNGCTRL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ 799 #define CRYPTOACC_RNGCTRL_BYPNIST_BYPASS (_CRYPTOACC_RNGCTRL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ 800 #define CRYPTOACC_RNGCTRL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ 801 #define _CRYPTOACC_RNGCTRL_BYPAIS31_SHIFT 13 /**< Shift value for CRYPTOACC_BYPAIS31 */ 802 #define _CRYPTOACC_RNGCTRL_BYPAIS31_MASK 0x2000UL /**< Bit mask for CRYPTOACC_BYPAIS31 */ 803 #define _CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 804 #define _CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ 805 #define _CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ 806 #define CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT (_CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 807 #define CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL (_CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ 808 #define CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS (_CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ 809 #define CRYPTOACC_RNGCTRL_HEALTHTESTSEL (0x1UL << 14) /**< Health test input select */ 810 #define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_SHIFT 14 /**< Shift value for CRYPTOACC_HEALTHTESTSEL */ 811 #define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_MASK 0x4000UL /**< Bit mask for CRYPTOACC_HEALTHTESTSEL */ 812 #define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 813 #define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE 0x00000000UL /**< Mode BEFORE for CRYPTOACC_RNGCTRL */ 814 #define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER 0x00000001UL /**< Mode AFTER for CRYPTOACC_RNGCTRL */ 815 #define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 816 #define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE << 14) /**< Shifted mode BEFORE for CRYPTOACC_RNGCTRL */ 817 #define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER << 14) /**< Shifted mode AFTER for CRYPTOACC_RNGCTRL */ 818 #define CRYPTOACC_RNGCTRL_AIS31TESTSEL (0x1UL << 15) /**< AIS31 test input select */ 819 #define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_SHIFT 15 /**< Shift value for CRYPTOACC_AIS31TESTSEL */ 820 #define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_MASK 0x8000UL /**< Bit mask for CRYPTOACC_AIS31TESTSEL */ 821 #define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 822 #define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE 0x00000000UL /**< Mode BEFORE for CRYPTOACC_RNGCTRL */ 823 #define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER 0x00000001UL /**< Mode AFTER for CRYPTOACC_RNGCTRL */ 824 #define CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 825 #define CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE << 15) /**< Shifted mode BEFORE for CRYPTOACC_RNGCTRL */ 826 #define CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER << 15) /**< Shifted mode AFTER for CRYPTOACC_RNGCTRL */ 827 #define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_SHIFT 16 /**< Shift value for CRYPTOACC_NB128BITBLOCKS */ 828 #define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_NB128BITBLOCKS */ 829 #define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT 0x00000004UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 830 #define CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT (_CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 831 #define CRYPTOACC_RNGCTRL_FIFOWRSTARTUP (0x1UL << 20) /**< Fifo Write Start Up */ 832 #define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_SHIFT 20 /**< Shift value for CRYPTOACC_FIFOWRSTARTUP */ 833 #define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_MASK 0x100000UL /**< Bit mask for CRYPTOACC_FIFOWRSTARTUP */ 834 #define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ 835 #define CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT (_CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ 836 837 /* Bit fields for CRYPTOACC FIFOLEVEL */ 838 #define _CRYPTOACC_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FIFOLEVEL */ 839 #define _CRYPTOACC_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFOLEVEL */ 840 #define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOLEVEL */ 841 #define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOLEVEL */ 842 #define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FIFOLEVEL */ 843 #define CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT (_CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFOLEVEL*/ 844 845 /* Bit fields for CRYPTOACC FIFOTHRESH */ 846 #define _CRYPTOACC_FIFOTHRESH_RESETVALUE 0x0000003FUL /**< Default value for CRYPTOACC_FIFOTHRESH */ 847 #define _CRYPTOACC_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFOTHRESH */ 848 #define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOTHRESH */ 849 #define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOTHRESH */ 850 #define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT 0x0000003FUL /**< Mode DEFAULT for CRYPTOACC_FIFOTHRESH */ 851 #define CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT (_CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFOTHRESH*/ 852 853 /* Bit fields for CRYPTOACC FIFODEPTH */ 854 #define _CRYPTOACC_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for CRYPTOACC_FIFODEPTH */ 855 #define _CRYPTOACC_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFODEPTH */ 856 #define _CRYPTOACC_FIFODEPTH_FIFODEPTH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFODEPTH */ 857 #define _CRYPTOACC_FIFODEPTH_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFODEPTH */ 858 #define _CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT 0x00000040UL /**< Mode DEFAULT for CRYPTOACC_FIFODEPTH */ 859 #define CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT (_CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFODEPTH*/ 860 861 /* Bit fields for CRYPTOACC KEY */ 862 #define _CRYPTOACC_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_KEY */ 863 #define _CRYPTOACC_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_KEY */ 864 #define _CRYPTOACC_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTOACC_KEY */ 865 #define _CRYPTOACC_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY */ 866 #define _CRYPTOACC_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_KEY */ 867 #define CRYPTOACC_KEY_KEY_DEFAULT (_CRYPTOACC_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_KEY */ 868 869 /* Bit fields for CRYPTOACC TESTDATA */ 870 #define _CRYPTOACC_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_TESTDATA */ 871 #define _CRYPTOACC_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_TESTDATA */ 872 #define _CRYPTOACC_TESTDATA_VALUE_SHIFT 0 /**< Shift value for CRYPTOACC_VALUE */ 873 #define _CRYPTOACC_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_VALUE */ 874 #define _CRYPTOACC_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_TESTDATA */ 875 #define CRYPTOACC_TESTDATA_VALUE_DEFAULT (_CRYPTOACC_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_TESTDATA */ 876 877 /* Bit fields for CRYPTOACC RNGSTATUS */ 878 #define _CRYPTOACC_RNGSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_RNGSTATUS */ 879 #define _CRYPTOACC_RNGSTATUS_MASK 0x000007FFUL /**< Mask for CRYPTOACC_RNGSTATUS */ 880 #define CRYPTOACC_RNGSTATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ 881 #define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for CRYPTOACC_TESTDATABUSY */ 882 #define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_TESTDATABUSY */ 883 #define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 884 #define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for CRYPTOACC_RNGSTATUS */ 885 #define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for CRYPTOACC_RNGSTATUS */ 886 #define CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 887 #define CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for CRYPTOACC_RNGSTATUS */ 888 #define CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for CRYPTOACC_RNGSTATUS */ 889 #define _CRYPTOACC_RNGSTATUS_STATE_SHIFT 1 /**< Shift value for CRYPTOACC_STATE */ 890 #define _CRYPTOACC_RNGSTATUS_STATE_MASK 0xEUL /**< Bit mask for CRYPTOACC_STATE */ 891 #define _CRYPTOACC_RNGSTATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 892 #define _CRYPTOACC_RNGSTATUS_STATE_RESET 0x00000000UL /**< Mode RESET for CRYPTOACC_RNGSTATUS */ 893 #define _CRYPTOACC_RNGSTATUS_STATE_STARTUP 0x00000001UL /**< Mode STARTUP for CRYPTOACC_RNGSTATUS */ 894 #define _CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON 0x00000002UL /**< Mode FIFOFULLON for CRYPTOACC_RNGSTATUS */ 895 #define _CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF 0x00000003UL /**< Mode FIFOFULLOFF for CRYPTOACC_RNGSTATUS */ 896 #define _CRYPTOACC_RNGSTATUS_STATE_RUNNING 0x00000004UL /**< Mode RUNNING for CRYPTOACC_RNGSTATUS */ 897 #define _CRYPTOACC_RNGSTATUS_STATE_ERROR 0x00000005UL /**< Mode ERROR for CRYPTOACC_RNGSTATUS */ 898 #define _CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 0x00000006UL /**< Mode UNUSED_6 for CRYPTOACC_RNGSTATUS */ 899 #define _CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 0x00000007UL /**< Mode UNUSED_7 for CRYPTOACC_RNGSTATUS */ 900 #define CRYPTOACC_RNGSTATUS_STATE_DEFAULT (_CRYPTOACC_RNGSTATUS_STATE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 901 #define CRYPTOACC_RNGSTATUS_STATE_RESET (_CRYPTOACC_RNGSTATUS_STATE_RESET << 1) /**< Shifted mode RESET for CRYPTOACC_RNGSTATUS */ 902 #define CRYPTOACC_RNGSTATUS_STATE_STARTUP (_CRYPTOACC_RNGSTATUS_STATE_STARTUP << 1) /**< Shifted mode STARTUP for CRYPTOACC_RNGSTATUS*/ 903 #define CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON (_CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON << 1) /**< Shifted mode FIFOFULLON for CRYPTOACC_RNGSTATUS*/ 904 #define CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF (_CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF << 1) /**< Shifted mode FIFOFULLOFF for CRYPTOACC_RNGSTATUS*/ 905 #define CRYPTOACC_RNGSTATUS_STATE_RUNNING (_CRYPTOACC_RNGSTATUS_STATE_RUNNING << 1) /**< Shifted mode RUNNING for CRYPTOACC_RNGSTATUS*/ 906 #define CRYPTOACC_RNGSTATUS_STATE_ERROR (_CRYPTOACC_RNGSTATUS_STATE_ERROR << 1) /**< Shifted mode ERROR for CRYPTOACC_RNGSTATUS */ 907 #define CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 (_CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 << 1) /**< Shifted mode UNUSED_6 for CRYPTOACC_RNGSTATUS*/ 908 #define CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 (_CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 << 1) /**< Shifted mode UNUSED_7 for CRYPTOACC_RNGSTATUS*/ 909 #define CRYPTOACC_RNGSTATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ 910 #define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for CRYPTOACC_REPCOUNTIF */ 911 #define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPCOUNTIF */ 912 #define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 913 #define CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT (_CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 914 #define CRYPTOACC_RNGSTATUS_APT64IF (0x1UL << 5) /**< 64-sample window Adaptive Proportion IF */ 915 #define _CRYPTOACC_RNGSTATUS_APT64IF_SHIFT 5 /**< Shift value for CRYPTOACC_APT64IF */ 916 #define _CRYPTOACC_RNGSTATUS_APT64IF_MASK 0x20UL /**< Bit mask for CRYPTOACC_APT64IF */ 917 #define _CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 918 #define CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT (_CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 919 #define CRYPTOACC_RNGSTATUS_APT4096IF (0x1UL << 6) /**< 4096-sample window Adaptive Prop. IF */ 920 #define _CRYPTOACC_RNGSTATUS_APT4096IF_SHIFT 6 /**< Shift value for CRYPTOACC_APT4096IF */ 921 #define _CRYPTOACC_RNGSTATUS_APT4096IF_MASK 0x40UL /**< Bit mask for CRYPTOACC_APT4096IF */ 922 #define _CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 923 #define CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT (_CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 924 #define CRYPTOACC_RNGSTATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ 925 #define _CRYPTOACC_RNGSTATUS_FULLIF_SHIFT 7 /**< Shift value for CRYPTOACC_FULLIF */ 926 #define _CRYPTOACC_RNGSTATUS_FULLIF_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLIF */ 927 #define _CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 928 #define CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT (_CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 929 #define CRYPTOACC_RNGSTATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm IF */ 930 #define _CRYPTOACC_RNGSTATUS_PREIF_SHIFT 8 /**< Shift value for CRYPTOACC_PREIF */ 931 #define _CRYPTOACC_RNGSTATUS_PREIF_MASK 0x100UL /**< Bit mask for CRYPTOACC_PREIF */ 932 #define _CRYPTOACC_RNGSTATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 933 #define CRYPTOACC_RNGSTATUS_PREIF_DEFAULT (_CRYPTOACC_RNGSTATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 934 #define CRYPTOACC_RNGSTATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ 935 #define _CRYPTOACC_RNGSTATUS_ALMIF_SHIFT 9 /**< Shift value for CRYPTOACC_ALMIF */ 936 #define _CRYPTOACC_RNGSTATUS_ALMIF_MASK 0x200UL /**< Bit mask for CRYPTOACC_ALMIF */ 937 #define _CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ 938 #define CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT (_CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ 939 940 /* Bit fields for CRYPTOACC INITWAITVAL */ 941 #define _CRYPTOACC_INITWAITVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_INITWAITVAL */ 942 #define _CRYPTOACC_INITWAITVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_INITWAITVAL */ 943 #define _CRYPTOACC_INITWAITVAL_INITWAITVAL_SHIFT 0 /**< Shift value for CRYPTOACC_INITWAITVAL */ 944 #define _CRYPTOACC_INITWAITVAL_INITWAITVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_INITWAITVAL */ 945 #define _CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_INITWAITVAL */ 946 #define CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT (_CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INITWAITVAL*/ 947 948 /* Bit fields for CRYPTOACC SWOFFTMRVAL */ 949 #define _CRYPTOACC_SWOFFTMRVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_SWOFFTMRVAL */ 950 #define _CRYPTOACC_SWOFFTMRVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_SWOFFTMRVAL */ 951 #define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_SHIFT 0 /**< Shift value for CRYPTOACC_SWOFFTMRVAL */ 952 #define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_SWOFFTMRVAL */ 953 #define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_SWOFFTMRVAL */ 954 #define CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT (_CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_SWOFFTMRVAL*/ 955 956 /* Bit fields for CRYPTOACC CLKDIV */ 957 #define _CRYPTOACC_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CLKDIV */ 958 #define _CRYPTOACC_CLKDIV_MASK 0x000000FFUL /**< Mask for CRYPTOACC_CLKDIV */ 959 #define _CRYPTOACC_CLKDIV_VALUE_SHIFT 0 /**< Shift value for CRYPTOACC_VALUE */ 960 #define _CRYPTOACC_CLKDIV_VALUE_MASK 0xFFUL /**< Bit mask for CRYPTOACC_VALUE */ 961 #define _CRYPTOACC_CLKDIV_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CLKDIV */ 962 #define CRYPTOACC_CLKDIV_VALUE_DEFAULT (_CRYPTOACC_CLKDIV_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CLKDIV */ 963 964 /* Bit fields for CRYPTOACC AIS31CONF0 */ 965 #define _CRYPTOACC_AIS31CONF0_RESETVALUE 0x43401040UL /**< Default value for CRYPTOACC_AIS31CONF0 */ 966 #define _CRYPTOACC_AIS31CONF0_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF0 */ 967 #define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_SHIFT 0 /**< Shift value for CRYPTOACC_STARTUPTHRES */ 968 #define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_STARTUPTHRES */ 969 #define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT 0x00001040UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF0 */ 970 #define CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT (_CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF0*/ 971 #define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINETHRESH */ 972 #define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINETHRESH */ 973 #define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT 0x00004340UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF0 */ 974 #define CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT (_CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF0*/ 975 976 /* Bit fields for CRYPTOACC AIS31CONF1 */ 977 #define _CRYPTOACC_AIS31CONF1_RESETVALUE 0x03C00680UL /**< Default value for CRYPTOACC_AIS31CONF1 */ 978 #define _CRYPTOACC_AIS31CONF1_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF1 */ 979 #define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_SHIFT 0 /**< Shift value for CRYPTOACC_HEXPECTEDVALUE */ 980 #define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HEXPECTEDVALUE */ 981 #define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT 0x00000680UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF1 */ 982 #define CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT (_CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF1*/ 983 #define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINEREPTHRESH */ 984 #define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINEREPTHRESH */ 985 #define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT 0x000003C0UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF1 */ 986 #define CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT (_CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF1*/ 987 988 /* Bit fields for CRYPTOACC AIS31CONF2 */ 989 #define _CRYPTOACC_AIS31CONF2_RESETVALUE 0x04400340UL /**< Default value for CRYPTOACC_AIS31CONF2 */ 990 #define _CRYPTOACC_AIS31CONF2_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF2 */ 991 #define _CRYPTOACC_AIS31CONF2_HMIN_SHIFT 0 /**< Shift value for CRYPTOACC_HMIN */ 992 #define _CRYPTOACC_AIS31CONF2_HMIN_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HMIN */ 993 #define _CRYPTOACC_AIS31CONF2_HMIN_DEFAULT 0x00000340UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF2 */ 994 #define CRYPTOACC_AIS31CONF2_HMIN_DEFAULT (_CRYPTOACC_AIS31CONF2_HMIN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF2*/ 995 #define _CRYPTOACC_AIS31CONF2_HMAX_SHIFT 16 /**< Shift value for CRYPTOACC_HMAX */ 996 #define _CRYPTOACC_AIS31CONF2_HMAX_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_HMAX */ 997 #define _CRYPTOACC_AIS31CONF2_HMAX_DEFAULT 0x00000440UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF2 */ 998 #define CRYPTOACC_AIS31CONF2_HMAX_DEFAULT (_CRYPTOACC_AIS31CONF2_HMAX_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF2*/ 999 1000 /* Bit fields for CRYPTOACC AIS31STATUS */ 1001 #define _CRYPTOACC_AIS31STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_AIS31STATUS */ 1002 #define _CRYPTOACC_AIS31STATUS_MASK 0x0003FFFFUL /**< Mask for CRYPTOACC_AIS31STATUS */ 1003 #define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_SHIFT 0 /**< Shift value for CRYPTOACC_NUMPRELIMALARMS */ 1004 #define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_NUMPRELIMALARMS */ 1005 #define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ 1006 #define CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT (_CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ 1007 #define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG (0x1UL << 16) /**< Preliminary noise alarm RNG */ 1008 #define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_SHIFT 16 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMRNG*/ 1009 #define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMRNG */ 1010 #define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ 1011 #define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT (_CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ 1012 #define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP (0x1UL << 17) /**< Preliminary noise alarm Rep */ 1013 #define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_SHIFT 17 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMREP*/ 1014 #define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMREP */ 1015 #define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ 1016 #define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT (_CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ 1017 1018 /** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL_BitFields */ 1019 /** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL */ 1020 /** @} End of group Parts */ 1021 1022 #endif /* EFR32BG22_CRYPTOACC_H */ 1023
