1 /**************************************************************************//** 2 * @file crypto_reg.h 3 * @version V1.00 4 * @brief CRYPTO register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRYPTO_REG_H__ 10 #define __CRYPTO_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CRPT Cryptographic Accelerator(CRPT) 23 Memory Mapped Structure for Cryptographic Accelerator 24 @{ */ 25 26 typedef struct 27 { 28 29 /** 30 * @var CRPT_T::INTEN 31 * Offset: 0x00 Crypto Interrupt Enable Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |AESIEN |AES Interrupt Enable Control 36 * | | |0 = AES interrupt Disabled. 37 * | | |1 = AES interrupt Enabled. 38 * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. 39 * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. 40 * |[1] |AESEIEN |AES Error Flag Enable Control 41 * | | |0 = AES error interrupt flag Disabled. 42 * | | |1 = AES error interrupt flag Enabled. 43 * |[8] |TDESIEN |TDES/DES Interrupt Enable Control 44 * | | |0 = TDES/DES interrupt Disabled. 45 * | | |1 = TDES/DES interrupt Enabled. 46 * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. 47 * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. 48 * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control 49 * | | |0 = TDES/DES error interrupt flag Disabled. 50 * | | |1 = TDES/DES error interrupt flag Enabled. 51 * |[16] |PRNGIEN |PRNG Interrupt Enable Control 52 * | | |0 = PRNG interrupt Disabled. 53 * | | |1 = PRNG interrupt Enabled. 54 * |[22] |ECCIEN |ECC Interrupt Enable Control 55 * | | |0 = ECC interrupt Disabled. 56 * | | |1 = ECC interrupt Enabled. 57 * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. 58 * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. 59 * |[23] |ECCEIEN |ECC Error Interrupt Enable Control 60 * | | |0 = ECC error interrupt flag Disabled. 61 * | | |1 = ECC error interrupt flag Enabled. 62 * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control 63 * | | |0 = SHA/HMAC interrupt Disabled. 64 * | | |1 = SHA/HMAC interrupt Enabled. 65 * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine 66 * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. 67 * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control 68 * | | |0 = SHA/HMAC error interrupt flag Disabled. 69 * | | |1 = SHA/HMAC error interrupt flag Enabled. 70 * @var CRPT_T::INTSTS 71 * Offset: 0x04 Crypto Interrupt Flag 72 * --------------------------------------------------------------------------------------------------- 73 * |Bits |Field |Descriptions 74 * | :----: | :----: | :---- | 75 * |[0] |AESIF |AES Finish Interrupt Flag 76 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 77 * | | |0 = No AES interrupt. 78 * | | |= AES encryption/decryption done interrupt. 79 * |[1] |AESEIF |AES Error Flag 80 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 81 * | | |0 = No AES error. 82 * | | |1 = AES encryption/decryption done interrupt. 83 * |[8] |TDESIF |TDES/DES Finish Interrupt Flag 84 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 85 * | | |0 = No TDES/DES interrupt. 86 * | | |1 = TDES/DES encryption/decryption done interrupt. 87 * |[9] |TDESEIF |TDES/DES Error Flag 88 * | | |This bit includes the operating and setting error 89 * | | |The detailed flag is shown in the CRPT_TDES_STS register 90 * | | |This includes operating and setting error. 91 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 92 * | | |0 = No TDES/DES error. 93 * | | |1 = TDES/DES encryption/decryption error interrupt. 94 * |[16] |PRNGIF |PRNG Finish Interrupt Flag 95 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 96 * | | |0 = No PRNG interrupt. 97 * | | |1 = PRNG key generation done interrupt. 98 * |[22] |ECCIF |ECC Finish Interrupt Flag 99 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 100 * | | |0 = No ECC interrupt. 101 * | | |1 = ECC operation done interrupt. 102 * |[23] |ECCEIF |ECC Error Flag 103 * | | |This register includes operating and setting error. The detail flag is shown in CRPT_ECC_STS register. 104 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 105 * | | |0 = No ECC error. 106 * | | |1 = ECC error interrupt. 107 * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag 108 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 109 * | | |0 = No SHA/HMAC interrupt. 110 * | | |1 = SHA/HMAC operation done interrupt. 111 * |[25] |HMACEIF |SHA/HMAC Error Flag 112 * | | |This register includes operating and setting error. The detail flag is shown in CRPT_HMAC_STS register. 113 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 114 * | | |0 = No SHA/HMAC error. 115 * | | |1 = SHA/HMAC error interrupt. 116 * @var CRPT_T::PRNG_CTL 117 * Offset: 0x08 PRNG Control Register 118 * --------------------------------------------------------------------------------------------------- 119 * |Bits |Field |Descriptions 120 * | :----: | :----: | :---- | 121 * |[0] |START |Start PRNG Engine 122 * | | |0 = Stop PRNG engine. 123 * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated. 124 * |[1] |SEEDRLD |Reload New Seed for PRNG Engine 125 * | | |0 = Generating key based on the current seed. 126 * | | |1 = Reload new seed. 127 * |[3:2] |KEYSZ |PRNG Generate Key Size 128 * | | |00 = 64 bits. 129 * | | |01 = 128 bits. 130 * | | |10 = 192 bits. 131 * | | |11 = 256 bits. 132 * |[8] |BUSY |PRNG Busy (Read Only) 133 * | | |0 = PRNG engine is idle. 134 * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. 135 * @var CRPT_T::PRNG_SEED 136 * Offset: 0x0C Seed for PRNG 137 * --------------------------------------------------------------------------------------------------- 138 * |Bits |Field |Descriptions 139 * | :----: | :----: | :---- | 140 * |[31:0] |SEED |Seed for PRNG (Write Only) 141 * | | |The bits store the seed for PRNG engine. 142 * @var CRPT_T::PRNG_KEY[8] 143 * Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7 144 * --------------------------------------------------------------------------------------------------- 145 * |Bits |Field |Descriptions 146 * | :----: | :----: | :---- | 147 * |[31:0] |KEY |Store PRNG Generated Key (Read Only) 148 * | | |The bits store the key that is generated by PRNG. 149 * @var CRPT_T::AES_FDBCK[4] 150 * Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data after Cryptographic Operation 151 * --------------------------------------------------------------------------------------------------- 152 * |Bits |Field |Descriptions 153 * | :----: | :----: | :---- | 154 * |[31:0] |FDBCK |AES Feedback Information 155 * | | |The feedback value is 128 bits in size. 156 * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode. 157 * | | |The AES engine outputs feedback information for IV in the next block's operation 158 * | | |Software can use this feedback information to implement more than four DMA channels 159 * | | |Software can store that feedback value temporarily 160 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. 161 * @var CRPT_T::TDES_FDBCKH 162 * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation 163 * --------------------------------------------------------------------------------------------------- 164 * |Bits |Field |Descriptions 165 * | :----: | :----: | :---- | 166 * |[31:0] |FDBCK |TDES/DES Feedback 167 * | | |The feedback value is 64 bits in size. 168 * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode 169 * | | |The feedback register is for CBC, CFB, and OFB mode. 170 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation 171 * | | |Software can use this feedback information to implement more than four DMA channels 172 * | | |Software can store that feedback value temporarily 173 * | | |After switching back, fill the stored feedback value to this register in the same channel operation 174 * | | |Then can continue the operation with the original setting. 175 * @var CRPT_T::TDES_FDBCKL 176 * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation 177 * --------------------------------------------------------------------------------------------------- 178 * |Bits |Field |Descriptions 179 * | :----: | :----: | :---- | 180 * |[31:0] |FDBCK |TDES/DES Feedback 181 * | | |The feedback value is 64 bits in size. 182 * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode 183 * | | |The feedback register is for CBC, CFB, and OFB mode. 184 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation 185 * | | |Software can use this feedback information to implement more than four DMA channels 186 * | | |Software can store that feedback value temporarily 187 * | | |After switching back, fill the stored feedback value to this register in the same channel operation 188 * | | |Then can continue the operation with the original setting. 189 * @var CRPT_T::AES_CTL 190 * Offset: 0x100 AES Control Register 191 * --------------------------------------------------------------------------------------------------- 192 * |Bits |Field |Descriptions 193 * | :----: | :----: | :---- | 194 * |[0] |START |AES Engine Start 195 * | | |0 = No effect. 196 * | | |1 = Start AES engine. BUSY flag will be set. 197 * | | |Note: This bit is always 0 when it's read back. 198 * |[1] |STOP |AES Engine Stop 199 * | | |0 = No effect. 200 * | | |1 = Stop AES engine. 201 * | | |Note: This bit is always 0 when it's read back. 202 * |[3:2] |KEYSZ |AES Key Size 203 * | | |This bit defines three different key size for AES operation. 204 * | | |2'b00 = 128 bits key. 205 * | | |2'b01 = 192 bits key. 206 * | | |2'b10 = 256 bits key. 207 * | | |2'b11 = Reserved. 208 * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. 209 * |[5] |DMALAST |AES Last Block 210 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. 211 * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. 212 * | | |This bit is always 0 when it's read back. Must be written again once START is triggered. 213 * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode 214 * | | |0 = DMA cascade function Disabled. 215 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 216 * |[7] |DMAEN |AES Engine DMA Enable Control 217 * | | |0 = AES DMA engine Disabled. 218 * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN. 219 * | | |1 = AES_DMA engine Enabled. 220 * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 221 * |[15:8] |OPMODE |AES Engine Operation Modes 222 * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). 223 * | | |0x02 = CFB (Cipher Feedback Mode). 224 * | | |0x03 = OFB (Output Feedback Mode). 225 * | | |0x04 = CTR (Counter Mode). 226 * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). 227 * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). 228 * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). 229 * |[16] |ENCRPT |AES Encryption/Decryption 230 * | | |0 = AES engine executes decryption operation. 231 * | | |1 = AES engine executes encryption operation. 232 * |[22] |OUTSWAP |AES Engine Output Data Swap 233 * | | |0 = Keep the original order. 234 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 235 * |[23] |INSWAP |AES Engine Input Data Swap 236 * | | |0 = Keep the original order. 237 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 238 * |[25:24] |CHANNEL |AES Engine Working Channel 239 * | | |00 = Current control register setting is for channel 0. 240 * | | |01 = Current control register setting is for channel 1. 241 * | | |10 = Current control register setting is for channel 2. 242 * | | |11 = Current control register setting is for channel 3. 243 * |[30:26] |KEYUNPRT |Unprotect Key 244 * | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key. 245 * | | |The KEYUNPRT can be read and written 246 * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 247 * |[31] |KEYPRT |Protect Key 248 * | | |Read as a flag to reflect KEYPRT. 249 * | | |0 = No effect. 250 * | | |1 = Protect the content of the AES key from reading 251 * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx 252 * | | |Once it is set, it can be cleared by asserting KEYUNPRT 253 * | | |And the key content would be cleared as well. 254 * @var CRPT_T::AES_STS 255 * Offset: 0x104 AES Engine Flag 256 * --------------------------------------------------------------------------------------------------- 257 * |Bits |Field |Descriptions 258 * | :----: | :----: | :---- | 259 * |[0] |BUSY |AES Engine Busy 260 * | | |0 = The AES engine is idle or finished. 261 * | | |1 = The AES engine is under processing. 262 * |[8] |INBUFEMPTY|AES Input Buffer Empty 263 * | | |0 = There are some data in input buffer waiting for the AES engine to process. 264 * | | |1 = AES input buffer is empty 265 * | | |Software needs to feed data to the AES engine 266 * | | |Otherwise, the AES engine will be pending to wait for input data. 267 * |[9] |INBUFFULL |AES Input Buffer Full Flag 268 * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. 269 * | | |1 = AES input buffer is full 270 * | | |Software cannot feed data to the AES engine 271 * | | |Otherwise, the flag INBUFERR will be set to 1. 272 * |[10] |INBUFERR |AES Input Buffer Error Flag 273 * | | |0 = No error. 274 * | | |1 = Error happens during feeding data to the AES engine. 275 * |[12] |CNTERR |CRPT_AESn_CNT Setting Error 276 * | | |0 = No error in CRPT_AESn_CNT setting. 277 * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode. 278 * |[16] |OUTBUFEMPTY|AES Out Buffer Empty 279 * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. 280 * | | |1 = AES output buffer is empty 281 * | | |Software cannot get data from CRPT_AES_DATOUT 282 * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. 283 * |[17] |OUTBUFFULL|AES Out Buffer Full Flag 284 * | | |0 = AES output buffer is not full. 285 * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT 286 * | | |Otherwise, the AES engine will be pending since the output buffer is full. 287 * |[18] |OUTBUFERR |AES Out Buffer Error Flag 288 * | | |0 = No error. 289 * | | |1 = Error happens during getting the result from AES engine. 290 * |[20] |BUSERR |AES DMA Access Bus Error Flag 291 * | | |0 = No error. 292 * | | |1 = Bus error will stop DMA operation and AES engine. 293 * @var CRPT_T::AES_DATIN 294 * Offset: 0x108 AES Engine Data Input Port Register 295 * --------------------------------------------------------------------------------------------------- 296 * |Bits |Field |Descriptions 297 * | :----: | :----: | :---- | 298 * |[31:0] |DATIN |AES Engine Input Port 299 * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. 300 * @var CRPT_T::AES_DATOUT 301 * Offset: 0x10C AES Engine Data Output Port Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[31:0] |DATOUT |AES Engine Output Port 306 * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS 307 * | | |Get data as OUTBUFEMPTY is 0. 308 * @var CRPT_T::AES0_KEY[8] 309 * Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register for Channel 0 310 * --------------------------------------------------------------------------------------------------- 311 * |Bits |Field |Descriptions 312 * | :----: | :----: | :---- | 313 * |[31:0] |KEY |CRPT_AESn_KEYx 314 * | | |The KEY keeps the security key for AES operation. 315 * | | |n = 0, 1..3. 316 * | | |x = 0, 1..7. 317 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 318 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 319 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 320 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 321 * @var CRPT_T::AES0_IV[4] 322 * Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register for Channel 0 323 * --------------------------------------------------------------------------------------------------- 324 * |Bits |Field |Descriptions 325 * | :----: | :----: | :---- | 326 * |[31:0] |IV |AES Initial Vectors 327 * | | |n = 0, 1..3. 328 * | | |x = 0, 1..3. 329 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 330 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 331 * @var CRPT_T::AES0_SADDR 332 * Offset: 0x140 AES DMA Source Address Register for Channel 0 333 * --------------------------------------------------------------------------------------------------- 334 * |Bits |Field |Descriptions 335 * | :----: | :----: | :---- | 336 * |[31:0] |SADDR |AES DMA Source Address 337 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 338 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 339 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 340 * | | |The start of source address should be located at word boundary 341 * | | |In other words, bit 1 and 0 of SADDR are ignored. 342 * | | |SADDR can be read and written 343 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 344 * | | |But the value of SADDR will be updated later on 345 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 346 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 347 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 348 * @var CRPT_T::AES0_DADDR 349 * Offset: 0x144 AES DMA Destination Address Register for Channel 0 350 * --------------------------------------------------------------------------------------------------- 351 * |Bits |Field |Descriptions 352 * | :----: | :----: | :---- | 353 * |[31:0] |DADDR |AES DMA Destination Address 354 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 355 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 356 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 357 * | | |The start of destination address should be located at word boundary 358 * | | |In other words, bit 1 and 0 of DADDR are ignored. 359 * | | |DADDR can be read and written 360 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 361 * | | |But the value of DADDR will be updated later on 362 * | | |Consequently, software can prepare the destination address for the next AES operation. 363 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 364 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 365 * @var CRPT_T::AES0_CNT 366 * Offset: 0x148 AES Byte Count Register for Channel 0 367 * --------------------------------------------------------------------------------------------------- 368 * |Bits |Field |Descriptions 369 * | :----: | :----: | :---- | 370 * |[31:0] |CNT |AES Byte Count 371 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 372 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 373 * | | |CRPT_AESn_CNT can be read and written 374 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 375 * | | |But the value of CRPT_AESn_CNT will be updated later on 376 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 377 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 378 * | | |Operations that are less than one block will output unexpected result. 379 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 380 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 381 * @var CRPT_T::AES1_KEY[8] 382 * Offset: 0x14C ~ 0x168 AES Key Word 0 ~ 7 Register for Channel 1 383 * --------------------------------------------------------------------------------------------------- 384 * |Bits |Field |Descriptions 385 * | :----: | :----: | :---- | 386 * |[31:0] |KEY |CRPT_AESn_KEYx 387 * | | |The KEY keeps the security key for AES operation. 388 * | | |n = 0, 1..3. 389 * | | |x = 0, 1..7. 390 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 391 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 392 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 393 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 394 * @var CRPT_T::AES1_IV[4] 395 * Offset: 0x16C ~ 0x178 AES Initial Vector Word 0 ~ 3 Register for Channel 1 396 * --------------------------------------------------------------------------------------------------- 397 * |Bits |Field |Descriptions 398 * | :----: | :----: | :---- | 399 * |[31:0] |IV |AES Initial Vectors 400 * | | |n = 0, 1..3. 401 * | | |x = 0, 1..3. 402 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 403 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 404 * @var CRPT_T::AES1_SADDR 405 * Offset: 0x17C AES DMA Source Address Register for Channel 1 406 * --------------------------------------------------------------------------------------------------- 407 * |Bits |Field |Descriptions 408 * | :----: | :----: | :---- | 409 * |[31:0] |SADDR |AES DMA Source Address 410 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 411 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 412 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 413 * | | |The start of source address should be located at word boundary 414 * | | |In other words, bit 1 and 0 of SADDR are ignored. 415 * | | |SADDR can be read and written 416 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 417 * | | |But the value of SADDR will be updated later on 418 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 419 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 420 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 421 * @var CRPT_T::AES1_DADDR 422 * Offset: 0x180 AES DMA Destination Address Register for Channel 1 423 * --------------------------------------------------------------------------------------------------- 424 * |Bits |Field |Descriptions 425 * | :----: | :----: | :---- | 426 * |[31:0] |DADDR |AES DMA Destination Address 427 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 428 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 429 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 430 * | | |The start of destination address should be located at word boundary 431 * | | |In other words, bit 1 and 0 of DADDR are ignored. 432 * | | |DADDR can be read and written 433 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 434 * | | |But the value of DADDR will be updated later on 435 * | | |Consequently, software can prepare the destination address for the next AES operation. 436 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 437 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 438 * @var CRPT_T::AES1_CNT 439 * Offset: 0x184 AES Byte Count Register for Channel 1 440 * --------------------------------------------------------------------------------------------------- 441 * |Bits |Field |Descriptions 442 * | :----: | :----: | :---- | 443 * |[31:0] |CNT |AES Byte Count 444 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 445 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 446 * | | |CRPT_AESn_CNT can be read and written 447 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 448 * | | |But the value of CRPT_AESn_CNT will be updated later on 449 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 450 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 451 * | | |Operations that are less than one block will output unexpected result. 452 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 453 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 454 * @var CRPT_T::AES2_KEY[8] 455 * Offset: 0x188 ~ 0x1A4 AES Key Word 0 ~ 7 Register for Channel 2 456 * --------------------------------------------------------------------------------------------------- 457 * |Bits |Field |Descriptions 458 * | :----: | :----: | :---- | 459 * |[31:0] |KEY |CRPT_AESn_KEYx 460 * | | |The KEY keeps the security key for AES operation. 461 * | | |n = 0, 1..3. 462 * | | |x = 0, 1..7. 463 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 464 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 465 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 466 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 467 * @var CRPT_T::AES2_IV[4] 468 * Offset: 0x1A8 ~ 0x1B4 AES Initial Vector Word 0 ~ 3 Register for Channel 2 469 * --------------------------------------------------------------------------------------------------- 470 * |Bits |Field |Descriptions 471 * | :----: | :----: | :---- | 472 * |[31:0] |IV |AES Initial Vectors 473 * | | |n = 0, 1..3. 474 * | | |x = 0, 1..3. 475 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 476 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 477 * @var CRPT_T::AES2_SADDR 478 * Offset: 0x1B8 AES DMA Source Address Register for Channel 2 479 * --------------------------------------------------------------------------------------------------- 480 * |Bits |Field |Descriptions 481 * | :----: | :----: | :---- | 482 * |[31:0] |SADDR |AES DMA Source Address 483 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 484 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 485 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 486 * | | |The start of source address should be located at word boundary 487 * | | |In other words, bit 1 and 0 of SADDR are ignored. 488 * | | |SADDR can be read and written 489 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 490 * | | |But the value of SADDR will be updated later on 491 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 492 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 493 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 494 * @var CRPT_T::AES2_DADDR 495 * Offset: 0x1BC AES DMA Destination Address Register for Channel 2 496 * --------------------------------------------------------------------------------------------------- 497 * |Bits |Field |Descriptions 498 * | :----: | :----: | :---- | 499 * |[31:0] |DADDR |AES DMA Destination Address 500 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 501 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 502 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 503 * | | |The start of destination address should be located at word boundary 504 * | | |In other words, bit 1 and 0 of DADDR are ignored. 505 * | | |DADDR can be read and written 506 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 507 * | | |But the value of DADDR will be updated later on 508 * | | |Consequently, software can prepare the destination address for the next AES operation. 509 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 510 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 511 * @var CRPT_T::AES2_CNT 512 * Offset: 0x1C0 AES Byte Count Register for Channel 2 513 * --------------------------------------------------------------------------------------------------- 514 * |Bits |Field |Descriptions 515 * | :----: | :----: | :---- | 516 * |[31:0] |CNT |AES Byte Count 517 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 518 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 519 * | | |CRPT_AESn_CNT can be read and written 520 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 521 * | | |But the value of CRPT_AESn_CNT will be updated later on 522 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 523 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 524 * | | |Operations that are less than one block will output unexpected result. 525 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 526 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 527 * @var CRPT_T::AES3_KEY[8] 528 * Offset: 0x1C4 ~ 0x1E0 AES Key Word 0 ~ 7 Register for Channel 3 529 * --------------------------------------------------------------------------------------------------- 530 * |Bits |Field |Descriptions 531 * | :----: | :----: | :---- | 532 * |[31:0] |KEY |CRPT_AESn_KEYx 533 * | | |The KEY keeps the security key for AES operation. 534 * | | |n = 0, 1..3. 535 * | | |x = 0, 1..7. 536 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 537 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 538 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 539 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 540 * @var CRPT_T::AES3_IV[4] 541 * Offset: 0x1E4 ~ 0x1F0 AES Initial Vector Word 0 ~ 3 Register for Channel 3 542 * --------------------------------------------------------------------------------------------------- 543 * |Bits |Field |Descriptions 544 * | :----: | :----: | :---- | 545 * |[31:0] |IV |AES Initial Vectors 546 * | | |n = 0, 1..3. 547 * | | |x = 0, 1..3. 548 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 549 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 550 * @var CRPT_T::AES3_SADDR 551 * Offset: 0x1F4 AES DMA Source Address Register for Channel 3 552 * --------------------------------------------------------------------------------------------------- 553 * |Bits |Field |Descriptions 554 * | :----: | :----: | :---- | 555 * |[31:0] |SADDR |AES DMA Source Address 556 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 557 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 558 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 559 * | | |The start of source address should be located at word boundary 560 * | | |In other words, bit 1 and 0 of SADDR are ignored. 561 * | | |SADDR can be read and written 562 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 563 * | | |But the value of SADDR will be updated later on 564 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 565 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 566 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 567 * @var CRPT_T::AES3_DADDR 568 * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3 569 * --------------------------------------------------------------------------------------------------- 570 * |Bits |Field |Descriptions 571 * | :----: | :----: | :---- | 572 * |[31:0] |DADDR |AES DMA Destination Address 573 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 574 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 575 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 576 * | | |The start of destination address should be located at word boundary 577 * | | |In other words, bit 1 and 0 of DADDR are ignored. 578 * | | |DADDR can be read and written 579 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 580 * | | |But the value of DADDR will be updated later on 581 * | | |Consequently, software can prepare the destination address for the next AES operation. 582 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 583 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 584 * @var CRPT_T::AES3_CNT 585 * Offset: 0x1FC AES Byte Count Register for Channel 3 586 * --------------------------------------------------------------------------------------------------- 587 * |Bits |Field |Descriptions 588 * | :----: | :----: | :---- | 589 * |[31:0] |CNT |AES Byte Count 590 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 591 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 592 * | | |CRPT_AESn_CNT can be read and written 593 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 594 * | | |But the value of CRPT_AESn_CNT will be updated later on 595 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 596 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 597 * | | |Operations that are less than one block will output unexpected result. 598 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 599 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 600 * @var CRPT_T::TDES_CTL 601 * Offset: 0x200 TDES/DES Control Register 602 * --------------------------------------------------------------------------------------------------- 603 * |Bits |Field |Descriptions 604 * | :----: | :----: | :---- | 605 * |[0] |START |TDES/DES Engine Start 606 * | | |0 = No effect. 607 * | | |1 = Start TDES/DES engine. The flag BUSY would be set. 608 * | | |Note: The bit is always 0 when it's read back. 609 * |[1] |STOP |TDES/DES Engine Stop 610 * | | |0 = No effect. 611 * | | |1 = Stop TDES/DES engine. 612 * | | |Note: The bit is always 0 when it's read back. 613 * |[2] |TMODE |TDES/DES Engine Operating Mode 614 * | | |0 = Set DES mode for TDES/DES engine. 615 * | | |1 = Set Triple DES mode for TDES/DES engine. 616 * |[3] |3KEYS |TDES/DES Key Number 617 * | | |0 = Select KEY1 and KEY2 in TDES/DES engine. 618 * | | |1 = Triple keys in TDES/DES engine Enabled. 619 * |[5] |DMALAST |TDES/DES Engine Start for the Last Block 620 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. 621 * | | |In Non-DMA mode, this bit must be set as feeding in last block of data. 622 * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode 623 * | | |0 = DMA cascade function Disabled. 624 * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 625 * |[7] |DMAEN |TDES/DES Engine DMA Enable Control 626 * | | |0 = TDES_DMA engine Disabled. 627 * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN. 628 * | | |1 = TDES_DMA engine Enabled. 629 * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 630 * |[10:8] |OPMODE |TDES/DES Engine Operation Mode 631 * | | |0x00 = ECB (Electronic Codebook Mode). 632 * | | |0x01 = CBC (Cipher Block Chaining Mode). 633 * | | |0x02 = CFB (Cipher Feedback Mode). 634 * | | |0x03 = OFB (Output Feedback Mode). 635 * | | |0x04 = CTR (Counter Mode). 636 * | | |Others = CTR (Counter Mode). 637 * |[16] |ENCRPT |TDES/DES Encryption/Decryption 638 * | | |0 = TDES engine executes decryption operation. 639 * | | |1 = TDES engine executes encryption operation. 640 * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap 641 * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}. 642 * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. 643 * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap 644 * | | |0 = Keep the original order. 645 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 646 * |[23] |INSWAP |TDES/DES Engine Input Data Swap 647 * | | |0 = Keep the original order. 648 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 649 * |[25:24] |CHANNEL |TDES/DES Engine Working Channel 650 * | | |00 = Current control register setting is for channel 0. 651 * | | |01 = Current control register setting is for channel 1. 652 * | | |10 = Current control register setting is for channel 2. 653 * | | |11 = Current control register setting is for channel 3. 654 * |[30:26] |KEYUNPRT |Unprotect Key 655 * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key. 656 * | | |The KEYUNPRT can be read and written 657 * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 658 * |[31] |KEYPRT |Protect Key 659 * | | |Read as a flag to reflect KEYPRT. 660 * | | |0 = No effect. 661 * | | |1 = This bit is to protect the content of TDES key from reading 662 * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L 663 * | | |Once it is set, it can be cleared by asserting KEYUNPRT 664 * | | |The key content would be cleared as well. 665 * @var CRPT_T::TDES_STS 666 * Offset: 0x204 TDES/DES Engine Flag 667 * --------------------------------------------------------------------------------------------------- 668 * |Bits |Field |Descriptions 669 * | :----: | :----: | :---- | 670 * |[0] |BUSY |TDES/DES Engine Busy 671 * | | |0 = TDES/DES engine is idle or finished. 672 * | | |1 = TDES/DES engine is under processing. 673 * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty 674 * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process. 675 * | | |1 = TDES/DES input buffer is empty 676 * | | |Software needs to feed data to the TDES/DES engine 677 * | | |Otherwise, the TDES/DES engine will be pending to wait for input data. 678 * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag 679 * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine. 680 * | | |1 = TDES input buffer is full 681 * | | |Software cannot feed data to the TDES/DES engine 682 * | | |Otherwise, the flag INBUFERR will be set to 1. 683 * |[10] |INBUFERR |TDES/DES in Buffer Error Flag 684 * | | |0 = No error. 685 * | | |1 = Error happens during feeding data to the TDES/DES engine. 686 * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag 687 * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer. 688 * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT 689 * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty. 690 * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag 691 * | | |0 = TDES/DES output buffer is not full. 692 * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT 693 * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full. 694 * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag 695 * | | |0 = No error. 696 * | | |1 = Error happens during getting test result from TDES/DES engine. 697 * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag 698 * | | |0 = No error. 699 * | | |1 = Bus error will stop DMA operation and TDES/DES engine. 700 * @var CRPT_T::TDES0_KEY1H 701 * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0 702 * --------------------------------------------------------------------------------------------------- 703 * |Bits |Field |Descriptions 704 * | :----: | :----: | :---- | 705 * |[31:0] |KEY |TDES/DES Key 1 High Word 706 * | | |The key registers for TDES/DES algorithm calculation 707 * | | |The security key for the TDES/DES accelerator is 64 bits 708 * | | |Thus, it needs two 32-bit registers to store a security key 709 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 710 * @var CRPT_T::TDES0_KEY1L 711 * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0 712 * --------------------------------------------------------------------------------------------------- 713 * |Bits |Field |Descriptions 714 * | :----: | :----: | :---- | 715 * |[31:0] |KEY |TDES/DES Key 1 Low Word 716 * | | |The key registers for TDES/DES algorithm calculation 717 * | | |The security key for the TDES/DES accelerator is 64 bits 718 * | | |Thus, it needs two 32-bit registers to store a security key 719 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 720 * @var CRPT_T::TDES0_KEY2H 721 * Offset: 0x210 TDES Key 2 High Word Register for Channel 0 722 * --------------------------------------------------------------------------------------------------- 723 * |Bits |Field |Descriptions 724 * | :----: | :----: | :---- | 725 * |[31:0] |KEY |TDES/DES Key 2 High Word 726 * | | |The key registers for TDES/DES algorithm calculation 727 * | | |The security key for the TDES/DES accelerator is 64 bits 728 * | | |Thus, it needs two 32-bit registers to store a security key 729 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 730 * @var CRPT_T::TDES0_KEY2L 731 * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0 732 * --------------------------------------------------------------------------------------------------- 733 * |Bits |Field |Descriptions 734 * | :----: | :----: | :---- | 735 * |[31:0] |KEY |TDES/DES Key 2 Low Word 736 * | | |The key registers for TDES/DES algorithm calculation 737 * | | |The security key for the TDES/DES accelerator is 64 bits 738 * | | |Thus, it needs two 32-bit registers to store a security key 739 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 740 * @var CRPT_T::TDES0_KEY3H 741 * Offset: 0x218 TDES Key 3 High Word Register for Channel 0 742 * --------------------------------------------------------------------------------------------------- 743 * |Bits |Field |Descriptions 744 * | :----: | :----: | :---- | 745 * |[31:0] |KEY |TDES/DES Key 3 High Word 746 * | | |The key registers for TDES/DES algorithm calculation 747 * | | |The security key for the TDES/DES accelerator is 64 bits 748 * | | |Thus, it needs two 32-bit registers to store a security key 749 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 750 * @var CRPT_T::TDES0_KEY3L 751 * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0 752 * --------------------------------------------------------------------------------------------------- 753 * |Bits |Field |Descriptions 754 * | :----: | :----: | :---- | 755 * |[31:0] |KEY |TDES/DES Key 3 Low Word 756 * | | |The key registers for TDES/DES algorithm calculation 757 * | | |The security key for the TDES/DES accelerator is 64 bits 758 * | | |Thus, it needs two 32-bit registers to store a security key 759 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 760 * @var CRPT_T::TDES0_IVH 761 * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0 762 * --------------------------------------------------------------------------------------------------- 763 * |Bits |Field |Descriptions 764 * | :----: | :----: | :---- | 765 * |[31:0] |IV |TDES/DES Initial Vector High Word 766 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 767 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 768 * @var CRPT_T::TDES0_IVL 769 * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0 770 * --------------------------------------------------------------------------------------------------- 771 * |Bits |Field |Descriptions 772 * | :----: | :----: | :---- | 773 * |[31:0] |IV |TDES/DES Initial Vector Low Word 774 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 775 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 776 * @var CRPT_T::TDES0_SA 777 * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0 778 * --------------------------------------------------------------------------------------------------- 779 * |Bits |Field |Descriptions 780 * | :----: | :----: | :---- | 781 * |[31:0] |SADDR |TDES/DES DMA Source Address 782 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 783 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 784 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 785 * | | |The start of source address should be located at word boundary 786 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 787 * | | |CRPT_TDESn_SA can be read and written 788 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 789 * | | |But the value of CRPT_TDESn_SA will be updated later on 790 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 791 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 792 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 793 * @var CRPT_T::TDES0_DA 794 * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0 795 * --------------------------------------------------------------------------------------------------- 796 * |Bits |Field |Descriptions 797 * | :----: | :----: | :---- | 798 * |[31:0] |DADDR |TDES/DES DMA Destination Address 799 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 800 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 801 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 802 * | | |The start of destination address should be located at word boundary 803 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 804 * | | |CRPT_TDESn_DA can be read and written 805 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 806 * | | |But the value of CRPT_TDESn_DA will be updated later on 807 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 808 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 809 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 810 * @var CRPT_T::TDES0_CNT 811 * Offset: 0x230 TDES/DES Byte Count Register for Channel 0 812 * --------------------------------------------------------------------------------------------------- 813 * |Bits |Field |Descriptions 814 * | :----: | :----: | :---- | 815 * |[31:0] |CNT |TDES/DES Byte Count 816 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 817 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 818 * | | |CRPT_TDESn_CNT can be read and written 819 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 820 * | | |But the value of CRPT_TDESn_CNT will be updated later on 821 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 822 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 823 * @var CRPT_T::TDES_DATIN 824 * Offset: 0x234 TDES/DES Engine Input data Word Register 825 * --------------------------------------------------------------------------------------------------- 826 * |Bits |Field |Descriptions 827 * | :----: | :----: | :---- | 828 * |[31:0] |DATIN |TDES/DES Engine Input Port 829 * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS 830 * | | |Feed data as INBUFFULL is 0. 831 * @var CRPT_T::TDES_DATOUT 832 * Offset: 0x238 TDES/DES Engine Output data Word Register 833 * --------------------------------------------------------------------------------------------------- 834 * |Bits |Field |Descriptions 835 * | :----: | :----: | :---- | 836 * |[31:0] |DATOUT |TDES/DES Engine Output Port 837 * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS 838 * | | |Get data as OUTBUFEMPTY is 0. 839 * @var CRPT_T::TDES1_KEY1H 840 * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1 841 * --------------------------------------------------------------------------------------------------- 842 * |Bits |Field |Descriptions 843 * | :----: | :----: | :---- | 844 * |[31:0] |KEY |TDES/DES Key 1 High Word 845 * | | |The key registers for TDES/DES algorithm calculation 846 * | | |The security key for the TDES/DES accelerator is 64 bits 847 * | | |Thus, it needs two 32-bit registers to store a security key 848 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 849 * @var CRPT_T::TDES1_KEY1L 850 * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1 851 * --------------------------------------------------------------------------------------------------- 852 * |Bits |Field |Descriptions 853 * | :----: | :----: | :---- | 854 * |[31:0] |KEY |TDES/DES Key 1 Low Word 855 * | | |The key registers for TDES/DES algorithm calculation 856 * | | |The security key for the TDES/DES accelerator is 64 bits 857 * | | |Thus, it needs two 32-bit registers to store a security key 858 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 859 * @var CRPT_T::TDES1_KEY2H 860 * Offset: 0x250 TDES Key 2 High Word Register for Channel 1 861 * --------------------------------------------------------------------------------------------------- 862 * |Bits |Field |Descriptions 863 * | :----: | :----: | :---- | 864 * |[31:0] |KEY |TDES/DES Key 2 High Word 865 * | | |The key registers for TDES/DES algorithm calculation 866 * | | |The security key for the TDES/DES accelerator is 64 bits 867 * | | |Thus, it needs two 32-bit registers to store a security key 868 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 869 * @var CRPT_T::TDES1_KEY2L 870 * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1 871 * --------------------------------------------------------------------------------------------------- 872 * |Bits |Field |Descriptions 873 * | :----: | :----: | :---- | 874 * |[31:0] |KEY |TDES/DES Key 2 Low Word 875 * | | |The key registers for TDES/DES algorithm calculation 876 * | | |The security key for the TDES/DES accelerator is 64 bits 877 * | | |Thus, it needs two 32-bit registers to store a security key 878 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 879 * @var CRPT_T::TDES1_KEY3H 880 * Offset: 0x258 TDES Key 3 High Word Register for Channel 1 881 * --------------------------------------------------------------------------------------------------- 882 * |Bits |Field |Descriptions 883 * | :----: | :----: | :---- | 884 * |[31:0] |KEY |TDES/DES Key 3 High Word 885 * | | |The key registers for TDES/DES algorithm calculation 886 * | | |The security key for the TDES/DES accelerator is 64 bits 887 * | | |Thus, it needs two 32-bit registers to store a security key 888 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 889 * @var CRPT_T::TDES1_KEY3L 890 * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1 891 * --------------------------------------------------------------------------------------------------- 892 * |Bits |Field |Descriptions 893 * | :----: | :----: | :---- | 894 * |[31:0] |KEY |TDES/DES Key 3 Low Word 895 * | | |The key registers for TDES/DES algorithm calculation 896 * | | |The security key for the TDES/DES accelerator is 64 bits 897 * | | |Thus, it needs two 32-bit registers to store a security key 898 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 899 * @var CRPT_T::TDES1_IVH 900 * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1 901 * --------------------------------------------------------------------------------------------------- 902 * |Bits |Field |Descriptions 903 * | :----: | :----: | :---- | 904 * |[31:0] |IV |TDES/DES Initial Vector High Word 905 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 906 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 907 * @var CRPT_T::TDES1_IVL 908 * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1 909 * --------------------------------------------------------------------------------------------------- 910 * |Bits |Field |Descriptions 911 * | :----: | :----: | :---- | 912 * |[31:0] |IV |TDES/DES Initial Vector Low Word 913 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 914 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 915 * @var CRPT_T::TDES1_SA 916 * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1 917 * --------------------------------------------------------------------------------------------------- 918 * |Bits |Field |Descriptions 919 * | :----: | :----: | :---- | 920 * |[31:0] |SADDR |TDES/DES DMA Source Address 921 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 922 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 923 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 924 * | | |The start of source address should be located at word boundary 925 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 926 * | | |CRPT_TDESn_SA can be read and written 927 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 928 * | | |But the value of CRPT_TDESn_SA will be updated later on 929 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 930 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 931 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 932 * @var CRPT_T::TDES1_DA 933 * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1 934 * --------------------------------------------------------------------------------------------------- 935 * |Bits |Field |Descriptions 936 * | :----: | :----: | :---- | 937 * |[31:0] |DADDR |TDES/DES DMA Destination Address 938 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 939 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 940 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 941 * | | |The start of destination address should be located at word boundary 942 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 943 * | | |CRPT_TDESn_DA can be read and written 944 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 945 * | | |But the value of CRPT_TDESn_DA will be updated later on 946 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 947 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 948 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 949 * @var CRPT_T::TDES1_CNT 950 * Offset: 0x270 TDES/DES Byte Count Register for Channel 1 951 * --------------------------------------------------------------------------------------------------- 952 * |Bits |Field |Descriptions 953 * | :----: | :----: | :---- | 954 * |[31:0] |CNT |TDES/DES Byte Count 955 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 956 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 957 * | | |CRPT_TDESn_CNT can be read and written 958 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 959 * | | |But the value of CRPT_TDESn_CNT will be updated later on 960 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 961 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 962 * @var CRPT_T::TDES2_KEY1H 963 * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2 964 * --------------------------------------------------------------------------------------------------- 965 * |Bits |Field |Descriptions 966 * | :----: | :----: | :---- | 967 * |[31:0] |KEY |TDES/DES Key 1 High Word 968 * | | |The key registers for TDES/DES algorithm calculation 969 * | | |The security key for the TDES/DES accelerator is 64 bits 970 * | | |Thus, it needs two 32-bit registers to store a security key 971 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 972 * @var CRPT_T::TDES2_KEY1L 973 * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2 974 * --------------------------------------------------------------------------------------------------- 975 * |Bits |Field |Descriptions 976 * | :----: | :----: | :---- | 977 * |[31:0] |KEY |TDES/DES Key 1 Low Word 978 * | | |The key registers for TDES/DES algorithm calculation 979 * | | |The security key for the TDES/DES accelerator is 64 bits 980 * | | |Thus, it needs two 32-bit registers to store a security key 981 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 982 * @var CRPT_T::TDES2_KEY2H 983 * Offset: 0x290 TDES Key 2 High Word Register for Channel 2 984 * --------------------------------------------------------------------------------------------------- 985 * |Bits |Field |Descriptions 986 * | :----: | :----: | :---- | 987 * |[31:0] |KEY |TDES/DES Key 2 High Word 988 * | | |The key registers for TDES/DES algorithm calculation 989 * | | |The security key for the TDES/DES accelerator is 64 bits 990 * | | |Thus, it needs two 32-bit registers to store a security key 991 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 992 * @var CRPT_T::TDES2_KEY2L 993 * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2 994 * --------------------------------------------------------------------------------------------------- 995 * |Bits |Field |Descriptions 996 * | :----: | :----: | :---- | 997 * |[31:0] |KEY |TDES/DES Key 2 Low Word 998 * | | |The key registers for TDES/DES algorithm calculation 999 * | | |The security key for the TDES/DES accelerator is 64 bits 1000 * | | |Thus, it needs two 32-bit registers to store a security key 1001 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1002 * @var CRPT_T::TDES2_KEY3H 1003 * Offset: 0x298 TDES Key 3 High Word Register for Channel 2 1004 * --------------------------------------------------------------------------------------------------- 1005 * |Bits |Field |Descriptions 1006 * | :----: | :----: | :---- | 1007 * |[31:0] |KEY |TDES/DES Key 3 High Word 1008 * | | |The key registers for TDES/DES algorithm calculation 1009 * | | |The security key for the TDES/DES accelerator is 64 bits 1010 * | | |Thus, it needs two 32-bit registers to store a security key 1011 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1012 * @var CRPT_T::TDES2_KEY3L 1013 * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2 1014 * --------------------------------------------------------------------------------------------------- 1015 * |Bits |Field |Descriptions 1016 * | :----: | :----: | :---- | 1017 * |[31:0] |KEY |TDES/DES Key 3 Low Word 1018 * | | |The key registers for TDES/DES algorithm calculation 1019 * | | |The security key for the TDES/DES accelerator is 64 bits 1020 * | | |Thus, it needs two 32-bit registers to store a security key 1021 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1022 * @var CRPT_T::TDES2_IVH 1023 * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2 1024 * --------------------------------------------------------------------------------------------------- 1025 * |Bits |Field |Descriptions 1026 * | :----: | :----: | :---- | 1027 * |[31:0] |IV |TDES/DES Initial Vector High Word 1028 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1029 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1030 * @var CRPT_T::TDES2_IVL 1031 * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2 1032 * --------------------------------------------------------------------------------------------------- 1033 * |Bits |Field |Descriptions 1034 * | :----: | :----: | :---- | 1035 * |[31:0] |IV |TDES/DES Initial Vector Low Word 1036 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1037 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1038 * @var CRPT_T::TDES2_SA 1039 * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2 1040 * --------------------------------------------------------------------------------------------------- 1041 * |Bits |Field |Descriptions 1042 * | :----: | :----: | :---- | 1043 * |[31:0] |SADDR |TDES/DES DMA Source Address 1044 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 1045 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 1046 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 1047 * | | |The start of source address should be located at word boundary 1048 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 1049 * | | |CRPT_TDESn_SA can be read and written 1050 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1051 * | | |But the value of CRPT_TDESn_SA will be updated later on 1052 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 1053 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 1054 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 1055 * @var CRPT_T::TDES2_DA 1056 * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2 1057 * --------------------------------------------------------------------------------------------------- 1058 * |Bits |Field |Descriptions 1059 * | :----: | :----: | :---- | 1060 * |[31:0] |DADDR |TDES/DES DMA Destination Address 1061 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 1062 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 1063 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 1064 * | | |The start of destination address should be located at word boundary 1065 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 1066 * | | |CRPT_TDESn_DA can be read and written 1067 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1068 * | | |But the value of CRPT_TDESn_DA will be updated later on 1069 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 1070 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 1071 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 1072 * @var CRPT_T::TDES2_CNT 1073 * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2 1074 * --------------------------------------------------------------------------------------------------- 1075 * |Bits |Field |Descriptions 1076 * | :----: | :----: | :---- | 1077 * |[31:0] |CNT |TDES/DES Byte Count 1078 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 1079 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 1080 * | | |CRPT_TDESn_CNT can be read and written 1081 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1082 * | | |But the value of CRPT_TDESn_CNT will be updated later on 1083 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 1084 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 1085 * @var CRPT_T::TDES3_KEY1H 1086 * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3 1087 * --------------------------------------------------------------------------------------------------- 1088 * |Bits |Field |Descriptions 1089 * | :----: | :----: | :---- | 1090 * |[31:0] |KEY |TDES/DES Key 1 High Word 1091 * | | |The key registers for TDES/DES algorithm calculation 1092 * | | |The security key for the TDES/DES accelerator is 64 bits 1093 * | | |Thus, it needs two 32-bit registers to store a security key 1094 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1095 * @var CRPT_T::TDES3_KEY1L 1096 * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3 1097 * --------------------------------------------------------------------------------------------------- 1098 * |Bits |Field |Descriptions 1099 * | :----: | :----: | :---- | 1100 * |[31:0] |KEY |TDES/DES Key 1 High Word 1101 * | | |The key registers for TDES/DES algorithm calculation 1102 * | | |The security key for the TDES/DES accelerator is 64 bits 1103 * | | |Thus, it needs two 32-bit registers to store a security key 1104 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1105 * @var CRPT_T::TDES3_KEY2H 1106 * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3 1107 * --------------------------------------------------------------------------------------------------- 1108 * |Bits |Field |Descriptions 1109 * | :----: | :----: | :---- | 1110 * |[31:0] |KEY |TDES/DES Key 2 High Word 1111 * | | |The key registers for TDES/DES algorithm calculation 1112 * | | |The security key for the TDES/DES accelerator is 64 bits 1113 * | | |Thus, it needs two 32-bit registers to store a security key 1114 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1115 * @var CRPT_T::TDES3_KEY2L 1116 * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3 1117 * --------------------------------------------------------------------------------------------------- 1118 * |Bits |Field |Descriptions 1119 * | :----: | :----: | :---- | 1120 * |[31:0] |KEY |TDES/DES Key 2 Low Word 1121 * | | |The key registers for TDES/DES algorithm calculation 1122 * | | |The security key for the TDES/DES accelerator is 64 bits 1123 * | | |Thus, it needs two 32-bit registers to store a security key 1124 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1125 * @var CRPT_T::TDES3_KEY3H 1126 * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3 1127 * --------------------------------------------------------------------------------------------------- 1128 * |Bits |Field |Descriptions 1129 * | :----: | :----: | :---- | 1130 * |[31:0] |KEY |TDES/DES Key 3 High Word 1131 * | | |The key registers for TDES/DES algorithm calculation 1132 * | | |The security key for the TDES/DES accelerator is 64 bits 1133 * | | |Thus, it needs two 32-bit registers to store a security key 1134 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1135 * @var CRPT_T::TDES3_KEY3L 1136 * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3 1137 * --------------------------------------------------------------------------------------------------- 1138 * |Bits |Field |Descriptions 1139 * | :----: | :----: | :---- | 1140 * |[31:0] |KEY |TDES/DES Key 3 Low Word 1141 * | | |The key registers for TDES/DES algorithm calculation 1142 * | | |The security key for the TDES/DES accelerator is 64 bits 1143 * | | |Thus, it needs two 32-bit registers to store a security key 1144 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1145 * @var CRPT_T::TDES3_IVH 1146 * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3 1147 * --------------------------------------------------------------------------------------------------- 1148 * |Bits |Field |Descriptions 1149 * | :----: | :----: | :---- | 1150 * |[31:0] |IV |TDES/DES Initial Vector High Word 1151 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1152 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1153 * @var CRPT_T::TDES3_IVL 1154 * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3 1155 * --------------------------------------------------------------------------------------------------- 1156 * |Bits |Field |Descriptions 1157 * | :----: | :----: | :---- | 1158 * |[31:0] |IV |TDES/DES Initial Vector Low Word 1159 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1160 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1161 * @var CRPT_T::TDES3_SA 1162 * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3 1163 * --------------------------------------------------------------------------------------------------- 1164 * |Bits |Field |Descriptions 1165 * | :----: | :----: | :---- | 1166 * |[31:0] |SADDR |TDES/DES DMA Source Address 1167 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 1168 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 1169 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 1170 * | | |The start of source address should be located at word boundary 1171 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 1172 * | | |CRPT_TDESn_SA can be read and written 1173 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1174 * | | |But the value of CRPT_TDESn_SA will be updated later on 1175 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 1176 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 1177 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 1178 * @var CRPT_T::TDES3_DA 1179 * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3 1180 * --------------------------------------------------------------------------------------------------- 1181 * |Bits |Field |Descriptions 1182 * | :----: | :----: | :---- | 1183 * |[31:0] |DADDR |TDES/DES DMA Destination Address 1184 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 1185 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 1186 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 1187 * | | |The start of destination address should be located at word boundary 1188 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 1189 * | | |CRPT_TDESn_DA can be read and written 1190 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1191 * | | |But the value of CRPT_TDESn_DA will be updated later on 1192 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 1193 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 1194 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 1195 * @var CRPT_T::TDES3_CNT 1196 * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3 1197 * --------------------------------------------------------------------------------------------------- 1198 * |Bits |Field |Descriptions 1199 * | :----: | :----: | :---- | 1200 * |[31:0] |CNT |TDES/DES Byte Count 1201 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 1202 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 1203 * | | |CRPT_TDESn_CNT can be read and written 1204 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1205 * | | |But the value of CRPT_TDESn_CNT will be updated later on 1206 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 1207 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 1208 * @var CRPT_T::HMAC_CTL 1209 * Offset: 0x300 SHA/HMAC Control Register 1210 * --------------------------------------------------------------------------------------------------- 1211 * |Bits |Field |Descriptions 1212 * | :----: | :----: | :---- | 1213 * |[0] |START |SHA/HMAC Engine Start 1214 * | | |0 = No effect. 1215 * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. 1216 * | | |This bit is always 0 when it's read back. 1217 * |[1] |STOP |SHA/HMAC Engine Stop 1218 * | | |0 = No effect. 1219 * | | |1 = Stop SHA/HMAC engine. 1220 * | | |This bit is always 0 when it's read back. 1221 * |[4] |HMACEN |HMAC_SHA Engine Operating Mode 1222 * | | |0 = execute SHA function. 1223 * | | |1 = execute HMAC function. 1224 * |[5] |DMALAST |SHA/HMAC Last Block 1225 * | | |This bit must be set as feeding in last byte of data. 1226 * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control 1227 * | | |0 = SHA/HMAC DMA engine Disabled. 1228 * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN. 1229 * | | |1 = SHA/HMAC DMA engine Enabled. 1230 * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 1231 * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes 1232 * | | |0x0xx: SHA160 1233 * | | |0x100: SHA256 1234 * | | |0x101: SHA224 1235 * | | |0x110: SHA512 1236 * | | |0x111: SHA384 1237 * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1. 1238 * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap 1239 * | | |0 = Keep the original order. 1240 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 1241 * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap 1242 * | | |0 = Keep the original order. 1243 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 1244 * @var CRPT_T::HMAC_STS 1245 * Offset: 0x304 SHA/HMAC Status Flag 1246 * --------------------------------------------------------------------------------------------------- 1247 * |Bits |Field |Descriptions 1248 * | :----: | :----: | :---- | 1249 * |[0] |BUSY |SHA/HMAC Engine Busy 1250 * | | |0 = SHA/HMAC engine is idle or finished. 1251 * | | |1 = SHA/HMAC engine is busy. 1252 * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag 1253 * | | |0 = SHA/HMAC DMA engine is idle or finished. 1254 * | | |1 = SHA/HMAC DMA engine is busy. 1255 * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag 1256 * | | |0 = Show the SHA/HMAC engine access normal. 1257 * | | |1 = Show the SHA/HMAC engine access error. 1258 * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request 1259 * | | |0 = No effect. 1260 * | | |1 = Request SHA/HMAC Non-DMA mode data input. 1261 * @var CRPT_T::HMAC_DGST[16] 1262 * Offset: 0x308 ~ 0x344 SHA/HMAC Digest Message 0 ~ 15 1263 * --------------------------------------------------------------------------------------------------- 1264 * |Bits |Field |Descriptions 1265 * | :----: | :----: | :---- | 1266 * |[31:0] |DGST |SHA/HMAC Digest Message Output Register 1267 * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. 1268 * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. 1269 * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. 1270 * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. 1271 * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. 1272 * @var CRPT_T::HMAC_KEYCNT 1273 * Offset: 0x348 SHA/HMAC Key Byte Count Register 1274 * --------------------------------------------------------------------------------------------------- 1275 * |Bits |Field |Descriptions 1276 * | :----: | :----: | :---- | 1277 * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count 1278 * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates 1279 * | | |The register is 32-bit and the maximum byte count is 4G bytes 1280 * | | |It can be read and written. 1281 * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation 1282 * | | |But the value of CRPT_SHA _KEYCNT will be updated later on 1283 * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. 1284 * @var CRPT_T::HMAC_SADDR 1285 * Offset: 0x34C SHA/HMAC DMA Source Address Register 1286 * --------------------------------------------------------------------------------------------------- 1287 * |Bits |Field |Descriptions 1288 * | :----: | :----: | :---- | 1289 * |[31:0] |SADDR |SHA/HMAC DMA Source Address 1290 * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 1291 * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored 1292 * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation 1293 * | | |The start of source address should be located at word boundary 1294 * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. 1295 * | | |CRPT_HMAC_SADDR can be read and written 1296 * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation 1297 * | | |But the value of CRPT_HMAC_SADDR will be updated later on 1298 * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. 1299 * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. 1300 * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. 1301 * @var CRPT_T::HMAC_DMACNT 1302 * Offset: 0x350 SHA/HMAC Byte Count Register 1303 * --------------------------------------------------------------------------------------------------- 1304 * |Bits |Field |Descriptions 1305 * | :----: | :----: | :---- | 1306 * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count 1307 * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode 1308 * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. 1309 * | | |CRPT_HMAC_DMACNT can be read and written 1310 * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation 1311 * | | |But the value of CRPT_HMAC_DMACNT will be updated later on 1312 * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. 1313 * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. 1314 * @var CRPT_T::HMAC_DATIN 1315 * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register 1316 * --------------------------------------------------------------------------------------------------- 1317 * |Bits |Field |Descriptions 1318 * | :----: | :----: | :---- | 1319 * |[31:0] |DATIN |SHA/HMAC Engine Input Port 1320 * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS 1321 * | | |Feed data as DATINREQ is 1. 1322 * @var CRPT_T::ECC_CTL 1323 * Offset: 0x800 ECC Control Register 1324 * --------------------------------------------------------------------------------------------------- 1325 * |Bits |Field |Descriptions 1326 * | :----: | :----: | :---- | 1327 * |[0] |START |ECC Accelerator Start 1328 * | | |0 = No effect. 1329 * | | |1 = Start ECC accelerator. BUSY flag will be set. 1330 * | | |This bit is always 0 when it's read back. 1331 * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. 1332 * |[1] |STOP |ECC Accelerator Stop 1333 * | | |0 = No effect. 1334 * | | |1 = Abort ECC accelerator and make it into idle state. 1335 * | | |This bit is always 0 when it's read back. 1336 * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. 1337 * |[7] |DMAEN |ECC Accelerator DMA Enable Control 1338 * | | |0 = ECC DMA engine Disabled. 1339 * | | |1 = ECC DMA engine Enabled. 1340 * | | |Only when START and DMAEN are 1, ECC DMA engine will be active 1341 * |[8] |FSEL |Field Selection 1342 * | | |0 = Binary Field (GF(2^m)). 1343 * | | |1 = Prime Field (GF(p)). 1344 * |[10:9] |ECCOP |Point Operation for BF and PF 1345 * | | |00 = Point multiplication :. 1346 * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). 1347 * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). 1348 * | | |10 = Point addition :. 1349 * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. 1350 * | | |(POINTX2, POINTY2) 1351 * | | |11 = Point doubling :. 1352 * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). 1353 * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 1354 * |[12:11] |MODOP |Modulus Operation for PF 1355 * | | |00 = Division :. 1356 * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. 1357 * | | |01 = Multiplication :. 1358 * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. 1359 * | | |10 = Addition :. 1360 * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. 1361 * | | |11 = Subtraction :. 1362 * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. 1363 * | | |MODOP is active only when ECCOP = 01. 1364 * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1) 1365 * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. 1366 * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. 1367 * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2) 1368 * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. 1369 * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. 1370 * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve 1371 * | | |0 = The register for CURVEA is not modified by DMA or user. 1372 * | | |1 = The register for CURVEA is modified by DMA or user. 1373 * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve 1374 * | | |0 = The register for CURVEB is not modified by DMA or user. 1375 * | | |1 = The register for CURVEB is modified by DMA or user. 1376 * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve 1377 * | | |0 = The register for CURVEN is not modified by DMA or user. 1378 * | | |1 = The register for CURVEN is modified by DMA or user. 1379 * |[21] |LDK |The Control Signal of Register for SCALARK 1380 * | | |0 = The register for SCALARK is not modified by DMA or user. 1381 * | | |1 = The register for SCALARK is modified by DMA or user. 1382 * |[31:22] |CURVEM |The key length of elliptic curve. 1383 * @var CRPT_T::ECC_STS 1384 * Offset: 0x804 ECC Status Register 1385 * --------------------------------------------------------------------------------------------------- 1386 * |Bits |Field |Descriptions 1387 * | :----: | :----: | :---- | 1388 * |[0] |BUSY |ECC Accelerator Busy Flag 1389 * | | |0 = The ECC accelerator is idle or finished. 1390 * | | |1 = The ECC accelerator is under processing and protects all registers. 1391 * | | |Remember to clear ECC interrupt flag after ECC accelerator finished 1392 * |[1] |DMABUSY |ECC DMA Busy Flag 1393 * | | |0 = ECC DMA is idle or finished. 1394 * | | |1 = ECC DMA is busy. 1395 * |[16] |BUSERR |ECC DMA Access Bus Error Flag 1396 * | | |0 = No error. 1397 * | | |1 = Bus error will stop DMA operation and ECC accelerator. 1398 * @var CRPT_T::ECC_X1[18] 1399 * Offset: 0x808 ~ 0x84C ECC The X-coordinate word 0 ~ 17 of the first point 1400 * --------------------------------------------------------------------------------------------------- 1401 * |Bits |Field |Descriptions 1402 * | :----: | :----: | :---- | 1403 * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1) 1404 * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 1405 * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 1406 * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 1407 * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 1408 * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 1409 * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 1410 * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 1411 * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 1412 * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 1413 * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 1414 * @var CRPT_T::ECC_Y1[18] 1415 * Offset: 0x850 ~ 0x894 ECC The Y-coordinate word 0 ~ 17 of the first point 1416 * --------------------------------------------------------------------------------------------------- 1417 * |Bits |Field |Descriptions 1418 * | :----: | :----: | :---- | 1419 * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1) 1420 * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 1421 * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 1422 * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 1423 * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 1424 * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 1425 * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 1426 * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 1427 * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 1428 * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 1429 * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 1430 * @var CRPT_T::ECC_X2[18] 1431 * Offset: 0x898 ~ 0x8DC ECC The X-coordinate word 0 ~ 17 of the second point 1432 * --------------------------------------------------------------------------------------------------- 1433 * |Bits |Field |Descriptions 1434 * | :----: | :----: | :---- | 1435 * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2) 1436 * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 1437 * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 1438 * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 1439 * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 1440 * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 1441 * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 1442 * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 1443 * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 1444 * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 1445 * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 1446 * @var CRPT_T::ECC_Y2[18] 1447 * Offset: 0x8E0 ~ 0x924 ECC The Y-coordinate word 0 ~ 17 of the second point 1448 * --------------------------------------------------------------------------------------------------- 1449 * |Bits |Field |Descriptions 1450 * | :----: | :----: | :---- | 1451 * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2) 1452 * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 1453 * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 1454 * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 1455 * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 1456 * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 1457 * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 1458 * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 1459 * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 1460 * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 1461 * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 1462 * @var CRPT_T::ECC_A[18] 1463 * Offset: 0x928 ~ 0x96C ECC The parameter CURVEA word 0 ~ 17 of elliptic curve 1464 * --------------------------------------------------------------------------------------------------- 1465 * |Bits |Field |Descriptions 1466 * | :----: | :----: | :---- | 1467 * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA) 1468 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). 1469 * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 1470 * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 1471 * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 1472 * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 1473 * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 1474 * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 1475 * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 1476 * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 1477 * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 1478 * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 1479 * @var CRPT_T::ECC_B[18] 1480 * Offset: 0x970 ~ 0x9B4 ECC The parameter CURVEB word 0 ~ 17 of elliptic curve 1481 * --------------------------------------------------------------------------------------------------- 1482 * |Bits |Field |Descriptions 1483 * | :----: | :----: | :---- | 1484 * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA) 1485 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2^m). 1486 * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 1487 * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 1488 * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 1489 * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 1490 * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 1491 * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 1492 * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 1493 * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 1494 * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 1495 * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 1496 * @var CRPT_T::ECC_N[18] 1497 * Offset: 0x9B8 ~ 0x9FC ECC The parameter CURVEN word 0 ~ 17 of elliptic curve 1498 * --------------------------------------------------------------------------------------------------- 1499 * |Bits |Field |Descriptions 1500 * | :----: | :----: | :---- | 1501 * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN) 1502 * | | |In GF(p), CURVEN is the prime p. 1503 * | | |In GF(2^m), CURVEN is the irreducible polynomial. 1504 * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 1505 * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 1506 * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 1507 * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 1508 * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 1509 * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 1510 * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 1511 * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 1512 * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 1513 * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 1514 * @var CRPT_T::ECC_K[18] 1515 * Offset: 0xA00 ~ 0xA44 ECC The scalar SCALARK word0 of point multiplication 1516 * --------------------------------------------------------------------------------------------------- 1517 * |Bits |Field |Descriptions 1518 * | :----: | :----: | :---- | 1519 * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK) 1520 * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. 1521 * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 1522 * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 1523 * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 1524 * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 1525 * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 1526 * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 1527 * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 1528 * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 1529 * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 1530 * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 1531 * @var CRPT_T::ECC_SADDR 1532 * Offset: 0xA48 ECC DMA Source Address Register 1533 * --------------------------------------------------------------------------------------------------- 1534 * |Bits |Field |Descriptions 1535 * | :----: | :----: | :---- | 1536 * |[31:0] |SADDR |ECC DMA Source Address 1537 * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between 1538 * | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data 1539 * | | |buffer where the source text is stored. Based on the source address, the ECC accelerator 1540 * | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start 1541 * | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are 1542 * | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR 1543 * | | |before triggering START. 1544 * @var CRPT_T::ECC_DADDR 1545 * Offset: 0xA4C ECC DMA Destination Address Register 1546 * --------------------------------------------------------------------------------------------------- 1547 * |Bits |Field |Descriptions 1548 * | :----: | :----: | :---- | 1549 * |[31:0] |DADDR |ECC DMA Destination Address 1550 * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator 1551 * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored 1552 * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished 1553 * | | |The start of destination address should be located at word boundary 1554 * | | |That is, bit 1 and 0 of DADDR are ignored 1555 * | | |DADDR can be read and written 1556 * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START 1557 * @var CRPT_T::ECC_STARTREG 1558 * Offset: 0xA50 ECC Starting Address of Updated Registers 1559 * --------------------------------------------------------------------------------------------------- 1560 * |Bits |Field |Descriptions 1561 * | :----: | :----: | :---- | 1562 * |[31:0] |STARTREG |ECC Starting Address of Updated Registers 1563 * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine 1564 * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG 1565 * | | |For example, we want to updated input data from register CRPT_ECC POINTX1 1566 * | | |Thus, the value of STARTREG is 0x808. 1567 * @var CRPT_T::ECC_WORDCNT 1568 * Offset: 0xA54 ECC DMA Word Count 1569 * --------------------------------------------------------------------------------------------------- 1570 * |Bits |Field |Descriptions 1571 * | :----: | :----: | :---- | 1572 * |[31:0] |WORDCNT |ECC DMA Word Count 1573 * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode 1574 * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words 1575 * | | |CRPT_ECC_WORDCNT can be read and written 1576 */ 1577 __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ 1578 __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ 1579 __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ 1580 __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ 1581 __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ 1582 /// @cond HIDDEN_SYMBOLS 1583 __I uint32_t RESERVE0[8]; 1584 /// @endcond //HIDDEN_SYMBOLS 1585 __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ 1586 __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */ 1587 __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */ 1588 /// @cond HIDDEN_SYMBOLS 1589 __I uint32_t RESERVE1[38]; 1590 /// @endcond //HIDDEN_SYMBOLS 1591 __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ 1592 __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ 1593 __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ 1594 __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ 1595 __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ 1596 __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ 1597 __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */ 1598 __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */ 1599 __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */ 1600 __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */ 1601 __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */ 1602 __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */ 1603 __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */ 1604 __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */ 1605 __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */ 1606 __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */ 1607 __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */ 1608 __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */ 1609 __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */ 1610 __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */ 1611 __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */ 1612 __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */ 1613 __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */ 1614 __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */ 1615 __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */ 1616 __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */ 1617 __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */ 1618 __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */ 1619 __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */ 1620 __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */ 1621 __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */ 1622 __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */ 1623 __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */ 1624 __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */ 1625 __IO uint32_t TDES0_SA; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */ 1626 __IO uint32_t TDES0_DA; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */ 1627 __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */ 1628 __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */ 1629 __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */ 1630 /// @cond HIDDEN_SYMBOLS 1631 __I uint32_t RESERVE2[3]; 1632 /// @endcond //HIDDEN_SYMBOLS 1633 __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */ 1634 __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */ 1635 __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */ 1636 __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */ 1637 __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */ 1638 __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */ 1639 __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */ 1640 __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */ 1641 __IO uint32_t TDES1_SA; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */ 1642 __IO uint32_t TDES1_DA; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */ 1643 __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */ 1644 /// @cond HIDDEN_SYMBOLS 1645 __I uint32_t RESERVE3[5]; 1646 /// @endcond //HIDDEN_SYMBOLS 1647 __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */ 1648 __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */ 1649 __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */ 1650 __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */ 1651 __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */ 1652 __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */ 1653 __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */ 1654 __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */ 1655 __IO uint32_t TDES2_SA; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */ 1656 __IO uint32_t TDES2_DA; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */ 1657 __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */ 1658 /// @cond HIDDEN_SYMBOLS 1659 __I uint32_t RESERVE4[5]; 1660 /// @endcond //HIDDEN_SYMBOLS 1661 __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */ 1662 __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */ 1663 __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */ 1664 __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */ 1665 __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */ 1666 __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */ 1667 __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */ 1668 __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */ 1669 __IO uint32_t TDES3_SA; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */ 1670 __IO uint32_t TDES3_DA; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */ 1671 __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */ 1672 /// @cond HIDDEN_SYMBOLS 1673 __I uint32_t RESERVE5[3]; 1674 /// @endcond //HIDDEN_SYMBOLS 1675 __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ 1676 __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ 1677 __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ 1678 __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ 1679 __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ 1680 __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ 1681 __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ 1682 /// @cond HIDDEN_SYMBOLS 1683 __I uint32_t RESERVE6[298]; 1684 /// @endcond //HIDDEN_SYMBOLS 1685 __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ 1686 __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ 1687 __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */ 1688 __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ 1689 __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ 1690 __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ 1691 __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ 1692 __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ 1693 __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ 1694 __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ 1695 __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ 1696 __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ 1697 __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ 1698 __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ 1699 1700 } CRPT_T; 1701 1702 /** 1703 @addtogroup CRPT_CONST CRPT Bit Field Definition 1704 Constant Definitions for CRPT Controller 1705 @{ */ 1706 1707 #define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ 1708 #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ 1709 1710 #define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ 1711 #define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ 1712 1713 #define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */ 1714 #define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */ 1715 1716 #define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */ 1717 #define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */ 1718 1719 #define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ 1720 #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ 1721 1722 #define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ 1723 #define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ 1724 1725 #define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ 1726 #define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ 1727 1728 #define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ 1729 #define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ 1730 1731 #define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ 1732 #define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ 1733 1734 #define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ 1735 #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ 1736 1737 #define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ 1738 #define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ 1739 1740 #define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */ 1741 #define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */ 1742 1743 #define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */ 1744 #define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */ 1745 1746 #define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ 1747 #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ 1748 1749 #define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ 1750 #define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ 1751 1752 #define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ 1753 #define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ 1754 1755 #define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ 1756 #define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ 1757 1758 #define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ 1759 #define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ 1760 1761 #define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ 1762 #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ 1763 1764 #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ 1765 #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ 1766 1767 #define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ 1768 #define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ 1769 1770 #define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ 1771 #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ 1772 1773 #define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ 1774 #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ 1775 1776 #define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */ 1777 #define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */ 1778 1779 #define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */ 1780 #define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */ 1781 1782 #define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */ 1783 #define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */ 1784 1785 #define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */ 1786 #define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */ 1787 1788 #define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ 1789 #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ 1790 1791 #define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ 1792 #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ 1793 1794 #define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ 1795 #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ 1796 1797 #define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ 1798 #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ 1799 1800 #define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ 1801 #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ 1802 1803 #define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ 1804 #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ 1805 1806 #define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ 1807 #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ 1808 1809 #define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ 1810 #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ 1811 1812 #define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ 1813 #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ 1814 1815 #define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ 1816 #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ 1817 1818 #define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */ 1819 #define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */ 1820 1821 #define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ 1822 #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ 1823 1824 #define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ 1825 #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ 1826 1827 #define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ 1828 #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ 1829 1830 #define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ 1831 #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ 1832 1833 #define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ 1834 #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ 1835 1836 #define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ 1837 #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ 1838 1839 #define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ 1840 #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ 1841 1842 #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */ 1843 #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ 1844 1845 #define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ 1846 #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ 1847 1848 #define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ 1849 #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ 1850 1851 #define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ 1852 #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ 1853 1854 #define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ 1855 #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ 1856 1857 #define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ 1858 #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ 1859 1860 #define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */ 1861 #define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */ 1862 1863 #define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */ 1864 #define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */ 1865 1866 #define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */ 1867 #define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */ 1868 1869 #define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */ 1870 #define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */ 1871 1872 #define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */ 1873 #define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */ 1874 1875 #define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */ 1876 #define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */ 1877 1878 #define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */ 1879 #define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */ 1880 1881 #define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */ 1882 #define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */ 1883 1884 #define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */ 1885 #define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */ 1886 1887 #define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */ 1888 #define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */ 1889 1890 #define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEY[8]: KEY Position */ 1891 #define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEY[8]: KEY Mask */ 1892 1893 #define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IV[4]: IV Position */ 1894 #define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IV[4]: IV Mask */ 1895 1896 #define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */ 1897 #define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */ 1898 1899 #define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */ 1900 #define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */ 1901 1902 #define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */ 1903 #define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */ 1904 1905 #define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */ 1906 #define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */ 1907 1908 #define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */ 1909 #define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */ 1910 1911 #define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */ 1912 #define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */ 1913 1914 #define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */ 1915 #define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */ 1916 1917 #define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */ 1918 #define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */ 1919 1920 #define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */ 1921 #define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */ 1922 1923 #define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */ 1924 #define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */ 1925 1926 #define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */ 1927 #define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */ 1928 1929 #define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */ 1930 #define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */ 1931 1932 #define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */ 1933 #define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */ 1934 1935 #define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */ 1936 #define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */ 1937 1938 #define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */ 1939 #define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */ 1940 1941 #define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */ 1942 #define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */ 1943 1944 #define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */ 1945 #define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */ 1946 1947 #define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */ 1948 #define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */ 1949 1950 #define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */ 1951 #define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */ 1952 1953 #define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */ 1954 #define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */ 1955 1956 #define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */ 1957 #define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */ 1958 1959 #define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */ 1960 #define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */ 1961 1962 #define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */ 1963 #define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */ 1964 1965 #define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */ 1966 #define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */ 1967 1968 #define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */ 1969 #define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */ 1970 1971 #define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */ 1972 #define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */ 1973 1974 #define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */ 1975 #define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */ 1976 1977 #define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */ 1978 #define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */ 1979 1980 #define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */ 1981 #define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */ 1982 1983 #define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */ 1984 #define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */ 1985 1986 #define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */ 1987 #define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */ 1988 1989 #define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */ 1990 #define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */ 1991 1992 #define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */ 1993 #define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */ 1994 1995 #define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */ 1996 #define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */ 1997 1998 #define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */ 1999 #define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */ 2000 2001 #define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */ 2002 #define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */ 2003 2004 #define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */ 2005 #define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */ 2006 2007 #define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */ 2008 #define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */ 2009 2010 #define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */ 2011 #define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */ 2012 2013 #define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */ 2014 #define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */ 2015 2016 #define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */ 2017 #define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */ 2018 2019 #define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */ 2020 #define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */ 2021 2022 #define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */ 2023 #define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */ 2024 2025 #define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */ 2026 #define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */ 2027 2028 #define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */ 2029 #define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */ 2030 2031 #define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */ 2032 #define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */ 2033 2034 #define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */ 2035 #define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */ 2036 2037 #define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */ 2038 #define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */ 2039 2040 #define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */ 2041 #define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */ 2042 2043 #define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */ 2044 #define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */ 2045 2046 #define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */ 2047 #define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */ 2048 2049 #define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */ 2050 #define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */ 2051 2052 #define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */ 2053 #define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */ 2054 2055 #define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */ 2056 #define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */ 2057 2058 #define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */ 2059 #define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */ 2060 2061 #define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */ 2062 #define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */ 2063 2064 #define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */ 2065 #define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */ 2066 2067 #define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */ 2068 #define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */ 2069 2070 #define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */ 2071 #define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */ 2072 2073 #define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */ 2074 #define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */ 2075 2076 #define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */ 2077 #define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */ 2078 2079 #define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ 2080 #define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ 2081 2082 #define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ 2083 #define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ 2084 2085 #define CRPT_HMAC_CTL_HMACEN_Pos (4) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ 2086 #define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ 2087 2088 #define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ 2089 #define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ 2090 2091 #define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ 2092 #define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ 2093 2094 #define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ 2095 #define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ 2096 2097 #define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ 2098 #define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ 2099 2100 #define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ 2101 #define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ 2102 2103 #define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ 2104 #define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ 2105 2106 #define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ 2107 #define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ 2108 2109 #define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ 2110 #define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ 2111 2112 #define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ 2113 #define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ 2114 2115 #define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST[16]: DGST Position */ 2116 #define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGST[16]: DGST Mask */ 2117 2118 #define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ 2119 #define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ 2120 2121 #define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ 2122 #define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ 2123 2124 #define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ 2125 #define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ 2126 2127 #define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ 2128 #define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ 2129 2130 #define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ 2131 #define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ 2132 2133 #define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ 2134 #define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ 2135 2136 #define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ 2137 #define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ 2138 2139 #define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ 2140 #define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ 2141 2142 #define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ 2143 #define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ 2144 2145 #define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ 2146 #define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ 2147 2148 #define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ 2149 #define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ 2150 2151 #define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ 2152 #define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ 2153 2154 #define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ 2155 #define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ 2156 2157 #define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ 2158 #define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ 2159 2160 #define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ 2161 #define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ 2162 2163 #define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ 2164 #define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ 2165 2166 #define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ 2167 #define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ 2168 2169 #define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ 2170 #define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ 2171 2172 #define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ 2173 #define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ 2174 2175 #define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ 2176 #define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ 2177 2178 #define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1[18]: POINTX1 Position */ 2179 #define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1[18]: POINTX1 Mask */ 2180 2181 #define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Position */ 2182 #define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1[18]: POINTY1 Mask */ 2183 2184 #define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2[18]: POINTX2 Position */ 2185 #define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2[18]: POINTX2 Mask */ 2186 2187 #define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Position */ 2188 #define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2[18]: POINTY2 Mask */ 2189 2190 #define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A[18]: CURVEA Position */ 2191 #define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A[18]: CURVEA Mask */ 2192 2193 #define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B[18]: CURVEB Position */ 2194 #define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B[18]: CURVEB Mask */ 2195 2196 #define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N[18]: CURVEN Position */ 2197 #define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N[18]: CURVEN Mask */ 2198 2199 #define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K[18]: SCALARK Position */ 2200 #define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K[18]: SCALARK Mask */ 2201 2202 #define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ 2203 #define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ 2204 2205 #define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ 2206 #define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ 2207 2208 #define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */ 2209 #define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ 2210 2211 /**@}*/ /* CRPT_CONST CRYPTO */ 2212 /**@}*/ /* end of CRYPTO register group */ 2213 /**@}*/ /* end of REGISTER group */ 2214 2215 #if defined ( __CC_ARM ) 2216 #pragma no_anon_unions 2217 #endif 2218 2219 #endif /* __CRYPTO_REG_H__ */ 2220
