1 /**************************************************************************//** 2 * @file crpt_reg.h 3 * @version V1.00 4 * @brief CRPT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRPT_REG_H__ 10 #define __CRPT_REG_H__ 11 12 13 /** @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Cryptographic Accelerator -------------------------*/ 21 /** 22 @addtogroup CRPT Cryptographic Accelerator(CRPT) 23 Memory Mapped Structure for CRPT Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var CRPT_T::INTEN 33 * Offset: 0x00 Crypto Interrupt Enable Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |AESIEN |AES Interrupt Enable Bit 38 * | | |0 = AES interrupt Disabled. 39 * | | |1 = AES interrupt Enabled. 40 * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. 41 * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. 42 * |[1] |AESEIEN |AES Error Flag Enable Bit 43 * | | |0 = AES error interrupt flag Disabled. 44 * | | |1 = AES error interrupt flag Enabled. 45 * |[16] |PRNGIEN |PRNG Interrupt Enable Bit 46 * | | |0 = PRNG interrupt Disabled. 47 * | | |1 = PRNG interrupt Enabled. 48 * |[17] |PRNGEIEN |PRNG Error Flag Enable Bit 49 * | | |0 = PRNG error interrupt flag Disabled. 50 * | | |1 = PRNG error interrupt flag Enabled. 51 * |[22] |ECCIEN |ECC Interrupt Enable Bit 52 * | | |0 = ECC interrupt Disabled. 53 * | | |1 = ECC interrupt Enabled. 54 * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine 55 * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. 56 * |[23] |ECCEIEN |ECC Error Interrupt Enable Bit 57 * | | |0 = ECC error interrupt flag Disabled. 58 * | | |1 = ECC error interrupt flag Enabled. 59 * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Bit 60 * | | |0 = SHA/HMAC interrupt Disabled. 61 * | | |1 = SHA/HMAC interrupt Enabled. 62 * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine 63 * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. 64 * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Bit 65 * | | |0 = SHA/HMAC error interrupt flag Disabled. 66 * | | |1 = HMAC error interrupt flag Enabled. 67 * |[30] |RSAIEN |RSA Interrupt Enable Bit 68 * | | |0 = RSA interrupt Disabled. 69 * | | |1 = RSA interrupt Enabled. 70 * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in RSA_DMA_CNT is fed into the RSA engine. 71 * |[31] |RSAEIEN |RSA Error Interrupt Enable Bit 72 * | | |0 = RSA error interrupt flag Disabled. 73 * | | |1 = RSA error interrupt flag Enabled. 74 * @var CRPT_T::INTSTS 75 * Offset: 0x04 Crypto Interrupt Flag 76 * --------------------------------------------------------------------------------------------------- 77 * |Bits |Field |Descriptions 78 * | :----: | :----: | :---- | 79 * |[0] |AESIF |AES Finish Interrupt Flag 80 * | | |0 = No AES interrupt. 81 * | | |1 = AES encryption/decryption done interrupt. 82 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 83 * |[1] |AESEIF |AES Error Flag 84 * | | |0 = No AES error. 85 * | | |1 = AES encryption/decryption error interrupt. 86 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 87 * |[16] |PRNGIF |PRNG Finish Interrupt Flag 88 * | | |0 = No PRNG interrupt. 89 * | | |1 = PRNG key generation done interrupt. 90 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 91 * |[17] |PRNGEIF |PRNGError Flag 92 * | | |0 = No PRNG error. 93 * | | |1 = PRNG key generation error interrupt. 94 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 95 * |[22] |ECCIF |ECC Finish Interrupt Flag 96 * | | |0 = No ECC interrupt. 97 * | | |1 = ECC operation done interrupt. 98 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 99 * |[23] |ECCEIF |ECC Error Flag 100 * | | |This register includes operating and setting error 101 * | | |The detail flag is shown in CRPT_ECC_STS register. 102 * | | |0 = No ECC error. 103 * | | |1 = ECC error interrupt. 104 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 105 * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag 106 * | | |0 = No SHA/HMAC interrupt. 107 * | | |1 = SHA/HMAC operation done interrupt. 108 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 109 * |[25] |HMACEIF |SHA/HMAC Error Flag 110 * | | |This register includes operating and setting error 111 * | | |The detail flag is shown in CRPT_HMAC_STS register. 112 * | | |0 = No SHA/HMAC error. 113 * | | |1 = SHA/HMAC error interrupt. 114 * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. 115 * |[30] |RSAIF |RSA Finish Interrupt Flag 116 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 117 * | | |0 = No RSA interrupt. 118 * | | |1 = RSA operation done interrupt. 119 * |[31] |RSAEIF |RSA Error Interrupt Flag 120 * | | |This register includes operating and setting error 121 * | | |The detail flag is shown in CRPT_RSA_STS register. 122 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 123 * | | |0 = No RSA error. 124 * | | |1 = RSA error interrupt. 125 * @var CRPT_T::PRNG_CTL 126 * Offset: 0x08 PRNG Control Register 127 * --------------------------------------------------------------------------------------------------- 128 * |Bits |Field |Descriptions 129 * | :----: | :----: | :---- | 130 * |[0] |START |Start PRNG Engine 131 * | | |0 = Stop PRNG engine. 132 * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated. 133 * |[1] |SEEDRLD |Reload New Seed for PRNG Engine 134 * | | |0 = Generating key based on the current seed. 135 * | | |1 = Reload new seed. 136 * |[5:2] |KEYSZ |PRNG Generate Key Size 137 * | | |0000 = 128 bits. 138 * | | |0001 = 163 bits. 139 * | | |0010 = 192 bits. 140 * | | |0011 = 224 bits. 141 * | | |0100 = 233 bits. 142 * | | |0101 = 255 bits. 143 * | | |0110 = 256 bits. 144 * | | |0111 = 283 bits (only for KS). 145 * | | |1000 = 384 bits (only for KS). 146 * | | |1001 = 409 bits (only for KS). 147 * | | |1010 = 512 bits (only for KS). 148 * | | |1011 = 521 bits (only for KS). 149 * | | |1100 = 571 bits (only for KS). 150 * | | |1101 = Reserved. 151 * | | |1110 = Reserved. 152 * | | |1111 = Reserved. 153 * | | |Note: 283~571 bits only generate for Key Store. 154 * |[6] |SEEDSEL |Seed Select 155 * | | |This bit can be set to 1 only after SEEDRDY (TRNG_CTL[9]) bit become to 1. 156 * | | |0 = Select the seed which is from PRNG. 157 * | | |1 = Select the seed which is from TRNG. (not from CRPT_PRNG_SEED) 158 * |[7] |SEEDSRC |Seed Source (Read Only) 159 * | | |0 = Seed is from PRNG. 160 * | | |1 = Seed is from TRNG. (not from CRPT_PRNG_SEED) 161 * | | |Note: This bit is cleared to u20180u2019 when SEEDSEL is 0. 162 * |[8] |BUSY |PRNG Busy (Read Only) 163 * | | |0 = PRNG engine is idle. 164 * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. 165 * @var CRPT_T::PRNG_SEED 166 * Offset: 0x0C Seed for PRNG 167 * --------------------------------------------------------------------------------------------------- 168 * |Bits |Field |Descriptions 169 * | :----: | :----: | :---- | 170 * |[31:0] |SEED |Seed for PRNG (Write Only) 171 * | | |The bits store the seed for PRNG engine. 172 * | | |Note: In TRNG+PRNG mode, the seed is from TRNGengine, and it will not store in this register. 173 * @var CRPT_T::PRNG_KEY 174 * Offset: 0x10-0x2C PRNG Generated Key 175 * --------------------------------------------------------------------------------------------------- 176 * |Bits |Field |Descriptions 177 * | :----: | :----: | :---- | 178 * |[31:0] |KEY |Store PRNG Generated Key (Read Only) 179 * | | |The bits store the key that is generated by PRNG. 180 * @var CRPT_T::PRNG_STS 181 * Offset: 0x30 PRNG Status Register 182 * --------------------------------------------------------------------------------------------------- 183 * |Bits |Field |Descriptions 184 * | :----: | :----: | :---- | 185 * |[0] |BUSY |PRNG Busy Flag 186 * | | |0 = PRNG engine is idle. 187 * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. 188 * |[16] |KCTLERR |PRNG Key Control Register Error Flag 189 * | | |0 = No error. 190 * | | |1 = PRNG key control error 191 * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). 192 * |[17] |KSERR |PRNG Access Key Store Error Flag 193 * | | |0 = No error. 194 * | | |1 = Access key store fail. 195 * @var CRPT_T::AES_FDBCK 196 * Offset: 0x50-0x5C AES Engine Output Feedback Data After Cryptographic Operation 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[31:0] |FDBCK |AES Feedback Information 201 * | | |The feedback value is 128 bits in size. 202 * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. 203 * | | |The AES engine outputs feedback information for IV in the next block operation 204 * | | |Software can use this feedback information to implement more than four DMA channels 205 * | | |Software can store that feedback value temporarily 206 * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. 207 * @var CRPT_T::AES_GCM_IVCNT 208 * Offset: 0x80-0x84 AES GCM IV Byte Count Register 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[31:0] |CNT |AES GCM IV Byte Count 213 * | | |The bit length of IV is 64 bits for AES GCM mode 214 * | | |The CRPT_AES_GCM_IVCNT keeps the low weightbyte count of initial vector (i.e., len(IV)[34:3])of AES GCM mode and can be read and written. 215 * @var CRPT_T::AES_GCM_ACNT 216 * Offset: 0x88-0x8C AES GCM A Byte Count Register 217 * --------------------------------------------------------------------------------------------------- 218 * |Bits |Field |Descriptions 219 * | :----: | :----: | :---- | 220 * |[31:0] |CNT |AES GCM aByte Count 221 * | | |The bit length of A is 64 bits for AES GCM mode 222 * | | |The CRPT_AES_GCM_ACNT keeps the low weightbyte count of theadditional authenticated data (i.e., len(A)[34:3])of AES GCM mode and can be read and written. 223 * @var CRPT_T::AES_GCM_PCNT 224 * Offset: 0x90-0x94 AES GCM P Byte Count Register 225 * --------------------------------------------------------------------------------------------------- 226 * |Bits |Field |Descriptions 227 * | :----: | :----: | :---- | 228 * |[31:0] |CNT |AES GCM PByte Count 229 * | | |The bit length of Por Cis 39 bits for AES GCM mode 230 * | | |The CRPT_AES_GCM_PCNT0 keeps the low weightbyte count of theplaintextor ciphertext (i.e., len(P)[34:3] or len(C)[34:3])of AES GCM mode and can be read and written. 231 * |[60:32] |CNT |AES GCM P Byte Count 232 * | | |The bit length of Por C is 39 bits for AES GCM mode 233 * | | |The CRPT_AES_GCM_PCNT1 keeps the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[38:35] or len(C)[38:35])of AES GCM mode and can be read and written. 234 * | | |The bit length of Por C is 64 bits for AES CCM mode 235 * | | |The CRPT_AES_GCM_PCNT1 keeps the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[63:35] or len(C)[63:35])of AES CCM mode and can be read and written. 236 * @var CRPT_T::AES_FBADDR 237 * Offset: 0xA0 AES DMA Feedback Address Register 238 * --------------------------------------------------------------------------------------------------- 239 * |Bits |Field |Descriptions 240 * | :----: | :----: | :---- | 241 * |[31:0] |FBADDR |AES DMA Feedback Address 242 * | | |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation 243 * | | |Based on the feedback address, the AES accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space 244 * | | |The start of feedback address should be located at word boundary 245 * | | |In other words, bit 1 and 0 of FBADDR are ignored. 246 * | | |FBADDR can be read and written. 247 * | | |In DMA mode, software can update the next CRPT_AES_FBADDR before triggering START. 248 * @var CRPT_T::AES_CTL 249 * Offset: 0x100 AES Control Register 250 * --------------------------------------------------------------------------------------------------- 251 * |Bits |Field |Descriptions 252 * | :----: | :----: | :---- | 253 * |[0] |START |AES Engine Start 254 * | | |0 = No effect. 255 * | | |1 = Start AES engine. BUSY flag will be set. 256 * | | |Note: This bit is always 0 when it read back. 257 * |[1] |STOP |AES Engine Stop 258 * | | |0 = No effect. 259 * | | |1 = Stop AES engine. 260 * | | |Note: This bit is always 0 when it read back. 261 * |[3:2] |KEYSZ |AES Key Size 262 * | | |This bit defines three different key size for AES operation. 263 * | | |2u2019b00 = 128 bits key. 264 * | | |2u2019b01 = 192 bits key. 265 * | | |2u2019b10 = 256 bits key. 266 * | | |2u2019b11 = Reserved. 267 * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. 268 * | | |Note:When SM4EN=1, the key size of AESmust be 128. 269 * |[5] |DMALAST |AES Last Block 270 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. 271 * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. 272 * | | |This bit is always 0 when it read back. Must be written again once START is triggered. 273 * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode 274 * | | |0 = DMA cascade function Disabled. 275 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 276 * |[7] |DMAEN |AES Engine DMA Enable Bit 277 * | | |0 = AES DMA engine Disabled. 278 * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN. 279 * | | |1 = AES_DMA engine Enabled. 280 * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 281 * |[15:8] |OPMODE |AES Engine Operation Modes 282 * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). 283 * | | |0x02 = CFB (Cipher Feedback Mode). 284 * | | |0x03 = OFB (Output Feedback Mode). 285 * | | |0x04 = CTR (Counter Mode). 286 * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). 287 * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). 288 * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). 289 * | | |0x20 = GCM (Galois/Counter Mode). 290 * | | |0x21 = GHASH (Galois Hash Function). 291 * | | |0x22 = CCM (Counter with CBC-MAC Mode). 292 * |[16] |ENCRYPTO |AES Encryption/Decryption 293 * | | |0 = AES engine executes decryption operation. 294 * | | |1 = AES engine executes encryption operation. 295 * |[17] |SM4EN |SM4 Engine Enable 296 * | | |0 = Enable AES engine. 297 * | | |1 =Enable SM4 engine. 298 * |[20] |FBIN |Feedback Input to AES Via DMA Automatically 299 * | | |0 = Disable DMA automatical feedback input fucntion. 300 * | | |1 =Enable DMA automatical feedback input fucntion.when DMAEN = 1. 301 * |[21] |FBOUT |Feedback Output From AES Via DMA Automatically 302 * | | |0 = Disable DMA automatical feedback output fucntion. 303 * | | |1 =Enable DMA automatical feedback output fucntion when DMAEN = 1. 304 * |[22] |OUTSWAP |AES Engine Output Data Swap 305 * | | |0 = Keep the original order. 306 * | | |1 =The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 307 * |[23] |INSWAP |AES Engine Input Data Swap 308 * | | |0 = Keep the original order. 309 * | | |1 =The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 310 * |[24] |KOUTSWAP |AES Engine Output Key, Initial Vector and Feedback Swap 311 * | | |0 = Keep the original order. 312 * | | |1 =The order that CPU readskey, initial vector and feeback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 313 * |[25] |KINSWAP |AES Engine Input Key and Initial Vector Swap 314 * | | |0 = Keep the original order. 315 * | | |1 =The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 316 * |[30:26] |KEYUNPRT |Unprotect Key 317 * | | |Writing 0 to CRPT_AES_CTL[31] and u201C10110u201D to CRPT_AES_CTL[30:26] is to unprotect theAES key. 318 * | | |The KEYUNPRT can be read and written 319 * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 320 * |[31] |KEYPRT |Protect Key 321 * | | |Read as a flag to reflect KEYPRT. 322 * | | |0 = No effect. 323 * | | |1 = Protect the content of the AES key from reading 324 * | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx 325 * | | |Once it is set, it can be cleared by asserting KEYUNPRT 326 * | | |And the key content would be cleared as well. 327 * @var CRPT_T::AES_STS 328 * Offset: 0x104 AES Engine Flag 329 * --------------------------------------------------------------------------------------------------- 330 * |Bits |Field |Descriptions 331 * | :----: | :----: | :---- | 332 * |[0] |BUSY |AES Engine Busy 333 * | | |0 = The AES engine is idle or finished. 334 * | | |1 = The AES engine is under processing. 335 * |[8] |INBUFEMPTY|AES Input Buffer Empty 336 * | | |0 = There are some data in input buffer waiting for the AES engine to process. 337 * | | |1 = AES input buffer is empty 338 * | | |Software needs to feed data to the AES engine 339 * | | |Otherwise, the AES engine will be pending to wait for input data. 340 * |[9] |INBUFFULL |AES Input Buffer Full Flag 341 * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. 342 * | | |1 = AES input buffer is full 343 * | | |Software cannot feed data to the AES engine 344 * | | |Otherwise, the flag INBUFERR will be set to 1. 345 * |[10] |INBUFERR |AES Input Buffer Error Flag 346 * | | |0 = No error. 347 * | | |1 = Error happens during feeding data to the AES engine. 348 * |[12] |CNTERR |CRPT_AES_CNT Setting Error 349 * | | |0 = No error in CRPT_AES_CNT setting. 350 * | | |1 = CRPT_AES_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRPT_AES_CTL[7]) is enabled. 351 * |[16] |OUTBUFEMPTY|AES Out Buffer Empty 352 * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. 353 * | | |1 = AES output buffer is empty 354 * | | |Software cannot get data from CRPT_AES_DATOUT 355 * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. 356 * |[17] |OUTBUFFULL|AES Out Buffer Full Flag 357 * | | |0 = AES output buffer is not full. 358 * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT 359 * | | |Otherwise, the AES engine will be pending since the output buffer is full. 360 * |[18] |OUTBUFERR |AES Out Buffer Error Flag 361 * | | |0 = No error. 362 * | | |1 = Error happens during getting the result from AES engine. 363 * |[20] |BUSERR |AES DMA Access Bus Error Flag 364 * | | |0 = No error. 365 * | | |1 = Bus error will stop DMA operation and AES engine. 366 * |[21] |KSERR |AES Engine Access Key Store Error Flag 367 * | | |0 = No error. 368 * | | |1 = Access error will stop AES engine. 369 * @var CRPT_T::AES_DATIN 370 * Offset: 0x108 AES Engine Data Input Port Register 371 * --------------------------------------------------------------------------------------------------- 372 * |Bits |Field |Descriptions 373 * | :----: | :----: | :---- | 374 * |[31:0] |DATIN |AES Engine Input Port 375 * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. 376 * @var CRPT_T::AES_DATOUT 377 * Offset: 0x10C AES Engine Data Output Port Register 378 * --------------------------------------------------------------------------------------------------- 379 * |Bits |Field |Descriptions 380 * | :----: | :----: | :---- | 381 * |[31:0] |DATOUT |AES Engine Output Port 382 * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS 383 * | | |Get data as OUTBUFEMPTY is 0. 384 * @var CRPT_T::AES_KEY 385 * Offset: 0x110-0x12C AES Key Word Register 386 * --------------------------------------------------------------------------------------------------- 387 * |Bits |Field |Descriptions 388 * | :----: | :----: | :---- | 389 * |[31:0] |KEY |CRPT_AES_KEYx 390 * | | |The KEY keeps the security key for AES operation. 391 * | | |x = 0, 1..7. 392 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. 393 * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. 394 * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. 395 * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. 396 * @var CRPT_T::AES_IV 397 * Offset: 0x130-0x13C AES Initial Vector Word Register 398 * --------------------------------------------------------------------------------------------------- 399 * |Bits |Field |Descriptions 400 * | :----: | :----: | :---- | 401 * |[31:0] |IV |AES Initial Vectors 402 * | | |x = 0, 1..3. 403 * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode 404 * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 405 * @var CRPT_T::AES_SADDR 406 * Offset: 0x140 AES DMA Source Address Register 407 * --------------------------------------------------------------------------------------------------- 408 * |Bits |Field |Descriptions 409 * | :----: | :----: | :---- | 410 * |[31:0] |SADDR |AES DMA Source Address 411 * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO 412 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 413 * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation 414 * | | |The start of source address should be located at word boundary 415 * | | |In other words, bit 1 and 0 of SADDR are ignored. 416 * | | |SADDR can be read and written 417 * | | |Writing to SADDR while the AES accelerator is operating doesnu2019t affect the current AES operation 418 * | | |But the value of SADDR will be updated later on 419 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 420 * | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START. 421 * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. 422 * @var CRPT_T::AES_DADDR 423 * Offset: 0x144 AES DMA Destination Address Register 424 * --------------------------------------------------------------------------------------------------- 425 * |Bits |Field |Descriptions 426 * | :----: | :----: | :---- | 427 * |[31:0] |DADDR |AES DMA Destination Address 428 * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO 429 * | | |The DADDR keeps the destination address of the data buffer where the engine output text will be stored 430 * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished 431 * | | |The start of destination address should be located at word boundary 432 * | | |In other words, bit 1 and 0 of DADDR are ignored. 433 * | | |DADDR can be read and written 434 * | | |Writing to DADDR while the AES accelerator is operating doesnu2019t affect the current AES operation 435 * | | |But the value of DADDR will be updated later on 436 * | | |Consequently, software can prepare the destination address for the next AES operation. 437 * | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START. 438 * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. 439 * @var CRPT_T::AES_CNT 440 * Offset: 0x148 AES Byte Count Register 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[31:0] |CNT |AES Byte Count 445 * | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 446 * | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. 447 * | | |CRPT_AES_CNT can be read and written 448 * | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesnu2019t affect the current AES operation 449 * | | |But the value of CRPT_AES_CNT will be updated later on 450 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 451 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes 452 * | | |Operations that are qual or less than one block will output unexpected result. 453 * | | |In Non-DMA ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data 454 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 455 * | | |In AES GCM mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to the total value of{CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. 456 * | | |In AES GCM mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte count of source text in this cascade function 457 * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment. 458 * | | |In AES CCM mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. 459 * | | |In AES CCM mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte count of source text in this cascade function 460 * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment, except for the last block of plaintext or ciphertext. 461 * @var CRPT_T::HMAC_CTL 462 * Offset: 0x300 SHA/HMAC Control Register 463 * --------------------------------------------------------------------------------------------------- 464 * |Bits |Field |Descriptions 465 * | :----: | :----: | :---- | 466 * |[0] |START |SHA/HMAC Engine Start 467 * | | |0 = No effect. 468 * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. 469 * | | |Note: This bit is always 0 when it read back. 470 * |[1] |STOP |SHA/HMAC Engine Stop 471 * | | |0 = No effect. 472 * | | |1 = Stop SHA/HMAC engine. 473 * | | |Note: This bit is always 0 when it read back. 474 * |[4] |DMAFIRST |SHA/HMAC First Blockin Cascadefunction 475 * | | |This bit must be set as feeding in first byte of data. 476 * |[5] |DMALAST |SHA/HMAC Last Block 477 * | | |This bit must be set as feeding in last byte of data. 478 * |[6] |DMACSCAD |SHA/HMAC Engine DMA with Cascade Mode 479 * | | |0 = DMA cascade function Disabled. 480 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 481 * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Bit 482 * | | |0 = SHA/HMAC DMA engine Disabled. 483 * | | |SHA/HMAC engine operates in Non-DMA mode. The data need to be written in CRPT_HMAC_DATIN. 484 * | | |1 = SHA/HMAC DMA engine Enabled. 485 * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 486 * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes 487 * | | |0x0xx: SHA1-160 488 * | | |0x100: SHA2-256 489 * | | |0x101: SHA2-224 490 * | | |0x110: SHA2-512 491 * | | |0x111: SHA2-384 492 * | | |Note: These bits can be read and written. But writing tothem wouldnu2019t take effect as BUSY is 1.. 493 * | | |Note:When SM3EN=1, SHA/HMAC only execute SM3-256. 494 * |[11] |HMACEN |HMAC_SHA Engine Operating Mode 495 * | | |0 = Execute SHA function. 496 * | | |1 = Execute HMAC function. 497 * |[13] |SM3EN |SM3 Engine Enable Bit 498 * | | |0 = Execute other function. 499 * | | |1 = Execute SM3 function. 500 * |[20] |FBIN |Feedback Input to SHA/HMAC Via DMA Automatically 501 * | | |0 = Disable DMA automatical feedback input fucntion.. 502 * | | |1 = Enable DMA automatical feedback input fucntion when DMAEN = 1. 503 * |[21] |FBOUT |Feedback Output From SHA/HMAC Via DMA Automatically 504 * | | |0 = Disable DMA automatical feedback output fucntion.. 505 * | | |1 = Enable DMA automatical feedback output fucntion when DMAEN = 1. 506 * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap 507 * | | |0 = Keep the original order. 508 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 509 * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap 510 * | | |0 = Keep the original order. 511 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 512 * @var CRPT_T::HMAC_STS 513 * Offset: 0x304 SHA/HMAC Status Flag 514 * --------------------------------------------------------------------------------------------------- 515 * |Bits |Field |Descriptions 516 * | :----: | :----: | :---- | 517 * |[0] |BUSY |SHA/HMAC Engine Busy 518 * | | |0 = SHA/HMAC engine is idle or finished. 519 * | | |1 = SHA/HMAC engine is busy. 520 * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag 521 * | | |0 = SHA/HMAC DMA engine is idle or finished. 522 * | | |1 = SHA/HMAC DMA engine is busy. 523 * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag 524 * | | |0 = Show the SHA/HMAC engine access normal. 525 * | | |1 = Show the SHA/HMAC engine access error. 526 * |[9] |KSERR |HMAC Engine Access Key Store Error Flag 527 * | | |0 = No error. 528 * | | |1 = Access error will stop HMAC engine. 529 * |[16] |DATINREQ |SHA/HMAC Non-dMA Mode Data Input Request 530 * | | |0 = No effect. 531 * | | |1 = Request SHA/HMAC Non-DMA mode data input. 532 * @var CRPT_T::HMAC_DGST 533 * Offset: 0x308-0x344 SHA/HMAC Output Feedback Data 534 * --------------------------------------------------------------------------------------------------- 535 * |Bits |Field |Descriptions 536 * | :----: | :----: | :---- | 537 * |[31:0] |DGST |SHA/HMACOutput Feedback Data Output Register 538 * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. 539 * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. 540 * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. 541 * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. 542 * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. 543 * @var CRPT_T::HMAC_KEYCNT 544 * Offset: 0x348 SHA/HMAC Key Byte Count Register 545 * --------------------------------------------------------------------------------------------------- 546 * |Bits |Field |Descriptions 547 * | :----: | :----: | :---- | 548 * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count 549 * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates 550 * | | |The register is 32-bit and the maximum byte count is 4G bytes 551 * | | |It can be read and written. 552 * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesnu2019t affect the current SHA/HMAC operation 553 * | | |But the value of CRPT_HMAC_KEYCNT will be updated later on 554 * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. 555 * @var CRPT_T::HMAC_SADDR 556 * Offset: 0x34C SHA/HMAC DMA Source Address Register 557 * --------------------------------------------------------------------------------------------------- 558 * |Bits |Field |Descriptions 559 * | :----: | :----: | :---- | 560 * |[31:0] |SADDR |SHA/HMAC DMA Source Address 561 * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO 562 * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored 563 * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation 564 * | | |The start of source address should be located at word boundary 565 * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. 566 * | | |CRPT_HMAC_SADDR can be read and written 567 * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation 568 * | | |But the value of CRPT_HMAC_SADDR will be updated later on 569 * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. 570 * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. 571 * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. 572 * @var CRPT_T::HMAC_DMACNT 573 * Offset: 0x350 SHA/HMAC Byte Count Register 574 * --------------------------------------------------------------------------------------------------- 575 * |Bits |Field |Descriptions 576 * | :----: | :----: | :---- | 577 * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count 578 * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode 579 * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. 580 * | | |CRPT_HMAC_DMACNT can be read and written 581 * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation 582 * | | |But the value of CRPT_HMAC_DMACNT will be updated later on 583 * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. 584 * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. 585 * @var CRPT_T::HMAC_DATIN 586 * Offset: 0x354 SHA/HMAC Engine Non-dMA Mode Data Input Port Register 587 * --------------------------------------------------------------------------------------------------- 588 * |Bits |Field |Descriptions 589 * | :----: | :----: | :---- | 590 * |[31:0] |DATIN |SHA/HMAC Engine Input Port 591 * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS 592 * | | |Feed data as DATINREQ is 1. 593 * @var CRPT_T::HMAC_FDBCK 594 * Offset: 0x358-0x42C SHA/HMAC Output Feedback Data After SHA/HMAC Operation 595 * --------------------------------------------------------------------------------------------------- 596 * |Bits |Field |Descriptions 597 * | :----: | :----: | :---- | 598 * |[31:0] |FDBCK |SHA/HMAC Feedback Information 599 * | | |The feedback value is 1728 bits in size for SHA1/2. 600 * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. 601 * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block operation 602 * | | |Software can store that feedback value temporarily 603 * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. 604 * @var CRPT_T::HMAC_FBADDR 605 * Offset: 0x4FC SHA/HMAC DMA Feedback Address Register 606 * --------------------------------------------------------------------------------------------------- 607 * |Bits |Field |Descriptions 608 * | :----: | :----: | :---- | 609 * |[31:0] |FBADDR |SHA/HMAC DMA Feedback Address 610 * | | |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation 611 * | | |Based on the feedback address, the SHA/HMAC accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space 612 * | | |The start of feedback address should be located at word boundary 613 * | | |In other words, bit 1 and 0 of FBADDR are ignored. 614 * | | |FBADDR can be read and written. 615 * | | |In DMA mode, software can update the next CRPT_HMAC_FBADDR before triggering START. 616 * @var CRPT_T::ECC_CTL 617 * Offset: 0x800 ECC Control Register 618 * --------------------------------------------------------------------------------------------------- 619 * |Bits |Field |Descriptions 620 * | :----: | :----: | :---- | 621 * |[0] |START |ECC Accelerator Start 622 * | | |0 = No effect. 623 * | | |1 = Start ECC accelerator. BUSY flag will be set. 624 * | | |This bit is always 0 when it read back. 625 * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. 626 * |[1] |STOP |ECC Accelerator Stop 627 * | | |0 = No effect. 628 * | | |1 = Abort ECC accelerator and make it into idle state. 629 * | | |This bit is always 0 when it read back. 630 * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. 631 * |[3] |PFA2C |Primg Field Adder with 2Cycles 632 * | | |0 = cost1 cycle . 633 * | | |1 = cost 2 cycles. 634 * |[4] |ECDSAS |Generate S in ECDSA Signature Generation 635 * | | |0 = No effect. 636 * | | |1 = Formula for generating S. 637 * | | |POINTX1 = ((POINTX2 * POINTY1 + POINTY2 ) / POINTX1) % CURVEN. 638 * |[5] |ECDSAR |Generate R in ECDSA Signature Generation 639 * | | |0 = No effect. 640 * | | |1 = Formula for generating R. 641 * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). 642 * |[7] |DMAEN |ECC Accelerator DMA Enable Bit 643 * | | |0 = ECC DMA engine Disabled. 644 * | | |1 = ECC DMA engine Enabled. 645 * | | |Only when START and DMAEN are 1, ECC DMA engine will be active 646 * |[8] |FSEL |Field Selection 647 * | | |0 = Binary Field (GF(2m )). 648 * | | |1 = Prime Field (GF(p)). 649 * |[10:9] |ECCOP |Point Operation for BF and PF 650 * | | |00 = Point multiplication :. 651 * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). 652 * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). 653 * | | |10 = Point addition :. 654 * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. 655 * | | |(POINTX2, POINTY2) 656 * | | |11 = Point doubling :. 657 * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). 658 * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 659 * |[12:11] |MODOP |Modulus Operation for PF 660 * | | |00 = Division :. 661 * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. 662 * | | |01 = Multiplication :. 663 * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. 664 * | | |10 = Addition :. 665 * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. 666 * | | |11 = Subtraction :. 667 * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. 668 * | | |MODOP is active only when ECCOP = 01. 669 * |[13] |CSEL |Curve Selection 670 * | | |0 = NISTsuggested curve. 671 * | | |1 = Montgomery curve. 672 * |[14] |SCAP |Side-channel Attack Protection 673 * | | |0 = Full speed without side-channel protection. 674 * | | |1 = Less speed with side-channel protection. 675 * |[15] |SBM |Secure-boot Mode 676 * | | |0 = (POINTX1,POINTY1)from user data. 677 * | | |1 = (POINTX1,POINTY1)from secure boot key. 678 * |[16] |LDP1 |The Control Signal of RegisterPOINTX1and POINTY1for the xand Y Coordinate of the First Point 679 * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. 680 * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. 681 * |[17] |LDP2 |The Control Signal of Register POINTX2and POINTY2for the xand Y Coordinate of the Second Point 682 * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. 683 * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. 684 * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve 685 * | | |0 = The register for CURVEA is not modified by DMA or user. 686 * | | |1 = The register for CURVEA is modified by DMA or user. 687 * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve 688 * | | |0 = The register for CURVEB is not modified by DMA or user. 689 * | | |1 = The register for CURVEB is modified by DMA or user. 690 * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve 691 * | | |0 = The register for CURVEN is not modified by DMA or user. 692 * | | |1 = The register for CURVEN is modified by DMA or user. 693 * |[21] |LDK |The Control Signal of Register for SCALARK 694 * | | |0 = The register for SCALARK is not modified by DMA or user. 695 * | | |1 = The register for SCALARK is modified by DMA or user. 696 * |[31:22] |CURVEM |The key length of elliptic curve. 697 * @var CRPT_T::ECC_STS 698 * Offset: 0x804 ECC Status Register 699 * --------------------------------------------------------------------------------------------------- 700 * |Bits |Field |Descriptions 701 * | :----: | :----: | :---- | 702 * |[0] |BUSY |ECC Accelerator Busy Flag 703 * | | |0 = The ECC accelerator is idle or finished. 704 * | | |1 = The ECC accelerator is under processing and protects all registers. 705 * | | |Remember to clear ECC interrupt flag after ECC accelerator finished 706 * |[1] |DMABUSY |ECC DMA Busy Flag 707 * | | |0 = ECC DMA is idle or finished. 708 * | | |1 = ECC DMA is busy. 709 * |[16] |BUSERR |ECC DMA Access Bus Error Flag 710 * | | |0 = No error. 711 * | | |1 = Bus error will stop DMA operation and ECC accelerator.. 712 * |[17] |KSERR |ECC Engine Access Key Store Error Flag 713 * | | |0 = No error. 714 * | | |1 = Access error will stop ECC engine. 715 * @var CRPT_T::ECC_X1 716 * Offset: 0x808-0x84C ECC the X-coordinate Word of the First Point 717 * --------------------------------------------------------------------------------------------------- 718 * |Bits |Field |Descriptions 719 * | :----: | :----: | :---- | 720 * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point 721 * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 722 * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 723 * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 724 * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 725 * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 726 * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 727 * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 728 * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 729 * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 730 * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 731 * @var CRPT_T::ECC_Y1 732 * Offset: 0x850-0x894 ECC the Y-coordinate Word of the First Point 733 * --------------------------------------------------------------------------------------------------- 734 * |Bits |Field |Descriptions 735 * | :----: | :----: | :---- | 736 * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point 737 * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 738 * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 739 * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 740 * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 741 * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 742 * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 743 * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 744 * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 745 * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 746 * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 747 * @var CRPT_T::ECC_X2 748 * Offset: 0x898-0x8DC ECC the X-coordinate Word of the Second Point 749 * --------------------------------------------------------------------------------------------------- 750 * |Bits |Field |Descriptions 751 * | :----: | :----: | :---- | 752 * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point 753 * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 754 * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 755 * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 756 * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 757 * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 758 * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 759 * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 760 * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 761 * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 762 * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 763 * @var CRPT_T::ECC_Y2 764 * Offset: 0x8E0-0x924 ECC the Y-coordinate Word of the Second Point 765 * --------------------------------------------------------------------------------------------------- 766 * |Bits |Field |Descriptions 767 * | :----: | :----: | :---- | 768 * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point 769 * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 770 * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 771 * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 772 * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 773 * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 774 * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 775 * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 776 * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 777 * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 778 * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 779 * @var CRPT_T::ECC_A 780 * Offset: 0x928-0x96C ECC the Parameter CURVEA Word of Elliptic Curve 781 * --------------------------------------------------------------------------------------------------- 782 * |Bits |Field |Descriptions 783 * | :----: | :----: | :---- | 784 * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve 785 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). 786 * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 787 * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 788 * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 789 * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 790 * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 791 * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 792 * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 793 * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 794 * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 795 * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 796 * @var CRPT_T::ECC_B 797 * Offset: 0x970-0x9B4 ECC the Parameter CURVEB Word of Elliptic Curve 798 * --------------------------------------------------------------------------------------------------- 799 * |Bits |Field |Descriptions 800 * | :----: | :----: | :---- | 801 * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve 802 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). 803 * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 804 * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 805 * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 806 * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 807 * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 808 * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 809 * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 810 * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 811 * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 812 * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 813 * @var CRPT_T::ECC_N 814 * Offset: 0x9B8-0x9FC ECC the Parameter CURVEN Word of Elliptic Curve 815 * --------------------------------------------------------------------------------------------------- 816 * |Bits |Field |Descriptions 817 * | :----: | :----: | :---- | 818 * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve 819 * | | |In GF(p), CURVEN is the prime p. 820 * | | |In GF(2m), CURVEN is the irreducible polynomial. 821 * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 822 * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 823 * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 824 * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 825 * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 826 * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 827 * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 828 * | | |For P-256, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 829 * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 830 * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 831 * @var CRPT_T::ECC_K 832 * Offset: 0xA00-0xA44 ECC the Scalar SCALARK Word of Point Multiplication 833 * --------------------------------------------------------------------------------------------------- 834 * |Bits |Field |Descriptions 835 * | :----: | :----: | :---- | 836 * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication 837 * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. 838 * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 839 * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 840 * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 841 * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 842 * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 843 * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 844 * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 845 * | | |For P-256, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 846 * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 847 * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 848 * @var CRPT_T::ECC_SADDR 849 * Offset: 0xA48 ECC DMA Source Address Register 850 * --------------------------------------------------------------------------------------------------- 851 * |Bits |Field |Descriptions 852 * | :----: | :----: | :---- | 853 * |[31:0] |SADDR |ECC DMA Source Address 854 * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and ECC accelerator. 855 * | | |The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, 856 * | | |the ECC accelerator can read the DATA and PARAMETER from SRAM memory space and do ECC operation. 857 * | | |The start of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are ignored. 858 * | | |SADDR can be read and written. In DMA mode, software must update the CRYPTO_ECC_SADDR before triggering START. 859 * @var CRPT_T::ECC_DADDR 860 * Offset: 0xA4C ECC DMA Destination Address Register 861 * --------------------------------------------------------------------------------------------------- 862 * |Bits |Field |Descriptions 863 * | :----: | :----: | :---- | 864 * |[31:0] |DADDR |ECC DMA Destination Address 865 * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator 866 * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored 867 * | | |Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished 868 * | | |The start of destination address should be located at word boundary 869 * | | |That is, bit 1 and 0 of DADDR are ignored 870 * | | |DADDR can be read and written 871 * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START 872 * @var CRPT_T::ECC_STARTREG 873 * Offset: 0xA50 ECC Starting Address of Updated Registers 874 * --------------------------------------------------------------------------------------------------- 875 * |Bits |Field |Descriptions 876 * | :----: | :----: | :---- | 877 * |[31:0] |STARTREG |ECC Starting Address of Updated Registers 878 * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine 879 * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG, for example, to update input data from register CRPT_ECC POINTX1 880 * | | |Thus, the value of STARTREG is 0x808. 881 * @var CRPT_T::ECC_WORDCNT 882 * Offset: 0xA54 ECC DMA Word Count 883 * --------------------------------------------------------------------------------------------------- 884 * |Bits |Field |Descriptions 885 * | :----: | :----: | :---- | 886 * |[31:0] |WORDCNT |ECC DMA Word Count 887 * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode 888 * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144words 889 * | | |CRPT_ECC_WORDCNT can be read and written 890 * @var CRPT_T::RSA_CTL 891 * Offset: 0xB00 RSA Control Register 892 * --------------------------------------------------------------------------------------------------- 893 * |Bits |Field |Descriptions 894 * | :----: | :----: | :---- | 895 * |[0] |START |RSA Accelerator Start 896 * | | |0 = No effect. 897 * | | |1 = Start RSAaccelerator. BUSY flag will be set. 898 * | | |This bit is always 0 when it read back. 899 * | | |RSAaccelerator will ignore this START signal when BUSY flag is 1. 900 * |[1] |STOP |RSA Accelerator Stop 901 * | | |0 = No effect. 902 * | | |1 = Abort RSA accelerator and make it into initialstate. 903 * | | |This bit is always 0 when it read back. 904 * | | |Remember to clear RSA interrupt flag after stopping RSA accelerator. 905 * |[2] |CRT |CRT Enable Control 906 * | | |0 = CRT Disabled. 907 * | | |1 = CRT Enabled. 908 * | | |CRT is only used in decryption with key length 2048, 3072,4096 bits. 909 * |[3] |CRTBYP |CRT BypassEnable Control 910 * | | |0 = CRT Bypass Disabled. 911 * | | |1 = CRT Bypass Enabled. 912 * | | |CRT bypass is only used in CRT decryption with the same key. 913 * | | |Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption(means the second time to the latest time), but they canu2019t set CRTBYP to 1 in non-CRT mode. 914 * |[5:4] |KEYLENG |The Key Length of RSA Operation 915 * | | |00 = 1024bits. 916 * | | |01 = 2048bits. 917 * | | |10 = 3072bits. 918 * | | |11 = 4096bits. 919 * |[8] |SCAP |Side Channel Attack Protection Enable Control 920 * | | |0 = Side Channel Attack Protection Disabled. 921 * | | |1 = Side Channel Attack Protection Enabled. 922 * @var CRPT_T::RSA_STS 923 * Offset: 0xB04 RSA Status Register 924 * --------------------------------------------------------------------------------------------------- 925 * |Bits |Field |Descriptions 926 * | :----: | :----: | :---- | 927 * |[0] |BUSY |RSA Accelerator Busy Flag 928 * | | |0 = The RSA accelerator is idle or finished. 929 * | | |1 = The RSA accelerator is under processing and protects all registers. 930 * | | |Remember to clear RSA interrupt flag after RSA accelerator finished 931 * |[1] |DMABUSY |RSA DMA Busy Flag 932 * | | |0 = RSA DMA is idle or finished. 933 * | | |1 = RSA DMA is busy. 934 * |[16] |BUSERR |RSA DMA Access Bus Error Flag 935 * | | |0 = No error. 936 * | | |1 = Bus error will stop DMA operation and RSA accelerator. 937 * |[17] |CTLERR |RSA Control Register Error Flag 938 * | | |0 = No error. 939 * | | |1 = RSA control error. RSA will not start in the unsupported situation. 940 * | | |Note: If user use the control error condition, but donu2019t set START(CRPT_RSA_CTL[0]) to 1, CTLERR still be set to 1. 941 * |[18] |KSERR |RSA Engine Access Key Store Error Flag 942 * | | |0 = No error. 943 * | | |1 = Access error will stop RSA engine. 944 * @var CRPT_T::RSA_SADDR 945 * Offset: 0xB08-0xB18 RSA DMA Source Address Register 946 * --------------------------------------------------------------------------------------------------- 947 * |Bits |Field |Descriptions 948 * | :----: | :----: | :---- | 949 * |[31:0] |SADDR0 |RSA DMA Source Address Register0 950 * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. 951 * | | |This register is stored the address of RSA the Base of Exponentiation (M,N,E,p,q). 952 * @var CRPT_T::RSA_DADDR 953 * Offset: 0xB1C RSA DMA Destination Address Register 954 * --------------------------------------------------------------------------------------------------- 955 * |Bits |Field |Descriptions 956 * | :----: | :----: | :---- | 957 * |[31:0] |DADDR |RSA DMA Destination Address Register 958 * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. 959 * | | |This register is stored the address of RSA DMA Destination Address Register (Ans). 960 * @var CRPT_T::RSA_MADDR 961 * Offset: 0xB20-0xB38 RSA DMA Middle Address Register 962 * --------------------------------------------------------------------------------------------------- 963 * |Bits |Field |Descriptions 964 * | :----: | :----: | :---- | 965 * |[31:0] |MADDR |RSA DMA Middle Address Register 966 * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. 967 * | | |This register is stored the address of RSA CRT the Temporary Value (Cp -> Mp -> Sp, Cq -> Mq -> Sq, Dp, Dq, Rp, Rq, E'). 968 * @var CRPT_T::PRNG_KSCTL 969 * Offset: 0xF00 PRNG Key Control Register 970 * --------------------------------------------------------------------------------------------------- 971 * |Bits |Field |Descriptions 972 * | :----: | :----: | :---- | 973 * |[4:0] |NUM |Write Key Number 974 * | | |The key number is sent to key store 975 * | | |Note: Only for destination Is OTP of Key Store. 976 * |[16] |TRUST |Write Key Trust Selection Bit 977 * | | |0 = Set written key as the non-secure key. 978 * | | |1 = Set written key as the secure key. 979 * |[18] |PRIV |Privilege Key Selection Bit 980 * | | |0 = Set key as the non-privilege key. 981 * | | |1 = Set key as the privilege key. 982 * |[19] |ECDH |ECDH Control Bit 983 * | | |0 =reserved. 984 * | | |1 = key is written to key store and used in ECDH. 985 * | | |Note:When ECDH was set to u20181u2019, 1 986 * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) 987 * | | |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16]) 988 * | | |2 989 * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) 990 * | | |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy. 991 * |[20] |ECDSA |ECDSA Control Bit 992 * | | |0 =reserved. 993 * | | |1 = key is written to key store and used in ECDSA. 994 * | | |Note:When ECDSA was set to u20181u2019, 1 995 * | | |PRNG seed must from TRNGand key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) 996 * | | |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16]) 997 * | | |2.Key must in the interval [1, n-1] (the parameter n is from ECC) 998 * | | |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy. 999 * |[21] |WDST |Write Key Destination 1000 * | | |0 = key is written to registers CRPT_PRNG_KEYx. 1001 * | | |1 = key is written to key store. 1002 * |[23:22] |WSDST |Write Key Store Destination 1003 * | | |00 = key is written to the SRAM of key store. 1004 * | | |10 = key is written to the OTP of key store. 1005 * | | |Others = reserved. 1006 * |[26:24] |OWNER |Write Key Owner Selection Bits 1007 * | | |000 = Only for AES used. 1008 * | | |001 = Only for HMAC engine used. 1009 * | | |100 = Only for ECC engine used. 1010 * | | |101 = Only for CPU engine use. 1011 * | | |Others = reserved. 1012 * @var CRPT_T::PRNG_KSSTS 1013 * Offset: 0xF04 PRNG Key Status Register 1014 * --------------------------------------------------------------------------------------------------- 1015 * |Bits |Field |Descriptions 1016 * | :----: | :----: | :---- | 1017 * |[4:0] |NUM |Key Number 1018 * | | |The key number is generated by key store 1019 * |[16] |KCTLERR |PRNG Key Control Register Error Flag 1020 * | | |0 = No error. 1021 * | | |1 = PRNG key control error 1022 * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). 1023 * @var CRPT_T::AES_KSCTL 1024 * Offset: 0xF10 AES Key Control Register 1025 * --------------------------------------------------------------------------------------------------- 1026 * |Bits |Field |Descriptions 1027 * | :----: | :----: | :---- | 1028 * |[4:0] |NUM |Read Key Number 1029 * | | |The key number is sent to key store 1030 * |[5] |RSRC |Read Key Destination 1031 * | | |0 = key is read from registers CRPT_AESx_KEYx. 1032 * | | |1 = key is read from key store. 1033 * |[7:6] |RSSRC |Read Key Store Destination 1034 * | | |00 = key is read from the SRAM of key store. 1035 * | | |10 = key is read from the OTP of key store. 1036 * | | |Others = reserved. 1037 * @var CRPT_T::HMAC_KSCTL 1038 * Offset: 0xF30 HMAC Key Control Register 1039 * --------------------------------------------------------------------------------------------------- 1040 * |Bits |Field |Descriptions 1041 * | :----: | :----: | :---- | 1042 * |[4:0] |NUM |Read Key Number 1043 * | | |The key number is sent to key store 1044 * |[5] |RSRC |Read Key Destination 1045 * | | |0 = key is read from HMAC registers. 1046 * | | |1 = key is read from key store. 1047 * |[7:6] |RSSRC |Read Key Store Destination 1048 * | | |00 = key is read from the SRAM of key store. 1049 * | | |10 = key is read from the OTP of key store. 1050 * | | |Others = reserved. 1051 * @var CRPT_T::ECC_KSCTL 1052 * Offset: 0xF40 ECC Key Control Register 1053 * --------------------------------------------------------------------------------------------------- 1054 * |Bits |Field |Descriptions 1055 * | :----: | :----: | :---- | 1056 * |[4:0] |NUMK |Read Key Number K 1057 * | | |The key number of CRPT_ECC_K is sent to key store when RSRCK =1. 1058 * |[5] |RSRCK |Read Key Destinationfor Key Number K 1059 * | | |0 = key is read from ECC registers. 1060 * | | |1 = key is read from key store. 1061 * |[7:6] |RSSRCK |Read Key Store Destinationfor Key Number K 1062 * | | |00 = key is read from the SRAM of key store. 1063 * | | |10 = key is read from the OTP of key store. 1064 * | | |Others = reserved. 1065 * |[14] |ECDH |ECDH Control Bit 1066 * | | |0 =reserved. 1067 * | | |1 = Set ECC opereration is in ECDH 1068 * | | |When this bit and RSRCK are equal to 0x1, ECC will read ECDH private key to CRPT_ECC_K from key store. 1069 * |[16] |TRUST |Write Key Trust Selection Bit 1070 * | | |0 = Set ECDH written key as the non-secure key. 1071 * | | |1 = Set ECDH written key as the secure key. 1072 * |[18] |PRIV |Write Key Privilege Selection Bit 1073 * | | |0 = Set ECDH written key as the non-privilege key. 1074 * | | |1 = Set ECDHwritten key as the privilege key. 1075 * |[20] |XY |ECDH Output Select Bit 1076 * | | |0 =The ECDH written key is from X-coordinate Value. 1077 * | | |1 = The ECDH written key is from Y-coordinate Value. 1078 * |[21] |WDST |Write Key Destination 1079 * | | |0 = The ECDH writtenkey is in registers CRPT_ECC_X1 and CRPT_ECC_Y. 1080 * | | |1 = The ECDH writtenkey is written to key store. 1081 * |[23:22] |WSDST |Write Key Store Destination 1082 * | | |00 = The ECDH writtenkey is written to the SRAM of key store. 1083 * | | |10 = The ECDH writtenkey is written to the OTP of key store. 1084 * | | |Others = reserved. 1085 * |[26:24] |OWNER |Write Key Owner Selection Bits 1086 * | | |000 = The ECDH written key is only for AES used. 1087 * | | |001 = The ECDH written key is only for HMAC engine used. 1088 * | | |100 = The ECDH written key is only for ECC engine used. 1089 * | | |101 = The ECDH written key is only for CPU engine use. 1090 * | | |Others = reserved. 1091 * @var CRPT_T::ECC_KSSTS 1092 * Offset: 0xF44 ECC Key Status Register 1093 * --------------------------------------------------------------------------------------------------- 1094 * |Bits |Field |Descriptions 1095 * | :----: | :----: | :---- | 1096 * |[4:0] |NUM |Key Number 1097 * | | |The key number is generated by key store after ECDH. 1098 * @var CRPT_T::ECC_KSXY 1099 * Offset: 0xF48 ECC XY Number Register 1100 * --------------------------------------------------------------------------------------------------- 1101 * |Bits |Field |Descriptions 1102 * | :----: | :----: | :---- | 1103 * |[4:0] |NUMX |Read Key Number X 1104 * | | |The key number of CRPT_ECC_X1 is sent to key store when RSRCXY =1. 1105 * |[5] |RSRCXY |Read Key Source for Key Number xand Y 1106 * | | |0 = key is read from ECC registers. 1107 * | | |1 = key is read from key store. 1108 * |[7:6] |RSSRCX |Read Key Store Source for Key Number X 1109 * | | |00 = key is read from the SRAM of key store. 1110 * | | |10 = key is read from the OTP of key store. 1111 * | | |Others = reserved. 1112 * |[12:8] |NUMY |Read Key Number Y 1113 * | | |The key number of CRPT_ECC_Y1 is sent to key store when RSRCXY =1. 1114 * |[15:14] |RSSRCY |Read Key Store Source for Key Number Y 1115 * | | |00 = key is read from the SRAM of key store. 1116 * | | |10 = key is read from the OTP of key store. 1117 * | | |Others = reserved. 1118 * @var CRPT_T::RSA_KSCTL 1119 * Offset: 0xF50 RSA Key Control Register 1120 * --------------------------------------------------------------------------------------------------- 1121 * |Bits |Field |Descriptions 1122 * | :----: | :----: | :---- | 1123 * |[4:0] |NUM |Read Key Number 1124 * | | |The key number is sent to key store 1125 * |[5] |RSRC |Read Key Destination 1126 * | | |0 = key is read from RSA engine. 1127 * | | |1 = key is read from key store. 1128 * |[7:6] |RSSRC |Read Key Store Destination 1129 * | | |00 = key is read from the SRAM of key store. 1130 * | | |10 = key is read from the OTP of key store. 1131 * | | |Others = reserved. 1132 * |[12:8] |BKNUM |Read Exponent Blind Key Number 1133 * | | |The key number is sent to key store, and its destination always be the SRAM of key store 1134 * | | |CPU canu2019t read the exponent blind key. 1135 * | | |Note:Use this key number, only when executing SCA protection but no-CRT mode. 1136 * @var CRPT_T::RSA_KSSTS 1137 * Offset: 0xF54-0xF58 RSA Key Status Register 1138 * --------------------------------------------------------------------------------------------------- 1139 * |Bits |Field |Descriptions 1140 * | :----: | :----: | :---- | 1141 * |[4:0] |NUM0 |Key Number0 1142 * | | |The key number is generated by key store, RSA can get complete p by key number in Key Store while operating. 1143 * |[12:8] |NUM1 |Key Number1 1144 * | | |The key number is generated by key store, RSA can get complete q by key number in Key Store while operating. 1145 * |[20:16] |NUM2 |Key Number2 1146 * | | |The key number is generated by key store, RSA can get or store Cp by key number in Key Store while operating. 1147 * |[28:24] |NUM3 |Key Number3 1148 * | | |The key number is generated by key store, RSA can get or store Cq by key number in Key Store while operating. 1149 * |[36:32] |NUM4 |Key Number4 1150 * | | |The key number is generated by key store, RSA can get or store Dp by key number in Key Store while operating. 1151 * |[44:40] |NUM5 |Key Number5 1152 * | | |The key number is generated by key store, RSA can get or store Dq by key number in Key Store while operating. 1153 * |[52:48] |NUM6 |Key Number6 1154 * | | |The key number is generated by key store, RSA can get or store Rp by key number in Key Store while operating. 1155 * |[60:56] |NUM7 |Key Number7 1156 * | | |The key number is generated by key store, RSA can get or store Rq by key number in Key Store while operating. 1157 */ 1158 __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ 1159 __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ 1160 __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ 1161 __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ 1162 __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ 1163 __I uint32_t PRNG_STS; /*!< [0x0030] PRNG Status Register */ 1164 __I uint32_t RESERVE0[7]; 1165 __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ 1166 __I uint32_t RESERVE1[8]; 1167 __IO uint32_t AES_GCM_IVCNT[2]; /*!< [0x0080] ~ [0x0084] AES GCM IV Byte Count Register 0 */ 1168 __IO uint32_t AES_GCM_ACNT[2]; /*!< [0x0088] ~ [0x008c] AES GCM A Byte Count Register 0 */ 1169 __IO uint32_t AES_GCM_PCNT[2]; /*!< [0x0090] ~ [0x0094] AES GCM P Byte Count Register 0 */ 1170 __I uint32_t RESERVE2[2]; 1171 __IO uint32_t AES_FBADDR; /*!< [0x00a0] AES DMA Feedback Address Register */ 1172 __I uint32_t RESERVE3[23]; 1173 __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ 1174 __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ 1175 __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ 1176 __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ 1177 __IO uint32_t AES_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ 1178 __IO uint32_t AES_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ 1179 __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ 1180 __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ 1181 __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ 1182 __I uint32_t RESERVE4[109]; 1183 __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ 1184 __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ 1185 __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ 1186 __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ 1187 __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ 1188 __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ 1189 __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-dMA Mode Data Input Port Register */ 1190 __IO uint32_t HMAC_FDBCK[54]; /*!< [0x0358] ~ [0x042c] SHA/HMAC Output Feedback Data 0After SHA/HMAC Operation */ 1191 __I uint32_t RESERVE5[51]; 1192 __IO uint32_t HMAC_FBADDR; /*!< [0x04fc] SHA/HMAC DMA Feedback Address Register */ 1193 __I uint32_t RESERVE6[192]; 1194 __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ 1195 __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ 1196 __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC the X-coordinate Word0 of the First Point */ 1197 __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ 1198 __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ 1199 __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ 1200 __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ 1201 __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ 1202 __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ 1203 __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ 1204 __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ 1205 __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ 1206 __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ 1207 __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ 1208 __I uint32_t RESERVE7[42]; 1209 __IO uint32_t RSA_CTL; /*!< [0x0b00] RSA Control Register */ 1210 __I uint32_t RSA_STS; /*!< [0x0b04] RSA Status Register */ 1211 __IO uint32_t RSA_SADDR[5]; /*!< [0x0b08] ~ [0x0b18] RSA DMA Source Address Register0 */ 1212 __IO uint32_t RSA_DADDR; /*!< [0x0b1c] RSA DMA Destination Address Register */ 1213 __IO uint32_t RSA_MADDR[7]; /*!< [0x0b20] ~ [0x0b38] RSA DMA Middle Address Register0 */ 1214 __I uint32_t RESERVE8[241]; 1215 __O uint32_t PRNG_KSCTL; /*!< [0x0f00] PRNG Key Control Register */ 1216 __I uint32_t PRNG_KSSTS; /*!< [0x0f04] PRNG Key Status Register */ 1217 __I uint32_t RESERVE9[2]; 1218 __O uint32_t AES_KSCTL; /*!< [0x0f10] AES Key Control Register */ 1219 __I uint32_t RESERVE10[7]; 1220 __O uint32_t HMAC_KSCTL; /*!< [0x0f30] HMAC Key Control Register */ 1221 __I uint32_t RESERVE11[3]; 1222 __O uint32_t ECC_KSCTL; /*!< [0x0f40] ECC Key Control Register */ 1223 __I uint32_t ECC_KSSTS; /*!< [0x0f44] ECC Key Status Register */ 1224 __O uint32_t ECC_KSXY; /*!< [0x0f48] ECC XY Number Register */ 1225 __I uint32_t RESERVE12[1]; 1226 __O uint32_t RSA_KSCTL; /*!< [0x0f50] RSA Key Control Register */ 1227 __IO uint32_t RSA_KSSTS[2]; /*!< [0x0f54] ~ [0x0f58] RSA Key Status Register 0 */ 1228 __I uint32_t RESERVE13[40]; 1229 1230 } CRPT_T; 1231 1232 /** 1233 @addtogroup CRPT_CONST CRYPTO Bit Field Definition 1234 Constant Definitions for CRYPTO Controller 1235 @{ 1236 */ 1237 1238 #define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ 1239 #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ 1240 1241 #define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ 1242 #define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ 1243 1244 #define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ 1245 #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ 1246 1247 #define CRPT_INTEN_PRNGEIEN_Pos (17) /*!< CRPT_T::INTEN: PRNGEIEN Position */ 1248 #define CRPT_INTEN_PRNGEIEN_Msk (0x1ul << CRPT_INTEN_PRNGEIEN_Pos) /*!< CRPT_T::INTEN: PRNGEIEN Mask */ 1249 1250 #define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ 1251 #define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ 1252 1253 #define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ 1254 #define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ 1255 1256 #define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ 1257 #define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ 1258 1259 #define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ 1260 #define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ 1261 1262 #define CRPT_INTEN_RSAIEN_Pos (30) /*!< CRPT_T::INTEN: RSAIEN Position */ 1263 #define CRPT_INTEN_RSAIEN_Msk (0x1ul << CRPT_INTEN_RSAIEN_Pos) /*!< CRPT_T::INTEN: RSAIEN Mask */ 1264 1265 #define CRPT_INTEN_RSAEIEN_Pos (31) /*!< CRPT_T::INTEN: RSAEIEN Position */ 1266 #define CRPT_INTEN_RSAEIEN_Msk (0x1ul << CRPT_INTEN_RSAEIEN_Pos) /*!< CRPT_T::INTEN: RSAEIEN Mask */ 1267 1268 #define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ 1269 #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ 1270 1271 #define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ 1272 #define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ 1273 1274 #define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ 1275 #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ 1276 1277 #define CRPT_INTSTS_PRNGEIF_Pos (17) /*!< CRPT_T::INTSTS: PRNGEIF Position */ 1278 #define CRPT_INTSTS_PRNGEIF_Msk (0x1ul << CRPT_INTSTS_PRNGEIF_Pos) /*!< CRPT_T::INTSTS: PRNGEIF Mask */ 1279 1280 #define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ 1281 #define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ 1282 1283 #define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ 1284 #define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ 1285 1286 #define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ 1287 #define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ 1288 1289 #define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ 1290 #define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ 1291 1292 #define CRPT_INTSTS_RSAIF_Pos (30) /*!< CRPT_T::INTSTS: RSAIF Position */ 1293 #define CRPT_INTSTS_RSAIF_Msk (0x1ul << CRPT_INTSTS_RSAIF_Pos) /*!< CRPT_T::INTSTS: RSAIF Mask */ 1294 1295 #define CRPT_INTSTS_RSAEIF_Pos (31) /*!< CRPT_T::INTSTS: RSAEIF Position */ 1296 #define CRPT_INTSTS_RSAEIF_Msk (0x1ul << CRPT_INTSTS_RSAEIF_Pos) /*!< CRPT_T::INTSTS: RSAEIF Mask */ 1297 1298 #define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ 1299 #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ 1300 1301 #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ 1302 #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ 1303 1304 #define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ 1305 #define CRPT_PRNG_CTL_KEYSZ_Msk (0xful << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ 1306 1307 #define CRPT_PRNG_CTL_SEEDSEL_Pos (6) /*!< CRPT_T::PRNG_CTL: SEEDSEL Position */ 1308 #define CRPT_PRNG_CTL_SEEDSEL_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSEL_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSEL Mask */ 1309 1310 #define CRPT_PRNG_CTL_SEEDSRC_Pos (7) /*!< CRPT_T::PRNG_CTL: SEEDSRC Position */ 1311 #define CRPT_PRNG_CTL_SEEDSRC_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSRC_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSRC Mask */ 1312 1313 #define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ 1314 #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ 1315 1316 #define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ 1317 #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ 1318 1319 #define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY0: KEY Position */ 1320 #define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT_T::PRNG_KEY0: KEY Mask */ 1321 1322 #define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY1: KEY Position */ 1323 #define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT_T::PRNG_KEY1: KEY Mask */ 1324 1325 #define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY2: KEY Position */ 1326 #define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT_T::PRNG_KEY2: KEY Mask */ 1327 1328 #define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY3: KEY Position */ 1329 #define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT_T::PRNG_KEY3: KEY Mask */ 1330 1331 #define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY4: KEY Position */ 1332 #define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT_T::PRNG_KEY4: KEY Mask */ 1333 1334 #define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY5: KEY Position */ 1335 #define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT_T::PRNG_KEY5: KEY Mask */ 1336 1337 #define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY6: KEY Position */ 1338 #define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT_T::PRNG_KEY6: KEY Mask */ 1339 1340 #define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY7: KEY Position */ 1341 #define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT_T::PRNG_KEY7: KEY Mask */ 1342 1343 #define CRPT_PRNG_STS_BUSY_Pos (0) /*!< CRPT_T::PRNG_STS: BUSY Position */ 1344 #define CRPT_PRNG_STS_BUSY_Msk (0x1ul << CRPT_PRNG_STS_BUSY_Pos) /*!< CRPT_T::PRNG_STS: BUSY Mask */ 1345 1346 #define CRPT_PRNG_STS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_STS: KCTLERR Position */ 1347 #define CRPT_PRNG_STS_KCTLERR_Msk (0x1ul << CRPT_PRNG_STS_KCTLERR_Pos) /*!< CRPT_T::PRNG_STS: KCTLERR Mask */ 1348 1349 #define CRPT_PRNG_STS_KSERR_Pos (17) /*!< CRPT_T::PRNG_STS: KSERR Position */ 1350 #define CRPT_PRNG_STS_KSERR_Msk (0x1ul << CRPT_PRNG_STS_KSERR_Pos) /*!< CRPT_T::PRNG_STS: KSERR Mask */ 1351 1352 #define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK0: FDBCK Position */ 1353 #define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK0: FDBCK Mask */ 1354 1355 #define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK1: FDBCK Position */ 1356 #define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK1: FDBCK Mask */ 1357 1358 #define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK2: FDBCK Position */ 1359 #define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK2: FDBCK Mask */ 1360 1361 #define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK3: FDBCK Position */ 1362 #define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK3: FDBCK Mask */ 1363 1364 #define CRPT_AES_GCM_IVCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Position */ 1365 #define CRPT_AES_GCM_IVCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_IVCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Mask */ 1366 1367 #define CRPT_AES_GCM_IVCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Position */ 1368 #define CRPT_AES_GCM_IVCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_IVCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Mask */ 1369 1370 #define CRPT_AES_GCM_ACNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT0: CNT Position */ 1371 #define CRPT_AES_GCM_ACNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_ACNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT0: CNT Mask */ 1372 1373 #define CRPT_AES_GCM_ACNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT1: CNT Position */ 1374 #define CRPT_AES_GCM_ACNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_ACNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT1: CNT Mask */ 1375 1376 #define CRPT_AES_GCM_PCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT0: CNT Position */ 1377 #define CRPT_AES_GCM_PCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_PCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT0: CNT Mask */ 1378 1379 #define CRPT_AES_GCM_PCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT1: CNT Position */ 1380 #define CRPT_AES_GCM_PCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_PCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT1: CNT Mask */ 1381 1382 #define CRPT_AES_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::AES_FBADDR: FBADDR Position */ 1383 #define CRPT_AES_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_AES_FBADDR_FBADDR_Pos) /*!< CRPT_T::AES_FBADDR: FBADDR Mask */ 1384 1385 #define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ 1386 #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ 1387 1388 #define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ 1389 #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ 1390 1391 #define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ 1392 #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ 1393 1394 #define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ 1395 #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ 1396 1397 #define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ 1398 #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ 1399 1400 #define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ 1401 #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ 1402 1403 #define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ 1404 #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ 1405 1406 #define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRYPTO Position */ 1407 #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRYPTO Mask */ 1408 1409 #define CRPT_AES_CTL_SM4EN_Pos (17) /*!< CRPT_T::AES_CTL: SM4EN Position */ 1410 #define CRPT_AES_CTL_SM4EN_Msk (0x1ul << CRPT_AES_CTL_SM4EN_Pos) /*!< CRPT_T::AES_CTL: SM4EN Mask */ 1411 1412 #define CRPT_AES_CTL_FBIN_Pos (20) /*!< CRPT_T::AES_CTL: FBIN Position */ 1413 #define CRPT_AES_CTL_FBIN_Msk (0x1ul << CRPT_AES_CTL_FBIN_Pos) /*!< CRPT_T::AES_CTL: FBIN Mask */ 1414 1415 #define CRPT_AES_CTL_FBOUT_Pos (21) /*!< CRPT_T::AES_CTL: FBOUT Position */ 1416 #define CRPT_AES_CTL_FBOUT_Msk (0x1ul << CRPT_AES_CTL_FBOUT_Pos) /*!< CRPT_T::AES_CTL: FBOUT Mask */ 1417 1418 #define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ 1419 #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ 1420 1421 #define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ 1422 #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ 1423 1424 #define CRPT_AES_CTL_KOUTSWAP_Pos (24) /*!< CRPT_T::AES_CTL: KOUTSWAP Position */ 1425 #define CRPT_AES_CTL_KOUTSWAP_Msk (0x1ul << CRPT_AES_CTL_KOUTSWAP_Pos) /*!< CRPT_T::AES_CTL: KOUTSWAP Mask */ 1426 1427 #define CRPT_AES_CTL_KINSWAP_Pos (25) /*!< CRPT_T::AES_CTL: KINSWAP Position */ 1428 #define CRPT_AES_CTL_KINSWAP_Msk (0x1ul << CRPT_AES_CTL_KINSWAP_Pos) /*!< CRPT_T::AES_CTL: KINSWAP Mask */ 1429 1430 #define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ 1431 #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ 1432 1433 #define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ 1434 #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ 1435 1436 #define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ 1437 #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ 1438 1439 #define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ 1440 #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ 1441 1442 #define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ 1443 #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ 1444 1445 #define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ 1446 #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ 1447 1448 #define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ 1449 #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ 1450 1451 #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/ 1452 #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ 1453 1454 #define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ 1455 #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ 1456 1457 #define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ 1458 #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ 1459 1460 #define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ 1461 #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ 1462 1463 #define CRPT_AES_STS_KSERR_Pos (21) /*!< CRPT_T::AES_STS: KSERR Position */ 1464 #define CRPT_AES_STS_KSERR_Msk (0x1ul << CRPT_AES_STS_KSERR_Pos) /*!< CRPT_T::AES_STS: KSERR Mask */ 1465 1466 #define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ 1467 #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ 1468 1469 #define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ 1470 #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ 1471 1472 #define CRPT_AES_KEY0_KEY_Pos (0) /*!< CRPT_T::AES_KEY0: KEY Position */ 1473 #define CRPT_AES_KEY0_KEY_Msk (0xfffffffful << CRPT_AES_KEY0_KEY_Pos) /*!< CRPT_T::AES_KEY0: KEY Mask */ 1474 1475 #define CRPT_AES_KEY1_KEY_Pos (0) /*!< CRPT_T::AES_KEY1: KEY Position */ 1476 #define CRPT_AES_KEY1_KEY_Msk (0xfffffffful << CRPT_AES_KEY1_KEY_Pos) /*!< CRPT_T::AES_KEY1: KEY Mask */ 1477 1478 #define CRPT_AES_KEY2_KEY_Pos (0) /*!< CRPT_T::AES_KEY2: KEY Position */ 1479 #define CRPT_AES_KEY2_KEY_Msk (0xfffffffful << CRPT_AES_KEY2_KEY_Pos) /*!< CRPT_T::AES_KEY2: KEY Mask */ 1480 1481 #define CRPT_AES_KEY3_KEY_Pos (0) /*!< CRPT_T::AES_KEY3: KEY Position */ 1482 #define CRPT_AES_KEY3_KEY_Msk (0xfffffffful << CRPT_AES_KEY3_KEY_Pos) /*!< CRPT_T::AES_KEY3: KEY Mask */ 1483 1484 #define CRPT_AES_KEY4_KEY_Pos (0) /*!< CRPT_T::AES_KEY4: KEY Position */ 1485 #define CRPT_AES_KEY4_KEY_Msk (0xfffffffful << CRPT_AES_KEY4_KEY_Pos) /*!< CRPT_T::AES_KEY4: KEY Mask */ 1486 1487 #define CRPT_AES_KEY5_KEY_Pos (0) /*!< CRPT_T::AES_KEY5: KEY Position */ 1488 #define CRPT_AES_KEY5_KEY_Msk (0xfffffffful << CRPT_AES_KEY5_KEY_Pos) /*!< CRPT_T::AES_KEY5: KEY Mask */ 1489 1490 #define CRPT_AES_KEY6_KEY_Pos (0) /*!< CRPT_T::AES_KEY6: KEY Position */ 1491 #define CRPT_AES_KEY6_KEY_Msk (0xfffffffful << CRPT_AES_KEY6_KEY_Pos) /*!< CRPT_T::AES_KEY6: KEY Mask */ 1492 1493 #define CRPT_AES_KEY7_KEY_Pos (0) /*!< CRPT_T::AES_KEY7: KEY Position */ 1494 #define CRPT_AES_KEY7_KEY_Msk (0xfffffffful << CRPT_AES_KEY7_KEY_Pos) /*!< CRPT_T::AES_KEY7: KEY Mask */ 1495 1496 #define CRPT_AES_IV0_IV_Pos (0) /*!< CRPT_T::AES_IV0: IV Position */ 1497 #define CRPT_AES_IV0_IV_Msk (0xfffffffful << CRPT_AES_IV0_IV_Pos) /*!< CRPT_T::AES_IV0: IV Mask */ 1498 1499 #define CRPT_AES_IV1_IV_Pos (0) /*!< CRPT_T::AES_IV1: IV Position */ 1500 #define CRPT_AES_IV1_IV_Msk (0xfffffffful << CRPT_AES_IV1_IV_Pos) /*!< CRPT_T::AES_IV1: IV Mask */ 1501 1502 #define CRPT_AES_IV2_IV_Pos (0) /*!< CRPT_T::AES_IV2: IV Position */ 1503 #define CRPT_AES_IV2_IV_Msk (0xfffffffful << CRPT_AES_IV2_IV_Pos) /*!< CRPT_T::AES_IV2: IV Mask */ 1504 1505 #define CRPT_AES_IV3_IV_Pos (0) /*!< CRPT_T::AES_IV3: IV Position */ 1506 #define CRPT_AES_IV3_IV_Msk (0xfffffffful << CRPT_AES_IV3_IV_Pos) /*!< CRPT_T::AES_IV3: IV Mask */ 1507 1508 #define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */ 1509 #define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */ 1510 1511 #define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */ 1512 #define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */ 1513 1514 #define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */ 1515 #define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */ 1516 1517 #define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ 1518 #define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ 1519 1520 #define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ 1521 #define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ 1522 1523 #define CRPT_HMAC_CTL_DMAFIRST_Pos (4) /*!< CRPT_T::HMAC_CTL: DMAFIRST Position */ 1524 #define CRPT_HMAC_CTL_DMAFIRST_Msk (0x1ul << CRPT_HMAC_CTL_DMAFIRST_Pos) /*!< CRPT_T::HMAC_CTL: DMAFIRST Mask */ 1525 1526 #define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ 1527 #define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ 1528 1529 #define CRPT_HMAC_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::HMAC_CTL: DMACSCAD Position */ 1530 #define CRPT_HMAC_CTL_DMACSCAD_Msk (0x1ul << CRPT_HMAC_CTL_DMACSCAD_Pos) /*!< CRPT_T::HMAC_CTL: DMACSCAD Mask */ 1531 1532 #define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ 1533 #define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ 1534 1535 #define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ 1536 #define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ 1537 1538 #define CRPT_HMAC_CTL_HMACEN_Pos (11) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ 1539 #define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ 1540 1541 #define CRPT_HMAC_CTL_SM3EN_Pos (13) /*!< CRPT_T::HMAC_CTL: SM3EN Position */ 1542 #define CRPT_HMAC_CTL_SM3EN_Msk (0x1ul << CRPT_HMAC_CTL_SM3EN_Pos) /*!< CRPT_T::HMAC_CTL: SM3EN Mask */ 1543 1544 #define CRPT_HMAC_CTL_FBIN_Pos (20) /*!< CRPT_T::HMAC_CTL: FBIN Position */ 1545 #define CRPT_HMAC_CTL_FBIN_Msk (0x1ul << CRPT_HMAC_CTL_FBIN_Pos) /*!< CRPT_T::HMAC_CTL: FBIN Mask */ 1546 1547 #define CRPT_HMAC_CTL_FBOUT_Pos (21) /*!< CRPT_T::HMAC_CTL: FBOUT Position */ 1548 #define CRPT_HMAC_CTL_FBOUT_Msk (0x1ul << CRPT_HMAC_CTL_FBOUT_Pos) /*!< CRPT_T::HMAC_CTL: FBOUT Mask */ 1549 1550 #define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ 1551 #define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ 1552 1553 #define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ 1554 #define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ 1555 1556 #define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ 1557 #define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ 1558 1559 #define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ 1560 #define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ 1561 1562 #define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ 1563 #define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ 1564 1565 #define CRPT_HMAC_STS_KSERR_Pos (9) /*!< CRPT_T::HMAC_STS: KSERR Position */ 1566 #define CRPT_HMAC_STS_KSERR_Msk (0x1ul << CRPT_HMAC_STS_KSERR_Pos) /*!< CRPT_T::HMAC_STS: KSERR Mask */ 1567 1568 #define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ 1569 #define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ 1570 1571 #define CRPT_HMAC_DGST0_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST0: DGST Position */ 1572 #define CRPT_HMAC_DGST0_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST0_DGST_Pos) /*!< CRPT_T::HMAC_DGST0: DGST Mask */ 1573 1574 #define CRPT_HMAC_DGST1_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST1: DGST Position */ 1575 #define CRPT_HMAC_DGST1_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST1_DGST_Pos) /*!< CRPT_T::HMAC_DGST1: DGST Mask */ 1576 1577 #define CRPT_HMAC_DGST2_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST2: DGST Position */ 1578 #define CRPT_HMAC_DGST2_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST2_DGST_Pos) /*!< CRPT_T::HMAC_DGST2: DGST Mask */ 1579 1580 #define CRPT_HMAC_DGST3_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST3: DGST Position */ 1581 #define CRPT_HMAC_DGST3_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST3_DGST_Pos) /*!< CRPT_T::HMAC_DGST3: DGST Mask */ 1582 1583 #define CRPT_HMAC_DGST4_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST4: DGST Position */ 1584 #define CRPT_HMAC_DGST4_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST4_DGST_Pos) /*!< CRPT_T::HMAC_DGST4: DGST Mask */ 1585 1586 #define CRPT_HMAC_DGST5_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST5: DGST Position */ 1587 #define CRPT_HMAC_DGST5_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST5_DGST_Pos) /*!< CRPT_T::HMAC_DGST5: DGST Mask */ 1588 1589 #define CRPT_HMAC_DGST6_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST6: DGST Position */ 1590 #define CRPT_HMAC_DGST6_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST6_DGST_Pos) /*!< CRPT_T::HMAC_DGST6: DGST Mask */ 1591 1592 #define CRPT_HMAC_DGST7_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST7: DGST Position */ 1593 #define CRPT_HMAC_DGST7_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST7_DGST_Pos) /*!< CRPT_T::HMAC_DGST7: DGST Mask */ 1594 1595 #define CRPT_HMAC_DGST8_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST8: DGST Position */ 1596 #define CRPT_HMAC_DGST8_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST8_DGST_Pos) /*!< CRPT_T::HMAC_DGST8: DGST Mask */ 1597 1598 #define CRPT_HMAC_DGST9_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST9: DGST Position */ 1599 #define CRPT_HMAC_DGST9_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST9_DGST_Pos) /*!< CRPT_T::HMAC_DGST9: DGST Mask */ 1600 1601 #define CRPT_HMAC_DGST10_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST10: DGST Position */ 1602 #define CRPT_HMAC_DGST10_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST10_DGST_Pos) /*!< CRPT_T::HMAC_DGST10: DGST Mask */ 1603 1604 #define CRPT_HMAC_DGST11_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST11: DGST Position */ 1605 #define CRPT_HMAC_DGST11_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST11_DGST_Pos) /*!< CRPT_T::HMAC_DGST11: DGST Mask */ 1606 1607 #define CRPT_HMAC_DGST12_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST12: DGST Position */ 1608 #define CRPT_HMAC_DGST12_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST12_DGST_Pos) /*!< CRPT_T::HMAC_DGST12: DGST Mask */ 1609 1610 #define CRPT_HMAC_DGST13_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST13: DGST Position */ 1611 #define CRPT_HMAC_DGST13_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST13_DGST_Pos) /*!< CRPT_T::HMAC_DGST13: DGST Mask */ 1612 1613 #define CRPT_HMAC_DGST14_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST14: DGST Position */ 1614 #define CRPT_HMAC_DGST14_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST14_DGST_Pos) /*!< CRPT_T::HMAC_DGST14: DGST Mask */ 1615 1616 #define CRPT_HMAC_DGST15_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST15: DGST Position */ 1617 #define CRPT_HMAC_DGST15_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST15_DGST_Pos) /*!< CRPT_T::HMAC_DGST15: DGST Mask */ 1618 1619 #define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ 1620 #define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ 1621 1622 #define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ 1623 #define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ 1624 1625 #define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ 1626 #define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ 1627 1628 #define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ 1629 #define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ 1630 1631 #define CRPT_HMAC_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Position */ 1632 #define CRPT_HMAC_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK0_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Mask */ 1633 1634 #define CRPT_HMAC_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Position */ 1635 #define CRPT_HMAC_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK1_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Mask */ 1636 1637 #define CRPT_HMAC_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Position */ 1638 #define CRPT_HMAC_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK2_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Mask */ 1639 1640 #define CRPT_HMAC_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Position */ 1641 #define CRPT_HMAC_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK3_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Mask */ 1642 1643 #define CRPT_HMAC_FDBCK4_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Position */ 1644 #define CRPT_HMAC_FDBCK4_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK4_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Mask */ 1645 1646 #define CRPT_HMAC_FDBCK5_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Position */ 1647 #define CRPT_HMAC_FDBCK5_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK5_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Mask */ 1648 1649 #define CRPT_HMAC_FDBCK6_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Position */ 1650 #define CRPT_HMAC_FDBCK6_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK6_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Mask */ 1651 1652 #define CRPT_HMAC_FDBCK7_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Position */ 1653 #define CRPT_HMAC_FDBCK7_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK7_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Mask */ 1654 1655 #define CRPT_HMAC_FDBCK8_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Position */ 1656 #define CRPT_HMAC_FDBCK8_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK8_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Mask */ 1657 1658 #define CRPT_HMAC_FDBCK9_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Position */ 1659 #define CRPT_HMAC_FDBCK9_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK9_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Mask */ 1660 1661 #define CRPT_HMAC_FDBCK10_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Position */ 1662 #define CRPT_HMAC_FDBCK10_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK10_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Mask */ 1663 1664 #define CRPT_HMAC_FDBCK11_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Position */ 1665 #define CRPT_HMAC_FDBCK11_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK11_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Mask */ 1666 1667 #define CRPT_HMAC_FDBCK12_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Position */ 1668 #define CRPT_HMAC_FDBCK12_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK12_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Mask */ 1669 1670 #define CRPT_HMAC_FDBCK13_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Position */ 1671 #define CRPT_HMAC_FDBCK13_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK13_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Mask */ 1672 1673 #define CRPT_HMAC_FDBCK14_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Position */ 1674 #define CRPT_HMAC_FDBCK14_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK14_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Mask */ 1675 1676 #define CRPT_HMAC_FDBCK15_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Position */ 1677 #define CRPT_HMAC_FDBCK15_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK15_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Mask */ 1678 1679 #define CRPT_HMAC_FDBCK16_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Position */ 1680 #define CRPT_HMAC_FDBCK16_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK16_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Mask */ 1681 1682 #define CRPT_HMAC_FDBCK17_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Position */ 1683 #define CRPT_HMAC_FDBCK17_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK17_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Mask */ 1684 1685 #define CRPT_HMAC_FDBCK18_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Position */ 1686 #define CRPT_HMAC_FDBCK18_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK18_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Mask */ 1687 1688 #define CRPT_HMAC_FDBCK19_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Position */ 1689 #define CRPT_HMAC_FDBCK19_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK19_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Mask */ 1690 1691 #define CRPT_HMAC_FDBCK20_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Position */ 1692 #define CRPT_HMAC_FDBCK20_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK20_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Mask */ 1693 1694 #define CRPT_HMAC_FDBCK21_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Position */ 1695 #define CRPT_HMAC_FDBCK21_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK21_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Mask */ 1696 1697 #define CRPT_HMAC_FDBCK22_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Position */ 1698 #define CRPT_HMAC_FDBCK22_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK22_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Mask */ 1699 1700 #define CRPT_HMAC_FDBCK23_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Position */ 1701 #define CRPT_HMAC_FDBCK23_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK23_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Mask */ 1702 1703 #define CRPT_HMAC_FDBCK24_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Position */ 1704 #define CRPT_HMAC_FDBCK24_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK24_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Mask */ 1705 1706 #define CRPT_HMAC_FDBCK25_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Position */ 1707 #define CRPT_HMAC_FDBCK25_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK25_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Mask */ 1708 1709 #define CRPT_HMAC_FDBCK26_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Position */ 1710 #define CRPT_HMAC_FDBCK26_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK26_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Mask */ 1711 1712 #define CRPT_HMAC_FDBCK27_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Position */ 1713 #define CRPT_HMAC_FDBCK27_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK27_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Mask */ 1714 1715 #define CRPT_HMAC_FDBCK28_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Position */ 1716 #define CRPT_HMAC_FDBCK28_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK28_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Mask */ 1717 1718 #define CRPT_HMAC_FDBCK29_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Position */ 1719 #define CRPT_HMAC_FDBCK29_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK29_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Mask */ 1720 1721 #define CRPT_HMAC_FDBCK30_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Position */ 1722 #define CRPT_HMAC_FDBCK30_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK30_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Mask */ 1723 1724 #define CRPT_HMAC_FDBCK31_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Position */ 1725 #define CRPT_HMAC_FDBCK31_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK31_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Mask */ 1726 1727 #define CRPT_HMAC_FDBCK32_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Position */ 1728 #define CRPT_HMAC_FDBCK32_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK32_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Mask */ 1729 1730 #define CRPT_HMAC_FDBCK33_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Position */ 1731 #define CRPT_HMAC_FDBCK33_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK33_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Mask */ 1732 1733 #define CRPT_HMAC_FDBCK34_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Position */ 1734 #define CRPT_HMAC_FDBCK34_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK34_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Mask */ 1735 1736 #define CRPT_HMAC_FDBCK35_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Position */ 1737 #define CRPT_HMAC_FDBCK35_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK35_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Mask */ 1738 1739 #define CRPT_HMAC_FDBCK36_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Position */ 1740 #define CRPT_HMAC_FDBCK36_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK36_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Mask */ 1741 1742 #define CRPT_HMAC_FDBCK37_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Position */ 1743 #define CRPT_HMAC_FDBCK37_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK37_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Mask */ 1744 1745 #define CRPT_HMAC_FDBCK38_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Position */ 1746 #define CRPT_HMAC_FDBCK38_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK38_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Mask */ 1747 1748 #define CRPT_HMAC_FDBCK39_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Position */ 1749 #define CRPT_HMAC_FDBCK39_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK39_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Mask */ 1750 1751 #define CRPT_HMAC_FDBCK40_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Position */ 1752 #define CRPT_HMAC_FDBCK40_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK40_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Mask */ 1753 1754 #define CRPT_HMAC_FDBCK41_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Position */ 1755 #define CRPT_HMAC_FDBCK41_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK41_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Mask */ 1756 1757 #define CRPT_HMAC_FDBCK42_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Position */ 1758 #define CRPT_HMAC_FDBCK42_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK42_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Mask */ 1759 1760 #define CRPT_HMAC_FDBCK43_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Position */ 1761 #define CRPT_HMAC_FDBCK43_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK43_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Mask */ 1762 1763 #define CRPT_HMAC_FDBCK44_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Position */ 1764 #define CRPT_HMAC_FDBCK44_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK44_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Mask */ 1765 1766 #define CRPT_HMAC_FDBCK45_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Position */ 1767 #define CRPT_HMAC_FDBCK45_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK45_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Mask */ 1768 1769 #define CRPT_HMAC_FDBCK46_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Position */ 1770 #define CRPT_HMAC_FDBCK46_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK46_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Mask */ 1771 1772 #define CRPT_HMAC_FDBCK47_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Position */ 1773 #define CRPT_HMAC_FDBCK47_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK47_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Mask */ 1774 1775 #define CRPT_HMAC_FDBCK48_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Position */ 1776 #define CRPT_HMAC_FDBCK48_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK48_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Mask */ 1777 1778 #define CRPT_HMAC_FDBCK49_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Position */ 1779 #define CRPT_HMAC_FDBCK49_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK49_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Mask */ 1780 1781 #define CRPT_HMAC_FDBCK50_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Position */ 1782 #define CRPT_HMAC_FDBCK50_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK50_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Mask */ 1783 1784 #define CRPT_HMAC_FDBCK51_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Position */ 1785 #define CRPT_HMAC_FDBCK51_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK51_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Mask */ 1786 1787 #define CRPT_HMAC_FDBCK52_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Position */ 1788 #define CRPT_HMAC_FDBCK52_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK52_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Mask */ 1789 1790 #define CRPT_HMAC_FDBCK53_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Position */ 1791 #define CRPT_HMAC_FDBCK53_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK53_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Mask */ 1792 1793 #define CRPT_HMAC_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::HMAC_FBADDR: FBADDR Position */ 1794 #define CRPT_HMAC_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_HMAC_FBADDR_FBADDR_Pos) /*!< CRPT_T::HMAC_FBADDR: FBADDR Mask */ 1795 1796 #define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ 1797 #define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ 1798 1799 #define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ 1800 #define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ 1801 1802 #define CRPT_ECC_CTL_PFA2C_Pos (3) /*!< CRPT_T::ECC_CTL: PFA2C Position */ 1803 #define CRPT_ECC_CTL_PFA2C_Msk (0x1ul << CRPT_ECC_CTL_PFA2C_Pos) /*!< CRPT_T::ECC_CTL: PFA2C Mask */ 1804 1805 #define CRPT_ECC_CTL_ECDSAS_Pos (4) /*!< CRPT_T::ECC_CTL: ECDSAS Position */ 1806 #define CRPT_ECC_CTL_ECDSAS_Msk (0x1ul << CRPT_ECC_CTL_ECDSAS_Pos) /*!< CRPT_T::ECC_CTL: ECDSAS Mask */ 1807 1808 #define CRPT_ECC_CTL_ECDSAR_Pos (5) /*!< CRPT_T::ECC_CTL: ECDSAR Position */ 1809 #define CRPT_ECC_CTL_ECDSAR_Msk (0x1ul << CRPT_ECC_CTL_ECDSAR_Pos) /*!< CRPT_T::ECC_CTL: ECDSAR Mask */ 1810 1811 #define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ 1812 #define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ 1813 1814 #define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ 1815 #define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ 1816 1817 #define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ 1818 #define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ 1819 1820 #define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ 1821 #define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ 1822 1823 #define CRPT_ECC_CTL_CSEL_Pos (13) /*!< CRPT_T::ECC_CTL: CSEL Position */ 1824 #define CRPT_ECC_CTL_CSEL_Msk (0x1ul << CRPT_ECC_CTL_CSEL_Pos) /*!< CRPT_T::ECC_CTL: CSEL Mask */ 1825 1826 #define CRPT_ECC_CTL_SCAP_Pos (14) /*!< CRPT_T::ECC_CTL: SCAP Position */ 1827 #define CRPT_ECC_CTL_SCAP_Msk (0x1ul << CRPT_ECC_CTL_SCAP_Pos) /*!< CRPT_T::ECC_CTL: SCAP Mask */ 1828 1829 #define CRPT_ECC_CTL_SBM_Pos (15) /*!< CRPT_T::ECC_CTL: SBM Position */ 1830 #define CRPT_ECC_CTL_SBM_Msk (0x1ul << CRPT_ECC_CTL_SBM_Pos) /*!< CRPT_T::ECC_CTL: SBM Mask */ 1831 1832 #define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ 1833 #define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ 1834 1835 #define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ 1836 #define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ 1837 1838 #define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ 1839 #define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ 1840 1841 #define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ 1842 #define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ 1843 1844 #define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ 1845 #define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ 1846 1847 #define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ 1848 #define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ 1849 1850 #define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ 1851 #define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ 1852 1853 #define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ 1854 #define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ 1855 1856 #define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ 1857 #define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ 1858 1859 #define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ 1860 #define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ 1861 1862 #define CRPT_ECC_STS_KSERR_Pos (17) /*!< CRPT_T::ECC_STS: KSERR Position */ 1863 #define CRPT_ECC_STS_KSERR_Msk (0x1ul << CRPT_ECC_STS_KSERR_Pos) /*!< CRPT_T::ECC_STS: KSERR Mask */ 1864 1865 #define CRPT_ECC_X1_Pos (0) /*!< CRPT_T::ECC_X1: POINTX Position */ 1866 #define CRPT_ECC_X1_Msk (0xfffffffful << CRPT_ECC_X1_Pos) /*!< CRPT_T::ECC_X1: POINTX Mask */ 1867 1868 1869 #define CRPT_ECC_X2_Pos (0) /*!< CRPT_T::ECC_X2: POINTX2 Position */ 1870 #define CRPT_ECC_X2TX_Msk (0xfffffffful << CRPT_ECC_X2_Pos) /*!< CRPT_T::ECC_X2: POINTX2 Mask */ 1871 1872 1873 #define CRPT_ECC_Y2_Pos (0) /*!< CRPT_T::ECC_Y2: POINTY2 Position */ 1874 #define CRPT_ECC_Y2_Msk (0xfffffffful << CRPT_ECC_Y2_Pos) /*!< CRPT_T::ECC_Y2: POINTY2 Mask */ 1875 1876 #define CRPT_ECC_A_Pos (0) /*!< CRPT_T::ECC_A: CURVEA Position */ 1877 #define CRPT_ECC_A_Msk (0xfffffffful << CRPT_ECC_A_Pos) /*!< CRPT_T::ECC_A: CURVEA Mask */ 1878 1879 #define CRPT_ECC_B_Pos (0) /*!< CRPT_T::ECC_B: CURVEB Position */ 1880 #define CRPT_ECC_B_Msk (0xfffffffful << CRPT_ECC_B_Pos) /*!< CRPT_T::ECC_B: CURVEB Mask */ 1881 1882 #define CRPT_ECC_N_Pos (0) /*!< CRPT_T::ECC_N: SCALARK Position */ 1883 #define CRPT_ECC_N_Msk (0xfffffffful << CRPT_ECC_N_Pos) /*!< CRPT_T::ECC_N: SCALARK Mask */ 1884 1885 #define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ 1886 #define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ 1887 1888 #define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ 1889 #define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ 1890 1891 #define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position*/ 1892 #define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ 1893 1894 #define CRPT_RSA_CTL_START_Pos (0) /*!< CRPT_T::RSA_CTL: START Position */ 1895 #define CRPT_RSA_CTL_START_Msk (0x1ul << CRPT_RSA_CTL_START_Pos) /*!< CRPT_T::RSA_CTL: START Mask */ 1896 1897 #define CRPT_RSA_CTL_STOP_Pos (1) /*!< CRPT_T::RSA_CTL: STOP Position */ 1898 #define CRPT_RSA_CTL_STOP_Msk (0x1ul << CRPT_RSA_CTL_STOP_Pos) /*!< CRPT_T::RSA_CTL: STOP Mask */ 1899 1900 #define CRPT_RSA_CTL_CRT_Pos (2) /*!< CRPT_T::RSA_CTL: CRT Position */ 1901 #define CRPT_RSA_CTL_CRT_Msk (0x1ul << CRPT_RSA_CTL_CRT_Pos) /*!< CRPT_T::RSA_CTL: CRT Mask */ 1902 1903 #define CRPT_RSA_CTL_CRTBYP_Pos (3) /*!< CRPT_T::RSA_CTL: CRTBYP Position */ 1904 #define CRPT_RSA_CTL_CRTBYP_Msk (0x1ul << CRPT_RSA_CTL_CRTBYP_Pos) /*!< CRPT_T::RSA_CTL: CRTBYP Mask */ 1905 1906 #define CRPT_RSA_CTL_KEYLENG_Pos (4) /*!< CRPT_T::RSA_CTL: KEYLENG Position */ 1907 #define CRPT_RSA_CTL_KEYLENG_Msk (0x3ul << CRPT_RSA_CTL_KEYLENG_Pos) /*!< CRPT_T::RSA_CTL: KEYLENG Mask */ 1908 1909 #define CRPT_RSA_CTL_SCAP_Pos (8) /*!< CRPT_T::RSA_CTL: SCAP Position */ 1910 #define CRPT_RSA_CTL_SCAP_Msk (0x1ul << CRPT_RSA_CTL_SCAP_Pos) /*!< CRPT_T::RSA_CTL: SCAP Mask */ 1911 1912 #define CRPT_RSA_STS_BUSY_Pos (0) /*!< CRPT_T::RSA_STS: BUSY Position */ 1913 #define CRPT_RSA_STS_BUSY_Msk (0x1ul << CRPT_RSA_STS_BUSY_Pos) /*!< CRPT_T::RSA_STS: BUSY Mask */ 1914 1915 #define CRPT_RSA_STS_DMABUSY_Pos (1) /*!< CRPT_T::RSA_STS: DMABUSY Position */ 1916 #define CRPT_RSA_STS_DMABUSY_Msk (0x1ul << CRPT_RSA_STS_DMABUSY_Pos) /*!< CRPT_T::RSA_STS: DMABUSY Mask */ 1917 1918 #define CRPT_RSA_STS_BUSERR_Pos (16) /*!< CRPT_T::RSA_STS: BUSERR Position */ 1919 #define CRPT_RSA_STS_BUSERR_Msk (0x1ul << CRPT_RSA_STS_BUSERR_Pos) /*!< CRPT_T::RSA_STS: BUSERR Mask */ 1920 1921 #define CRPT_RSA_STS_CTLERR_Pos (17) /*!< CRPT_T::RSA_STS: CTLERR Position */ 1922 #define CRPT_RSA_STS_CTLERR_Msk (0x1ul << CRPT_RSA_STS_CTLERR_Pos) /*!< CRPT_T::RSA_STS: CTLERR Mask */ 1923 1924 #define CRPT_RSA_STS_KSERR_Pos (18) /*!< CRPT_T::RSA_STS: KSERR Position */ 1925 #define CRPT_RSA_STS_KSERR_Msk (0x1ul << CRPT_RSA_STS_KSERR_Pos) /*!< CRPT_T::RSA_STS: KSERR Mask */ 1926 1927 #define CRPT_RSA_SADDR_Pos (0) /*!< CRPT_T::RSA_SADDR: SADDR Position */ 1928 #define CRPT_RSA_SADDR_Msk (0xfffffffful << CRPT_RSA_SADDR_Pos) /*!< CRPT_T::RSA_SADDR: SADDR Mask */ 1929 1930 #define CRPT_RSA_DADDR_Pos (0) /*!< CRPT_T::RSA_DADDR: DADDR Position */ 1931 #define CRPT_RSA_DADDR_Msk (0xfffffffful << CRPT_RSA_DADDR_Pos) /*!< CRPT_T::RSA_DADDR: DADDR Mask */ 1932 1933 #define CRPT_RSA_MADDR_Pos (0) /*!< CRPT_T::RSA_MADDR: MADDR Position */ 1934 #define CRPT_RSA_MADDR_Msk (0xfffffffful << CRPT_RSA_MADDR_Pos) /*!< CRPT_T::RSA_MADDR: MADDR Mask */ 1935 1936 #define CRPT_PRNG_KSCTL_NUM_Pos (0) /*!< CRPT_T::PRNG_KSCTL: NUM Position */ 1937 #define CRPT_PRNG_KSCTL_NUM_Msk (0x1ful << CRPT_PRNG_KSCTL_NUM_Pos) /*!< CRPT_T::PRNG_KSCTL: NUM Mask */ 1938 1939 #define CRPT_PRNG_KSCTL_TRUST_Pos (16) /*!< CRPT_T::PRNG_KSCTL: TRUST Position */ 1940 #define CRPT_PRNG_KSCTL_TRUST_Msk (0x1ul << CRPT_PRNG_KSCTL_TRUST_Pos) /*!< CRPT_T::PRNG_KSCTL: TRUST Mask */ 1941 1942 #define CRPT_PRNG_KSCTL_PRIV_Pos (18) /*!< CRPT_T::PRNG_KSCTL: PRIV Position */ 1943 #define CRPT_PRNG_KSCTL_PRIV_Msk (0x1ul << CRPT_PRNG_KSCTL_PRIV_Pos) /*!< CRPT_T::PRNG_KSCTL: PRIV Mask */ 1944 1945 #define CRPT_PRNG_KSCTL_ECDH_Pos (19) /*!< CRPT_T::PRNG_KSCTL: ECDH Position */ 1946 #define CRPT_PRNG_KSCTL_ECDH_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDH_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDH Mask */ 1947 1948 #define CRPT_PRNG_KSCTL_ECDSA_Pos (20) /*!< CRPT_T::PRNG_KSCTL: ECDSA Position */ 1949 #define CRPT_PRNG_KSCTL_ECDSA_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDSA_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDSA Mask */ 1950 1951 #define CRPT_PRNG_KSCTL_WDST_Pos (21) /*!< CRPT_T::PRNG_KSCTL: WDST Position */ 1952 #define CRPT_PRNG_KSCTL_WDST_Msk (0x1ul << CRPT_PRNG_KSCTL_WDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WDST Mask */ 1953 1954 #define CRPT_PRNG_KSCTL_WSDST_Pos (22) /*!< CRPT_T::PRNG_KSCTL: WSDST Position */ 1955 #define CRPT_PRNG_KSCTL_WSDST_Msk (0x3ul << CRPT_PRNG_KSCTL_WSDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WSDST Mask */ 1956 1957 #define CRPT_PRNG_KSCTL_OWNER_Pos (24) /*!< CRPT_T::PRNG_KSCTL: OWNER Position */ 1958 #define CRPT_PRNG_KSCTL_OWNER_Msk (0x7ul << CRPT_PRNG_KSCTL_OWNER_Pos) /*!< CRPT_T::PRNG_KSCTL: OWNER Mask */ 1959 1960 #define CRPT_PRNG_KSSTS_NUM_Pos (0) /*!< CRPT_T::PRNG_KSSTS: NUM Position */ 1961 #define CRPT_PRNG_KSSTS_NUM_Msk (0x1ful << CRPT_PRNG_KSSTS_NUM_Pos) /*!< CRPT_T::PRNG_KSSTS: NUM Mask */ 1962 1963 #define CRPT_PRNG_KSSTS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Position */ 1964 #define CRPT_PRNG_KSSTS_KCTLERR_Msk (0x1ul << CRPT_PRNG_KSSTS_KCTLERR_Pos) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Mask */ 1965 1966 #define CRPT_AES_KSCTL_NUM_Pos (0) /*!< CRPT_T::AES_KSCTL: NUM Position */ 1967 #define CRPT_AES_KSCTL_NUM_Msk (0x1ful << CRPT_AES_KSCTL_NUM_Pos) /*!< CRPT_T::AES_KSCTL: NUM Mask */ 1968 1969 #define CRPT_AES_KSCTL_RSRC_Pos (5) /*!< CRPT_T::AES_KSCTL: RSRC Position */ 1970 #define CRPT_AES_KSCTL_RSRC_Msk (0x1ul << CRPT_AES_KSCTL_RSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSRC Mask */ 1971 1972 #define CRPT_AES_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::AES_KSCTL: RSSRC Position */ 1973 #define CRPT_AES_KSCTL_RSSRC_Msk (0x3ul << CRPT_AES_KSCTL_RSSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSSRC Mask */ 1974 1975 #define CRPT_HMAC_KSCTL_NUM_Pos (0) /*!< CRPT_T::HMAC_KSCTL: NUM Position */ 1976 #define CRPT_HMAC_KSCTL_NUM_Msk (0x1ful << CRPT_HMAC_KSCTL_NUM_Pos) /*!< CRPT_T::HMAC_KSCTL: NUM Mask */ 1977 1978 #define CRPT_HMAC_KSCTL_RSRC_Pos (5) /*!< CRPT_T::HMAC_KSCTL: RSRC Position */ 1979 #define CRPT_HMAC_KSCTL_RSRC_Msk (0x1ul << CRPT_HMAC_KSCTL_RSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSRC Mask */ 1980 1981 #define CRPT_HMAC_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::HMAC_KSCTL: RSSRC Position */ 1982 #define CRPT_HMAC_KSCTL_RSSRC_Msk (0x3ul << CRPT_HMAC_KSCTL_RSSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSSRC Mask */ 1983 1984 #define CRPT_ECC_KSCTL_NUMK_Pos (0) /*!< CRPT_T::ECC_KSCTL: NUMK Position */ 1985 #define CRPT_ECC_KSCTL_NUMK_Msk (0x1ful << CRPT_ECC_KSCTL_NUMK_Pos) /*!< CRPT_T::ECC_KSCTL: NUMK Mask */ 1986 1987 #define CRPT_ECC_KSCTL_RSRCK_Pos (5) /*!< CRPT_T::ECC_KSCTL: RSRCK Position */ 1988 #define CRPT_ECC_KSCTL_RSRCK_Msk (0x1ul << CRPT_ECC_KSCTL_RSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSRCK Mask */ 1989 1990 #define CRPT_ECC_KSCTL_RSSRCK_Pos (6) /*!< CRPT_T::ECC_KSCTL: RSSRCK Position */ 1991 #define CRPT_ECC_KSCTL_RSSRCK_Msk (0x3ul << CRPT_ECC_KSCTL_RSSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSSRCK Mask */ 1992 1993 #define CRPT_ECC_KSCTL_ECDH_Pos (14) /*!< CRPT_T::ECC_KSCTL: ECDH Position */ 1994 #define CRPT_ECC_KSCTL_ECDH_Msk (0x1ul << CRPT_ECC_KSCTL_ECDH_Pos) /*!< CRPT_T::ECC_KSCTL: ECDH Mask */ 1995 1996 #define CRPT_ECC_KSCTL_TRUST_Pos (16) /*!< CRPT_T::ECC_KSCTL: TRUST Position */ 1997 #define CRPT_ECC_KSCTL_TRUST_Msk (0x1ul << CRPT_ECC_KSCTL_TRUST_Pos) /*!< CRPT_T::ECC_KSCTL: TRUST Mask */ 1998 1999 #define CRPT_ECC_KSCTL_PRIV_Pos (18) /*!< CRPT_T::ECC_KSCTL: PRIV Position */ 2000 #define CRPT_ECC_KSCTL_PRIV_Msk (0x1ul << CRPT_ECC_KSCTL_PRIV_Pos) /*!< CRPT_T::ECC_KSCTL: PRIV Mask */ 2001 2002 #define CRPT_ECC_KSCTL_XY_Pos (20) /*!< CRPT_T::ECC_KSCTL: XY Position */ 2003 #define CRPT_ECC_KSCTL_XY_Msk (0x1ul << CRPT_ECC_KSCTL_XY_Pos) /*!< CRPT_T::ECC_KSCTL: XY Mask */ 2004 2005 #define CRPT_ECC_KSCTL_WDST_Pos (21) /*!< CRPT_T::ECC_KSCTL: WDST Position */ 2006 #define CRPT_ECC_KSCTL_WDST_Msk (0x1ul << CRPT_ECC_KSCTL_WDST_Pos) /*!< CRPT_T::ECC_KSCTL: WDST Mask */ 2007 2008 #define CRPT_ECC_KSCTL_WSDST_Pos (22) /*!< CRPT_T::ECC_KSCTL: WSDST Position */ 2009 #define CRPT_ECC_KSCTL_WSDST_Msk (0x3ul << CRPT_ECC_KSCTL_WSDST_Pos) /*!< CRPT_T::ECC_KSCTL: WSDST Mask */ 2010 2011 #define CRPT_ECC_KSCTL_OWNER_Pos (24) /*!< CRPT_T::ECC_KSCTL: OWNER Position */ 2012 #define CRPT_ECC_KSCTL_OWNER_Msk (0x7ul << CRPT_ECC_KSCTL_OWNER_Pos) /*!< CRPT_T::ECC_KSCTL: OWNER Mask */ 2013 2014 #define CRPT_ECC_KSSTS_NUM_Pos (0) /*!< CRPT_T::ECC_KSSTS: NUM Position */ 2015 #define CRPT_ECC_KSSTS_NUM_Msk (0x1ful << CRPT_ECC_KSSTS_NUM_Pos) /*!< CRPT_T::ECC_KSSTS: NUM Mask */ 2016 2017 #define CRPT_ECC_KSXY_NUMX_Pos (0) /*!< CRPT_T::ECC_KSXY: NUMX Position */ 2018 #define CRPT_ECC_KSXY_NUMX_Msk (0x1ful << CRPT_ECC_KSXY_NUMX_Pos) /*!< CRPT_T::ECC_KSXY: NUMX Mask */ 2019 2020 #define CRPT_ECC_KSXY_RSRCXY_Pos (5) /*!< CRPT_T::ECC_KSXY: RSRCXY Position */ 2021 #define CRPT_ECC_KSXY_RSRCXY_Msk (0x1ul << CRPT_ECC_KSXY_RSRCXY_Pos) /*!< CRPT_T::ECC_KSXY: RSRCXY Mask */ 2022 2023 #define CRPT_ECC_KSXY_RSSRCX_Pos (6) /*!< CRPT_T::ECC_KSXY: RSSRCX Position */ 2024 #define CRPT_ECC_KSXY_RSSRCX_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCX_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCX Mask */ 2025 2026 #define CRPT_ECC_KSXY_NUMY_Pos (8) /*!< CRPT_T::ECC_KSXY: NUMY Position */ 2027 #define CRPT_ECC_KSXY_NUMY_Msk (0x1ful << CRPT_ECC_KSXY_NUMY_Pos) /*!< CRPT_T::ECC_KSXY: NUMY Mask */ 2028 2029 #define CRPT_ECC_KSXY_RSSRCY_Pos (14) /*!< CRPT_T::ECC_KSXY: RSSRCY Position */ 2030 #define CRPT_ECC_KSXY_RSSRCY_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCY_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCY Mask */ 2031 2032 #define CRPT_RSA_KSCTL_NUM_Pos (0) /*!< CRPT_T::RSA_KSCTL: NUM Position */ 2033 #define CRPT_RSA_KSCTL_NUM_Msk (0x1ful << CRPT_RSA_KSCTL_NUM_Pos) /*!< CRPT_T::RSA_KSCTL: NUM Mask */ 2034 2035 #define CRPT_RSA_KSCTL_RSRC_Pos (5) /*!< CRPT_T::RSA_KSCTL: RSRC Position */ 2036 #define CRPT_RSA_KSCTL_RSRC_Msk (0x1ul << CRPT_RSA_KSCTL_RSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSRC Mask */ 2037 2038 #define CRPT_RSA_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::RSA_KSCTL: RSSRC Position */ 2039 #define CRPT_RSA_KSCTL_RSSRC_Msk (0x3ul << CRPT_RSA_KSCTL_RSSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSSRC Mask */ 2040 2041 #define CRPT_RSA_KSCTL_BKNUM_Pos (8) /*!< CRPT_T::RSA_KSCTL: BKNUM Position */ 2042 #define CRPT_RSA_KSCTL_BKNUM_Msk (0x1ful << CRPT_RSA_KSCTL_BKNUM_Pos) /*!< CRPT_T::RSA_KSCTL: BKNUM Mask */ 2043 2044 #define CRPT_RSA_KSSTS0_NUM0_Pos (0) /*!< CRPT_T::RSA_KSSTS0: NUM0 Position */ 2045 #define CRPT_RSA_KSSTS0_NUM0_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM0_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM0 Mask */ 2046 2047 #define CRPT_RSA_KSSTS0_NUM1_Pos (8) /*!< CRPT_T::RSA_KSSTS0: NUM1 Position */ 2048 #define CRPT_RSA_KSSTS0_NUM1_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM1_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM1 Mask */ 2049 2050 #define CRPT_RSA_KSSTS0_NUM2_Pos (16) /*!< CRPT_T::RSA_KSSTS0: NUM2 Position */ 2051 #define CRPT_RSA_KSSTS0_NUM2_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM2_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM2 Mask */ 2052 2053 #define CRPT_RSA_KSSTS0_NUM3_Pos (24) /*!< CRPT_T::RSA_KSSTS0: NUM3 Position */ 2054 #define CRPT_RSA_KSSTS0_NUM3_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM3_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM3 Mask */ 2055 2056 #define CRPT_RSA_KSSTS1_NUM4_Pos (0) /*!< CRPT_T::RSA_KSSTS1: NUM4 Position */ 2057 #define CRPT_RSA_KSSTS1_NUM4_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM4_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM4 Mask */ 2058 2059 #define CRPT_RSA_KSSTS1_NUM5_Pos (8) /*!< CRPT_T::RSA_KSSTS1: NUM5 Position */ 2060 #define CRPT_RSA_KSSTS1_NUM5_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM5_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM5 Mask */ 2061 2062 #define CRPT_RSA_KSSTS1_NUM6_Pos (16) /*!< CRPT_T::RSA_KSSTS1: NUM6 Position */ 2063 #define CRPT_RSA_KSSTS1_NUM6_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM6_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM6 Mask */ 2064 2065 #define CRPT_RSA_KSSTS1_NUM7_Pos (24) /*!< CRPT_T::RSA_KSSTS1: NUM7 Position */ 2066 #define CRPT_RSA_KSSTS1_NUM7_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM7_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM7 Mask */ 2067 2068 #define CRPT_VERSION_MINOR_Pos (0) /*!< CRPT_T::VERSION: MINOR Position */ 2069 #define CRPT_VERSION_MINOR_Msk (0xfffful << CRPT_VERSION_MINOR_Pos) /*!< CRPT_T::VERSION: MINOR Mask */ 2070 2071 #define CRPT_VERSION_SUB_Pos (16) /*!< CRPT_T::VERSION: SUB Position */ 2072 #define CRPT_VERSION_SUB_Msk (0xfful << CRPT_VERSION_SUB_Pos) /*!< CRPT_T::VERSION: SUB Mask */ 2073 2074 #define CRPT_VERSION_MAJOR_Pos (24) /*!< CRPT_T::VERSION: MAJOR Position */ 2075 #define CRPT_VERSION_MAJOR_Msk (0xfful << CRPT_VERSION_MAJOR_Pos) /*!< CRPT_T::VERSION: MAJOR Mask */ 2076 2077 /**@}*/ /* CRPT_CONST */ 2078 /**@}*/ /* end of CRYPTO register group */ 2079 2080 2081 /**@}*/ /* end of REGISTER group */ 2082 2083 #endif /* __CRPT_REG_H__ */ 2084
