1 /* 2 * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_cadence 1 14 #define ZYNQMP_CONSOLE_ID_cadence0 1 15 #define ZYNQMP_CONSOLE_ID_cadence1 2 16 #define ZYNQMP_CONSOLE_ID_dcc 3 17 18 #define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 19 20 /* Default counter frequency */ 21 #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U 22 23 /* Firmware Image Package */ 24 #define ZYNQMP_PRIMARY_CPU 0 25 26 /* Memory location options for Shared data and TSP in ZYNQMP */ 27 #define ZYNQMP_IN_TRUSTED_SRAM 0 28 #define ZYNQMP_IN_TRUSTED_DRAM 1 29 30 /******************************************************************************* 31 * ZYNQMP memory map related constants 32 ******************************************************************************/ 33 /* Aggregate of all devices in the first GB */ 34 #define DEVICE0_BASE U(0xFF000000) 35 #define DEVICE0_SIZE U(0x00E00000) 36 #define DEVICE1_BASE U(0xF9000000) 37 #define DEVICE1_SIZE U(0x00800000) 38 39 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 40 #define CRF_APB_BASE U(0xFD1A0000) 41 #define CRF_APB_SIZE U(0x00600000) 42 #define CRF_APB_CLK_BASE U(0xFD1A0020) 43 44 /* CRF registers and bitfields */ 45 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 46 47 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 48 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 49 50 /* CRL registers and bitfields */ 51 #define CRL_APB_BASE U(0xFF5E0000) 52 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 53 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 54 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 55 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 56 #define CRL_APB_CLK_BASE U(0xFF5E0020) 57 58 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 59 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 60 61 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 62 63 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 64 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 65 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 66 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 67 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 68 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 69 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 70 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 71 #define ZYNQMP_BOOTMODE_JTAG U(0) 72 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 73 CRL_APB_BOOT_DRIVE_PIN_1) 74 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 75 76 /* system counter registers and bitfields */ 77 #define IOU_SCNTRS_BASE U(0xFF260000) 78 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 79 80 /* APU registers and bitfields */ 81 #define APU_BASE U(0xFD5C0000) 82 #define APU_CONFIG_0 (APU_BASE + 0x20) 83 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 84 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 85 #define APU_PWRCTL (APU_BASE + 0x90) 86 87 #define APU_CONFIG_0_VINITHI_SHIFT 8 88 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 89 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 90 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 91 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 92 93 /* PMU registers and bitfields */ 94 #define PMU_GLOBAL_BASE U(0xFFD80000) 95 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 96 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 97 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 98 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 99 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 100 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 101 102 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 103 104 /******************************************************************************* 105 * CCI-400 related constants 106 ******************************************************************************/ 107 #define PLAT_ARM_CCI_BASE U(0xFD6E0000) 108 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 109 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 110 111 /******************************************************************************* 112 * GIC-400 & interrupt handling related constants 113 ******************************************************************************/ 114 #define BASE_GICD_BASE U(0xF9010000) 115 #define BASE_GICC_BASE U(0xF9020000) 116 #define BASE_GICH_BASE U(0xF9040000) 117 #define BASE_GICV_BASE U(0xF9060000) 118 119 #if ZYNQMP_WDT_RESTART 120 #define IRQ_SEC_IPI_APU 67 121 #define IRQ_TTC3_1 77 122 #define TTC3_BASE_ADDR U(0xFF140000) 123 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 124 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 125 #endif 126 127 #define ARM_IRQ_SEC_PHY_TIMER 29 128 129 #define ARM_IRQ_SEC_SGI_0 8 130 #define ARM_IRQ_SEC_SGI_1 9 131 #define ARM_IRQ_SEC_SGI_2 10 132 #define ARM_IRQ_SEC_SGI_3 11 133 #define ARM_IRQ_SEC_SGI_4 12 134 #define ARM_IRQ_SEC_SGI_5 13 135 #define ARM_IRQ_SEC_SGI_6 14 136 #define ARM_IRQ_SEC_SGI_7 15 137 138 #define MAX_INTR_EL3 128 139 140 /******************************************************************************* 141 * UART related constants 142 ******************************************************************************/ 143 #define ZYNQMP_UART0_BASE U(0xFF000000) 144 #define ZYNQMP_UART1_BASE U(0xFF010000) 145 146 #if ZYNQMP_CONSOLE_IS(cadence) || ZYNQMP_CONSOLE_IS(dcc) 147 # define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE 148 #elif ZYNQMP_CONSOLE_IS(cadence1) 149 # define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE 150 #else 151 # error "invalid ZYNQMP_CONSOLE" 152 #endif 153 154 #define ZYNQMP_CRASH_UART_BASE ZYNQMP_UART_BASE 155 /* impossible to call C routine how it is done now - hardcode any value */ 156 #define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */ 157 /* Must be non zero */ 158 #define ZYNQMP_UART_BAUDRATE 115200 159 160 /* Silicon version detection */ 161 #define ZYNQMP_SILICON_VER_MASK 0xF000 162 #define ZYNQMP_SILICON_VER_SHIFT 12 163 #define ZYNQMP_CSU_VERSION_SILICON 0 164 #define ZYNQMP_CSU_VERSION_QEMU 3 165 166 #define ZYNQMP_RTL_VER_MASK 0xFF0U 167 #define ZYNQMP_RTL_VER_SHIFT 4 168 169 #define ZYNQMP_PS_VER_MASK 0xFU 170 #define ZYNQMP_PS_VER_SHIFT 0 171 172 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) 173 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40U 174 175 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U 176 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ 177 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 178 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 179 180 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U 181 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ 182 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 183 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U 184 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ 185 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 186 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U 187 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ 188 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 189 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U 190 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ 191 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 192 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 193 194 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U 195 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ 196 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 197 #define ZYNQMP_CSU_IDCODE_REVISION 0U 198 199 #define ZYNQMP_CSU_VERSION_OFFSET 0x44U 200 201 /* Efuse */ 202 #define EFUSE_BASEADDR U(0xFFCC0000) 203 #define EFUSE_IPDISABLE_OFFSET 0x1018 204 #define EFUSE_IPDISABLE_VERSION 0x1FFU 205 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 206 207 /* Access control register defines */ 208 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 209 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 210 211 #define FPD_SLCR_BASEADDR U(0xFD610000) 212 #define IOU_SLCR_BASEADDR U(0xFF180000) 213 214 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 215 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 216 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 217 #define ZYNQMP_SLSPLIT_MASK U(0x08) 218 #define ZYNQMP_TCM_COMB_MASK U(0x40) 219 #define ZYNQMP_SLCLAMP_MASK U(0x10) 220 #define ZYNQMP_VINITHI_MASK U(0x04) 221 222 /* Tap delay bypass */ 223 #define IOU_TAPDLY_BYPASS U(0XFF180390) 224 #define TAP_DELAY_MASK U(0x7) 225 226 /* SGMII mode */ 227 #define IOU_GEM_CTRL U(0xFF180360) 228 #define IOU_GEM_CLK_CTRL U(0xFF180308) 229 #define SGMII_SD_MASK U(0x3) 230 #define SGMII_SD_OFFSET U(2) 231 #define SGMII_PCS_SD_0 U(0x0) 232 #define SGMII_PCS_SD_1 U(0x1) 233 #define SGMII_PCS_SD_PHY U(0x2) 234 #define GEM_SGMII_MASK U(0x4) 235 #define GEM_CLK_CTRL_MASK U(0xF) 236 #define GEM_CLK_CTRL_OFFSET U(5) 237 #define GEM_RX_SRC_SEL_GTR U(0x1) 238 #define GEM_SGMII_MODE U(0x4) 239 240 /* SD DLL reset */ 241 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 242 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 243 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 244 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 245 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 246 247 /* SD tap delay */ 248 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 249 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 250 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 251 #define ZYNQMP_SD_TAP_OFFSET U(16) 252 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 253 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 254 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 255 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 256 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 257 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 258 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 259 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 260 261 /* Clock control registers */ 262 /* Full power domain clocks */ 263 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 264 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 265 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 266 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 267 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 268 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 269 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 270 /* Peripheral clocks */ 271 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 272 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 273 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 274 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 275 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 276 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 277 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 278 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 279 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 280 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 281 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 282 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 283 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 284 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 285 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 286 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 287 288 /* Low power domain clocks */ 289 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 290 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 291 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 292 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 293 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 294 /* Peripheral clocks */ 295 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 296 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 297 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 298 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 299 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 300 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 301 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 302 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 303 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 304 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 305 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 306 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 307 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 308 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 309 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 310 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 311 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 312 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 313 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 314 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 315 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 316 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 317 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 318 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 319 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 320 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 321 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 322 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 323 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 324 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 325 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 326 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 327 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 328 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 329 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 330 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 331 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 332 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 333 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 334 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 335 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 336 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 337 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 338 339 /* Global general storage register base address */ 340 #define GGS_BASEADDR (0xFFD80030U) 341 #define GGS_NUM_REGS U(4) 342 343 /* Persistent global general storage register base address */ 344 #define PGGS_BASEADDR (0xFFD80050U) 345 #define PGGS_NUM_REGS U(4) 346 347 /* PMU GGS4 register 4 is used for warm restart boot health status */ 348 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 349 /* Warm restart boot health status mask */ 350 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 351 /* WDT restart scope shift and mask */ 352 #define RESTART_SCOPE_SHIFT (3) 353 #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) 354 355 /* AFI registers */ 356 #define AFIFM6_WRCTRL U(13) 357 #define FABRIC_WIDTH U(3) 358 359 /* CSUDMA Module Base Address*/ 360 #define CSUDMA_BASE U(0xFFC80000) 361 362 /* RSA-CORE Module Base Address*/ 363 #define RSA_CORE_BASE U(0xFFCE0000) 364 365 #endif /* ZYNQMP_DEF_H */ 366
