1 /*
2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2019-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #include "fsl_crc.h"
9
10 /*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14 /* Component ID definition, used by tools. */
15 #ifndef FSL_COMPONENT_ID
16 #define FSL_COMPONENT_ID "platform.drivers.lpc_crc"
17 #endif
18
19 #if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
20 /* @brief Default user configuration structure for CRC-CCITT */
21 #define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
22 /*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
23 #define CRC_DRIVER_DEFAULT_REVERSE_IN false
24 /*< Default is no bit reverse */
25 #define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
26 /*< Default is without complement of written data */
27 #define CRC_DRIVER_DEFAULT_REVERSE_OUT false
28 /*< Default is no bit reverse */
29 #define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
30 /*< Default is without complement of CRC data register read data */
31 #define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
32 /*< Default initial checksum */
33 #endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
34
35 /*******************************************************************************
36 * Code
37 ******************************************************************************/
38
39 /*!
40 * brief Enables and configures the CRC peripheral module.
41 *
42 * This functions enables the CRC peripheral clock in the LPC SYSCON block.
43 * It also configures the CRC engine and starts checksum computation by writing the seed.
44 *
45 * param base CRC peripheral address.
46 * param config CRC module configuration structure.
47 */
CRC_Init(CRC_Type * base,const crc_config_t * config)48 void CRC_Init(CRC_Type *base, const crc_config_t *config)
49 {
50 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
51 /* enable clock to CRC */
52 CLOCK_EnableClock(kCLOCK_Crc);
53 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
54
55 #if !(defined(FSL_FEATURE_CRC_HAS_NO_RESET) && FSL_FEATURE_CRC_HAS_NO_RESET)
56 RESET_PeripheralReset(kCRC_RST_SHIFT_RSTn);
57 #endif
58
59 /* configure CRC module and write the seed */
60 base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
61 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
62 CRC_MODE_CMPL_SUM(config->complementOut);
63 base->SEED = config->seed;
64 }
65
66 /*!
67 * brief Loads default values to CRC protocol configuration structure.
68 *
69 * Loads default values to CRC protocol configuration structure. The default values are:
70 * code
71 * config->polynomial = kCRC_Polynomial_CRC_CCITT;
72 * config->reverseIn = false;
73 * config->complementIn = false;
74 * config->reverseOut = false;
75 * config->complementOut = false;
76 * config->seed = 0xFFFFU;
77 * endcode
78 *
79 * param config CRC protocol configuration structure
80 */
CRC_GetDefaultConfig(crc_config_t * config)81 void CRC_GetDefaultConfig(crc_config_t *config)
82 {
83 /* Initializes the configure structure to zero. */
84 (void)memset(config, 0, sizeof(*config));
85
86 static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN,
87 CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT,
88 CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
89
90 *config = default_config;
91 }
92
93 /*!
94 * brief resets CRC peripheral module.
95 *
96 * param base CRC peripheral address.
97 */
CRC_Reset(CRC_Type * base)98 void CRC_Reset(CRC_Type *base)
99 {
100 crc_config_t config;
101 CRC_GetDefaultConfig(&config);
102 CRC_Init(base, &config);
103 }
104
105 /*!
106 * brief Write seed (initial checksum) to CRC peripheral module.
107 *
108 * param base CRC peripheral address.
109 * param seed CRC Seed value.
110 */
CRC_WriteSeed(CRC_Type * base,uint32_t seed)111 void CRC_WriteSeed(CRC_Type *base, uint32_t seed)
112 {
113 /* write the seed (initial checksum) */
114 base->SEED = seed;
115 }
116
117 /*!
118 * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
119 *
120 * The values, including seed, can be used to resume CRC calculation later.
121
122 * param base CRC peripheral address.
123 * param config CRC protocol configuration structure
124 */
CRC_GetConfig(CRC_Type * base,crc_config_t * config)125 void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
126 {
127 /* extract CRC mode settings */
128 uint32_t mode = base->MODE;
129 config->polynomial =
130 (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT);
131 config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
132 config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
133 config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
134 config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
135
136 /* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
137 base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
138
139 /* now we can obtain intermediate raw CRC sum value */
140 config->seed = base->SUM;
141
142 /* restore original CRC sum bit reverse and 1's complement setting */
143 base->MODE = mode;
144 }
145
146 /*!
147 * brief Writes data to the CRC module.
148 *
149 * Writes input data buffer bytes to CRC data register.
150 *
151 * param base CRC peripheral address.
152 * param data Input data stream, MSByte in data[0].
153 * param dataSize Size of the input data buffer in bytes.
154 */
CRC_WriteData(CRC_Type * base,const uint8_t * data,size_t dataSize)155 void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
156 {
157 const uint32_t *data32;
158
159 /* 8-bit reads and writes till source address is aligned 4 bytes */
160 while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
161 {
162 *((__O uint8_t *)&(base->WR_DATA)) = *data;
163 data++;
164 dataSize--;
165 }
166
167 /* use 32-bit reads and writes as long as possible */
168 data32 = (const uint32_t *)(uint32_t)data;
169 while (dataSize >= sizeof(uint32_t))
170 {
171 *((__O uint32_t *)&(base->WR_DATA)) = *data32;
172 data32++;
173 dataSize -= sizeof(uint32_t);
174 }
175
176 data = (const uint8_t *)data32;
177
178 /* 8-bit reads and writes till end of data buffer */
179 while (0U != dataSize)
180 {
181 *((__O uint8_t *)&(base->WR_DATA)) = *data;
182 data++;
183 dataSize--;
184 }
185 }
186
