1 /* 2 * Copyright (c) 2017 Oticon A/S 3 * Copyright (c) 2023 Nordic Semiconductor ASA 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 * Private types definitions for the RADIO peripheral 8 */ 9 #ifndef _NRF_RADIO_PRIVATE_H 10 #define _NRF_RADIO_PRIVATE_H 11 12 #ifdef __cplusplus 13 extern "C"{ 14 #endif 15 16 typedef enum {TIFS_DISABLE = 0, TIFS_WAITING_FOR_DISABLE, TIFS_TRIGGERING_TRX_EN} TIFS_state_t; 17 typedef enum {No_pending_abort_reeval = 0, Tx_Abort_reeval, Rx_Abort_reeval, CCA_Abort_reeval} abort_state_t; 18 19 typedef enum { //Note: This should match the real RADIO state values in the STATE register 20 RAD_DISABLED = 0, //No operations are going on inside the radio and the power consumption is at a minimum 21 RAD_RXRU, //The radio is ramping up and preparing for reception 22 RAD_RXIDLE, //The radio is ready for reception to start 23 RAD_RX, //Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored 24 RAD_RXDISABLE, //The radio is disabling the receiver 25 26 RAD_TXRU = 9, //The radio is ramping up and preparing for transmission 27 RAD_TXIDLE, //The radio is ready for transmission to start 28 RAD_TXSTARTING, //The radio is starting to Tx (it will be in this state for TxChainDelay) 29 RAD_TX, //The radio is transmitting a packet 30 RAD_TXDISABLE, //The radio is disabling the transmitter 31 32 RAD_CCA_ED, //We are in either a CCA or ED procedure 33 //Not a real HW state. In real HW the RADIO is in RXIDLE or some other RX state. Seems the CCA and ED procedures as separate machines 34 } nrfra_state_t; 35 36 typedef enum {SUB_STATE_INVALID, /*The timer should not trigger in TX or RX state with this substate*/ 37 TX_WAIT_FOR_ADDRESS_END, TX_WAIT_FOR_FEC1_END, TX_WAIT_FOR_PAYLOAD_END, TX_WAIT_FOR_CRC_END, 38 RX_WAIT_FOR_ADDRESS_END, RX_WAIT_FOR_FEC1_END, RX_WAIT_FOR_PAYLOAD_END, RX_WAIT_FOR_CRC_END 39 } nrfra_sub_state_t; 40 41 typedef struct { 42 bs_time_t ADDRESS_End_Time; 43 bs_time_t FEC2_start_time; /* In air */ 44 bs_time_t PAYLOAD_End_Time; 45 bs_time_t CRC_End_Time; 46 bs_time_t CRC_duration; 47 p2G4_rxv2_t rx_req_fec1; 48 p2G4_rxv2_t rx_req; 49 p2G4_rxv2_done_t rx_resp; 50 bool CRC_OK; 51 bool packet_rejected; 52 bool S1Offset; 53 bool codedphy; 54 uint8_t CI; 55 bool inFEC1; 56 bool CI_error; 57 } RADIO_Rx_status_t; 58 59 typedef struct { 60 bs_time_t ADDRESS_end_time; 61 bs_time_t FEC2_start_time; /* In air */ 62 bs_time_t PAYLOAD_end_time; 63 bs_time_t CRC_end_time; 64 p2G4_txv2_t tx_req_fec1; 65 p2G4_txv2_t tx_req; 66 p2G4_tx_done_t tx_resp; 67 bool codedphy; 68 } RADIO_Tx_status_t; 69 70 typedef struct { 71 bs_time_t CCA_end_time; 72 p2G4_cca_t cca_req; 73 p2G4_cca_done_t cca_resp; 74 bool is_busy; 75 bool CCA_notED; //Is it a CCA procedure (1), or ED procedure (0) 76 } RADIO_CCA_status_t; 77 78 #ifndef RADIO_EDCTRL_EDPERIOD_Msk 79 /* Workaround for missing mask in some MDK versions */ 80 /* To be removed once it is added to the MDK */ 81 #define RADIO_EDCTRL_EDPERIOD_Pos 24 82 #define RADIO_EDCTRL_EDPERIOD_Msk (0x3FUL << RADIO_EDCTRL_EDPERIOD_Pos) 83 #endif 84 85 #define _NRF_MAX_PACKET_SIZE (256+2+4) 86 87 #ifdef __cplusplus 88 } 89 #endif 90 91 #endif 92
