1 /**************************************************************************//** 2 * @file crc_reg.h 3 * @version V1.00 4 * @brief CRC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRC_REG_H__ 10 #define __CRC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup CRC Cyclic Redundancy Check Controller(CRC) 23 Memory Mapped Structure for CRC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var CRC_T::CTL 32 * Offset: 0x00 CRC Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |CRCEN |CRC Channel Enable Bit 37 * | | |0 = No effect. 38 * | | |1 = CRC operation Enabled. 39 * |[1] |CHKSINIT |Checksum Initialization 40 * | | |0 = No effect. 41 * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. 42 * | | |Note: This bit will be cleared automatically. 43 * |[24] |DATREV |Write Data Bit Order Reverse 44 * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. 45 * | | |0 = Bit order reversed for CRC write data in Disabled. 46 * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). 47 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. 48 * |[25] |CHKSREV |Checksum Bit Order Reverse 49 * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. 50 * | | |0 = Bit order reverse for CRC checksum Disabled. 51 * | | |1 = Bit order reverse for CRC checksum Enabled. 52 * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. 53 * |[26] |DATFMT |Write Data 1's Complement 54 * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. 55 * | | |0 = 1's complement for CRC writes data in Disabled. 56 * | | |1 = 1's complement for CRC writes data in Enabled. 57 * |[27] |CHKSFMT |Checksum 1's Complement 58 * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. 59 * | | |0 = 1's complement for CRC checksum Disabled. 60 * | | |1 = 1's complement for CRC checksum Enabled. 61 * |[29:28] |DATLEN |CPU Write Data Length 62 * | | |This field indicates the write data length. 63 * | | |00 = Data length is 8-bit mode. 64 * | | |01 = Data length is 16-bit mode. 65 * | | |1x = Data length is 32-bit mode. 66 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] 67 * |[31:30] |CRCMODE |CRC Polynomial Mode 68 * | | |This field indicates the CRC operation polynomial mode. 69 * | | |00 = CRC-CCITT Polynomial mode. 70 * | | |01 = CRC-8 Polynomial mode. 71 * | | |10 = CRC-16 Polynomial mode. 72 * | | |11 = CRC-32 Polynomial mode. 73 * @var CRC_T::DAT 74 * Offset: 0x04 CRC Write Data Register 75 * --------------------------------------------------------------------------------------------------- 76 * |Bits |Field |Descriptions 77 * | :----: | :----: | :---- | 78 * |[31:0] |DATA |CRC Write Data Bits 79 * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. 80 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. 81 * @var CRC_T::SEED 82 * Offset: 0x08 CRC Seed Register 83 * --------------------------------------------------------------------------------------------------- 84 * |Bits |Field |Descriptions 85 * | :----: | :----: | :---- | 86 * |[31:0] |SEED |CRC Seed Value 87 * | | |This field indicates the CRC seed value. 88 * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). 89 * @var CRC_T::CHECKSUM 90 * Offset: 0x0C CRC Checksum Register 91 * --------------------------------------------------------------------------------------------------- 92 * |Bits |Field |Descriptions 93 * | :----: | :----: | :---- | 94 * |[31:0] |CHECKSUM |CRC Checksum Results 95 * | | |This field indicates the CRC checksum result. 96 */ 97 __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ 98 __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ 99 __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ 100 __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ 101 102 } CRC_T; 103 104 /** 105 @addtogroup CRC_CONST CRC Bit Field Definition 106 Constant Definitions for CRC Controller 107 @{ */ 108 109 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ 110 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ 111 112 #define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ 113 #define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ 114 115 #define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ 116 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ 117 118 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ 119 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ 120 121 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ 122 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ 123 124 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ 125 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ 126 127 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ 128 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ 129 130 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ 131 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ 132 133 #define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ 134 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ 135 136 #define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ 137 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ 138 139 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ 140 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ 141 142 /**@}*/ /* CRC_CONST */ 143 /**@}*/ /* end of CRC register group */ 144 /**@}*/ /* end of REGISTER group */ 145 146 #if defined ( __CC_ARM ) 147 #pragma no_anon_unions 148 #endif 149 150 #endif /* __CRC_REG_H__ */ 151
