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Searched defs:CR1 (Results 1 – 25 of 84) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_ERM_GTM.h74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ member
DS32Z2_ERM.h74 …__IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4, a… member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_ERM.h74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/
DMCXC041.h598 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/
DMCXC242.h834 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h763 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h772 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/
DMCXC141.h834 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/
DMCXC144.h805 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/
DMCXC142.h832 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/
DMCXC143.h805 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h604 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h831 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/
DMCXC243.h803 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/
DMCXC244.h805 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h835 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h749 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h3096 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h848 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h740 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h1527 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h850 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h850 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h850 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B21A/
DK32L2B21A.h788 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member

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