1 /*
2 * Copyright (c) 2017 Linaro Limited
3 * Copyright (c) 2017 BayLibre, SAS.
4 * Copyright (c) 2023 Google Inc
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
10 #define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
11
12 #include <zephyr/drivers/flash.h>
13 #include "stm32_hsem.h"
14
15 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
16 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
17 #include <zephyr/drivers/clock_control.h>
18 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
19 #endif
20
21 /* Get the base address of the flash from the DTS node */
22 #define FLASH_STM32_BASE_ADDRESS DT_REG_ADDR(DT_INST(0, st_stm32_nv_flash))
23
24 struct flash_stm32_priv {
25 FLASH_TypeDef *regs;
26 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \
27 DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks)
28 /* clock subsystem driving this peripheral */
29 struct stm32_pclken pclken;
30 #endif
31 struct k_sem sem;
32 };
33
34 #if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
35 #define FLASH_STM32_WRITE_BLOCK_SIZE \
36 DT_PROP(DT_INST(0, soc_nv_flash), write_block_size)
37 #else
38 #error Flash write block size not available
39 /* Flash Write block size is extracted from device tree */
40 /* as flash node property 'write-block-size' */
41 #endif
42
43 #if defined(CONFIG_SOC_SERIES_STM32H5X)
44 /* FLASH register names differ for this serie */
45 #define FLASH_NSSR_BSY FLASH_SR_BSY
46 #define OPTR OPTCR
47 #endif /* CONFIG_SOC_SERIES_STM32H5X */
48
49 /* Register mapping for the stm32H7RS serie (single bank)*/
50 #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
51 #define FLASH_NB_32BITWORD_IN_FLASHWORD 4 /* 128 bits */
52 #define CR1 CR
53 #define SR1 SR
54 /* flash sectore Nb [0-7] */
55 #define FLASH_CR_SNB FLASH_CR_SSN
56 #define FLASH_CR_SNB_Pos FLASH_CR_SSN_Pos
57 #define KEYR1 KEYR
58 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */
59
60 /* Differentiate between arm trust-zone non-secure/secure, and others. */
61 #if defined(FLASH_NSSR_NSBSY) || defined(FLASH_NSSR_BSY) /* For mcu w. TZ in non-secure mode */
62 #define FLASH_SECURITY_NS
63 #define FLASH_STM32_SR NSSR
64 #elif defined(FLASH_SECSR_SECBSY) /* For mcu w. TZ in secured mode */
65 #error Flash is not supported in secure mode
66 #define FLASH_SECURITY_SEC
67 #else
68 #define FLASH_SECURITY_NA /* For series which does not have
69 * secured or non-secured mode
70 */
71 #define FLASH_STM32_SR SR
72 #endif
73
74
75 #define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
76 #define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)
77
78
79 /* Redefinitions of flags and masks to harmonize stm32 series: */
80 #if defined(CONFIG_SOC_SERIES_STM32U5X)
81 #define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK
82 #define FLASH_STM32_DBANK FLASH_OPTR_DUALBANK
83 #define FLASH_STM32_NSPG FLASH_NSCR_PG
84 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_BKER_Msk
85 #define FLASH_STM32_NSBKER FLASH_NSCR_BKER
86 #define FLASH_STM32_NSPER FLASH_NSCR_PER
87 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_PNB_Msk
88 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_PNB_Pos
89 #define FLASH_STM32_NSPNB FLASH_NSCR_PNB
90 #define FLASH_STM32_NSSTRT FLASH_NSCR_STRT
91 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
92 #elif defined(CONFIG_SOC_SERIES_STM32H5X)
93 #define FLASH_OPTR_SWAP_BANK FLASH_OPTCR_SWAP_BANK
94 #define FLASH_STM32_NSLOCK FLASH_CR_LOCK
95 #define FLASH_STM32_DBANK 1
96 #define FLASH_STM32_NSPG FLASH_CR_PG
97 #define FLASH_STM32_NSBKER_MSK FLASH_CR_BKSEL_Msk
98 #define FLASH_STM32_NSBKER FLASH_CR_BKSEL
99 #define FLASH_STM32_NSPER FLASH_CR_SER
100 #define FLASH_STM32_NSPNB_MSK FLASH_CR_SNB_Msk
101 #define FLASH_STM32_NSPNB_POS FLASH_CR_SNB_Pos
102 #define FLASH_STM32_NSPNB FLASH_CR_PNB
103 #define FLASH_STM32_NSSTRT FLASH_CR_START
104 /* TODO: get values from the cmsis and stm32h5_hal_flash.h */
105 #undef FLASH_SIZE
106 /* Retrieve the FLASH SIZE from the DTS instead of cmsis as it seems erroneous */
107 #define FLASH_SIZE (CONFIG_FLASH_SIZE * 1024)
108 /* Values are redefined below from the stm32h5_hal_flash.h */
109 #define FLASH_PAGE_SIZE (FLASH_SECTOR_SIZE)
110 #define FLASH_PAGE_NB (FLASH_SECTOR_NB)
111 #define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
112 #define FLASH_PAGE_SIZE_128_BITS FLASH_PAGE_SIZE
113 #elif defined(CONFIG_SOC_SERIES_STM32L5X)
114 #define FLASH_STM32_NSLOCK FLASH_NSCR_NSLOCK
115 #define FLASH_STM32_NSPG FLASH_NSCR_NSPG
116 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR_NSBKER_Pos
117 #define FLASH_STM32_NSBKER FLASH_NSCR_NSBKER
118 #define FLASH_STM32_NSPER FLASH_NSCR_NSPER
119 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR_NSPNB_Msk
120 #define FLASH_STM32_NSPNB_POS FLASH_NSCR_NSPNB_Pos
121 #define FLASH_STM32_NSPNB FLASH_NSCR_NSPNB
122 #define FLASH_STM32_NSSTRT FLASH_NSCR_NSSTRT
123 #elif defined(CONFIG_SOC_SERIES_STM32WBAX)
124 #define NSCR NSCR1
125 #define FLASH_STM32_NSLOCK FLASH_NSCR1_LOCK
126 #define FLASH_STM32_NSPG FLASH_NSCR1_PG
127 #define FLASH_STM32_NSBKER_MSK FLASH_NSCR1_BKER_Msk
128 #define FLASH_STM32_NSBKER FLASH_NSCR1_BKER
129 #define FLASH_STM32_NSPER FLASH_NSCR1_PER
130 #define FLASH_STM32_NSPNB_MSK FLASH_NSCR1_PNB_Msk
131 #define FLASH_STM32_NSPNB_POS FLASH_NSCR1_PNB_Pos
132 #define FLASH_STM32_NSPNB FLASH_NSCR1_PNB
133 #define FLASH_STM32_NSSTRT FLASH_NSCR1_STRT
134 #endif /* CONFIG_SOC_SERIES_STM32U5X */
135 #if defined(FLASH_OPTR_DBANK)
136 #define FLASH_STM32_DBANK FLASH_OPTR_DBANK
137 #endif /* FLASH_OPTR_DBANK */
138
139 #if defined(CONFIG_SOC_SERIES_STM32G0X)
140 #if defined(FLASH_FLAG_BSY2)
141 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY1 | FLASH_FLAG_BSY2);
142 #else
143 #define FLASH_STM32_SR_BUSY (FLASH_SR_BSY1)
144 #endif /* defined(FLASH_FLAG_BSY2) */
145 #else
146 #define FLASH_STM32_SR_BUSY (FLASH_FLAG_BSY)
147 #endif
148
149 #if defined(CONFIG_SOC_SERIES_STM32G0X)
150 #define FLASH_STM32_SR_CFGBSY (FLASH_SR_CFGBSY)
151 #elif defined(FLASH_FLAG_CFGBSY)
152 #define FLASH_STM32_SR_CFGBSY (FLASH_FLAG_CFGBSY)
153 #endif
154
155 #if defined(CONFIG_SOC_SERIES_STM32G0X)
156 /* STM32G0 HAL FLASH_FLAG_x don't represent bit-masks, need FLASH_SR_x instead */
157 #define FLASH_STM32_SR_OPERR FLASH_SR_OPERR
158 #define FLASH_STM32_SR_PGERR 0
159 #define FLASH_STM32_SR_PROGERR FLASH_SR_PROGERR
160 #define FLASH_STM32_SR_WRPERR FLASH_SR_WRPERR
161 #define FLASH_STM32_SR_PGAERR FLASH_SR_PGAERR
162 #define FLASH_STM32_SR_SIZERR FLASH_SR_SIZERR
163 #define FLASH_STM32_SR_PGSERR FLASH_SR_PGSERR
164 #define FLASH_STM32_SR_MISERR FLASH_SR_MISERR
165 #define FLASH_STM32_SR_FASTERR FLASH_SR_FASTERR
166 #if defined(FLASH_SR_RDERR)
167 #define FLASH_STM32_SR_RDERR FLASH_SR_RDERR
168 #else
169 #define FLASH_STM32_SR_RDERR 0
170 #endif
171 #define FLASH_STM32_SR_PGPERR 0
172
173 #else /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
174 #if defined(FLASH_FLAG_OPERR)
175 #define FLASH_STM32_SR_OPERR FLASH_FLAG_OPERR
176 #else
177 #define FLASH_STM32_SR_OPERR 0
178 #endif
179
180 #if defined(FLASH_FLAG_PGERR)
181 #define FLASH_STM32_SR_PGERR FLASH_FLAG_PGERR
182 #else
183 #define FLASH_STM32_SR_PGERR 0
184 #endif
185
186 #if defined(FLASH_FLAG_PROGERR)
187 #define FLASH_STM32_SR_PROGERR FLASH_FLAG_PROGERR
188 #else
189 #define FLASH_STM32_SR_PROGERR 0
190 #endif
191
192 #if defined(FLASH_FLAG_WRPERR)
193 #define FLASH_STM32_SR_WRPERR FLASH_FLAG_WRPERR
194 #else
195 #define FLASH_STM32_SR_WRPERR 0
196 #endif
197
198 #if defined(FLASH_FLAG_PGAERR)
199 #define FLASH_STM32_SR_PGAERR FLASH_FLAG_PGAERR
200 #else
201 #define FLASH_STM32_SR_PGAERR 0
202 #endif
203
204 #if defined(FLASH_FLAG_SIZERR)
205 #define FLASH_STM32_SR_SIZERR FLASH_FLAG_SIZERR
206 #else
207 #define FLASH_STM32_SR_SIZERR 0
208 #endif
209
210 #if defined(FLASH_FLAG_PGSERR)
211 #define FLASH_STM32_SR_PGSERR FLASH_FLAG_PGSERR
212 #else
213 #define FLASH_STM32_SR_PGSERR 0
214 #endif
215
216 #if defined(FLASH_FLAG_MISERR)
217 #define FLASH_STM32_SR_MISERR FLASH_FLAG_MISERR
218 #else
219 #define FLASH_STM32_SR_MISERR 0
220 #endif
221
222 #if defined(FLASH_FLAG_FASTERR)
223 #define FLASH_STM32_SR_FASTERR FLASH_FLAG_FASTERR
224 #else
225 #define FLASH_STM32_SR_FASTERR 0
226 #endif
227
228 #if defined(FLASH_FLAG_RDERR)
229 #define FLASH_STM32_SR_RDERR FLASH_FLAG_RDERR
230 #else
231 #define FLASH_STM32_SR_RDERR 0
232 #endif
233
234 #if defined(FLASH_FLAG_PGPERR)
235 #define FLASH_STM32_SR_PGPERR FLASH_FLAG_PGPERR
236 #else
237 #define FLASH_STM32_SR_PGPERR 0
238 #endif
239
240 #endif /* !defined(CONFIG_SOC_SERIES_STM32G0X) */
241
242 #define FLASH_STM32_SR_ERRORS (FLASH_STM32_SR_OPERR | \
243 FLASH_STM32_SR_PGERR | \
244 FLASH_STM32_SR_PROGERR | \
245 FLASH_STM32_SR_WRPERR | \
246 FLASH_STM32_SR_PGAERR | \
247 FLASH_STM32_SR_SIZERR | \
248 FLASH_STM32_SR_PGSERR | \
249 FLASH_STM32_SR_MISERR | \
250 FLASH_STM32_SR_FASTERR | \
251 FLASH_STM32_SR_RDERR | \
252 FLASH_STM32_SR_PGPERR)
253
254 #define FLASH_STM32_RDP0 0xAA
255 #define FLASH_STM32_RDP2 0xCC
256 #define FLASH_STM32_RDP1 \
257 DT_PROP(DT_INST(0, st_stm32_flash_controller), st_rdp1_enable_byte)
258
259 #if FLASH_STM32_RDP1 == FLASH_STM32_RDP0 || FLASH_STM32_RDP1 == FLASH_STM32_RDP2
260 #error RDP1 byte has to be different than RDP0 and RDP2 byte
261 #endif
262
263 #ifdef CONFIG_FLASH_PAGE_LAYOUT
flash_stm32_range_exists(const struct device * dev,off_t offset,uint32_t len)264 static inline bool flash_stm32_range_exists(const struct device *dev,
265 off_t offset,
266 uint32_t len)
267 {
268 struct flash_pages_info info;
269
270 return !(flash_get_page_info_by_offs(dev, offset, &info) ||
271 flash_get_page_info_by_offs(dev, offset + len - 1, &info));
272 }
273 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
274
275
276 #if defined(CONFIG_MULTITHREADING) || defined(CONFIG_STM32H7_DUAL_CORE)
277 /*
278 * This is named flash_stm32_sem_take instead of flash_stm32_lock (and
279 * similarly for flash_stm32_sem_give) to avoid confusion with locking
280 * actual flash pages.
281 */
282
_flash_stm32_sem_take(const struct device * dev)283 static inline void _flash_stm32_sem_take(const struct device *dev)
284 {
285 k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
286 z_stm32_hsem_lock(CFG_HW_FLASH_SEMID, HSEM_LOCK_WAIT_FOREVER);
287 }
288
_flash_stm32_sem_give(const struct device * dev)289 static inline void _flash_stm32_sem_give(const struct device *dev)
290 {
291 z_stm32_hsem_unlock(CFG_HW_FLASH_SEMID);
292 k_sem_give(&FLASH_STM32_PRIV(dev)->sem);
293 }
294
295 #define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1)
296 #define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev)
297 #define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev)
298 #else
299 #define flash_stm32_sem_init(dev)
300 #define flash_stm32_sem_take(dev)
301 #define flash_stm32_sem_give(dev)
302 #endif /* CONFIG_MULTITHREADING */
303
304 #ifdef CONFIG_FLASH_EX_OP_ENABLED
305 int flash_stm32_ex_op(const struct device *dev, uint16_t code,
306 const uintptr_t in, void *out);
307 #endif /* CONFIG_FLASH_EX_OP_ENABLED */
308
flash_stm32_valid_write(off_t offset,uint32_t len)309 static inline bool flash_stm32_valid_write(off_t offset, uint32_t len)
310 {
311 return ((offset % FLASH_STM32_WRITE_BLOCK_SIZE == 0) &&
312 (len % FLASH_STM32_WRITE_BLOCK_SIZE == 0U));
313 }
314
315 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
316 uint32_t len, bool write);
317
318 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
319 const void *data, unsigned int len);
320
321 int flash_stm32_block_erase_loop(const struct device *dev,
322 unsigned int offset,
323 unsigned int len);
324
325 int flash_stm32_wait_flash_idle(const struct device *dev);
326
327 int flash_stm32_option_bytes_lock(const struct device *dev, bool enable);
328
329 uint32_t flash_stm32_option_bytes_read(const struct device *dev);
330
331 int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
332 uint32_t value);
333
334 #ifdef CONFIG_SOC_SERIES_STM32WBX
335 int flash_stm32_check_status(const struct device *dev);
336 #endif /* CONFIG_SOC_SERIES_STM32WBX */
337
338 #ifdef CONFIG_FLASH_PAGE_LAYOUT
339 void flash_stm32_page_layout(const struct device *dev,
340 const struct flash_pages_layout **layout,
341 size_t *layout_size);
342 #endif
343
344 #if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
345
346 int flash_stm32_update_wp_sectors(const struct device *dev,
347 uint64_t changed_sectors,
348 uint64_t protected_sectors);
349
350 int flash_stm32_get_wp_sectors(const struct device *dev,
351 uint64_t *protected_sectors);
352 #endif
353 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
354 uint8_t flash_stm32_get_rdp_level(const struct device *dev);
355
356 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level);
357 #endif
358
359 #if defined(CONFIG_FLASH_STM32_BLOCK_REGISTERS)
360 int flash_stm32_control_register_disable(const struct device *dev);
361 int flash_stm32_option_bytes_disable(const struct device *dev);
362 #endif
363
364 #endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */
365
