1 /***************************************************************************//** 2 * \file cyip_cpuss_v2.h 3 * 4 * \brief 5 * CPUSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CPUSS_V2_H_ 28 #define _CYIP_CPUSS_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CPUSS 34 *******************************************************************************/ 35 36 #define CPUSS_V2_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief CPU subsystem (CPUSS) (CPUSS) 40 */ 41 typedef struct { 42 __IM uint32_t IDENTITY; /*!< 0x00000000 Identity */ 43 __IM uint32_t CM4_STATUS; /*!< 0x00000004 CM4 status */ 44 __IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000008 CM4 clock control */ 45 __IOM uint32_t CM4_CTL; /*!< 0x0000000C CM4 control */ 46 __IM uint32_t RESERVED[60]; 47 __IM uint32_t CM4_INT0_STATUS; /*!< 0x00000100 CM4 interrupt 0 status */ 48 __IM uint32_t CM4_INT1_STATUS; /*!< 0x00000104 CM4 interrupt 1 status */ 49 __IM uint32_t CM4_INT2_STATUS; /*!< 0x00000108 CM4 interrupt 2 status */ 50 __IM uint32_t CM4_INT3_STATUS; /*!< 0x0000010C CM4 interrupt 3 status */ 51 __IM uint32_t CM4_INT4_STATUS; /*!< 0x00000110 CM4 interrupt 4 status */ 52 __IM uint32_t CM4_INT5_STATUS; /*!< 0x00000114 CM4 interrupt 5 status */ 53 __IM uint32_t CM4_INT6_STATUS; /*!< 0x00000118 CM4 interrupt 6 status */ 54 __IM uint32_t CM4_INT7_STATUS; /*!< 0x0000011C CM4 interrupt 7 status */ 55 __IM uint32_t RESERVED1[56]; 56 __IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x00000200 CM4 vector table base */ 57 __IM uint32_t RESERVED2[15]; 58 __IOM uint32_t CM4_NMI_CTL[4]; /*!< 0x00000240 CM4 NMI control */ 59 __IM uint32_t RESERVED3[44]; 60 __IOM uint32_t UDB_PWR_CTL; /*!< 0x00000300 UDB power control */ 61 __IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x00000304 UDB power control */ 62 __IM uint32_t RESERVED4[830]; 63 __IOM uint32_t CM0_CTL; /*!< 0x00001000 CM0+ control */ 64 __IM uint32_t CM0_STATUS; /*!< 0x00001004 CM0+ status */ 65 __IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00001008 CM0+ clock control */ 66 __IM uint32_t RESERVED5[61]; 67 __IM uint32_t CM0_INT0_STATUS; /*!< 0x00001100 CM0+ interrupt 0 status */ 68 __IM uint32_t CM0_INT1_STATUS; /*!< 0x00001104 CM0+ interrupt 1 status */ 69 __IM uint32_t CM0_INT2_STATUS; /*!< 0x00001108 CM0+ interrupt 2 status */ 70 __IM uint32_t CM0_INT3_STATUS; /*!< 0x0000110C CM0+ interrupt 3 status */ 71 __IM uint32_t CM0_INT4_STATUS; /*!< 0x00001110 CM0+ interrupt 4 status */ 72 __IM uint32_t CM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */ 73 __IM uint32_t CM0_INT6_STATUS; /*!< 0x00001118 CM0+ interrupt 6 status */ 74 __IM uint32_t CM0_INT7_STATUS; /*!< 0x0000111C CM0+ interrupt 7 status */ 75 __IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x00001120 CM0+ vector table base */ 76 __IM uint32_t RESERVED6[7]; 77 __IOM uint32_t CM0_NMI_CTL[4]; /*!< 0x00001140 CM0+ NMI control */ 78 __IM uint32_t RESERVED7[44]; 79 __IOM uint32_t CM4_PWR_CTL; /*!< 0x00001200 CM4 power control */ 80 __IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00001204 CM4 power control */ 81 __IM uint32_t RESERVED8[62]; 82 __IOM uint32_t RAM0_CTL0; /*!< 0x00001300 RAM 0 control */ 83 __IM uint32_t RAM0_STATUS; /*!< 0x00001304 RAM 0 status */ 84 __IM uint32_t RESERVED9[14]; 85 __IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00001340 RAM 0 power control */ 86 __IOM uint32_t RAM1_CTL0; /*!< 0x00001380 RAM 1 control */ 87 __IM uint32_t RAM1_STATUS; /*!< 0x00001384 RAM 1 status */ 88 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */ 89 __IM uint32_t RESERVED10[5]; 90 __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ 91 __IM uint32_t RAM2_STATUS; /*!< 0x000013A4 RAM 2 status */ 92 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */ 93 __IM uint32_t RESERVED11[5]; 94 __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000013C0 Power up delay used for all SRAM power domains */ 95 __IOM uint32_t ROM_CTL; /*!< 0x000013C4 ROM control */ 96 __IOM uint32_t ECC_CTL; /*!< 0x000013C8 ECC control */ 97 __IM uint32_t RESERVED12[13]; 98 __IM uint32_t PRODUCT_ID; /*!< 0x00001400 Product identifier and version (same as CoreSight RomTables) */ 99 __IM uint32_t RESERVED13[3]; 100 __IM uint32_t DP_STATUS; /*!< 0x00001410 Debug port status */ 101 __IOM uint32_t AP_CTL; /*!< 0x00001414 Access port control */ 102 __IM uint32_t RESERVED14[58]; 103 __IOM uint32_t BUFF_CTL; /*!< 0x00001500 Buffer control */ 104 __IM uint32_t RESERVED15[63]; 105 __IOM uint32_t SYSTICK_CTL; /*!< 0x00001600 SysTick timer control */ 106 __IM uint32_t RESERVED16[64]; 107 __IM uint32_t MBIST_STAT; /*!< 0x00001704 Memory BIST status */ 108 __IM uint32_t RESERVED17[62]; 109 __IOM uint32_t CAL_SUP_SET; /*!< 0x00001800 Calibration support set and read */ 110 __IOM uint32_t CAL_SUP_CLR; /*!< 0x00001804 Calibration support clear and reset */ 111 __IM uint32_t RESERVED18[510]; 112 __IOM uint32_t CM0_PC_CTL; /*!< 0x00002000 CM0+ protection context control */ 113 __IM uint32_t RESERVED19[15]; 114 __IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00002040 CM0+ protection context 0 handler */ 115 __IOM uint32_t CM0_PC1_HANDLER; /*!< 0x00002044 CM0+ protection context 1 handler */ 116 __IOM uint32_t CM0_PC2_HANDLER; /*!< 0x00002048 CM0+ protection context 2 handler */ 117 __IOM uint32_t CM0_PC3_HANDLER; /*!< 0x0000204C CM0+ protection context 3 handler */ 118 __IM uint32_t RESERVED20[29]; 119 __IOM uint32_t PROTECTION; /*!< 0x000020C4 Protection status */ 120 __IM uint32_t RESERVED21[14]; 121 __IOM uint32_t TRIM_ROM_CTL; /*!< 0x00002100 ROM trim control */ 122 __IOM uint32_t TRIM_RAM_CTL; /*!< 0x00002104 RAM trim control */ 123 __IM uint32_t RESERVED22[6078]; 124 __IOM uint32_t CM0_SYSTEM_INT_CTL[1023]; /*!< 0x00008000 CM0+ system interrupt control */ 125 __IM uint32_t RESERVED23[1025]; 126 __IOM uint32_t CM4_SYSTEM_INT_CTL[1023]; /*!< 0x0000A000 CM4 system interrupt control */ 127 } CPUSS_V2_Type; /*!< Size = 45052 (0xAFFC) */ 128 129 130 /* CPUSS.IDENTITY */ 131 #define CPUSS_V2_IDENTITY_P_Pos 0UL 132 #define CPUSS_V2_IDENTITY_P_Msk 0x1UL 133 #define CPUSS_V2_IDENTITY_NS_Pos 1UL 134 #define CPUSS_V2_IDENTITY_NS_Msk 0x2UL 135 #define CPUSS_V2_IDENTITY_PC_Pos 4UL 136 #define CPUSS_V2_IDENTITY_PC_Msk 0xF0UL 137 #define CPUSS_V2_IDENTITY_MS_Pos 8UL 138 #define CPUSS_V2_IDENTITY_MS_Msk 0xF00UL 139 /* CPUSS.CM4_STATUS */ 140 #define CPUSS_V2_CM4_STATUS_SLEEPING_Pos 0UL 141 #define CPUSS_V2_CM4_STATUS_SLEEPING_Msk 0x1UL 142 #define CPUSS_V2_CM4_STATUS_SLEEPDEEP_Pos 1UL 143 #define CPUSS_V2_CM4_STATUS_SLEEPDEEP_Msk 0x2UL 144 #define CPUSS_V2_CM4_STATUS_PWR_DONE_Pos 4UL 145 #define CPUSS_V2_CM4_STATUS_PWR_DONE_Msk 0x10UL 146 /* CPUSS.CM4_CLOCK_CTL */ 147 #define CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL 148 #define CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL 149 /* CPUSS.CM4_CTL */ 150 #define CPUSS_V2_CM4_CTL_IOC_MASK_Pos 24UL 151 #define CPUSS_V2_CM4_CTL_IOC_MASK_Msk 0x1000000UL 152 #define CPUSS_V2_CM4_CTL_DZC_MASK_Pos 25UL 153 #define CPUSS_V2_CM4_CTL_DZC_MASK_Msk 0x2000000UL 154 #define CPUSS_V2_CM4_CTL_OFC_MASK_Pos 26UL 155 #define CPUSS_V2_CM4_CTL_OFC_MASK_Msk 0x4000000UL 156 #define CPUSS_V2_CM4_CTL_UFC_MASK_Pos 27UL 157 #define CPUSS_V2_CM4_CTL_UFC_MASK_Msk 0x8000000UL 158 #define CPUSS_V2_CM4_CTL_IXC_MASK_Pos 28UL 159 #define CPUSS_V2_CM4_CTL_IXC_MASK_Msk 0x10000000UL 160 #define CPUSS_V2_CM4_CTL_IDC_MASK_Pos 31UL 161 #define CPUSS_V2_CM4_CTL_IDC_MASK_Msk 0x80000000UL 162 /* CPUSS.CM4_INT0_STATUS */ 163 #define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL 164 #define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 165 #define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL 166 #define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 167 /* CPUSS.CM4_INT1_STATUS */ 168 #define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL 169 #define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 170 #define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL 171 #define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 172 /* CPUSS.CM4_INT2_STATUS */ 173 #define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL 174 #define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 175 #define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL 176 #define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 177 /* CPUSS.CM4_INT3_STATUS */ 178 #define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL 179 #define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 180 #define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL 181 #define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 182 /* CPUSS.CM4_INT4_STATUS */ 183 #define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL 184 #define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 185 #define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL 186 #define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 187 /* CPUSS.CM4_INT5_STATUS */ 188 #define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL 189 #define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 190 #define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL 191 #define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 192 /* CPUSS.CM4_INT6_STATUS */ 193 #define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL 194 #define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 195 #define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL 196 #define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 197 /* CPUSS.CM4_INT7_STATUS */ 198 #define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL 199 #define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 200 #define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL 201 #define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 202 /* CPUSS.CM4_VECTOR_TABLE_BASE */ 203 #define CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL 204 #define CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL 205 /* CPUSS.CM4_NMI_CTL */ 206 #define CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL 207 #define CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL 208 /* CPUSS.UDB_PWR_CTL */ 209 #define CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Pos 0UL 210 #define CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL 211 #define CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL 212 #define CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 213 /* CPUSS.UDB_PWR_DELAY_CTL */ 214 #define CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Pos 0UL 215 #define CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL 216 /* CPUSS.CM0_CTL */ 217 #define CPUSS_V2_CM0_CTL_SLV_STALL_Pos 0UL 218 #define CPUSS_V2_CM0_CTL_SLV_STALL_Msk 0x1UL 219 #define CPUSS_V2_CM0_CTL_ENABLED_Pos 1UL 220 #define CPUSS_V2_CM0_CTL_ENABLED_Msk 0x2UL 221 #define CPUSS_V2_CM0_CTL_VECTKEYSTAT_Pos 16UL 222 #define CPUSS_V2_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 223 /* CPUSS.CM0_STATUS */ 224 #define CPUSS_V2_CM0_STATUS_SLEEPING_Pos 0UL 225 #define CPUSS_V2_CM0_STATUS_SLEEPING_Msk 0x1UL 226 #define CPUSS_V2_CM0_STATUS_SLEEPDEEP_Pos 1UL 227 #define CPUSS_V2_CM0_STATUS_SLEEPDEEP_Msk 0x2UL 228 /* CPUSS.CM0_CLOCK_CTL */ 229 #define CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL 230 #define CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL 231 #define CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL 232 #define CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL 233 /* CPUSS.CM0_INT0_STATUS */ 234 #define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL 235 #define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 236 #define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL 237 #define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 238 /* CPUSS.CM0_INT1_STATUS */ 239 #define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL 240 #define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 241 #define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL 242 #define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 243 /* CPUSS.CM0_INT2_STATUS */ 244 #define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL 245 #define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 246 #define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL 247 #define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 248 /* CPUSS.CM0_INT3_STATUS */ 249 #define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL 250 #define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 251 #define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL 252 #define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 253 /* CPUSS.CM0_INT4_STATUS */ 254 #define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL 255 #define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 256 #define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL 257 #define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 258 /* CPUSS.CM0_INT5_STATUS */ 259 #define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL 260 #define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 261 #define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL 262 #define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 263 /* CPUSS.CM0_INT6_STATUS */ 264 #define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL 265 #define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 266 #define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL 267 #define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 268 /* CPUSS.CM0_INT7_STATUS */ 269 #define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL 270 #define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL 271 #define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL 272 #define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL 273 /* CPUSS.CM0_VECTOR_TABLE_BASE */ 274 #define CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL 275 #define CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL 276 /* CPUSS.CM0_NMI_CTL */ 277 #define CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL 278 #define CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL 279 /* CPUSS.CM4_PWR_CTL */ 280 #define CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Pos 0UL 281 #define CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL 282 #define CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL 283 #define CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 284 /* CPUSS.CM4_PWR_DELAY_CTL */ 285 #define CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Pos 0UL 286 #define CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL 287 /* CPUSS.RAM0_CTL0 */ 288 #define CPUSS_V2_RAM0_CTL0_SLOW_WS_Pos 0UL 289 #define CPUSS_V2_RAM0_CTL0_SLOW_WS_Msk 0x3UL 290 #define CPUSS_V2_RAM0_CTL0_FAST_WS_Pos 8UL 291 #define CPUSS_V2_RAM0_CTL0_FAST_WS_Msk 0x300UL 292 #define CPUSS_V2_RAM0_CTL0_ECC_EN_Pos 16UL 293 #define CPUSS_V2_RAM0_CTL0_ECC_EN_Msk 0x10000UL 294 #define CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Pos 17UL 295 #define CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL 296 #define CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Pos 18UL 297 #define CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Msk 0x40000UL 298 /* CPUSS.RAM0_STATUS */ 299 #define CPUSS_V2_RAM0_STATUS_WB_EMPTY_Pos 0UL 300 #define CPUSS_V2_RAM0_STATUS_WB_EMPTY_Msk 0x1UL 301 /* CPUSS.RAM0_PWR_MACRO_CTL */ 302 #define CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL 303 #define CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL 304 #define CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL 305 #define CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 306 /* CPUSS.RAM1_CTL0 */ 307 #define CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos 0UL 308 #define CPUSS_V2_RAM1_CTL0_SLOW_WS_Msk 0x3UL 309 #define CPUSS_V2_RAM1_CTL0_FAST_WS_Pos 8UL 310 #define CPUSS_V2_RAM1_CTL0_FAST_WS_Msk 0x300UL 311 #define CPUSS_V2_RAM1_CTL0_ECC_EN_Pos 16UL 312 #define CPUSS_V2_RAM1_CTL0_ECC_EN_Msk 0x10000UL 313 #define CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Pos 17UL 314 #define CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL 315 #define CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Pos 18UL 316 #define CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Msk 0x40000UL 317 /* CPUSS.RAM1_STATUS */ 318 #define CPUSS_V2_RAM1_STATUS_WB_EMPTY_Pos 0UL 319 #define CPUSS_V2_RAM1_STATUS_WB_EMPTY_Msk 0x1UL 320 /* CPUSS.RAM1_PWR_CTL */ 321 #define CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Pos 0UL 322 #define CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL 323 #define CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL 324 #define CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 325 /* CPUSS.RAM2_CTL0 */ 326 #define CPUSS_V2_RAM2_CTL0_SLOW_WS_Pos 0UL 327 #define CPUSS_V2_RAM2_CTL0_SLOW_WS_Msk 0x3UL 328 #define CPUSS_V2_RAM2_CTL0_FAST_WS_Pos 8UL 329 #define CPUSS_V2_RAM2_CTL0_FAST_WS_Msk 0x300UL 330 #define CPUSS_V2_RAM2_CTL0_ECC_EN_Pos 16UL 331 #define CPUSS_V2_RAM2_CTL0_ECC_EN_Msk 0x10000UL 332 #define CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Pos 17UL 333 #define CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL 334 #define CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Pos 18UL 335 #define CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Msk 0x40000UL 336 /* CPUSS.RAM2_STATUS */ 337 #define CPUSS_V2_RAM2_STATUS_WB_EMPTY_Pos 0UL 338 #define CPUSS_V2_RAM2_STATUS_WB_EMPTY_Msk 0x1UL 339 /* CPUSS.RAM2_PWR_CTL */ 340 #define CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Pos 0UL 341 #define CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL 342 #define CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL 343 #define CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL 344 /* CPUSS.RAM_PWR_DELAY_CTL */ 345 #define CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL 346 #define CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL 347 /* CPUSS.ROM_CTL */ 348 #define CPUSS_V2_ROM_CTL_SLOW_WS_Pos 0UL 349 #define CPUSS_V2_ROM_CTL_SLOW_WS_Msk 0x3UL 350 #define CPUSS_V2_ROM_CTL_FAST_WS_Pos 8UL 351 #define CPUSS_V2_ROM_CTL_FAST_WS_Msk 0x300UL 352 /* CPUSS.ECC_CTL */ 353 #define CPUSS_V2_ECC_CTL_WORD_ADDR_Pos 0UL 354 #define CPUSS_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFFFFUL 355 #define CPUSS_V2_ECC_CTL_PARITY_Pos 25UL 356 #define CPUSS_V2_ECC_CTL_PARITY_Msk 0xFE000000UL 357 /* CPUSS.PRODUCT_ID */ 358 #define CPUSS_V2_PRODUCT_ID_FAMILY_ID_Pos 0UL 359 #define CPUSS_V2_PRODUCT_ID_FAMILY_ID_Msk 0xFFFUL 360 #define CPUSS_V2_PRODUCT_ID_MAJOR_REV_Pos 16UL 361 #define CPUSS_V2_PRODUCT_ID_MAJOR_REV_Msk 0xF0000UL 362 #define CPUSS_V2_PRODUCT_ID_MINOR_REV_Pos 20UL 363 #define CPUSS_V2_PRODUCT_ID_MINOR_REV_Msk 0xF00000UL 364 /* CPUSS.DP_STATUS */ 365 #define CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Pos 0UL 366 #define CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL 367 #define CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL 368 #define CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL 369 #define CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL 370 #define CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL 371 /* CPUSS.AP_CTL */ 372 #define CPUSS_V2_AP_CTL_CM0_ENABLE_Pos 0UL 373 #define CPUSS_V2_AP_CTL_CM0_ENABLE_Msk 0x1UL 374 #define CPUSS_V2_AP_CTL_CM4_ENABLE_Pos 1UL 375 #define CPUSS_V2_AP_CTL_CM4_ENABLE_Msk 0x2UL 376 #define CPUSS_V2_AP_CTL_SYS_ENABLE_Pos 2UL 377 #define CPUSS_V2_AP_CTL_SYS_ENABLE_Msk 0x4UL 378 #define CPUSS_V2_AP_CTL_CM0_DISABLE_Pos 16UL 379 #define CPUSS_V2_AP_CTL_CM0_DISABLE_Msk 0x10000UL 380 #define CPUSS_V2_AP_CTL_CM4_DISABLE_Pos 17UL 381 #define CPUSS_V2_AP_CTL_CM4_DISABLE_Msk 0x20000UL 382 #define CPUSS_V2_AP_CTL_SYS_DISABLE_Pos 18UL 383 #define CPUSS_V2_AP_CTL_SYS_DISABLE_Msk 0x40000UL 384 /* CPUSS.BUFF_CTL */ 385 #define CPUSS_V2_BUFF_CTL_WRITE_BUFF_Pos 0UL 386 #define CPUSS_V2_BUFF_CTL_WRITE_BUFF_Msk 0x1UL 387 /* CPUSS.SYSTICK_CTL */ 388 #define CPUSS_V2_SYSTICK_CTL_TENMS_Pos 0UL 389 #define CPUSS_V2_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL 390 #define CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL 391 #define CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL 392 #define CPUSS_V2_SYSTICK_CTL_SKEW_Pos 30UL 393 #define CPUSS_V2_SYSTICK_CTL_SKEW_Msk 0x40000000UL 394 #define CPUSS_V2_SYSTICK_CTL_NOREF_Pos 31UL 395 #define CPUSS_V2_SYSTICK_CTL_NOREF_Msk 0x80000000UL 396 /* CPUSS.MBIST_STAT */ 397 #define CPUSS_V2_MBIST_STAT_SFP_READY_Pos 0UL 398 #define CPUSS_V2_MBIST_STAT_SFP_READY_Msk 0x1UL 399 #define CPUSS_V2_MBIST_STAT_SFP_FAIL_Pos 1UL 400 #define CPUSS_V2_MBIST_STAT_SFP_FAIL_Msk 0x2UL 401 /* CPUSS.CAL_SUP_SET */ 402 #define CPUSS_V2_CAL_SUP_SET_DATA_Pos 0UL 403 #define CPUSS_V2_CAL_SUP_SET_DATA_Msk 0xFFFFFFFFUL 404 /* CPUSS.CAL_SUP_CLR */ 405 #define CPUSS_V2_CAL_SUP_CLR_DATA_Pos 0UL 406 #define CPUSS_V2_CAL_SUP_CLR_DATA_Msk 0xFFFFFFFFUL 407 /* CPUSS.CM0_PC_CTL */ 408 #define CPUSS_V2_CM0_PC_CTL_VALID_Pos 0UL 409 #define CPUSS_V2_CM0_PC_CTL_VALID_Msk 0xFUL 410 /* CPUSS.CM0_PC0_HANDLER */ 411 #define CPUSS_V2_CM0_PC0_HANDLER_ADDR_Pos 0UL 412 #define CPUSS_V2_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL 413 /* CPUSS.CM0_PC1_HANDLER */ 414 #define CPUSS_V2_CM0_PC1_HANDLER_ADDR_Pos 0UL 415 #define CPUSS_V2_CM0_PC1_HANDLER_ADDR_Msk 0xFFFFFFFFUL 416 /* CPUSS.CM0_PC2_HANDLER */ 417 #define CPUSS_V2_CM0_PC2_HANDLER_ADDR_Pos 0UL 418 #define CPUSS_V2_CM0_PC2_HANDLER_ADDR_Msk 0xFFFFFFFFUL 419 /* CPUSS.CM0_PC3_HANDLER */ 420 #define CPUSS_V2_CM0_PC3_HANDLER_ADDR_Pos 0UL 421 #define CPUSS_V2_CM0_PC3_HANDLER_ADDR_Msk 0xFFFFFFFFUL 422 /* CPUSS.PROTECTION */ 423 #define CPUSS_V2_PROTECTION_STATE_Pos 0UL 424 #define CPUSS_V2_PROTECTION_STATE_Msk 0x7UL 425 /* CPUSS.TRIM_ROM_CTL */ 426 #define CPUSS_V2_TRIM_ROM_CTL_TRIM_Pos 0UL 427 #define CPUSS_V2_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL 428 /* CPUSS.TRIM_RAM_CTL */ 429 #define CPUSS_V2_TRIM_RAM_CTL_TRIM_Pos 0UL 430 #define CPUSS_V2_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL 431 /* CPUSS.CM0_SYSTEM_INT_CTL */ 432 #define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL 433 #define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0x7UL 434 #define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL 435 #define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL 436 /* CPUSS.CM4_SYSTEM_INT_CTL */ 437 #define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL 438 #define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0x7UL 439 #define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL 440 #define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL 441 442 443 #endif /* _CYIP_CPUSS_V2_H_ */ 444 445 446 /* [] END OF FILE */ 447
