1 /*
2 * Copyright (c) 2021 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <kernel_internal.h>
9 #include <zephyr/toolchain.h>
10 #include <zephyr/debug/gdbstub.h>
11
12 #include <xtensa_asm2_context.h>
13 #include <xtensa/corebits.h>
14
15 static bool not_first_break;
16
17 extern struct gdb_ctx xtensa_gdb_ctx;
18
19 /*
20 * Special register number (from specreg.h).
21 *
22 * These should be the same across different Xtensa SoCs.
23 */
24 enum {
25 LBEG = 0,
26 LEND = 1,
27 LCOUNT = 2,
28 SAR = 3,
29 SCOMPARE1 = 12,
30 WINDOWBASE = 72,
31 WINDOWSTART = 73,
32 IBREAKENABLE = 96,
33 MEMCTL = 97,
34 ATOMCTL = 99,
35 IBREAKA0 = 128,
36 IBREAKA1 = 129,
37 CONFIGID0 = 176,
38 EPC_1 = 177,
39 EPC_2 = 178,
40 EPC_3 = 179,
41 EPC_4 = 180,
42 EPC_5 = 181,
43 EPC_6 = 182,
44 EPC_7 = 183,
45 DEPC = 192,
46 EPS_2 = 194,
47 EPS_3 = 195,
48 EPS_4 = 196,
49 EPS_5 = 197,
50 EPS_6 = 198,
51 EPS_7 = 199,
52 CONFIGID1 = 208,
53 EXCSAVE_1 = 209,
54 EXCSAVE_2 = 210,
55 EXCSAVE_3 = 211,
56 EXCSAVE_4 = 212,
57 EXCSAVE_5 = 213,
58 EXCSAVE_6 = 214,
59 EXCSAVE_7 = 215,
60 CPENABLE = 224,
61 INTERRUPT = 226,
62 INTENABLE = 228,
63 PS = 230,
64 THREADPTR = 231,
65 EXCCAUSE = 232,
66 DEBUGCAUSE = 233,
67 CCOUNT = 234,
68 PRID = 235,
69 ICOUNT = 236,
70 ICOUNTLEVEL = 237,
71 EXCVADDR = 238,
72 CCOMPARE_0 = 240,
73 CCOMPARE_1 = 241,
74 CCOMPARE_2 = 242,
75 MISC_REG_0 = 244,
76 MISC_REG_1 = 245,
77 MISC_REG_2 = 246,
78 MISC_REG_3 = 247,
79 };
80
81 #define get_one_sreg(regnum_p) ({ \
82 unsigned int retval; \
83 __asm__ volatile( \
84 "rsr %[retval], %[regnum]\n\t" \
85 : [retval] "=r" (retval) \
86 : [regnum] "i" (regnum_p)); \
87 retval; \
88 })
89
90 #define set_one_sreg(regnum_p, regval) { \
91 __asm__ volatile( \
92 "wsr %[val], %[regnum]\n\t" \
93 :: \
94 [val] "r" (regval), \
95 [regnum] "i" (regnum_p)); \
96 }
97
98 /**
99 * Read one special register.
100 *
101 * @param ctx GDB context
102 * @param reg Register descriptor
103 */
read_sreg(struct gdb_ctx * ctx,struct xtensa_register * reg)104 static void read_sreg(struct gdb_ctx *ctx, struct xtensa_register *reg)
105 {
106 uint8_t regno;
107 uint32_t val;
108 bool has_val = true;
109
110 if (!gdb_xtensa_is_special_reg(reg)) {
111 return;
112 }
113
114 /*
115 * Special registers have 0x300 added to the register number
116 * in the register descriptor. So need to extract the actual
117 * special register number recognized by architecture,
118 * which is 0-255.
119 */
120 regno = reg->regno & 0xFF;
121
122 /*
123 * Each special register has to be done separately
124 * as the register number in RSR/WSR needs to be
125 * hard-coded at compile time.
126 */
127 switch (regno) {
128 case SAR:
129 val = get_one_sreg(SAR);
130 break;
131 case PS:
132 val = get_one_sreg(PS);
133 break;
134 case MEMCTL:
135 val = get_one_sreg(MEMCTL);
136 break;
137 case ATOMCTL:
138 val = get_one_sreg(ATOMCTL);
139 break;
140 case CONFIGID0:
141 val = get_one_sreg(CONFIGID0);
142 break;
143 case CONFIGID1:
144 val = get_one_sreg(CONFIGID1);
145 break;
146 case DEBUGCAUSE:
147 val = get_one_sreg(DEBUGCAUSE);
148 break;
149 case EXCCAUSE:
150 val = get_one_sreg(EXCCAUSE);
151 break;
152 case DEPC:
153 val = get_one_sreg(DEPC);
154 break;
155 case EPC_1:
156 val = get_one_sreg(EPC_1);
157 break;
158 case EXCSAVE_1:
159 val = get_one_sreg(EXCSAVE_1);
160 break;
161 case EXCVADDR:
162 val = get_one_sreg(EXCVADDR);
163 break;
164 #if XCHAL_HAVE_LOOPS
165 case LBEG:
166 val = get_one_sreg(LBEG);
167 break;
168 case LEND:
169 val = get_one_sreg(LEND);
170 break;
171 case LCOUNT:
172 val = get_one_sreg(LCOUNT);
173 break;
174 #endif
175 #if XCHAL_HAVE_S32C1I
176 case SCOMPARE1:
177 val = get_one_sreg(SCOMPARE1);
178 break;
179 #endif
180 #if XCHAL_HAVE_WINDOWED
181 case WINDOWBASE:
182 val = get_one_sreg(WINDOWBASE);
183 break;
184 case WINDOWSTART:
185 val = get_one_sreg(WINDOWSTART);
186 break;
187 #endif
188 #if XCHAL_NUM_INTLEVELS > 0
189 case EPS_2:
190 val = get_one_sreg(EPS_2);
191 break;
192 case EPC_2:
193 val = get_one_sreg(EPC_2);
194 break;
195 case EXCSAVE_2:
196 val = get_one_sreg(EXCSAVE_2);
197 break;
198 #endif
199 #if XCHAL_NUM_INTLEVELS > 1
200 case EPS_3:
201 val = get_one_sreg(EPS_3);
202 break;
203 case EPC_3:
204 val = get_one_sreg(EPC_3);
205 break;
206 case EXCSAVE_3:
207 val = get_one_sreg(EXCSAVE_3);
208 break;
209 #endif
210 #if XCHAL_NUM_INTLEVELS > 2
211 case EPC_4:
212 val = get_one_sreg(EPC_4);
213 break;
214 case EPS_4:
215 val = get_one_sreg(EPS_4);
216 break;
217 case EXCSAVE_4:
218 val = get_one_sreg(EXCSAVE_4);
219 break;
220 #endif
221 #if XCHAL_NUM_INTLEVELS > 3
222 case EPC_5:
223 val = get_one_sreg(EPC_5);
224 break;
225 case EPS_5:
226 val = get_one_sreg(EPS_5);
227 break;
228 case EXCSAVE_5:
229 val = get_one_sreg(EXCSAVE_5);
230 break;
231 #endif
232 #if XCHAL_NUM_INTLEVELS > 4
233 case EPC_6:
234 val = get_one_sreg(EPC_6);
235 break;
236 case EPS_6:
237 val = get_one_sreg(EPS_6);
238 break;
239 case EXCSAVE_6:
240 val = get_one_sreg(EXCSAVE_6);
241 break;
242 #endif
243 #if XCHAL_NUM_INTLEVELS > 5
244 case EPC_7:
245 val = get_one_sreg(EPC_7);
246 break;
247 case EPS_7:
248 val = get_one_sreg(EPS_7);
249 break;
250 case EXCSAVE_7:
251 val = get_one_sreg(EXCSAVE_7);
252 break;
253 #endif
254 #if XCHAL_HAVE_CP
255 case CPENABLE:
256 val = get_one_sreg(CPENABLE);
257 break;
258 #endif
259 #if XCHAL_HAVE_INTERRUPTS
260 case INTERRUPT:
261 val = get_one_sreg(INTERRUPT);
262 break;
263 case INTENABLE:
264 val = get_one_sreg(INTENABLE);
265 break;
266 #endif
267 #if XCHAL_HAVE_THREADPTR
268 case THREADPTR:
269 val = get_one_sreg(THREADPTR);
270 break;
271 #endif
272 #if XCHAL_HAVE_CCOUNT
273 case CCOUNT:
274 val = get_one_sreg(CCOUNT);
275 break;
276 #endif
277 #if XCHAL_HAVE_PRID
278 case PRID:
279 val = get_one_sreg(PRID);
280 break;
281 #endif
282 #if XCHAL_NUM_TIMERS > 0
283 case CCOMPARE_0:
284 val = get_one_sreg(CCOMPARE_0);
285 break;
286 #endif
287 #if XCHAL_NUM_TIMERS > 1
288 case CCOMPARE_1:
289 val = get_one_sreg(CCOMPARE_1);
290 break;
291 #endif
292 #if XCHAL_NUM_TIMERS > 2
293 case CCOMPARE_2:
294 val = get_one_sreg(CCOMPARE_2);
295 break;
296 #endif
297 #if XCHAL_NUM_MISC_REGS > 0
298 case MISC_REG_0:
299 val = get_one_sreg(MISC_REG_0);
300 break;
301 #endif
302 #if XCHAL_NUM_MISC_REGS > 1
303 case MISC_REG_1:
304 val = get_one_sreg(MISC_REG_1);
305 break;
306 #endif
307 #if XCHAL_NUM_MISC_REGS > 2
308 case MISC_REG_2:
309 val = get_one_sreg(MISC_REG_2);
310 break;
311 #endif
312 #if XCHAL_NUM_MISC_REGS > 3
313 case MISC_REG_3:
314 val = get_one_sreg(MISC_REG_3);
315 break;
316 #endif
317 default:
318 has_val = false;
319 break;
320 }
321
322 if (has_val) {
323 reg->val = val;
324 reg->seqno = ctx->seqno;
325 }
326 }
327
328 /**
329 * Translate exception into GDB exception reason.
330 *
331 * @param reason Reason for exception
332 */
get_gdb_exception_reason(unsigned int reason)333 static unsigned int get_gdb_exception_reason(unsigned int reason)
334 {
335 unsigned int exception;
336
337 switch (reason) {
338 case EXCCAUSE_ILLEGAL:
339 /* illegal instruction */
340 exception = GDB_EXCEPTION_INVALID_INSTRUCTION;
341 break;
342 case EXCCAUSE_INSTR_ERROR:
343 /* instr fetch error */
344 exception = GDB_EXCEPTION_MEMORY_FAULT;
345 break;
346 case EXCCAUSE_LOAD_STORE_ERROR:
347 /* load/store error */
348 exception = GDB_EXCEPTION_MEMORY_FAULT;
349 break;
350 case EXCCAUSE_DIVIDE_BY_ZERO:
351 /* divide by zero */
352 exception = GDB_EXCEPTION_DIVIDE_ERROR;
353 break;
354 case EXCCAUSE_UNALIGNED:
355 /* load/store alignment */
356 exception = GDB_EXCEPTION_MEMORY_FAULT;
357 break;
358 case EXCCAUSE_INSTR_DATA_ERROR:
359 /* instr PIF data error */
360 exception = GDB_EXCEPTION_MEMORY_FAULT;
361 break;
362 case EXCCAUSE_LOAD_STORE_DATA_ERROR:
363 /* load/store PIF data error */
364 exception = GDB_EXCEPTION_MEMORY_FAULT;
365 break;
366 case EXCCAUSE_INSTR_ADDR_ERROR:
367 /* instr PIF addr error */
368 exception = GDB_EXCEPTION_MEMORY_FAULT;
369 break;
370 case EXCCAUSE_LOAD_STORE_ADDR_ERROR:
371 /* load/store PIF addr error */
372 exception = GDB_EXCEPTION_MEMORY_FAULT;
373 break;
374 case EXCCAUSE_INSTR_PROHIBITED:
375 /* inst fetch prohibited */
376 exception = GDB_EXCEPTION_INVALID_MEMORY;
377 break;
378 case EXCCAUSE_LOAD_STORE_RING:
379 /* load/store privilege */
380 exception = GDB_EXCEPTION_INVALID_MEMORY;
381 break;
382 case EXCCAUSE_LOAD_PROHIBITED:
383 /* load prohibited */
384 exception = GDB_EXCEPTION_INVALID_MEMORY;
385 break;
386 case EXCCAUSE_STORE_PROHIBITED:
387 /* store prohibited */
388 exception = GDB_EXCEPTION_INVALID_MEMORY;
389 break;
390 case EXCCAUSE_CP0_DISABLED:
391 __fallthrough;
392 case EXCCAUSE_CP1_DISABLED:
393 __fallthrough;
394 case EXCCAUSE_CP2_DISABLED:
395 __fallthrough;
396 case EXCCAUSE_CP3_DISABLED:
397 __fallthrough;
398 case EXCCAUSE_CP4_DISABLED:
399 __fallthrough;
400 case EXCCAUSE_CP5_DISABLED:
401 __fallthrough;
402 case EXCCAUSE_CP6_DISABLED:
403 __fallthrough;
404 case EXCCAUSE_CP7_DISABLED:
405 /* coprocessor disabled */
406 exception = GDB_EXCEPTION_INVALID_INSTRUCTION;
407 break;
408 default:
409 exception = GDB_EXCEPTION_MEMORY_FAULT;
410 break;
411 }
412
413 return exception;
414 }
415
416 /**
417 * Copy debug information from stack into GDB context.
418 *
419 * This copies the information stored in the stack into the GDB
420 * context for the thread being debugged.
421 *
422 * @param ctx GDB context
423 * @param stack Pointer to the stack frame
424 */
copy_to_ctx(struct gdb_ctx * ctx,const struct arch_esf * stack)425 static void copy_to_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack)
426 {
427 struct xtensa_register *reg;
428 int idx, num_laddr_regs;
429
430 uint32_t *bsa = *(int **)stack;
431
432 if ((int *)bsa - stack > 4) {
433 num_laddr_regs = 8;
434 } else if ((int *)bsa - stack > 8) {
435 num_laddr_regs = 12;
436 } else if ((int *)bsa - stack > 12) {
437 num_laddr_regs = 16;
438 } else {
439 num_laddr_regs = 4;
440 }
441
442 /* Get logical address registers A0 - A<num_laddr_regs> from stack */
443 for (idx = 0; idx < num_laddr_regs; idx++) {
444 reg = &xtensa_gdb_ctx.regs[xtensa_gdb_ctx.a0_idx + idx];
445
446 if (reg->regno == SOC_GDB_REGNO_A1) {
447 /* A1 is calculated */
448 reg->val = POINTER_TO_UINT(
449 ((char *)bsa) + BASE_SAVE_AREA_SIZE);
450 reg->seqno = ctx->seqno;
451 } else {
452 reg->val = bsa[reg->stack_offset / 4];
453 reg->seqno = ctx->seqno;
454 }
455 }
456
457 /* For registers other than logical address registers */
458 for (idx = 0; idx < xtensa_gdb_ctx.num_regs; idx++) {
459 reg = &xtensa_gdb_ctx.regs[idx];
460
461 if (gdb_xtensa_is_logical_addr_reg(reg)) {
462 /* Logical address registers are handled above */
463 continue;
464 } else if (reg->stack_offset != 0) {
465 /* For those registers stashed in stack */
466 reg->val = bsa[reg->stack_offset / 4];
467 reg->seqno = ctx->seqno;
468 } else if (gdb_xtensa_is_special_reg(reg)) {
469 read_sreg(ctx, reg);
470 }
471 }
472
473 #if XCHAL_HAVE_WINDOWED
474 uint8_t a0_idx, ar_idx, wb_start;
475
476 wb_start = (uint8_t)xtensa_gdb_ctx.regs[xtensa_gdb_ctx.wb_idx].val;
477
478 /*
479 * Copied the logical registers A0-A15 to physical registers (AR*)
480 * according to WINDOWBASE.
481 */
482 for (idx = 0; idx < num_laddr_regs; idx++) {
483 /* Index to register description array for A */
484 a0_idx = xtensa_gdb_ctx.a0_idx + idx;
485
486 /* Find the start of window (== WINDOWBASE * 4) */
487 ar_idx = wb_start * 4;
488 /* Which logical register we are working on... */
489 ar_idx += idx;
490 /* Wrap around A64 (or A32) -> A0 */
491 ar_idx %= XCHAL_NUM_AREGS;
492 /* Index to register description array for AR */
493 ar_idx += xtensa_gdb_ctx.ar_idx;
494
495 xtensa_gdb_ctx.regs[ar_idx].val = xtensa_gdb_ctx.regs[a0_idx].val;
496 xtensa_gdb_ctx.regs[ar_idx].seqno = xtensa_gdb_ctx.regs[a0_idx].seqno;
497 }
498 #endif
499
500 /* Disable stepping */
501 set_one_sreg(ICOUNT, 0);
502 set_one_sreg(ICOUNTLEVEL, 0);
503 __asm__ volatile("isync");
504 }
505
506 /**
507 * Restore debug information from stack into GDB context.
508 *
509 * This copies the information stored the GDB context back into
510 * the stack. So that the thread being debugged has new values
511 * after context switch from GDB stub back to the thread.
512 *
513 * @param ctx GDB context
514 * @param stack Pointer to the stack frame
515 */
restore_from_ctx(struct gdb_ctx * ctx,const struct arch_esf * stack)516 static void restore_from_ctx(struct gdb_ctx *ctx, const struct arch_esf *stack)
517 {
518 struct xtensa_register *reg;
519 int idx, num_laddr_regs;
520
521 _xtensa_irq_bsa_t *bsa = (void *)*(int **)stack;
522
523 if ((int *)bsa - stack > 4) {
524 num_laddr_regs = 8;
525 } else if ((int *)bsa - stack > 8) {
526 num_laddr_regs = 12;
527 } else if ((int *)bsa - stack > 12) {
528 num_laddr_regs = 16;
529 } else {
530 num_laddr_regs = 4;
531 }
532
533 /*
534 * Note that we don't need to copy AR* back to A* for
535 * windowed registers. GDB manipulates A0-A15 directly
536 * without going through AR*.
537 */
538
539 /*
540 * Push values of logical address registers A0 - A<num_laddr_regs>
541 * back to stack.
542 */
543 for (idx = 0; idx < num_laddr_regs; idx++) {
544 reg = &xtensa_gdb_ctx.regs[xtensa_gdb_ctx.a0_idx + idx];
545
546 if (reg->regno == SOC_GDB_REGNO_A1) {
547 /* Shouldn't be changing stack pointer */
548 continue;
549 } else {
550 bsa[reg->stack_offset / 4] = reg->val;
551 }
552 }
553
554 for (idx = 0; idx < xtensa_gdb_ctx.num_regs; idx++) {
555 reg = &xtensa_gdb_ctx.regs[idx];
556
557 if (gdb_xtensa_is_logical_addr_reg(reg)) {
558 /* Logical address registers are handled above */
559 continue;
560 } else if (reg->stack_offset != 0) {
561 /* For those registers stashed in stack */
562 bsa[reg->stack_offset / 4] = reg->val;
563 } else if (gdb_xtensa_is_special_reg(reg)) {
564 /*
565 * Currently not writing back any special
566 * registers.
567 */
568 continue;
569 }
570 }
571
572 if (!not_first_break) {
573 /*
574 * Need to go past the BREAK.N instruction (16-bit)
575 * in arch_gdb_init(). Or else the SoC will simply
576 * go back to execute the BREAK.N instruction,
577 * which raises debug interrupt, and we will be
578 * stuck in an infinite loop.
579 */
580 bsa->pc += 2;
581 not_first_break = true;
582 }
583 }
584
arch_gdb_continue(void)585 void arch_gdb_continue(void)
586 {
587 /*
588 * No need to do anything. Simply let the GDB stub main
589 * loop to return from debug interrupt for code to
590 * continue running.
591 */
592 }
593
arch_gdb_step(void)594 void arch_gdb_step(void)
595 {
596 set_one_sreg(ICOUNT, 0xFFFFFFFEU);
597 set_one_sreg(ICOUNTLEVEL, XCHAL_DEBUGLEVEL);
598 __asm__ volatile("isync");
599 }
600
601 /**
602 * Convert a register value into hex string.
603 *
604 * Note that this assumes the output buffer always has enough
605 * space.
606 *
607 * @param reg Xtensa register
608 * @param hex Pointer to output buffer
609 * @return Number of bytes written to output buffer
610 */
reg2hex(const struct xtensa_register * reg,char * hex)611 static size_t reg2hex(const struct xtensa_register *reg, char *hex)
612 {
613 uint8_t *bin = (uint8_t *)®->val;
614 size_t binlen = reg->byte_size;
615
616 for (size_t i = 0; i < binlen; i++) {
617 if (hex2char(bin[i] >> 4, &hex[2 * i]) < 0) {
618 return 0;
619 }
620 if (hex2char(bin[i] & 0xf, &hex[2 * i + 1]) < 0) {
621 return 0;
622 }
623 }
624
625 return 2 * binlen;
626 }
627
arch_gdb_reg_readall(struct gdb_ctx * ctx,uint8_t * buf,size_t buflen)628 size_t arch_gdb_reg_readall(struct gdb_ctx *ctx, uint8_t *buf, size_t buflen)
629 {
630 struct xtensa_register *reg;
631 int idx;
632 uint8_t *output;
633 size_t ret;
634
635 if (buflen < SOC_GDB_GPKT_HEX_SIZE) {
636 ret = 0;
637 goto out;
638 }
639
640 /*
641 * Fill with 'x' to mark them as available since most registers
642 * are not available in the stack.
643 */
644 memset(buf, 'x', SOC_GDB_GPKT_HEX_SIZE);
645
646 ret = 0;
647 for (idx = 0; idx < ctx->num_regs; idx++) {
648 reg = &ctx->regs[idx];
649
650 if (reg->seqno != ctx->seqno) {
651 /*
652 * Register struct has stale value from
653 * previous debug interrupt. Don't
654 * send it out.
655 */
656 continue;
657 }
658
659 if ((reg->gpkt_offset < 0) ||
660 (reg->gpkt_offset >= SOC_GDB_GPKT_BIN_SIZE)) {
661 /*
662 * Register is not in G-packet, or
663 * beyond maximum size of G-packet.
664 *
665 * xtensa-config.c may specify G-packet
666 * offset beyond what GDB expects, so
667 * need to make sure we won't write beyond
668 * the buffer.
669 */
670 continue;
671 }
672
673 /* Two hex characters per byte */
674 output = &buf[reg->gpkt_offset * 2];
675
676 if (reg2hex(reg, output) == 0) {
677 goto out;
678 }
679 }
680
681 ret = SOC_GDB_GPKT_HEX_SIZE;
682
683 out:
684 return ret;
685 }
686
arch_gdb_reg_writeall(struct gdb_ctx * ctx,uint8_t * hex,size_t hexlen)687 size_t arch_gdb_reg_writeall(struct gdb_ctx *ctx, uint8_t *hex, size_t hexlen)
688 {
689 /*
690 * GDB on Xtensa does not seem to use G-packet to write register
691 * values. So we can skip this function.
692 */
693
694 ARG_UNUSED(ctx);
695 ARG_UNUSED(hex);
696 ARG_UNUSED(hexlen);
697
698 return 0;
699 }
700
arch_gdb_reg_readone(struct gdb_ctx * ctx,uint8_t * buf,size_t buflen,uint32_t regno)701 size_t arch_gdb_reg_readone(struct gdb_ctx *ctx, uint8_t *buf, size_t buflen,
702 uint32_t regno)
703 {
704 struct xtensa_register *reg;
705 int idx;
706 size_t ret;
707
708 ret = 0;
709 for (idx = 0; idx < ctx->num_regs; idx++) {
710 reg = &ctx->regs[idx];
711
712 /*
713 * GDB sends the G-packet index as register number
714 * instead of the actual Xtensa register number.
715 */
716 if (reg->idx == regno) {
717 if (reg->seqno != ctx->seqno) {
718 /*
719 * Register value has stale value from
720 * previous debug interrupt. Report
721 * register value as unavailable.
722 *
723 * Don't report error here, or else GDB
724 * may stop the debug session.
725 */
726
727 if (buflen < 2) {
728 /* Output buffer cannot hold 'xx' */
729 goto out;
730 }
731
732 buf[0] = 'x';
733 buf[1] = 'x';
734 ret = 2;
735 goto out;
736 }
737
738 /* Make sure output buffer is large enough */
739 if (buflen < (reg->byte_size * 2)) {
740 goto out;
741 }
742
743 ret = reg2hex(reg, buf);
744
745 break;
746 }
747 }
748
749 out:
750 return ret;
751 }
752
arch_gdb_reg_writeone(struct gdb_ctx * ctx,uint8_t * hex,size_t hexlen,uint32_t regno)753 size_t arch_gdb_reg_writeone(struct gdb_ctx *ctx, uint8_t *hex, size_t hexlen,
754 uint32_t regno)
755 {
756 struct xtensa_register *reg = NULL;
757 int idx;
758 size_t ret;
759
760 ret = 0;
761 for (idx = 0; idx < ctx->num_regs; idx++) {
762 reg = &ctx->regs[idx];
763
764 /*
765 * Remember GDB sends index number instead of
766 * actual register number (as defined in Xtensa
767 * architecture).
768 */
769 if (reg->idx != regno) {
770 continue;
771 }
772
773 if (hexlen < (reg->byte_size * 2)) {
774 /* Not enough hex digits to fill the register */
775 goto out;
776 }
777
778 /* Register value is now up-to-date */
779 reg->seqno = ctx->seqno;
780
781 /* Convert from hexadecimal into binary */
782 ret = hex2bin(hex, hexlen,
783 (uint8_t *)®->val, reg->byte_size);
784 break;
785 }
786
787 out:
788 return ret;
789 }
790
arch_gdb_add_breakpoint(struct gdb_ctx * ctx,uint8_t type,uintptr_t addr,uint32_t kind)791 int arch_gdb_add_breakpoint(struct gdb_ctx *ctx, uint8_t type,
792 uintptr_t addr, uint32_t kind)
793 {
794 int ret, idx;
795 uint32_t ibreakenable;
796
797 switch (type) {
798 case 1:
799 /* Hardware breakpoint */
800 ibreakenable = get_one_sreg(IBREAKENABLE);
801 for (idx = 0; idx < MAX(XCHAL_NUM_IBREAK, 2); idx++) {
802 /* Find an empty IBREAK slot */
803 if ((ibreakenable & BIT(idx)) == 0) {
804 /* Set breakpoint address */
805
806 if (idx == 0) {
807 set_one_sreg(IBREAKA0, addr);
808 } else if (idx == 1) {
809 set_one_sreg(IBREAKA1, addr);
810 } else {
811 ret = -1;
812 goto out;
813 }
814
815 /* Enable the breakpoint */
816 ibreakenable |= BIT(idx);
817 set_one_sreg(IBREAKENABLE, ibreakenable);
818
819 ret = 0;
820 goto out;
821 }
822 }
823
824 /* Cannot find an empty slot, return error */
825 ret = -1;
826 break;
827 case 0:
828 /*
829 * Software breakpoint is to replace the instruction at
830 * target address with BREAK or BREAK.N. GDB, by default,
831 * does this by using memory write packets to replace
832 * instructions. So there is no need to implement
833 * software breakpoint here.
834 */
835 __fallthrough;
836 default:
837 /* Breakpoint type not supported */
838 ret = -2;
839 break;
840 }
841
842 out:
843 return ret;
844 }
845
arch_gdb_remove_breakpoint(struct gdb_ctx * ctx,uint8_t type,uintptr_t addr,uint32_t kind)846 int arch_gdb_remove_breakpoint(struct gdb_ctx *ctx, uint8_t type,
847 uintptr_t addr, uint32_t kind)
848 {
849 int ret, idx;
850 uint32_t ibreakenable, ibreak;
851
852 switch (type) {
853 case 1:
854 /* Hardware breakpoint */
855 ibreakenable = get_one_sreg(IBREAKENABLE);
856 for (idx = 0; idx < MAX(XCHAL_NUM_IBREAK, 2); idx++) {
857 /* Find an active IBREAK slot and compare address */
858 if ((ibreakenable & BIT(idx)) == BIT(idx)) {
859 if (idx == 0) {
860 ibreak = get_one_sreg(IBREAKA0);
861 } else if (idx == 1) {
862 ibreak = get_one_sreg(IBREAKA1);
863 } else {
864 ret = -1;
865 goto out;
866 }
867
868 if (ibreak == addr) {
869 /* Clear breakpoint address */
870 if (idx == 0) {
871 set_one_sreg(IBREAKA0, 0U);
872 } else if (idx == 1) {
873 set_one_sreg(IBREAKA1, 0U);
874 } else {
875 ret = -1;
876 goto out;
877 }
878
879 /* Disable the breakpoint */
880 ibreakenable &= ~BIT(idx);
881 set_one_sreg(IBREAKENABLE,
882 ibreakenable);
883
884 ret = 0;
885 goto out;
886 }
887 }
888 }
889
890 /*
891 * Cannot find matching breakpoint address,
892 * return error.
893 */
894 ret = -1;
895
896 break;
897 case 0:
898 /*
899 * Software breakpoint is to replace the instruction at
900 * target address with BREAK or BREAK.N. GDB, by default,
901 * does this by using memory write packets to restore
902 * instructions. So there is no need to implement
903 * software breakpoint here.
904 */
905 __fallthrough;
906 default:
907 /* Breakpoint type not supported */
908 ret = -2;
909 break;
910 }
911
912 out:
913 return ret;
914 }
915
z_gdb_isr(struct arch_esf * esf)916 void z_gdb_isr(struct arch_esf *esf)
917 {
918 uint32_t reg;
919
920 reg = get_one_sreg(DEBUGCAUSE);
921 if (reg != 0) {
922 /* Manual breaking */
923 xtensa_gdb_ctx.exception = GDB_EXCEPTION_BREAKPOINT;
924 } else {
925 /* Actual exception */
926 reg = get_one_sreg(EXCCAUSE);
927 xtensa_gdb_ctx.exception = get_gdb_exception_reason(reg);
928 }
929
930 xtensa_gdb_ctx.seqno++;
931
932 /* Copy registers into GDB context */
933 copy_to_ctx(&xtensa_gdb_ctx, esf);
934
935 z_gdb_main_loop(&xtensa_gdb_ctx);
936
937 /* Restore registers from GDB context */
938 restore_from_ctx(&xtensa_gdb_ctx, esf);
939 }
940
arch_gdb_init(void)941 void arch_gdb_init(void)
942 {
943 int idx;
944
945 /*
946 * Find out the starting index in the register
947 * description array of certain registers.
948 */
949 for (idx = 0; idx < xtensa_gdb_ctx.num_regs; idx++) {
950 switch (xtensa_gdb_ctx.regs[idx].regno) {
951 case 0x0000:
952 /* A0: 0x0000 */
953 xtensa_gdb_ctx.a0_idx = idx;
954 break;
955 case XTREG_GRP_ADDR:
956 /* AR0: 0x0100 */
957 xtensa_gdb_ctx.ar_idx = idx;
958 break;
959 case (XTREG_GRP_SPECIAL + WINDOWBASE):
960 /* WINDOWBASE (Special Register) */
961 xtensa_gdb_ctx.wb_idx = idx;
962 break;
963 default:
964 break;
965 };
966 }
967
968 /*
969 * The interrupt enable bits for higher level interrupts
970 * (level 2+) sit just after the level-1 interrupts.
971 * The need to do a minus 2 is simply that the first bit
972 * after level-1 interrupts is for level-2 interrupt.
973 * So need to do an offset by subtraction.
974 */
975 xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS + XCHAL_DEBUGLEVEL - 2);
976
977 /*
978 * Break and go into the GDB stub.
979 * The underscore in front is to avoid toolchain
980 * converting BREAK.N into BREAK which is bigger.
981 * This is needed as the GDB stub will need to change
982 * the program counter past this instruction to
983 * continue working. Or else SoC would repeatedly
984 * raise debug exception on this instruction and
985 * won't go forward.
986 */
987 __asm__ volatile ("_break.n 0");
988 }
989
