1 /* 2 * Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com> 3 * 4 * Macros for MIPS CP0 registers manipulations 5 * inspired by linux/arch/mips/include/asm/mipsregs.h 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 #ifndef _ZEPHYR_ARCH_MIPS_INCLUDE_MIPS_MIPSREGS_H_ 11 #define _ZEPHYR_ARCH_MIPS_INCLUDE_MIPS_MIPSREGS_H_ 12 13 #define CP0_BADVADDR $8 14 #define CP0_COUNT $9 15 #define CP0_COMPARE $11 16 #define CP0_STATUS $12 17 #define CP0_CAUSE $13 18 #define CP0_EPC $14 19 20 /* CP0_STATUS bits */ 21 #define ST0_IE 0x00000001 22 #define ST0_EXL 0x00000002 23 #define ST0_ERL 0x00000004 24 #define ST0_IP0 0x00000100 25 #define ST0_BEV 0x00400000 26 27 /* CP0_CAUSE bits */ 28 #define CAUSE_EXP_MASK 0x0000007c 29 #define CAUSE_EXP_SHIFT 2 30 #define CAUSE_IP_MASK 0x0000ff00 31 #define CAUSE_IP_SHIFT 8 32 33 #define _mips_read_32bit_c0_register(reg) \ 34 ({ \ 35 uint32_t val; \ 36 __asm__ __volatile__("mfc0\t%0, " STRINGIFY(reg) "\n" \ 37 : "=r" (val)); \ 38 val; \ 39 }) 40 41 #define _mips_write_32bit_c0_register(reg, val) \ 42 ({ \ 43 __asm__ __volatile__("mtc0 %z0, " STRINGIFY(reg) "\n" \ 44 : \ 45 : "Jr" ((uint32_t)(val))); \ 46 }) 47 48 #define read_c0_status() _mips_read_32bit_c0_register(CP0_STATUS) 49 #define write_c0_status(val) _mips_write_32bit_c0_register(CP0_STATUS, val) 50 51 #define read_c0_cause() _mips_read_32bit_c0_register(CP0_CAUSE) 52 53 #endif /* _ZEPHYR_ARCH_MIPS_INCLUDE_MIPS_MIPSREGS_H_ */ 54
