1 /*
2  * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_X2_H
8 #define CORTEX_X2_H
9 
10 #define CORTEX_X2_MIDR						U(0x410FD480)
11 
12 /* Cortex-X2 loop count for CVE-2022-23960 mitigation */
13 #define CORTEX_X2_BHB_LOOP_COUNT       				U(32)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions
17  ******************************************************************************/
18 #define CORTEX_X2_CPUECTLR_EL1					S3_0_C15_C1_4
19 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT			(ULL(1) << 8)
20 
21 /*******************************************************************************
22  * CPU Extended Control register 2 specific definitions
23  ******************************************************************************/
24 #define CORTEX_X2_CPUECTLR2_EL1					S3_0_C15_C1_5
25 
26 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT			U(11)
27 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH			U(4)
28 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV			ULL(0x9)
29 
30 /*******************************************************************************
31  * CPU Auxiliary Control register 3 specific definitions.
32  ******************************************************************************/
33 #define CORTEX_X2_CPUACTLR3_EL1				S3_0_C15_C1_2
34 
35 /*******************************************************************************
36  * CPU Power Control register specific definitions
37  ******************************************************************************/
38 #define CORTEX_X2_CPUPWRCTLR_EL1				S3_0_C15_C2_7
39 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT			U(1)
40 
41 /*******************************************************************************
42  * CPU Auxiliary Control Register definitions
43  ******************************************************************************/
44 #define CORTEX_X2_CPUACTLR_EL1					S3_0_C15_C1_0
45 #define CORTEX_X2_CPUACTLR_EL1_BIT_22				(ULL(1) << 22)
46 
47 /*******************************************************************************
48  * CPU Auxiliary Control Register 2 definitions
49  ******************************************************************************/
50 #define CORTEX_X2_CPUACTLR2_EL1					S3_0_C15_C1_1
51 #define CORTEX_X2_CPUACTLR2_EL1_BIT_40				(ULL(1) << 40)
52 
53 /*******************************************************************************
54  * CPU Auxiliary Control Register 5 definitions
55  ******************************************************************************/
56 #define CORTEX_X2_CPUACTLR5_EL1					S3_0_C15_C8_0
57 #define CORTEX_X2_CPUACTLR5_EL1_BIT_17				(ULL(1) << 17)
58 
59 /*******************************************************************************
60  * CPU Implementation Specific Selected Instruction registers
61  ******************************************************************************/
62 #define CORTEX_X2_IMP_CPUPSELR_EL3				S3_6_C15_C8_0
63 #define CORTEX_X2_IMP_CPUPCR_EL3				S3_6_C15_C8_1
64 #define CORTEX_X2_IMP_CPUPOR_EL3				S3_6_C15_C8_2
65 #define CORTEX_X2_IMP_CPUPMR_EL3				S3_6_C15_C8_3
66 
67 #endif /* CORTEX_X2_H */
68