1 /* 2 * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A72_H 8 #define CORTEX_A72_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A72 midr for revision 0 */ 13 #define CORTEX_A72_MIDR U(0x410FD080) 14 15 /* Cortex-A72 loop count for CVE-2022-23960 mitigation */ 16 #define CORTEX_A72_BHB_LOOP_COUNT U(8) 17 18 /******************************************************************************* 19 * CPU Extended Control register specific definitions. 20 ******************************************************************************/ 21 #define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 22 23 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 24 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 25 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 26 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 27 28 /******************************************************************************* 29 * CPU Memory Error Syndrome register specific definitions. 30 ******************************************************************************/ 31 #define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 32 33 /******************************************************************************* 34 * CPU Auxiliary Control register specific definitions. 35 ******************************************************************************/ 36 #define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 37 38 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 39 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 40 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 41 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 42 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 43 #define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31) 44 45 /******************************************************************************* 46 * L2 Auxiliary Control register specific definitions. 47 ******************************************************************************/ 48 #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 49 50 #define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28) 51 #define CORTEX_A72_L2ACTLR_FORCE_L2_LOGIC_CLK_ACTIVE (ULL(1) << 27) 52 #define CORTEX_A72_L2ACTLR_FORCE_L2_GIC_TIMER_RCG_CLK_ACTIVE (ULL(1) << 26) 53 #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) 54 #define CORTEX_A72_L2ACTLR_DISABLE_DSB_WITH_NO_DVM_SYNC (ULL(1) << 11) 55 #define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8) 56 #define CORTEX_A72_L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT (ULL(1) << 7) 57 #define CORTEX_A72_L2ACTLR_DISABLE_ACE_SH_OR_CHI (ULL(1) << 6) 58 59 /******************************************************************************* 60 * L2 Control register specific definitions. 61 ******************************************************************************/ 62 #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 63 64 #define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) 65 #define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) 66 67 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 68 #define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) 69 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 70 #define CORTEX_A72_L2CTLR_TAG_RAM_SETUP_SHIFT U(9) 71 72 #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) 73 #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) 74 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 75 #define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) 76 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) 77 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 78 79 /******************************************************************************* 80 * L2 Memory Error Syndrome register specific definitions. 81 ******************************************************************************/ 82 #define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 83 84 #endif /* CORTEX_A72_H */ 85
